1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MDIO bus driver for the Xilinx Axi Ethernet device 4 * 5 * Copyright (c) 2009 Secret Lab Technologies, Ltd. 6 * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu> 7 * Copyright (c) 2010 - 2011 PetaLogix 8 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved. 9 */ 10 11 #include <linux/of_address.h> 12 #include <linux/of_mdio.h> 13 #include <linux/jiffies.h> 14 #include <linux/iopoll.h> 15 16 #include "xilinx_axienet.h" 17 18 #define MAX_MDIO_FREQ 2500000 /* 2.5 MHz */ 19 #define DEFAULT_CLOCK_DIVISOR XAE_MDIO_DIV_DFT 20 21 /* Wait till MDIO interface is ready to accept a new transaction.*/ 22 int axienet_mdio_wait_until_ready(struct axienet_local *lp) 23 { 24 u32 val; 25 26 return readx_poll_timeout(axinet_ior_read_mcr, lp, 27 val, val & XAE_MDIO_MCR_READY_MASK, 28 1, 20000); 29 } 30 31 /** 32 * axienet_mdio_read - MDIO interface read function 33 * @bus: Pointer to mii bus structure 34 * @phy_id: Address of the PHY device 35 * @reg: PHY register to read 36 * 37 * Return: The register contents on success, -ETIMEDOUT on a timeout 38 * 39 * Reads the contents of the requested register from the requested PHY 40 * address by first writing the details into MCR register. After a while 41 * the register MRD is read to obtain the PHY register content. 42 */ 43 static int axienet_mdio_read(struct mii_bus *bus, int phy_id, int reg) 44 { 45 u32 rc; 46 int ret; 47 struct axienet_local *lp = bus->priv; 48 49 ret = axienet_mdio_wait_until_ready(lp); 50 if (ret < 0) 51 return ret; 52 53 axienet_iow(lp, XAE_MDIO_MCR_OFFSET, 54 (((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) & 55 XAE_MDIO_MCR_PHYAD_MASK) | 56 ((reg << XAE_MDIO_MCR_REGAD_SHIFT) & 57 XAE_MDIO_MCR_REGAD_MASK) | 58 XAE_MDIO_MCR_INITIATE_MASK | 59 XAE_MDIO_MCR_OP_READ_MASK)); 60 61 ret = axienet_mdio_wait_until_ready(lp); 62 if (ret < 0) 63 return ret; 64 65 rc = axienet_ior(lp, XAE_MDIO_MRD_OFFSET) & 0x0000FFFF; 66 67 dev_dbg(lp->dev, "axienet_mdio_read(phy_id=%i, reg=%x) == %x\n", 68 phy_id, reg, rc); 69 70 return rc; 71 } 72 73 /** 74 * axienet_mdio_write - MDIO interface write function 75 * @bus: Pointer to mii bus structure 76 * @phy_id: Address of the PHY device 77 * @reg: PHY register to write to 78 * @val: Value to be written into the register 79 * 80 * Return: 0 on success, -ETIMEDOUT on a timeout 81 * 82 * Writes the value to the requested register by first writing the value 83 * into MWD register. The the MCR register is then appropriately setup 84 * to finish the write operation. 85 */ 86 static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg, 87 u16 val) 88 { 89 int ret; 90 struct axienet_local *lp = bus->priv; 91 92 dev_dbg(lp->dev, "axienet_mdio_write(phy_id=%i, reg=%x, val=%x)\n", 93 phy_id, reg, val); 94 95 ret = axienet_mdio_wait_until_ready(lp); 96 if (ret < 0) 97 return ret; 98 99 axienet_iow(lp, XAE_MDIO_MWD_OFFSET, (u32) val); 100 axienet_iow(lp, XAE_MDIO_MCR_OFFSET, 101 (((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) & 102 XAE_MDIO_MCR_PHYAD_MASK) | 103 ((reg << XAE_MDIO_MCR_REGAD_SHIFT) & 104 XAE_MDIO_MCR_REGAD_MASK) | 105 XAE_MDIO_MCR_INITIATE_MASK | 106 XAE_MDIO_MCR_OP_WRITE_MASK)); 107 108 ret = axienet_mdio_wait_until_ready(lp); 109 if (ret < 0) 110 return ret; 111 return 0; 112 } 113 114 /** 115 * axienet_mdio_setup - MDIO setup function 116 * @lp: Pointer to axienet local data structure. 117 * @np: Pointer to device node 118 * 119 * Return: 0 on success, -ETIMEDOUT on a timeout, -ENOMEM when 120 * mdiobus_alloc (to allocate memory for mii bus structure) fails. 121 * 122 * Sets up the MDIO interface by initializing the MDIO clock and enabling the 123 * MDIO interface in hardware. Register the MDIO interface. 124 **/ 125 int axienet_mdio_setup(struct axienet_local *lp, struct device_node *np) 126 { 127 int ret; 128 u32 clk_div, host_clock; 129 struct mii_bus *bus; 130 struct resource res; 131 struct device_node *np1; 132 133 /* clk_div can be calculated by deriving it from the equation: 134 * fMDIO = fHOST / ((1 + clk_div) * 2) 135 * 136 * Where fMDIO <= 2500000, so we get: 137 * fHOST / ((1 + clk_div) * 2) <= 2500000 138 * 139 * Then we get: 140 * 1 / ((1 + clk_div) * 2) <= (2500000 / fHOST) 141 * 142 * Then we get: 143 * 1 / (1 + clk_div) <= ((2500000 * 2) / fHOST) 144 * 145 * Then we get: 146 * 1 / (1 + clk_div) <= (5000000 / fHOST) 147 * 148 * So: 149 * (1 + clk_div) >= (fHOST / 5000000) 150 * 151 * And finally: 152 * clk_div >= (fHOST / 5000000) - 1 153 * 154 * fHOST can be read from the flattened device tree as property 155 * "clock-frequency" from the CPU 156 */ 157 158 np1 = of_find_node_by_name(NULL, "cpu"); 159 if (!np1) { 160 netdev_warn(lp->ndev, "Could not find CPU device node.\n"); 161 netdev_warn(lp->ndev, 162 "Setting MDIO clock divisor to default %d\n", 163 DEFAULT_CLOCK_DIVISOR); 164 clk_div = DEFAULT_CLOCK_DIVISOR; 165 goto issue; 166 } 167 if (of_property_read_u32(np1, "clock-frequency", &host_clock)) { 168 netdev_warn(lp->ndev, "clock-frequency property not found.\n"); 169 netdev_warn(lp->ndev, 170 "Setting MDIO clock divisor to default %d\n", 171 DEFAULT_CLOCK_DIVISOR); 172 clk_div = DEFAULT_CLOCK_DIVISOR; 173 of_node_put(np1); 174 goto issue; 175 } 176 177 clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1; 178 /* If there is any remainder from the division of 179 * fHOST / (MAX_MDIO_FREQ * 2), then we need to add 180 * 1 to the clock divisor or we will surely be above 2.5 MHz 181 */ 182 if (host_clock % (MAX_MDIO_FREQ * 2)) 183 clk_div++; 184 185 netdev_dbg(lp->ndev, 186 "Setting MDIO clock divisor to %u/%u Hz host clock.\n", 187 clk_div, host_clock); 188 189 of_node_put(np1); 190 issue: 191 axienet_iow(lp, XAE_MDIO_MC_OFFSET, 192 (((u32) clk_div) | XAE_MDIO_MC_MDIOEN_MASK)); 193 194 ret = axienet_mdio_wait_until_ready(lp); 195 if (ret < 0) 196 return ret; 197 198 bus = mdiobus_alloc(); 199 if (!bus) 200 return -ENOMEM; 201 202 np1 = of_get_parent(lp->phy_node); 203 of_address_to_resource(np1, 0, &res); 204 snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx", 205 (unsigned long long) res.start); 206 207 bus->priv = lp; 208 bus->name = "Xilinx Axi Ethernet MDIO"; 209 bus->read = axienet_mdio_read; 210 bus->write = axienet_mdio_write; 211 bus->parent = lp->dev; 212 lp->mii_bus = bus; 213 214 ret = of_mdiobus_register(bus, np1); 215 if (ret) { 216 mdiobus_free(bus); 217 lp->mii_bus = NULL; 218 return ret; 219 } 220 return 0; 221 } 222 223 /** 224 * axienet_mdio_teardown - MDIO remove function 225 * @lp: Pointer to axienet local data structure. 226 * 227 * Unregisters the MDIO and frees any associate memory for mii bus. 228 */ 229 void axienet_mdio_teardown(struct axienet_local *lp) 230 { 231 mdiobus_unregister(lp->mii_bus); 232 mdiobus_free(lp->mii_bus); 233 lp->mii_bus = NULL; 234 } 235