1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Xilinx Axi Ethernet device driver
4  *
5  * Copyright (c) 2008 Nissin Systems Co., Ltd.,  Yoshio Kashiwagi
6  * Copyright (c) 2005-2008 DLA Systems,  David H. Lynch Jr. <dhlii@dlasys.net>
7  * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8  * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
9  * Copyright (c) 2010 - 2011 PetaLogix
10  * Copyright (c) 2019 - 2022 Calian Advanced Technologies
11  * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
12  *
13  * This is a driver for the Xilinx Axi Ethernet which is used in the Virtex6
14  * and Spartan6.
15  *
16  * TODO:
17  *  - Add Axi Fifo support.
18  *  - Factor out Axi DMA code into separate driver.
19  *  - Test and fix basic multicast filtering.
20  *  - Add support for extended multicast filtering.
21  *  - Test basic VLAN support.
22  *  - Add support for extended VLAN support.
23  */
24 
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/etherdevice.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/of_mdio.h>
31 #include <linux/of_net.h>
32 #include <linux/of_platform.h>
33 #include <linux/of_irq.h>
34 #include <linux/of_address.h>
35 #include <linux/skbuff.h>
36 #include <linux/math64.h>
37 #include <linux/phy.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 
41 #include "xilinx_axienet.h"
42 
43 /* Descriptors defines for Tx and Rx DMA */
44 #define TX_BD_NUM_DEFAULT		128
45 #define RX_BD_NUM_DEFAULT		1024
46 #define TX_BD_NUM_MIN			(MAX_SKB_FRAGS + 1)
47 #define TX_BD_NUM_MAX			4096
48 #define RX_BD_NUM_MAX			4096
49 
50 /* Must be shorter than length of ethtool_drvinfo.driver field to fit */
51 #define DRIVER_NAME		"xaxienet"
52 #define DRIVER_DESCRIPTION	"Xilinx Axi Ethernet driver"
53 #define DRIVER_VERSION		"1.00a"
54 
55 #define AXIENET_REGS_N		40
56 
57 /* Match table for of_platform binding */
58 static const struct of_device_id axienet_of_match[] = {
59 	{ .compatible = "xlnx,axi-ethernet-1.00.a", },
60 	{ .compatible = "xlnx,axi-ethernet-1.01.a", },
61 	{ .compatible = "xlnx,axi-ethernet-2.01.a", },
62 	{},
63 };
64 
65 MODULE_DEVICE_TABLE(of, axienet_of_match);
66 
67 /* Option table for setting up Axi Ethernet hardware options */
68 static struct axienet_option axienet_options[] = {
69 	/* Turn on jumbo packet support for both Rx and Tx */
70 	{
71 		.opt = XAE_OPTION_JUMBO,
72 		.reg = XAE_TC_OFFSET,
73 		.m_or = XAE_TC_JUM_MASK,
74 	}, {
75 		.opt = XAE_OPTION_JUMBO,
76 		.reg = XAE_RCW1_OFFSET,
77 		.m_or = XAE_RCW1_JUM_MASK,
78 	}, { /* Turn on VLAN packet support for both Rx and Tx */
79 		.opt = XAE_OPTION_VLAN,
80 		.reg = XAE_TC_OFFSET,
81 		.m_or = XAE_TC_VLAN_MASK,
82 	}, {
83 		.opt = XAE_OPTION_VLAN,
84 		.reg = XAE_RCW1_OFFSET,
85 		.m_or = XAE_RCW1_VLAN_MASK,
86 	}, { /* Turn on FCS stripping on receive packets */
87 		.opt = XAE_OPTION_FCS_STRIP,
88 		.reg = XAE_RCW1_OFFSET,
89 		.m_or = XAE_RCW1_FCS_MASK,
90 	}, { /* Turn on FCS insertion on transmit packets */
91 		.opt = XAE_OPTION_FCS_INSERT,
92 		.reg = XAE_TC_OFFSET,
93 		.m_or = XAE_TC_FCS_MASK,
94 	}, { /* Turn off length/type field checking on receive packets */
95 		.opt = XAE_OPTION_LENTYPE_ERR,
96 		.reg = XAE_RCW1_OFFSET,
97 		.m_or = XAE_RCW1_LT_DIS_MASK,
98 	}, { /* Turn on Rx flow control */
99 		.opt = XAE_OPTION_FLOW_CONTROL,
100 		.reg = XAE_FCC_OFFSET,
101 		.m_or = XAE_FCC_FCRX_MASK,
102 	}, { /* Turn on Tx flow control */
103 		.opt = XAE_OPTION_FLOW_CONTROL,
104 		.reg = XAE_FCC_OFFSET,
105 		.m_or = XAE_FCC_FCTX_MASK,
106 	}, { /* Turn on promiscuous frame filtering */
107 		.opt = XAE_OPTION_PROMISC,
108 		.reg = XAE_FMI_OFFSET,
109 		.m_or = XAE_FMI_PM_MASK,
110 	}, { /* Enable transmitter */
111 		.opt = XAE_OPTION_TXEN,
112 		.reg = XAE_TC_OFFSET,
113 		.m_or = XAE_TC_TX_MASK,
114 	}, { /* Enable receiver */
115 		.opt = XAE_OPTION_RXEN,
116 		.reg = XAE_RCW1_OFFSET,
117 		.m_or = XAE_RCW1_RX_MASK,
118 	},
119 	{}
120 };
121 
122 /**
123  * axienet_dma_in32 - Memory mapped Axi DMA register read
124  * @lp:		Pointer to axienet local structure
125  * @reg:	Address offset from the base address of the Axi DMA core
126  *
127  * Return: The contents of the Axi DMA register
128  *
129  * This function returns the contents of the corresponding Axi DMA register.
130  */
131 static inline u32 axienet_dma_in32(struct axienet_local *lp, off_t reg)
132 {
133 	return ioread32(lp->dma_regs + reg);
134 }
135 
136 static void desc_set_phys_addr(struct axienet_local *lp, dma_addr_t addr,
137 			       struct axidma_bd *desc)
138 {
139 	desc->phys = lower_32_bits(addr);
140 	if (lp->features & XAE_FEATURE_DMA_64BIT)
141 		desc->phys_msb = upper_32_bits(addr);
142 }
143 
144 static dma_addr_t desc_get_phys_addr(struct axienet_local *lp,
145 				     struct axidma_bd *desc)
146 {
147 	dma_addr_t ret = desc->phys;
148 
149 	if (lp->features & XAE_FEATURE_DMA_64BIT)
150 		ret |= ((dma_addr_t)desc->phys_msb << 16) << 16;
151 
152 	return ret;
153 }
154 
155 /**
156  * axienet_dma_bd_release - Release buffer descriptor rings
157  * @ndev:	Pointer to the net_device structure
158  *
159  * This function is used to release the descriptors allocated in
160  * axienet_dma_bd_init. axienet_dma_bd_release is called when Axi Ethernet
161  * driver stop api is called.
162  */
163 static void axienet_dma_bd_release(struct net_device *ndev)
164 {
165 	int i;
166 	struct axienet_local *lp = netdev_priv(ndev);
167 
168 	/* If we end up here, tx_bd_v must have been DMA allocated. */
169 	dma_free_coherent(lp->dev,
170 			  sizeof(*lp->tx_bd_v) * lp->tx_bd_num,
171 			  lp->tx_bd_v,
172 			  lp->tx_bd_p);
173 
174 	if (!lp->rx_bd_v)
175 		return;
176 
177 	for (i = 0; i < lp->rx_bd_num; i++) {
178 		dma_addr_t phys;
179 
180 		/* A NULL skb means this descriptor has not been initialised
181 		 * at all.
182 		 */
183 		if (!lp->rx_bd_v[i].skb)
184 			break;
185 
186 		dev_kfree_skb(lp->rx_bd_v[i].skb);
187 
188 		/* For each descriptor, we programmed cntrl with the (non-zero)
189 		 * descriptor size, after it had been successfully allocated.
190 		 * So a non-zero value in there means we need to unmap it.
191 		 */
192 		if (lp->rx_bd_v[i].cntrl) {
193 			phys = desc_get_phys_addr(lp, &lp->rx_bd_v[i]);
194 			dma_unmap_single(lp->dev, phys,
195 					 lp->max_frm_size, DMA_FROM_DEVICE);
196 		}
197 	}
198 
199 	dma_free_coherent(lp->dev,
200 			  sizeof(*lp->rx_bd_v) * lp->rx_bd_num,
201 			  lp->rx_bd_v,
202 			  lp->rx_bd_p);
203 }
204 
205 /**
206  * axienet_usec_to_timer - Calculate IRQ delay timer value
207  * @lp:		Pointer to the axienet_local structure
208  * @coalesce_usec: Microseconds to convert into timer value
209  */
210 static u32 axienet_usec_to_timer(struct axienet_local *lp, u32 coalesce_usec)
211 {
212 	u32 result;
213 	u64 clk_rate = 125000000; /* arbitrary guess if no clock rate set */
214 
215 	if (lp->axi_clk)
216 		clk_rate = clk_get_rate(lp->axi_clk);
217 
218 	/* 1 Timeout Interval = 125 * (clock period of SG clock) */
219 	result = DIV64_U64_ROUND_CLOSEST((u64)coalesce_usec * clk_rate,
220 					 (u64)125000000);
221 	if (result > 255)
222 		result = 255;
223 
224 	return result;
225 }
226 
227 /**
228  * axienet_dma_start - Set up DMA registers and start DMA operation
229  * @lp:		Pointer to the axienet_local structure
230  */
231 static void axienet_dma_start(struct axienet_local *lp)
232 {
233 	/* Start updating the Rx channel control register */
234 	lp->rx_dma_cr = (lp->coalesce_count_rx << XAXIDMA_COALESCE_SHIFT) |
235 			XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_ERROR_MASK;
236 	/* Only set interrupt delay timer if not generating an interrupt on
237 	 * the first RX packet. Otherwise leave at 0 to disable delay interrupt.
238 	 */
239 	if (lp->coalesce_count_rx > 1)
240 		lp->rx_dma_cr |= (axienet_usec_to_timer(lp, lp->coalesce_usec_rx)
241 					<< XAXIDMA_DELAY_SHIFT) |
242 				 XAXIDMA_IRQ_DELAY_MASK;
243 	axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp->rx_dma_cr);
244 
245 	/* Start updating the Tx channel control register */
246 	lp->tx_dma_cr = (lp->coalesce_count_tx << XAXIDMA_COALESCE_SHIFT) |
247 			XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_ERROR_MASK;
248 	/* Only set interrupt delay timer if not generating an interrupt on
249 	 * the first TX packet. Otherwise leave at 0 to disable delay interrupt.
250 	 */
251 	if (lp->coalesce_count_tx > 1)
252 		lp->tx_dma_cr |= (axienet_usec_to_timer(lp, lp->coalesce_usec_tx)
253 					<< XAXIDMA_DELAY_SHIFT) |
254 				 XAXIDMA_IRQ_DELAY_MASK;
255 	axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, lp->tx_dma_cr);
256 
257 	/* Populate the tail pointer and bring the Rx Axi DMA engine out of
258 	 * halted state. This will make the Rx side ready for reception.
259 	 */
260 	axienet_dma_out_addr(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
261 	lp->rx_dma_cr |= XAXIDMA_CR_RUNSTOP_MASK;
262 	axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp->rx_dma_cr);
263 	axienet_dma_out_addr(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
264 			     (sizeof(*lp->rx_bd_v) * (lp->rx_bd_num - 1)));
265 
266 	/* Write to the RS (Run-stop) bit in the Tx channel control register.
267 	 * Tx channel is now ready to run. But only after we write to the
268 	 * tail pointer register that the Tx channel will start transmitting.
269 	 */
270 	axienet_dma_out_addr(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
271 	lp->tx_dma_cr |= XAXIDMA_CR_RUNSTOP_MASK;
272 	axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, lp->tx_dma_cr);
273 }
274 
275 /**
276  * axienet_dma_bd_init - Setup buffer descriptor rings for Axi DMA
277  * @ndev:	Pointer to the net_device structure
278  *
279  * Return: 0, on success -ENOMEM, on failure
280  *
281  * This function is called to initialize the Rx and Tx DMA descriptor
282  * rings. This initializes the descriptors with required default values
283  * and is called when Axi Ethernet driver reset is called.
284  */
285 static int axienet_dma_bd_init(struct net_device *ndev)
286 {
287 	int i;
288 	struct sk_buff *skb;
289 	struct axienet_local *lp = netdev_priv(ndev);
290 
291 	/* Reset the indexes which are used for accessing the BDs */
292 	lp->tx_bd_ci = 0;
293 	lp->tx_bd_tail = 0;
294 	lp->rx_bd_ci = 0;
295 
296 	/* Allocate the Tx and Rx buffer descriptors. */
297 	lp->tx_bd_v = dma_alloc_coherent(lp->dev,
298 					 sizeof(*lp->tx_bd_v) * lp->tx_bd_num,
299 					 &lp->tx_bd_p, GFP_KERNEL);
300 	if (!lp->tx_bd_v)
301 		return -ENOMEM;
302 
303 	lp->rx_bd_v = dma_alloc_coherent(lp->dev,
304 					 sizeof(*lp->rx_bd_v) * lp->rx_bd_num,
305 					 &lp->rx_bd_p, GFP_KERNEL);
306 	if (!lp->rx_bd_v)
307 		goto out;
308 
309 	for (i = 0; i < lp->tx_bd_num; i++) {
310 		dma_addr_t addr = lp->tx_bd_p +
311 				  sizeof(*lp->tx_bd_v) *
312 				  ((i + 1) % lp->tx_bd_num);
313 
314 		lp->tx_bd_v[i].next = lower_32_bits(addr);
315 		if (lp->features & XAE_FEATURE_DMA_64BIT)
316 			lp->tx_bd_v[i].next_msb = upper_32_bits(addr);
317 	}
318 
319 	for (i = 0; i < lp->rx_bd_num; i++) {
320 		dma_addr_t addr;
321 
322 		addr = lp->rx_bd_p + sizeof(*lp->rx_bd_v) *
323 			((i + 1) % lp->rx_bd_num);
324 		lp->rx_bd_v[i].next = lower_32_bits(addr);
325 		if (lp->features & XAE_FEATURE_DMA_64BIT)
326 			lp->rx_bd_v[i].next_msb = upper_32_bits(addr);
327 
328 		skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size);
329 		if (!skb)
330 			goto out;
331 
332 		lp->rx_bd_v[i].skb = skb;
333 		addr = dma_map_single(lp->dev, skb->data,
334 				      lp->max_frm_size, DMA_FROM_DEVICE);
335 		if (dma_mapping_error(lp->dev, addr)) {
336 			netdev_err(ndev, "DMA mapping error\n");
337 			goto out;
338 		}
339 		desc_set_phys_addr(lp, addr, &lp->rx_bd_v[i]);
340 
341 		lp->rx_bd_v[i].cntrl = lp->max_frm_size;
342 	}
343 
344 	axienet_dma_start(lp);
345 
346 	return 0;
347 out:
348 	axienet_dma_bd_release(ndev);
349 	return -ENOMEM;
350 }
351 
352 /**
353  * axienet_set_mac_address - Write the MAC address
354  * @ndev:	Pointer to the net_device structure
355  * @address:	6 byte Address to be written as MAC address
356  *
357  * This function is called to initialize the MAC address of the Axi Ethernet
358  * core. It writes to the UAW0 and UAW1 registers of the core.
359  */
360 static void axienet_set_mac_address(struct net_device *ndev,
361 				    const void *address)
362 {
363 	struct axienet_local *lp = netdev_priv(ndev);
364 
365 	if (address)
366 		eth_hw_addr_set(ndev, address);
367 	if (!is_valid_ether_addr(ndev->dev_addr))
368 		eth_hw_addr_random(ndev);
369 
370 	/* Set up unicast MAC address filter set its mac address */
371 	axienet_iow(lp, XAE_UAW0_OFFSET,
372 		    (ndev->dev_addr[0]) |
373 		    (ndev->dev_addr[1] << 8) |
374 		    (ndev->dev_addr[2] << 16) |
375 		    (ndev->dev_addr[3] << 24));
376 	axienet_iow(lp, XAE_UAW1_OFFSET,
377 		    (((axienet_ior(lp, XAE_UAW1_OFFSET)) &
378 		      ~XAE_UAW1_UNICASTADDR_MASK) |
379 		     (ndev->dev_addr[4] |
380 		     (ndev->dev_addr[5] << 8))));
381 }
382 
383 /**
384  * netdev_set_mac_address - Write the MAC address (from outside the driver)
385  * @ndev:	Pointer to the net_device structure
386  * @p:		6 byte Address to be written as MAC address
387  *
388  * Return: 0 for all conditions. Presently, there is no failure case.
389  *
390  * This function is called to initialize the MAC address of the Axi Ethernet
391  * core. It calls the core specific axienet_set_mac_address. This is the
392  * function that goes into net_device_ops structure entry ndo_set_mac_address.
393  */
394 static int netdev_set_mac_address(struct net_device *ndev, void *p)
395 {
396 	struct sockaddr *addr = p;
397 	axienet_set_mac_address(ndev, addr->sa_data);
398 	return 0;
399 }
400 
401 /**
402  * axienet_set_multicast_list - Prepare the multicast table
403  * @ndev:	Pointer to the net_device structure
404  *
405  * This function is called to initialize the multicast table during
406  * initialization. The Axi Ethernet basic multicast support has a four-entry
407  * multicast table which is initialized here. Additionally this function
408  * goes into the net_device_ops structure entry ndo_set_multicast_list. This
409  * means whenever the multicast table entries need to be updated this
410  * function gets called.
411  */
412 static void axienet_set_multicast_list(struct net_device *ndev)
413 {
414 	int i;
415 	u32 reg, af0reg, af1reg;
416 	struct axienet_local *lp = netdev_priv(ndev);
417 
418 	if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
419 	    netdev_mc_count(ndev) > XAE_MULTICAST_CAM_TABLE_NUM) {
420 		/* We must make the kernel realize we had to move into
421 		 * promiscuous mode. If it was a promiscuous mode request
422 		 * the flag is already set. If not we set it.
423 		 */
424 		ndev->flags |= IFF_PROMISC;
425 		reg = axienet_ior(lp, XAE_FMI_OFFSET);
426 		reg |= XAE_FMI_PM_MASK;
427 		axienet_iow(lp, XAE_FMI_OFFSET, reg);
428 		dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
429 	} else if (!netdev_mc_empty(ndev)) {
430 		struct netdev_hw_addr *ha;
431 
432 		i = 0;
433 		netdev_for_each_mc_addr(ha, ndev) {
434 			if (i >= XAE_MULTICAST_CAM_TABLE_NUM)
435 				break;
436 
437 			af0reg = (ha->addr[0]);
438 			af0reg |= (ha->addr[1] << 8);
439 			af0reg |= (ha->addr[2] << 16);
440 			af0reg |= (ha->addr[3] << 24);
441 
442 			af1reg = (ha->addr[4]);
443 			af1reg |= (ha->addr[5] << 8);
444 
445 			reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00;
446 			reg |= i;
447 
448 			axienet_iow(lp, XAE_FMI_OFFSET, reg);
449 			axienet_iow(lp, XAE_AF0_OFFSET, af0reg);
450 			axienet_iow(lp, XAE_AF1_OFFSET, af1reg);
451 			i++;
452 		}
453 	} else {
454 		reg = axienet_ior(lp, XAE_FMI_OFFSET);
455 		reg &= ~XAE_FMI_PM_MASK;
456 
457 		axienet_iow(lp, XAE_FMI_OFFSET, reg);
458 
459 		for (i = 0; i < XAE_MULTICAST_CAM_TABLE_NUM; i++) {
460 			reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00;
461 			reg |= i;
462 
463 			axienet_iow(lp, XAE_FMI_OFFSET, reg);
464 			axienet_iow(lp, XAE_AF0_OFFSET, 0);
465 			axienet_iow(lp, XAE_AF1_OFFSET, 0);
466 		}
467 
468 		dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
469 	}
470 }
471 
472 /**
473  * axienet_setoptions - Set an Axi Ethernet option
474  * @ndev:	Pointer to the net_device structure
475  * @options:	Option to be enabled/disabled
476  *
477  * The Axi Ethernet core has multiple features which can be selectively turned
478  * on or off. The typical options could be jumbo frame option, basic VLAN
479  * option, promiscuous mode option etc. This function is used to set or clear
480  * these options in the Axi Ethernet hardware. This is done through
481  * axienet_option structure .
482  */
483 static void axienet_setoptions(struct net_device *ndev, u32 options)
484 {
485 	int reg;
486 	struct axienet_local *lp = netdev_priv(ndev);
487 	struct axienet_option *tp = &axienet_options[0];
488 
489 	while (tp->opt) {
490 		reg = ((axienet_ior(lp, tp->reg)) & ~(tp->m_or));
491 		if (options & tp->opt)
492 			reg |= tp->m_or;
493 		axienet_iow(lp, tp->reg, reg);
494 		tp++;
495 	}
496 
497 	lp->options |= options;
498 }
499 
500 static int __axienet_device_reset(struct axienet_local *lp)
501 {
502 	u32 value;
503 	int ret;
504 
505 	/* Reset Axi DMA. This would reset Axi Ethernet core as well. The reset
506 	 * process of Axi DMA takes a while to complete as all pending
507 	 * commands/transfers will be flushed or completed during this
508 	 * reset process.
509 	 * Note that even though both TX and RX have their own reset register,
510 	 * they both reset the entire DMA core, so only one needs to be used.
511 	 */
512 	axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, XAXIDMA_CR_RESET_MASK);
513 	ret = read_poll_timeout(axienet_dma_in32, value,
514 				!(value & XAXIDMA_CR_RESET_MASK),
515 				DELAY_OF_ONE_MILLISEC, 50000, false, lp,
516 				XAXIDMA_TX_CR_OFFSET);
517 	if (ret) {
518 		dev_err(lp->dev, "%s: DMA reset timeout!\n", __func__);
519 		return ret;
520 	}
521 
522 	/* Wait for PhyRstCmplt bit to be set, indicating the PHY reset has finished */
523 	ret = read_poll_timeout(axienet_ior, value,
524 				value & XAE_INT_PHYRSTCMPLT_MASK,
525 				DELAY_OF_ONE_MILLISEC, 50000, false, lp,
526 				XAE_IS_OFFSET);
527 	if (ret) {
528 		dev_err(lp->dev, "%s: timeout waiting for PhyRstCmplt\n", __func__);
529 		return ret;
530 	}
531 
532 	return 0;
533 }
534 
535 /**
536  * axienet_dma_stop - Stop DMA operation
537  * @lp:		Pointer to the axienet_local structure
538  */
539 static void axienet_dma_stop(struct axienet_local *lp)
540 {
541 	int count;
542 	u32 cr, sr;
543 
544 	cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
545 	cr &= ~(XAXIDMA_CR_RUNSTOP_MASK | XAXIDMA_IRQ_ALL_MASK);
546 	axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
547 	synchronize_irq(lp->rx_irq);
548 
549 	cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
550 	cr &= ~(XAXIDMA_CR_RUNSTOP_MASK | XAXIDMA_IRQ_ALL_MASK);
551 	axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
552 	synchronize_irq(lp->tx_irq);
553 
554 	/* Give DMAs a chance to halt gracefully */
555 	sr = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);
556 	for (count = 0; !(sr & XAXIDMA_SR_HALT_MASK) && count < 5; ++count) {
557 		msleep(20);
558 		sr = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);
559 	}
560 
561 	sr = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);
562 	for (count = 0; !(sr & XAXIDMA_SR_HALT_MASK) && count < 5; ++count) {
563 		msleep(20);
564 		sr = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);
565 	}
566 
567 	/* Do a reset to ensure DMA is really stopped */
568 	axienet_lock_mii(lp);
569 	__axienet_device_reset(lp);
570 	axienet_unlock_mii(lp);
571 }
572 
573 /**
574  * axienet_device_reset - Reset and initialize the Axi Ethernet hardware.
575  * @ndev:	Pointer to the net_device structure
576  *
577  * This function is called to reset and initialize the Axi Ethernet core. This
578  * is typically called during initialization. It does a reset of the Axi DMA
579  * Rx/Tx channels and initializes the Axi DMA BDs. Since Axi DMA reset lines
580  * are connected to Axi Ethernet reset lines, this in turn resets the Axi
581  * Ethernet core. No separate hardware reset is done for the Axi Ethernet
582  * core.
583  * Returns 0 on success or a negative error number otherwise.
584  */
585 static int axienet_device_reset(struct net_device *ndev)
586 {
587 	u32 axienet_status;
588 	struct axienet_local *lp = netdev_priv(ndev);
589 	int ret;
590 
591 	ret = __axienet_device_reset(lp);
592 	if (ret)
593 		return ret;
594 
595 	lp->max_frm_size = XAE_MAX_VLAN_FRAME_SIZE;
596 	lp->options |= XAE_OPTION_VLAN;
597 	lp->options &= (~XAE_OPTION_JUMBO);
598 
599 	if ((ndev->mtu > XAE_MTU) &&
600 	    (ndev->mtu <= XAE_JUMBO_MTU)) {
601 		lp->max_frm_size = ndev->mtu + VLAN_ETH_HLEN +
602 					XAE_TRL_SIZE;
603 
604 		if (lp->max_frm_size <= lp->rxmem)
605 			lp->options |= XAE_OPTION_JUMBO;
606 	}
607 
608 	ret = axienet_dma_bd_init(ndev);
609 	if (ret) {
610 		netdev_err(ndev, "%s: descriptor allocation failed\n",
611 			   __func__);
612 		return ret;
613 	}
614 
615 	axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);
616 	axienet_status &= ~XAE_RCW1_RX_MASK;
617 	axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
618 
619 	axienet_status = axienet_ior(lp, XAE_IP_OFFSET);
620 	if (axienet_status & XAE_INT_RXRJECT_MASK)
621 		axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
622 	axienet_iow(lp, XAE_IE_OFFSET, lp->eth_irq > 0 ?
623 		    XAE_INT_RECV_ERROR_MASK : 0);
624 
625 	axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
626 
627 	/* Sync default options with HW but leave receiver and
628 	 * transmitter disabled.
629 	 */
630 	axienet_setoptions(ndev, lp->options &
631 			   ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
632 	axienet_set_mac_address(ndev, NULL);
633 	axienet_set_multicast_list(ndev);
634 	axienet_setoptions(ndev, lp->options);
635 
636 	netif_trans_update(ndev);
637 
638 	return 0;
639 }
640 
641 /**
642  * axienet_free_tx_chain - Clean up a series of linked TX descriptors.
643  * @lp:		Pointer to the axienet_local structure
644  * @first_bd:	Index of first descriptor to clean up
645  * @nr_bds:	Max number of descriptors to clean up
646  * @force:	Whether to clean descriptors even if not complete
647  * @sizep:	Pointer to a u32 filled with the total sum of all bytes
648  *		in all cleaned-up descriptors. Ignored if NULL.
649  * @budget:	NAPI budget (use 0 when not called from NAPI poll)
650  *
651  * Would either be called after a successful transmit operation, or after
652  * there was an error when setting up the chain.
653  * Returns the number of descriptors handled.
654  */
655 static int axienet_free_tx_chain(struct axienet_local *lp, u32 first_bd,
656 				 int nr_bds, bool force, u32 *sizep, int budget)
657 {
658 	struct axidma_bd *cur_p;
659 	unsigned int status;
660 	dma_addr_t phys;
661 	int i;
662 
663 	for (i = 0; i < nr_bds; i++) {
664 		cur_p = &lp->tx_bd_v[(first_bd + i) % lp->tx_bd_num];
665 		status = cur_p->status;
666 
667 		/* If force is not specified, clean up only descriptors
668 		 * that have been completed by the MAC.
669 		 */
670 		if (!force && !(status & XAXIDMA_BD_STS_COMPLETE_MASK))
671 			break;
672 
673 		/* Ensure we see complete descriptor update */
674 		dma_rmb();
675 		phys = desc_get_phys_addr(lp, cur_p);
676 		dma_unmap_single(lp->dev, phys,
677 				 (cur_p->cntrl & XAXIDMA_BD_CTRL_LENGTH_MASK),
678 				 DMA_TO_DEVICE);
679 
680 		if (cur_p->skb && (status & XAXIDMA_BD_STS_COMPLETE_MASK))
681 			napi_consume_skb(cur_p->skb, budget);
682 
683 		cur_p->app0 = 0;
684 		cur_p->app1 = 0;
685 		cur_p->app2 = 0;
686 		cur_p->app4 = 0;
687 		cur_p->skb = NULL;
688 		/* ensure our transmit path and device don't prematurely see status cleared */
689 		wmb();
690 		cur_p->cntrl = 0;
691 		cur_p->status = 0;
692 
693 		if (sizep)
694 			*sizep += status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
695 	}
696 
697 	return i;
698 }
699 
700 /**
701  * axienet_check_tx_bd_space - Checks if a BD/group of BDs are currently busy
702  * @lp:		Pointer to the axienet_local structure
703  * @num_frag:	The number of BDs to check for
704  *
705  * Return: 0, on success
706  *	    NETDEV_TX_BUSY, if any of the descriptors are not free
707  *
708  * This function is invoked before BDs are allocated and transmission starts.
709  * This function returns 0 if a BD or group of BDs can be allocated for
710  * transmission. If the BD or any of the BDs are not free the function
711  * returns a busy status.
712  */
713 static inline int axienet_check_tx_bd_space(struct axienet_local *lp,
714 					    int num_frag)
715 {
716 	struct axidma_bd *cur_p;
717 
718 	/* Ensure we see all descriptor updates from device or TX polling */
719 	rmb();
720 	cur_p = &lp->tx_bd_v[(READ_ONCE(lp->tx_bd_tail) + num_frag) %
721 			     lp->tx_bd_num];
722 	if (cur_p->cntrl)
723 		return NETDEV_TX_BUSY;
724 	return 0;
725 }
726 
727 /**
728  * axienet_tx_poll - Invoked once a transmit is completed by the
729  * Axi DMA Tx channel.
730  * @napi:	Pointer to NAPI structure.
731  * @budget:	Max number of TX packets to process.
732  *
733  * Return: Number of TX packets processed.
734  *
735  * This function is invoked from the NAPI processing to notify the completion
736  * of transmit operation. It clears fields in the corresponding Tx BDs and
737  * unmaps the corresponding buffer so that CPU can regain ownership of the
738  * buffer. It finally invokes "netif_wake_queue" to restart transmission if
739  * required.
740  */
741 static int axienet_tx_poll(struct napi_struct *napi, int budget)
742 {
743 	struct axienet_local *lp = container_of(napi, struct axienet_local, napi_tx);
744 	struct net_device *ndev = lp->ndev;
745 	u32 size = 0;
746 	int packets;
747 
748 	packets = axienet_free_tx_chain(lp, lp->tx_bd_ci, budget, false, &size, budget);
749 
750 	if (packets) {
751 		lp->tx_bd_ci += packets;
752 		if (lp->tx_bd_ci >= lp->tx_bd_num)
753 			lp->tx_bd_ci %= lp->tx_bd_num;
754 
755 		u64_stats_update_begin(&lp->tx_stat_sync);
756 		u64_stats_add(&lp->tx_packets, packets);
757 		u64_stats_add(&lp->tx_bytes, size);
758 		u64_stats_update_end(&lp->tx_stat_sync);
759 
760 		/* Matches barrier in axienet_start_xmit */
761 		smp_mb();
762 
763 		if (!axienet_check_tx_bd_space(lp, MAX_SKB_FRAGS + 1))
764 			netif_wake_queue(ndev);
765 	}
766 
767 	if (packets < budget && napi_complete_done(napi, packets)) {
768 		/* Re-enable TX completion interrupts. This should
769 		 * cause an immediate interrupt if any TX packets are
770 		 * already pending.
771 		 */
772 		axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, lp->tx_dma_cr);
773 	}
774 	return packets;
775 }
776 
777 /**
778  * axienet_start_xmit - Starts the transmission.
779  * @skb:	sk_buff pointer that contains data to be Txed.
780  * @ndev:	Pointer to net_device structure.
781  *
782  * Return: NETDEV_TX_OK, on success
783  *	    NETDEV_TX_BUSY, if any of the descriptors are not free
784  *
785  * This function is invoked from upper layers to initiate transmission. The
786  * function uses the next available free BDs and populates their fields to
787  * start the transmission. Additionally if checksum offloading is supported,
788  * it populates AXI Stream Control fields with appropriate values.
789  */
790 static netdev_tx_t
791 axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
792 {
793 	u32 ii;
794 	u32 num_frag;
795 	u32 csum_start_off;
796 	u32 csum_index_off;
797 	skb_frag_t *frag;
798 	dma_addr_t tail_p, phys;
799 	u32 orig_tail_ptr, new_tail_ptr;
800 	struct axienet_local *lp = netdev_priv(ndev);
801 	struct axidma_bd *cur_p;
802 
803 	orig_tail_ptr = lp->tx_bd_tail;
804 	new_tail_ptr = orig_tail_ptr;
805 
806 	num_frag = skb_shinfo(skb)->nr_frags;
807 	cur_p = &lp->tx_bd_v[orig_tail_ptr];
808 
809 	if (axienet_check_tx_bd_space(lp, num_frag + 1)) {
810 		/* Should not happen as last start_xmit call should have
811 		 * checked for sufficient space and queue should only be
812 		 * woken when sufficient space is available.
813 		 */
814 		netif_stop_queue(ndev);
815 		if (net_ratelimit())
816 			netdev_warn(ndev, "TX ring unexpectedly full\n");
817 		return NETDEV_TX_BUSY;
818 	}
819 
820 	if (skb->ip_summed == CHECKSUM_PARTIAL) {
821 		if (lp->features & XAE_FEATURE_FULL_TX_CSUM) {
822 			/* Tx Full Checksum Offload Enabled */
823 			cur_p->app0 |= 2;
824 		} else if (lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) {
825 			csum_start_off = skb_transport_offset(skb);
826 			csum_index_off = csum_start_off + skb->csum_offset;
827 			/* Tx Partial Checksum Offload Enabled */
828 			cur_p->app0 |= 1;
829 			cur_p->app1 = (csum_start_off << 16) | csum_index_off;
830 		}
831 	} else if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
832 		cur_p->app0 |= 2; /* Tx Full Checksum Offload Enabled */
833 	}
834 
835 	phys = dma_map_single(lp->dev, skb->data,
836 			      skb_headlen(skb), DMA_TO_DEVICE);
837 	if (unlikely(dma_mapping_error(lp->dev, phys))) {
838 		if (net_ratelimit())
839 			netdev_err(ndev, "TX DMA mapping error\n");
840 		ndev->stats.tx_dropped++;
841 		return NETDEV_TX_OK;
842 	}
843 	desc_set_phys_addr(lp, phys, cur_p);
844 	cur_p->cntrl = skb_headlen(skb) | XAXIDMA_BD_CTRL_TXSOF_MASK;
845 
846 	for (ii = 0; ii < num_frag; ii++) {
847 		if (++new_tail_ptr >= lp->tx_bd_num)
848 			new_tail_ptr = 0;
849 		cur_p = &lp->tx_bd_v[new_tail_ptr];
850 		frag = &skb_shinfo(skb)->frags[ii];
851 		phys = dma_map_single(lp->dev,
852 				      skb_frag_address(frag),
853 				      skb_frag_size(frag),
854 				      DMA_TO_DEVICE);
855 		if (unlikely(dma_mapping_error(lp->dev, phys))) {
856 			if (net_ratelimit())
857 				netdev_err(ndev, "TX DMA mapping error\n");
858 			ndev->stats.tx_dropped++;
859 			axienet_free_tx_chain(lp, orig_tail_ptr, ii + 1,
860 					      true, NULL, 0);
861 			return NETDEV_TX_OK;
862 		}
863 		desc_set_phys_addr(lp, phys, cur_p);
864 		cur_p->cntrl = skb_frag_size(frag);
865 	}
866 
867 	cur_p->cntrl |= XAXIDMA_BD_CTRL_TXEOF_MASK;
868 	cur_p->skb = skb;
869 
870 	tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * new_tail_ptr;
871 	if (++new_tail_ptr >= lp->tx_bd_num)
872 		new_tail_ptr = 0;
873 	WRITE_ONCE(lp->tx_bd_tail, new_tail_ptr);
874 
875 	/* Start the transfer */
876 	axienet_dma_out_addr(lp, XAXIDMA_TX_TDESC_OFFSET, tail_p);
877 
878 	/* Stop queue if next transmit may not have space */
879 	if (axienet_check_tx_bd_space(lp, MAX_SKB_FRAGS + 1)) {
880 		netif_stop_queue(ndev);
881 
882 		/* Matches barrier in axienet_tx_poll */
883 		smp_mb();
884 
885 		/* Space might have just been freed - check again */
886 		if (!axienet_check_tx_bd_space(lp, MAX_SKB_FRAGS + 1))
887 			netif_wake_queue(ndev);
888 	}
889 
890 	return NETDEV_TX_OK;
891 }
892 
893 /**
894  * axienet_rx_poll - Triggered by RX ISR to complete the BD processing.
895  * @napi:	Pointer to NAPI structure.
896  * @budget:	Max number of RX packets to process.
897  *
898  * Return: Number of RX packets processed.
899  */
900 static int axienet_rx_poll(struct napi_struct *napi, int budget)
901 {
902 	u32 length;
903 	u32 csumstatus;
904 	u32 size = 0;
905 	int packets = 0;
906 	dma_addr_t tail_p = 0;
907 	struct axidma_bd *cur_p;
908 	struct sk_buff *skb, *new_skb;
909 	struct axienet_local *lp = container_of(napi, struct axienet_local, napi_rx);
910 
911 	cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
912 
913 	while (packets < budget && (cur_p->status & XAXIDMA_BD_STS_COMPLETE_MASK)) {
914 		dma_addr_t phys;
915 
916 		/* Ensure we see complete descriptor update */
917 		dma_rmb();
918 
919 		skb = cur_p->skb;
920 		cur_p->skb = NULL;
921 
922 		/* skb could be NULL if a previous pass already received the
923 		 * packet for this slot in the ring, but failed to refill it
924 		 * with a newly allocated buffer. In this case, don't try to
925 		 * receive it again.
926 		 */
927 		if (likely(skb)) {
928 			length = cur_p->app4 & 0x0000FFFF;
929 
930 			phys = desc_get_phys_addr(lp, cur_p);
931 			dma_unmap_single(lp->dev, phys, lp->max_frm_size,
932 					 DMA_FROM_DEVICE);
933 
934 			skb_put(skb, length);
935 			skb->protocol = eth_type_trans(skb, lp->ndev);
936 			/*skb_checksum_none_assert(skb);*/
937 			skb->ip_summed = CHECKSUM_NONE;
938 
939 			/* if we're doing Rx csum offload, set it up */
940 			if (lp->features & XAE_FEATURE_FULL_RX_CSUM) {
941 				csumstatus = (cur_p->app2 &
942 					      XAE_FULL_CSUM_STATUS_MASK) >> 3;
943 				if (csumstatus == XAE_IP_TCP_CSUM_VALIDATED ||
944 				    csumstatus == XAE_IP_UDP_CSUM_VALIDATED) {
945 					skb->ip_summed = CHECKSUM_UNNECESSARY;
946 				}
947 			} else if ((lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) != 0 &&
948 				   skb->protocol == htons(ETH_P_IP) &&
949 				   skb->len > 64) {
950 				skb->csum = be32_to_cpu(cur_p->app3 & 0xFFFF);
951 				skb->ip_summed = CHECKSUM_COMPLETE;
952 			}
953 
954 			napi_gro_receive(napi, skb);
955 
956 			size += length;
957 			packets++;
958 		}
959 
960 		new_skb = napi_alloc_skb(napi, lp->max_frm_size);
961 		if (!new_skb)
962 			break;
963 
964 		phys = dma_map_single(lp->dev, new_skb->data,
965 				      lp->max_frm_size,
966 				      DMA_FROM_DEVICE);
967 		if (unlikely(dma_mapping_error(lp->dev, phys))) {
968 			if (net_ratelimit())
969 				netdev_err(lp->ndev, "RX DMA mapping error\n");
970 			dev_kfree_skb(new_skb);
971 			break;
972 		}
973 		desc_set_phys_addr(lp, phys, cur_p);
974 
975 		cur_p->cntrl = lp->max_frm_size;
976 		cur_p->status = 0;
977 		cur_p->skb = new_skb;
978 
979 		/* Only update tail_p to mark this slot as usable after it has
980 		 * been successfully refilled.
981 		 */
982 		tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
983 
984 		if (++lp->rx_bd_ci >= lp->rx_bd_num)
985 			lp->rx_bd_ci = 0;
986 		cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
987 	}
988 
989 	u64_stats_update_begin(&lp->rx_stat_sync);
990 	u64_stats_add(&lp->rx_packets, packets);
991 	u64_stats_add(&lp->rx_bytes, size);
992 	u64_stats_update_end(&lp->rx_stat_sync);
993 
994 	if (tail_p)
995 		axienet_dma_out_addr(lp, XAXIDMA_RX_TDESC_OFFSET, tail_p);
996 
997 	if (packets < budget && napi_complete_done(napi, packets)) {
998 		/* Re-enable RX completion interrupts. This should
999 		 * cause an immediate interrupt if any RX packets are
1000 		 * already pending.
1001 		 */
1002 		axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp->rx_dma_cr);
1003 	}
1004 	return packets;
1005 }
1006 
1007 /**
1008  * axienet_tx_irq - Tx Done Isr.
1009  * @irq:	irq number
1010  * @_ndev:	net_device pointer
1011  *
1012  * Return: IRQ_HANDLED if device generated a TX interrupt, IRQ_NONE otherwise.
1013  *
1014  * This is the Axi DMA Tx done Isr. It invokes NAPI polling to complete the
1015  * TX BD processing.
1016  */
1017 static irqreturn_t axienet_tx_irq(int irq, void *_ndev)
1018 {
1019 	unsigned int status;
1020 	struct net_device *ndev = _ndev;
1021 	struct axienet_local *lp = netdev_priv(ndev);
1022 
1023 	status = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);
1024 
1025 	if (!(status & XAXIDMA_IRQ_ALL_MASK))
1026 		return IRQ_NONE;
1027 
1028 	axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status);
1029 
1030 	if (unlikely(status & XAXIDMA_IRQ_ERROR_MASK)) {
1031 		netdev_err(ndev, "DMA Tx error 0x%x\n", status);
1032 		netdev_err(ndev, "Current BD is at: 0x%x%08x\n",
1033 			   (lp->tx_bd_v[lp->tx_bd_ci]).phys_msb,
1034 			   (lp->tx_bd_v[lp->tx_bd_ci]).phys);
1035 		schedule_work(&lp->dma_err_task);
1036 	} else {
1037 		/* Disable further TX completion interrupts and schedule
1038 		 * NAPI to handle the completions.
1039 		 */
1040 		u32 cr = lp->tx_dma_cr;
1041 
1042 		cr &= ~(XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK);
1043 		axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
1044 
1045 		napi_schedule(&lp->napi_tx);
1046 	}
1047 
1048 	return IRQ_HANDLED;
1049 }
1050 
1051 /**
1052  * axienet_rx_irq - Rx Isr.
1053  * @irq:	irq number
1054  * @_ndev:	net_device pointer
1055  *
1056  * Return: IRQ_HANDLED if device generated a RX interrupt, IRQ_NONE otherwise.
1057  *
1058  * This is the Axi DMA Rx Isr. It invokes NAPI polling to complete the RX BD
1059  * processing.
1060  */
1061 static irqreturn_t axienet_rx_irq(int irq, void *_ndev)
1062 {
1063 	unsigned int status;
1064 	struct net_device *ndev = _ndev;
1065 	struct axienet_local *lp = netdev_priv(ndev);
1066 
1067 	status = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);
1068 
1069 	if (!(status & XAXIDMA_IRQ_ALL_MASK))
1070 		return IRQ_NONE;
1071 
1072 	axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status);
1073 
1074 	if (unlikely(status & XAXIDMA_IRQ_ERROR_MASK)) {
1075 		netdev_err(ndev, "DMA Rx error 0x%x\n", status);
1076 		netdev_err(ndev, "Current BD is at: 0x%x%08x\n",
1077 			   (lp->rx_bd_v[lp->rx_bd_ci]).phys_msb,
1078 			   (lp->rx_bd_v[lp->rx_bd_ci]).phys);
1079 		schedule_work(&lp->dma_err_task);
1080 	} else {
1081 		/* Disable further RX completion interrupts and schedule
1082 		 * NAPI receive.
1083 		 */
1084 		u32 cr = lp->rx_dma_cr;
1085 
1086 		cr &= ~(XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK);
1087 		axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
1088 
1089 		napi_schedule(&lp->napi_rx);
1090 	}
1091 
1092 	return IRQ_HANDLED;
1093 }
1094 
1095 /**
1096  * axienet_eth_irq - Ethernet core Isr.
1097  * @irq:	irq number
1098  * @_ndev:	net_device pointer
1099  *
1100  * Return: IRQ_HANDLED if device generated a core interrupt, IRQ_NONE otherwise.
1101  *
1102  * Handle miscellaneous conditions indicated by Ethernet core IRQ.
1103  */
1104 static irqreturn_t axienet_eth_irq(int irq, void *_ndev)
1105 {
1106 	struct net_device *ndev = _ndev;
1107 	struct axienet_local *lp = netdev_priv(ndev);
1108 	unsigned int pending;
1109 
1110 	pending = axienet_ior(lp, XAE_IP_OFFSET);
1111 	if (!pending)
1112 		return IRQ_NONE;
1113 
1114 	if (pending & XAE_INT_RXFIFOOVR_MASK)
1115 		ndev->stats.rx_missed_errors++;
1116 
1117 	if (pending & XAE_INT_RXRJECT_MASK)
1118 		ndev->stats.rx_frame_errors++;
1119 
1120 	axienet_iow(lp, XAE_IS_OFFSET, pending);
1121 	return IRQ_HANDLED;
1122 }
1123 
1124 static void axienet_dma_err_handler(struct work_struct *work);
1125 
1126 /**
1127  * axienet_open - Driver open routine.
1128  * @ndev:	Pointer to net_device structure
1129  *
1130  * Return: 0, on success.
1131  *	    non-zero error value on failure
1132  *
1133  * This is the driver open routine. It calls phylink_start to start the
1134  * PHY device.
1135  * It also allocates interrupt service routines, enables the interrupt lines
1136  * and ISR handling. Axi Ethernet core is reset through Axi DMA core. Buffer
1137  * descriptors are initialized.
1138  */
1139 static int axienet_open(struct net_device *ndev)
1140 {
1141 	int ret;
1142 	struct axienet_local *lp = netdev_priv(ndev);
1143 
1144 	dev_dbg(&ndev->dev, "axienet_open()\n");
1145 
1146 	/* When we do an Axi Ethernet reset, it resets the complete core
1147 	 * including the MDIO. MDIO must be disabled before resetting.
1148 	 * Hold MDIO bus lock to avoid MDIO accesses during the reset.
1149 	 */
1150 	axienet_lock_mii(lp);
1151 	ret = axienet_device_reset(ndev);
1152 	axienet_unlock_mii(lp);
1153 
1154 	ret = phylink_of_phy_connect(lp->phylink, lp->dev->of_node, 0);
1155 	if (ret) {
1156 		dev_err(lp->dev, "phylink_of_phy_connect() failed: %d\n", ret);
1157 		return ret;
1158 	}
1159 
1160 	phylink_start(lp->phylink);
1161 
1162 	/* Enable worker thread for Axi DMA error handling */
1163 	INIT_WORK(&lp->dma_err_task, axienet_dma_err_handler);
1164 
1165 	napi_enable(&lp->napi_rx);
1166 	napi_enable(&lp->napi_tx);
1167 
1168 	/* Enable interrupts for Axi DMA Tx */
1169 	ret = request_irq(lp->tx_irq, axienet_tx_irq, IRQF_SHARED,
1170 			  ndev->name, ndev);
1171 	if (ret)
1172 		goto err_tx_irq;
1173 	/* Enable interrupts for Axi DMA Rx */
1174 	ret = request_irq(lp->rx_irq, axienet_rx_irq, IRQF_SHARED,
1175 			  ndev->name, ndev);
1176 	if (ret)
1177 		goto err_rx_irq;
1178 	/* Enable interrupts for Axi Ethernet core (if defined) */
1179 	if (lp->eth_irq > 0) {
1180 		ret = request_irq(lp->eth_irq, axienet_eth_irq, IRQF_SHARED,
1181 				  ndev->name, ndev);
1182 		if (ret)
1183 			goto err_eth_irq;
1184 	}
1185 
1186 	return 0;
1187 
1188 err_eth_irq:
1189 	free_irq(lp->rx_irq, ndev);
1190 err_rx_irq:
1191 	free_irq(lp->tx_irq, ndev);
1192 err_tx_irq:
1193 	napi_disable(&lp->napi_tx);
1194 	napi_disable(&lp->napi_rx);
1195 	phylink_stop(lp->phylink);
1196 	phylink_disconnect_phy(lp->phylink);
1197 	cancel_work_sync(&lp->dma_err_task);
1198 	dev_err(lp->dev, "request_irq() failed\n");
1199 	return ret;
1200 }
1201 
1202 /**
1203  * axienet_stop - Driver stop routine.
1204  * @ndev:	Pointer to net_device structure
1205  *
1206  * Return: 0, on success.
1207  *
1208  * This is the driver stop routine. It calls phylink_disconnect to stop the PHY
1209  * device. It also removes the interrupt handlers and disables the interrupts.
1210  * The Axi DMA Tx/Rx BDs are released.
1211  */
1212 static int axienet_stop(struct net_device *ndev)
1213 {
1214 	struct axienet_local *lp = netdev_priv(ndev);
1215 
1216 	dev_dbg(&ndev->dev, "axienet_close()\n");
1217 
1218 	napi_disable(&lp->napi_tx);
1219 	napi_disable(&lp->napi_rx);
1220 
1221 	phylink_stop(lp->phylink);
1222 	phylink_disconnect_phy(lp->phylink);
1223 
1224 	axienet_setoptions(ndev, lp->options &
1225 			   ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1226 
1227 	axienet_dma_stop(lp);
1228 
1229 	axienet_iow(lp, XAE_IE_OFFSET, 0);
1230 
1231 	cancel_work_sync(&lp->dma_err_task);
1232 
1233 	if (lp->eth_irq > 0)
1234 		free_irq(lp->eth_irq, ndev);
1235 	free_irq(lp->tx_irq, ndev);
1236 	free_irq(lp->rx_irq, ndev);
1237 
1238 	axienet_dma_bd_release(ndev);
1239 	return 0;
1240 }
1241 
1242 /**
1243  * axienet_change_mtu - Driver change mtu routine.
1244  * @ndev:	Pointer to net_device structure
1245  * @new_mtu:	New mtu value to be applied
1246  *
1247  * Return: Always returns 0 (success).
1248  *
1249  * This is the change mtu driver routine. It checks if the Axi Ethernet
1250  * hardware supports jumbo frames before changing the mtu. This can be
1251  * called only when the device is not up.
1252  */
1253 static int axienet_change_mtu(struct net_device *ndev, int new_mtu)
1254 {
1255 	struct axienet_local *lp = netdev_priv(ndev);
1256 
1257 	if (netif_running(ndev))
1258 		return -EBUSY;
1259 
1260 	if ((new_mtu + VLAN_ETH_HLEN +
1261 		XAE_TRL_SIZE) > lp->rxmem)
1262 		return -EINVAL;
1263 
1264 	ndev->mtu = new_mtu;
1265 
1266 	return 0;
1267 }
1268 
1269 #ifdef CONFIG_NET_POLL_CONTROLLER
1270 /**
1271  * axienet_poll_controller - Axi Ethernet poll mechanism.
1272  * @ndev:	Pointer to net_device structure
1273  *
1274  * This implements Rx/Tx ISR poll mechanisms. The interrupts are disabled prior
1275  * to polling the ISRs and are enabled back after the polling is done.
1276  */
1277 static void axienet_poll_controller(struct net_device *ndev)
1278 {
1279 	struct axienet_local *lp = netdev_priv(ndev);
1280 	disable_irq(lp->tx_irq);
1281 	disable_irq(lp->rx_irq);
1282 	axienet_rx_irq(lp->tx_irq, ndev);
1283 	axienet_tx_irq(lp->rx_irq, ndev);
1284 	enable_irq(lp->tx_irq);
1285 	enable_irq(lp->rx_irq);
1286 }
1287 #endif
1288 
1289 static int axienet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1290 {
1291 	struct axienet_local *lp = netdev_priv(dev);
1292 
1293 	if (!netif_running(dev))
1294 		return -EINVAL;
1295 
1296 	return phylink_mii_ioctl(lp->phylink, rq, cmd);
1297 }
1298 
1299 static void
1300 axienet_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1301 {
1302 	struct axienet_local *lp = netdev_priv(dev);
1303 	unsigned int start;
1304 
1305 	netdev_stats_to_stats64(stats, &dev->stats);
1306 
1307 	do {
1308 		start = u64_stats_fetch_begin(&lp->rx_stat_sync);
1309 		stats->rx_packets = u64_stats_read(&lp->rx_packets);
1310 		stats->rx_bytes = u64_stats_read(&lp->rx_bytes);
1311 	} while (u64_stats_fetch_retry(&lp->rx_stat_sync, start));
1312 
1313 	do {
1314 		start = u64_stats_fetch_begin(&lp->tx_stat_sync);
1315 		stats->tx_packets = u64_stats_read(&lp->tx_packets);
1316 		stats->tx_bytes = u64_stats_read(&lp->tx_bytes);
1317 	} while (u64_stats_fetch_retry(&lp->tx_stat_sync, start));
1318 }
1319 
1320 static const struct net_device_ops axienet_netdev_ops = {
1321 	.ndo_open = axienet_open,
1322 	.ndo_stop = axienet_stop,
1323 	.ndo_start_xmit = axienet_start_xmit,
1324 	.ndo_get_stats64 = axienet_get_stats64,
1325 	.ndo_change_mtu	= axienet_change_mtu,
1326 	.ndo_set_mac_address = netdev_set_mac_address,
1327 	.ndo_validate_addr = eth_validate_addr,
1328 	.ndo_eth_ioctl = axienet_ioctl,
1329 	.ndo_set_rx_mode = axienet_set_multicast_list,
1330 #ifdef CONFIG_NET_POLL_CONTROLLER
1331 	.ndo_poll_controller = axienet_poll_controller,
1332 #endif
1333 };
1334 
1335 /**
1336  * axienet_ethtools_get_drvinfo - Get various Axi Ethernet driver information.
1337  * @ndev:	Pointer to net_device structure
1338  * @ed:		Pointer to ethtool_drvinfo structure
1339  *
1340  * This implements ethtool command for getting the driver information.
1341  * Issue "ethtool -i ethX" under linux prompt to execute this function.
1342  */
1343 static void axienet_ethtools_get_drvinfo(struct net_device *ndev,
1344 					 struct ethtool_drvinfo *ed)
1345 {
1346 	strscpy(ed->driver, DRIVER_NAME, sizeof(ed->driver));
1347 	strscpy(ed->version, DRIVER_VERSION, sizeof(ed->version));
1348 }
1349 
1350 /**
1351  * axienet_ethtools_get_regs_len - Get the total regs length present in the
1352  *				   AxiEthernet core.
1353  * @ndev:	Pointer to net_device structure
1354  *
1355  * This implements ethtool command for getting the total register length
1356  * information.
1357  *
1358  * Return: the total regs length
1359  */
1360 static int axienet_ethtools_get_regs_len(struct net_device *ndev)
1361 {
1362 	return sizeof(u32) * AXIENET_REGS_N;
1363 }
1364 
1365 /**
1366  * axienet_ethtools_get_regs - Dump the contents of all registers present
1367  *			       in AxiEthernet core.
1368  * @ndev:	Pointer to net_device structure
1369  * @regs:	Pointer to ethtool_regs structure
1370  * @ret:	Void pointer used to return the contents of the registers.
1371  *
1372  * This implements ethtool command for getting the Axi Ethernet register dump.
1373  * Issue "ethtool -d ethX" to execute this function.
1374  */
1375 static void axienet_ethtools_get_regs(struct net_device *ndev,
1376 				      struct ethtool_regs *regs, void *ret)
1377 {
1378 	u32 *data = (u32 *)ret;
1379 	size_t len = sizeof(u32) * AXIENET_REGS_N;
1380 	struct axienet_local *lp = netdev_priv(ndev);
1381 
1382 	regs->version = 0;
1383 	regs->len = len;
1384 
1385 	memset(data, 0, len);
1386 	data[0] = axienet_ior(lp, XAE_RAF_OFFSET);
1387 	data[1] = axienet_ior(lp, XAE_TPF_OFFSET);
1388 	data[2] = axienet_ior(lp, XAE_IFGP_OFFSET);
1389 	data[3] = axienet_ior(lp, XAE_IS_OFFSET);
1390 	data[4] = axienet_ior(lp, XAE_IP_OFFSET);
1391 	data[5] = axienet_ior(lp, XAE_IE_OFFSET);
1392 	data[6] = axienet_ior(lp, XAE_TTAG_OFFSET);
1393 	data[7] = axienet_ior(lp, XAE_RTAG_OFFSET);
1394 	data[8] = axienet_ior(lp, XAE_UAWL_OFFSET);
1395 	data[9] = axienet_ior(lp, XAE_UAWU_OFFSET);
1396 	data[10] = axienet_ior(lp, XAE_TPID0_OFFSET);
1397 	data[11] = axienet_ior(lp, XAE_TPID1_OFFSET);
1398 	data[12] = axienet_ior(lp, XAE_PPST_OFFSET);
1399 	data[13] = axienet_ior(lp, XAE_RCW0_OFFSET);
1400 	data[14] = axienet_ior(lp, XAE_RCW1_OFFSET);
1401 	data[15] = axienet_ior(lp, XAE_TC_OFFSET);
1402 	data[16] = axienet_ior(lp, XAE_FCC_OFFSET);
1403 	data[17] = axienet_ior(lp, XAE_EMMC_OFFSET);
1404 	data[18] = axienet_ior(lp, XAE_PHYC_OFFSET);
1405 	data[19] = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
1406 	data[20] = axienet_ior(lp, XAE_MDIO_MCR_OFFSET);
1407 	data[21] = axienet_ior(lp, XAE_MDIO_MWD_OFFSET);
1408 	data[22] = axienet_ior(lp, XAE_MDIO_MRD_OFFSET);
1409 	data[27] = axienet_ior(lp, XAE_UAW0_OFFSET);
1410 	data[28] = axienet_ior(lp, XAE_UAW1_OFFSET);
1411 	data[29] = axienet_ior(lp, XAE_FMI_OFFSET);
1412 	data[30] = axienet_ior(lp, XAE_AF0_OFFSET);
1413 	data[31] = axienet_ior(lp, XAE_AF1_OFFSET);
1414 	data[32] = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1415 	data[33] = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);
1416 	data[34] = axienet_dma_in32(lp, XAXIDMA_TX_CDESC_OFFSET);
1417 	data[35] = axienet_dma_in32(lp, XAXIDMA_TX_TDESC_OFFSET);
1418 	data[36] = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1419 	data[37] = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);
1420 	data[38] = axienet_dma_in32(lp, XAXIDMA_RX_CDESC_OFFSET);
1421 	data[39] = axienet_dma_in32(lp, XAXIDMA_RX_TDESC_OFFSET);
1422 }
1423 
1424 static void
1425 axienet_ethtools_get_ringparam(struct net_device *ndev,
1426 			       struct ethtool_ringparam *ering,
1427 			       struct kernel_ethtool_ringparam *kernel_ering,
1428 			       struct netlink_ext_ack *extack)
1429 {
1430 	struct axienet_local *lp = netdev_priv(ndev);
1431 
1432 	ering->rx_max_pending = RX_BD_NUM_MAX;
1433 	ering->rx_mini_max_pending = 0;
1434 	ering->rx_jumbo_max_pending = 0;
1435 	ering->tx_max_pending = TX_BD_NUM_MAX;
1436 	ering->rx_pending = lp->rx_bd_num;
1437 	ering->rx_mini_pending = 0;
1438 	ering->rx_jumbo_pending = 0;
1439 	ering->tx_pending = lp->tx_bd_num;
1440 }
1441 
1442 static int
1443 axienet_ethtools_set_ringparam(struct net_device *ndev,
1444 			       struct ethtool_ringparam *ering,
1445 			       struct kernel_ethtool_ringparam *kernel_ering,
1446 			       struct netlink_ext_ack *extack)
1447 {
1448 	struct axienet_local *lp = netdev_priv(ndev);
1449 
1450 	if (ering->rx_pending > RX_BD_NUM_MAX ||
1451 	    ering->rx_mini_pending ||
1452 	    ering->rx_jumbo_pending ||
1453 	    ering->tx_pending < TX_BD_NUM_MIN ||
1454 	    ering->tx_pending > TX_BD_NUM_MAX)
1455 		return -EINVAL;
1456 
1457 	if (netif_running(ndev))
1458 		return -EBUSY;
1459 
1460 	lp->rx_bd_num = ering->rx_pending;
1461 	lp->tx_bd_num = ering->tx_pending;
1462 	return 0;
1463 }
1464 
1465 /**
1466  * axienet_ethtools_get_pauseparam - Get the pause parameter setting for
1467  *				     Tx and Rx paths.
1468  * @ndev:	Pointer to net_device structure
1469  * @epauseparm:	Pointer to ethtool_pauseparam structure.
1470  *
1471  * This implements ethtool command for getting axi ethernet pause frame
1472  * setting. Issue "ethtool -a ethX" to execute this function.
1473  */
1474 static void
1475 axienet_ethtools_get_pauseparam(struct net_device *ndev,
1476 				struct ethtool_pauseparam *epauseparm)
1477 {
1478 	struct axienet_local *lp = netdev_priv(ndev);
1479 
1480 	phylink_ethtool_get_pauseparam(lp->phylink, epauseparm);
1481 }
1482 
1483 /**
1484  * axienet_ethtools_set_pauseparam - Set device pause parameter(flow control)
1485  *				     settings.
1486  * @ndev:	Pointer to net_device structure
1487  * @epauseparm:Pointer to ethtool_pauseparam structure
1488  *
1489  * This implements ethtool command for enabling flow control on Rx and Tx
1490  * paths. Issue "ethtool -A ethX tx on|off" under linux prompt to execute this
1491  * function.
1492  *
1493  * Return: 0 on success, -EFAULT if device is running
1494  */
1495 static int
1496 axienet_ethtools_set_pauseparam(struct net_device *ndev,
1497 				struct ethtool_pauseparam *epauseparm)
1498 {
1499 	struct axienet_local *lp = netdev_priv(ndev);
1500 
1501 	return phylink_ethtool_set_pauseparam(lp->phylink, epauseparm);
1502 }
1503 
1504 /**
1505  * axienet_ethtools_get_coalesce - Get DMA interrupt coalescing count.
1506  * @ndev:	Pointer to net_device structure
1507  * @ecoalesce:	Pointer to ethtool_coalesce structure
1508  * @kernel_coal: ethtool CQE mode setting structure
1509  * @extack:	extack for reporting error messages
1510  *
1511  * This implements ethtool command for getting the DMA interrupt coalescing
1512  * count on Tx and Rx paths. Issue "ethtool -c ethX" under linux prompt to
1513  * execute this function.
1514  *
1515  * Return: 0 always
1516  */
1517 static int
1518 axienet_ethtools_get_coalesce(struct net_device *ndev,
1519 			      struct ethtool_coalesce *ecoalesce,
1520 			      struct kernel_ethtool_coalesce *kernel_coal,
1521 			      struct netlink_ext_ack *extack)
1522 {
1523 	struct axienet_local *lp = netdev_priv(ndev);
1524 
1525 	ecoalesce->rx_max_coalesced_frames = lp->coalesce_count_rx;
1526 	ecoalesce->rx_coalesce_usecs = lp->coalesce_usec_rx;
1527 	ecoalesce->tx_max_coalesced_frames = lp->coalesce_count_tx;
1528 	ecoalesce->tx_coalesce_usecs = lp->coalesce_usec_tx;
1529 	return 0;
1530 }
1531 
1532 /**
1533  * axienet_ethtools_set_coalesce - Set DMA interrupt coalescing count.
1534  * @ndev:	Pointer to net_device structure
1535  * @ecoalesce:	Pointer to ethtool_coalesce structure
1536  * @kernel_coal: ethtool CQE mode setting structure
1537  * @extack:	extack for reporting error messages
1538  *
1539  * This implements ethtool command for setting the DMA interrupt coalescing
1540  * count on Tx and Rx paths. Issue "ethtool -C ethX rx-frames 5" under linux
1541  * prompt to execute this function.
1542  *
1543  * Return: 0, on success, Non-zero error value on failure.
1544  */
1545 static int
1546 axienet_ethtools_set_coalesce(struct net_device *ndev,
1547 			      struct ethtool_coalesce *ecoalesce,
1548 			      struct kernel_ethtool_coalesce *kernel_coal,
1549 			      struct netlink_ext_ack *extack)
1550 {
1551 	struct axienet_local *lp = netdev_priv(ndev);
1552 
1553 	if (netif_running(ndev)) {
1554 		netdev_err(ndev,
1555 			   "Please stop netif before applying configuration\n");
1556 		return -EFAULT;
1557 	}
1558 
1559 	if (ecoalesce->rx_max_coalesced_frames)
1560 		lp->coalesce_count_rx = ecoalesce->rx_max_coalesced_frames;
1561 	if (ecoalesce->rx_coalesce_usecs)
1562 		lp->coalesce_usec_rx = ecoalesce->rx_coalesce_usecs;
1563 	if (ecoalesce->tx_max_coalesced_frames)
1564 		lp->coalesce_count_tx = ecoalesce->tx_max_coalesced_frames;
1565 	if (ecoalesce->tx_coalesce_usecs)
1566 		lp->coalesce_usec_tx = ecoalesce->tx_coalesce_usecs;
1567 
1568 	return 0;
1569 }
1570 
1571 static int
1572 axienet_ethtools_get_link_ksettings(struct net_device *ndev,
1573 				    struct ethtool_link_ksettings *cmd)
1574 {
1575 	struct axienet_local *lp = netdev_priv(ndev);
1576 
1577 	return phylink_ethtool_ksettings_get(lp->phylink, cmd);
1578 }
1579 
1580 static int
1581 axienet_ethtools_set_link_ksettings(struct net_device *ndev,
1582 				    const struct ethtool_link_ksettings *cmd)
1583 {
1584 	struct axienet_local *lp = netdev_priv(ndev);
1585 
1586 	return phylink_ethtool_ksettings_set(lp->phylink, cmd);
1587 }
1588 
1589 static int axienet_ethtools_nway_reset(struct net_device *dev)
1590 {
1591 	struct axienet_local *lp = netdev_priv(dev);
1592 
1593 	return phylink_ethtool_nway_reset(lp->phylink);
1594 }
1595 
1596 static const struct ethtool_ops axienet_ethtool_ops = {
1597 	.supported_coalesce_params = ETHTOOL_COALESCE_MAX_FRAMES |
1598 				     ETHTOOL_COALESCE_USECS,
1599 	.get_drvinfo    = axienet_ethtools_get_drvinfo,
1600 	.get_regs_len   = axienet_ethtools_get_regs_len,
1601 	.get_regs       = axienet_ethtools_get_regs,
1602 	.get_link       = ethtool_op_get_link,
1603 	.get_ringparam	= axienet_ethtools_get_ringparam,
1604 	.set_ringparam	= axienet_ethtools_set_ringparam,
1605 	.get_pauseparam = axienet_ethtools_get_pauseparam,
1606 	.set_pauseparam = axienet_ethtools_set_pauseparam,
1607 	.get_coalesce   = axienet_ethtools_get_coalesce,
1608 	.set_coalesce   = axienet_ethtools_set_coalesce,
1609 	.get_link_ksettings = axienet_ethtools_get_link_ksettings,
1610 	.set_link_ksettings = axienet_ethtools_set_link_ksettings,
1611 	.nway_reset	= axienet_ethtools_nway_reset,
1612 };
1613 
1614 static struct axienet_local *pcs_to_axienet_local(struct phylink_pcs *pcs)
1615 {
1616 	return container_of(pcs, struct axienet_local, pcs);
1617 }
1618 
1619 static void axienet_pcs_get_state(struct phylink_pcs *pcs,
1620 				  struct phylink_link_state *state)
1621 {
1622 	struct mdio_device *pcs_phy = pcs_to_axienet_local(pcs)->pcs_phy;
1623 
1624 	phylink_mii_c22_pcs_get_state(pcs_phy, state);
1625 }
1626 
1627 static void axienet_pcs_an_restart(struct phylink_pcs *pcs)
1628 {
1629 	struct mdio_device *pcs_phy = pcs_to_axienet_local(pcs)->pcs_phy;
1630 
1631 	phylink_mii_c22_pcs_an_restart(pcs_phy);
1632 }
1633 
1634 static int axienet_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
1635 			      phy_interface_t interface,
1636 			      const unsigned long *advertising,
1637 			      bool permit_pause_to_mac)
1638 {
1639 	struct mdio_device *pcs_phy = pcs_to_axienet_local(pcs)->pcs_phy;
1640 	struct net_device *ndev = pcs_to_axienet_local(pcs)->ndev;
1641 	struct axienet_local *lp = netdev_priv(ndev);
1642 	int ret;
1643 
1644 	if (lp->switch_x_sgmii) {
1645 		ret = mdiodev_write(pcs_phy, XLNX_MII_STD_SELECT_REG,
1646 				    interface == PHY_INTERFACE_MODE_SGMII ?
1647 					XLNX_MII_STD_SELECT_SGMII : 0);
1648 		if (ret < 0) {
1649 			netdev_warn(ndev,
1650 				    "Failed to switch PHY interface: %d\n",
1651 				    ret);
1652 			return ret;
1653 		}
1654 	}
1655 
1656 	ret = phylink_mii_c22_pcs_config(pcs_phy, mode, interface, advertising);
1657 	if (ret < 0)
1658 		netdev_warn(ndev, "Failed to configure PCS: %d\n", ret);
1659 
1660 	return ret;
1661 }
1662 
1663 static const struct phylink_pcs_ops axienet_pcs_ops = {
1664 	.pcs_get_state = axienet_pcs_get_state,
1665 	.pcs_config = axienet_pcs_config,
1666 	.pcs_an_restart = axienet_pcs_an_restart,
1667 };
1668 
1669 static struct phylink_pcs *axienet_mac_select_pcs(struct phylink_config *config,
1670 						  phy_interface_t interface)
1671 {
1672 	struct net_device *ndev = to_net_dev(config->dev);
1673 	struct axienet_local *lp = netdev_priv(ndev);
1674 
1675 	if (interface == PHY_INTERFACE_MODE_1000BASEX ||
1676 	    interface ==  PHY_INTERFACE_MODE_SGMII)
1677 		return &lp->pcs;
1678 
1679 	return NULL;
1680 }
1681 
1682 static void axienet_mac_config(struct phylink_config *config, unsigned int mode,
1683 			       const struct phylink_link_state *state)
1684 {
1685 	/* nothing meaningful to do */
1686 }
1687 
1688 static void axienet_mac_link_down(struct phylink_config *config,
1689 				  unsigned int mode,
1690 				  phy_interface_t interface)
1691 {
1692 	/* nothing meaningful to do */
1693 }
1694 
1695 static void axienet_mac_link_up(struct phylink_config *config,
1696 				struct phy_device *phy,
1697 				unsigned int mode, phy_interface_t interface,
1698 				int speed, int duplex,
1699 				bool tx_pause, bool rx_pause)
1700 {
1701 	struct net_device *ndev = to_net_dev(config->dev);
1702 	struct axienet_local *lp = netdev_priv(ndev);
1703 	u32 emmc_reg, fcc_reg;
1704 
1705 	emmc_reg = axienet_ior(lp, XAE_EMMC_OFFSET);
1706 	emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
1707 
1708 	switch (speed) {
1709 	case SPEED_1000:
1710 		emmc_reg |= XAE_EMMC_LINKSPD_1000;
1711 		break;
1712 	case SPEED_100:
1713 		emmc_reg |= XAE_EMMC_LINKSPD_100;
1714 		break;
1715 	case SPEED_10:
1716 		emmc_reg |= XAE_EMMC_LINKSPD_10;
1717 		break;
1718 	default:
1719 		dev_err(&ndev->dev,
1720 			"Speed other than 10, 100 or 1Gbps is not supported\n");
1721 		break;
1722 	}
1723 
1724 	axienet_iow(lp, XAE_EMMC_OFFSET, emmc_reg);
1725 
1726 	fcc_reg = axienet_ior(lp, XAE_FCC_OFFSET);
1727 	if (tx_pause)
1728 		fcc_reg |= XAE_FCC_FCTX_MASK;
1729 	else
1730 		fcc_reg &= ~XAE_FCC_FCTX_MASK;
1731 	if (rx_pause)
1732 		fcc_reg |= XAE_FCC_FCRX_MASK;
1733 	else
1734 		fcc_reg &= ~XAE_FCC_FCRX_MASK;
1735 	axienet_iow(lp, XAE_FCC_OFFSET, fcc_reg);
1736 }
1737 
1738 static const struct phylink_mac_ops axienet_phylink_ops = {
1739 	.mac_select_pcs = axienet_mac_select_pcs,
1740 	.mac_config = axienet_mac_config,
1741 	.mac_link_down = axienet_mac_link_down,
1742 	.mac_link_up = axienet_mac_link_up,
1743 };
1744 
1745 /**
1746  * axienet_dma_err_handler - Work queue task for Axi DMA Error
1747  * @work:	pointer to work_struct
1748  *
1749  * Resets the Axi DMA and Axi Ethernet devices, and reconfigures the
1750  * Tx/Rx BDs.
1751  */
1752 static void axienet_dma_err_handler(struct work_struct *work)
1753 {
1754 	u32 i;
1755 	u32 axienet_status;
1756 	struct axidma_bd *cur_p;
1757 	struct axienet_local *lp = container_of(work, struct axienet_local,
1758 						dma_err_task);
1759 	struct net_device *ndev = lp->ndev;
1760 
1761 	napi_disable(&lp->napi_tx);
1762 	napi_disable(&lp->napi_rx);
1763 
1764 	axienet_setoptions(ndev, lp->options &
1765 			   ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1766 
1767 	axienet_dma_stop(lp);
1768 
1769 	for (i = 0; i < lp->tx_bd_num; i++) {
1770 		cur_p = &lp->tx_bd_v[i];
1771 		if (cur_p->cntrl) {
1772 			dma_addr_t addr = desc_get_phys_addr(lp, cur_p);
1773 
1774 			dma_unmap_single(lp->dev, addr,
1775 					 (cur_p->cntrl &
1776 					  XAXIDMA_BD_CTRL_LENGTH_MASK),
1777 					 DMA_TO_DEVICE);
1778 		}
1779 		if (cur_p->skb)
1780 			dev_kfree_skb_irq(cur_p->skb);
1781 		cur_p->phys = 0;
1782 		cur_p->phys_msb = 0;
1783 		cur_p->cntrl = 0;
1784 		cur_p->status = 0;
1785 		cur_p->app0 = 0;
1786 		cur_p->app1 = 0;
1787 		cur_p->app2 = 0;
1788 		cur_p->app3 = 0;
1789 		cur_p->app4 = 0;
1790 		cur_p->skb = NULL;
1791 	}
1792 
1793 	for (i = 0; i < lp->rx_bd_num; i++) {
1794 		cur_p = &lp->rx_bd_v[i];
1795 		cur_p->status = 0;
1796 		cur_p->app0 = 0;
1797 		cur_p->app1 = 0;
1798 		cur_p->app2 = 0;
1799 		cur_p->app3 = 0;
1800 		cur_p->app4 = 0;
1801 	}
1802 
1803 	lp->tx_bd_ci = 0;
1804 	lp->tx_bd_tail = 0;
1805 	lp->rx_bd_ci = 0;
1806 
1807 	axienet_dma_start(lp);
1808 
1809 	axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);
1810 	axienet_status &= ~XAE_RCW1_RX_MASK;
1811 	axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
1812 
1813 	axienet_status = axienet_ior(lp, XAE_IP_OFFSET);
1814 	if (axienet_status & XAE_INT_RXRJECT_MASK)
1815 		axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
1816 	axienet_iow(lp, XAE_IE_OFFSET, lp->eth_irq > 0 ?
1817 		    XAE_INT_RECV_ERROR_MASK : 0);
1818 	axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
1819 
1820 	/* Sync default options with HW but leave receiver and
1821 	 * transmitter disabled.
1822 	 */
1823 	axienet_setoptions(ndev, lp->options &
1824 			   ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1825 	axienet_set_mac_address(ndev, NULL);
1826 	axienet_set_multicast_list(ndev);
1827 	axienet_setoptions(ndev, lp->options);
1828 	napi_enable(&lp->napi_rx);
1829 	napi_enable(&lp->napi_tx);
1830 }
1831 
1832 /**
1833  * axienet_probe - Axi Ethernet probe function.
1834  * @pdev:	Pointer to platform device structure.
1835  *
1836  * Return: 0, on success
1837  *	    Non-zero error value on failure.
1838  *
1839  * This is the probe routine for Axi Ethernet driver. This is called before
1840  * any other driver routines are invoked. It allocates and sets up the Ethernet
1841  * device. Parses through device tree and populates fields of
1842  * axienet_local. It registers the Ethernet device.
1843  */
1844 static int axienet_probe(struct platform_device *pdev)
1845 {
1846 	int ret;
1847 	struct device_node *np;
1848 	struct axienet_local *lp;
1849 	struct net_device *ndev;
1850 	struct resource *ethres;
1851 	u8 mac_addr[ETH_ALEN];
1852 	int addr_width = 32;
1853 	u32 value;
1854 
1855 	ndev = alloc_etherdev(sizeof(*lp));
1856 	if (!ndev)
1857 		return -ENOMEM;
1858 
1859 	platform_set_drvdata(pdev, ndev);
1860 
1861 	SET_NETDEV_DEV(ndev, &pdev->dev);
1862 	ndev->flags &= ~IFF_MULTICAST;  /* clear multicast */
1863 	ndev->features = NETIF_F_SG;
1864 	ndev->netdev_ops = &axienet_netdev_ops;
1865 	ndev->ethtool_ops = &axienet_ethtool_ops;
1866 
1867 	/* MTU range: 64 - 9000 */
1868 	ndev->min_mtu = 64;
1869 	ndev->max_mtu = XAE_JUMBO_MTU;
1870 
1871 	lp = netdev_priv(ndev);
1872 	lp->ndev = ndev;
1873 	lp->dev = &pdev->dev;
1874 	lp->options = XAE_OPTION_DEFAULTS;
1875 	lp->rx_bd_num = RX_BD_NUM_DEFAULT;
1876 	lp->tx_bd_num = TX_BD_NUM_DEFAULT;
1877 
1878 	u64_stats_init(&lp->rx_stat_sync);
1879 	u64_stats_init(&lp->tx_stat_sync);
1880 
1881 	netif_napi_add(ndev, &lp->napi_rx, axienet_rx_poll);
1882 	netif_napi_add(ndev, &lp->napi_tx, axienet_tx_poll);
1883 
1884 	lp->axi_clk = devm_clk_get_optional(&pdev->dev, "s_axi_lite_clk");
1885 	if (!lp->axi_clk) {
1886 		/* For backward compatibility, if named AXI clock is not present,
1887 		 * treat the first clock specified as the AXI clock.
1888 		 */
1889 		lp->axi_clk = devm_clk_get_optional(&pdev->dev, NULL);
1890 	}
1891 	if (IS_ERR(lp->axi_clk)) {
1892 		ret = PTR_ERR(lp->axi_clk);
1893 		goto free_netdev;
1894 	}
1895 	ret = clk_prepare_enable(lp->axi_clk);
1896 	if (ret) {
1897 		dev_err(&pdev->dev, "Unable to enable AXI clock: %d\n", ret);
1898 		goto free_netdev;
1899 	}
1900 
1901 	lp->misc_clks[0].id = "axis_clk";
1902 	lp->misc_clks[1].id = "ref_clk";
1903 	lp->misc_clks[2].id = "mgt_clk";
1904 
1905 	ret = devm_clk_bulk_get_optional(&pdev->dev, XAE_NUM_MISC_CLOCKS, lp->misc_clks);
1906 	if (ret)
1907 		goto cleanup_clk;
1908 
1909 	ret = clk_bulk_prepare_enable(XAE_NUM_MISC_CLOCKS, lp->misc_clks);
1910 	if (ret)
1911 		goto cleanup_clk;
1912 
1913 	/* Map device registers */
1914 	lp->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &ethres);
1915 	if (IS_ERR(lp->regs)) {
1916 		ret = PTR_ERR(lp->regs);
1917 		goto cleanup_clk;
1918 	}
1919 	lp->regs_start = ethres->start;
1920 
1921 	/* Setup checksum offload, but default to off if not specified */
1922 	lp->features = 0;
1923 
1924 	ret = of_property_read_u32(pdev->dev.of_node, "xlnx,txcsum", &value);
1925 	if (!ret) {
1926 		switch (value) {
1927 		case 1:
1928 			lp->csum_offload_on_tx_path =
1929 				XAE_FEATURE_PARTIAL_TX_CSUM;
1930 			lp->features |= XAE_FEATURE_PARTIAL_TX_CSUM;
1931 			/* Can checksum TCP/UDP over IPv4. */
1932 			ndev->features |= NETIF_F_IP_CSUM;
1933 			break;
1934 		case 2:
1935 			lp->csum_offload_on_tx_path =
1936 				XAE_FEATURE_FULL_TX_CSUM;
1937 			lp->features |= XAE_FEATURE_FULL_TX_CSUM;
1938 			/* Can checksum TCP/UDP over IPv4. */
1939 			ndev->features |= NETIF_F_IP_CSUM;
1940 			break;
1941 		default:
1942 			lp->csum_offload_on_tx_path = XAE_NO_CSUM_OFFLOAD;
1943 		}
1944 	}
1945 	ret = of_property_read_u32(pdev->dev.of_node, "xlnx,rxcsum", &value);
1946 	if (!ret) {
1947 		switch (value) {
1948 		case 1:
1949 			lp->csum_offload_on_rx_path =
1950 				XAE_FEATURE_PARTIAL_RX_CSUM;
1951 			lp->features |= XAE_FEATURE_PARTIAL_RX_CSUM;
1952 			break;
1953 		case 2:
1954 			lp->csum_offload_on_rx_path =
1955 				XAE_FEATURE_FULL_RX_CSUM;
1956 			lp->features |= XAE_FEATURE_FULL_RX_CSUM;
1957 			break;
1958 		default:
1959 			lp->csum_offload_on_rx_path = XAE_NO_CSUM_OFFLOAD;
1960 		}
1961 	}
1962 	/* For supporting jumbo frames, the Axi Ethernet hardware must have
1963 	 * a larger Rx/Tx Memory. Typically, the size must be large so that
1964 	 * we can enable jumbo option and start supporting jumbo frames.
1965 	 * Here we check for memory allocated for Rx/Tx in the hardware from
1966 	 * the device-tree and accordingly set flags.
1967 	 */
1968 	of_property_read_u32(pdev->dev.of_node, "xlnx,rxmem", &lp->rxmem);
1969 
1970 	lp->switch_x_sgmii = of_property_read_bool(pdev->dev.of_node,
1971 						   "xlnx,switch-x-sgmii");
1972 
1973 	/* Start with the proprietary, and broken phy_type */
1974 	ret = of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &value);
1975 	if (!ret) {
1976 		netdev_warn(ndev, "Please upgrade your device tree binary blob to use phy-mode");
1977 		switch (value) {
1978 		case XAE_PHY_TYPE_MII:
1979 			lp->phy_mode = PHY_INTERFACE_MODE_MII;
1980 			break;
1981 		case XAE_PHY_TYPE_GMII:
1982 			lp->phy_mode = PHY_INTERFACE_MODE_GMII;
1983 			break;
1984 		case XAE_PHY_TYPE_RGMII_2_0:
1985 			lp->phy_mode = PHY_INTERFACE_MODE_RGMII_ID;
1986 			break;
1987 		case XAE_PHY_TYPE_SGMII:
1988 			lp->phy_mode = PHY_INTERFACE_MODE_SGMII;
1989 			break;
1990 		case XAE_PHY_TYPE_1000BASE_X:
1991 			lp->phy_mode = PHY_INTERFACE_MODE_1000BASEX;
1992 			break;
1993 		default:
1994 			ret = -EINVAL;
1995 			goto cleanup_clk;
1996 		}
1997 	} else {
1998 		ret = of_get_phy_mode(pdev->dev.of_node, &lp->phy_mode);
1999 		if (ret)
2000 			goto cleanup_clk;
2001 	}
2002 	if (lp->switch_x_sgmii && lp->phy_mode != PHY_INTERFACE_MODE_SGMII &&
2003 	    lp->phy_mode != PHY_INTERFACE_MODE_1000BASEX) {
2004 		dev_err(&pdev->dev, "xlnx,switch-x-sgmii only supported with SGMII or 1000BaseX\n");
2005 		ret = -EINVAL;
2006 		goto cleanup_clk;
2007 	}
2008 
2009 	/* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
2010 	np = of_parse_phandle(pdev->dev.of_node, "axistream-connected", 0);
2011 	if (np) {
2012 		struct resource dmares;
2013 
2014 		ret = of_address_to_resource(np, 0, &dmares);
2015 		if (ret) {
2016 			dev_err(&pdev->dev,
2017 				"unable to get DMA resource\n");
2018 			of_node_put(np);
2019 			goto cleanup_clk;
2020 		}
2021 		lp->dma_regs = devm_ioremap_resource(&pdev->dev,
2022 						     &dmares);
2023 		lp->rx_irq = irq_of_parse_and_map(np, 1);
2024 		lp->tx_irq = irq_of_parse_and_map(np, 0);
2025 		of_node_put(np);
2026 		lp->eth_irq = platform_get_irq_optional(pdev, 0);
2027 	} else {
2028 		/* Check for these resources directly on the Ethernet node. */
2029 		lp->dma_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
2030 		lp->rx_irq = platform_get_irq(pdev, 1);
2031 		lp->tx_irq = platform_get_irq(pdev, 0);
2032 		lp->eth_irq = platform_get_irq_optional(pdev, 2);
2033 	}
2034 	if (IS_ERR(lp->dma_regs)) {
2035 		dev_err(&pdev->dev, "could not map DMA regs\n");
2036 		ret = PTR_ERR(lp->dma_regs);
2037 		goto cleanup_clk;
2038 	}
2039 	if ((lp->rx_irq <= 0) || (lp->tx_irq <= 0)) {
2040 		dev_err(&pdev->dev, "could not determine irqs\n");
2041 		ret = -ENOMEM;
2042 		goto cleanup_clk;
2043 	}
2044 
2045 	/* Autodetect the need for 64-bit DMA pointers.
2046 	 * When the IP is configured for a bus width bigger than 32 bits,
2047 	 * writing the MSB registers is mandatory, even if they are all 0.
2048 	 * We can detect this case by writing all 1's to one such register
2049 	 * and see if that sticks: when the IP is configured for 32 bits
2050 	 * only, those registers are RES0.
2051 	 * Those MSB registers were introduced in IP v7.1, which we check first.
2052 	 */
2053 	if ((axienet_ior(lp, XAE_ID_OFFSET) >> 24) >= 0x9) {
2054 		void __iomem *desc = lp->dma_regs + XAXIDMA_TX_CDESC_OFFSET + 4;
2055 
2056 		iowrite32(0x0, desc);
2057 		if (ioread32(desc) == 0) {	/* sanity check */
2058 			iowrite32(0xffffffff, desc);
2059 			if (ioread32(desc) > 0) {
2060 				lp->features |= XAE_FEATURE_DMA_64BIT;
2061 				addr_width = 64;
2062 				dev_info(&pdev->dev,
2063 					 "autodetected 64-bit DMA range\n");
2064 			}
2065 			iowrite32(0x0, desc);
2066 		}
2067 	}
2068 	if (!IS_ENABLED(CONFIG_64BIT) && lp->features & XAE_FEATURE_DMA_64BIT) {
2069 		dev_err(&pdev->dev, "64-bit addressable DMA is not compatible with 32-bit archecture\n");
2070 		ret = -EINVAL;
2071 		goto cleanup_clk;
2072 	}
2073 
2074 	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_width));
2075 	if (ret) {
2076 		dev_err(&pdev->dev, "No suitable DMA available\n");
2077 		goto cleanup_clk;
2078 	}
2079 
2080 	/* Check for Ethernet core IRQ (optional) */
2081 	if (lp->eth_irq <= 0)
2082 		dev_info(&pdev->dev, "Ethernet core IRQ not defined\n");
2083 
2084 	/* Retrieve the MAC address */
2085 	ret = of_get_mac_address(pdev->dev.of_node, mac_addr);
2086 	if (!ret) {
2087 		axienet_set_mac_address(ndev, mac_addr);
2088 	} else {
2089 		dev_warn(&pdev->dev, "could not find MAC address property: %d\n",
2090 			 ret);
2091 		axienet_set_mac_address(ndev, NULL);
2092 	}
2093 
2094 	lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
2095 	lp->coalesce_usec_rx = XAXIDMA_DFT_RX_USEC;
2096 	lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
2097 	lp->coalesce_usec_tx = XAXIDMA_DFT_TX_USEC;
2098 
2099 	/* Reset core now that clocks are enabled, prior to accessing MDIO */
2100 	ret = __axienet_device_reset(lp);
2101 	if (ret)
2102 		goto cleanup_clk;
2103 
2104 	ret = axienet_mdio_setup(lp);
2105 	if (ret)
2106 		dev_warn(&pdev->dev,
2107 			 "error registering MDIO bus: %d\n", ret);
2108 
2109 	if (lp->phy_mode == PHY_INTERFACE_MODE_SGMII ||
2110 	    lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2111 		np = of_parse_phandle(pdev->dev.of_node, "pcs-handle", 0);
2112 		if (!np) {
2113 			/* Deprecated: Always use "pcs-handle" for pcs_phy.
2114 			 * Falling back to "phy-handle" here is only for
2115 			 * backward compatibility with old device trees.
2116 			 */
2117 			np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
2118 		}
2119 		if (!np) {
2120 			dev_err(&pdev->dev, "pcs-handle (preferred) or phy-handle required for 1000BaseX/SGMII\n");
2121 			ret = -EINVAL;
2122 			goto cleanup_mdio;
2123 		}
2124 		lp->pcs_phy = of_mdio_find_device(np);
2125 		if (!lp->pcs_phy) {
2126 			ret = -EPROBE_DEFER;
2127 			of_node_put(np);
2128 			goto cleanup_mdio;
2129 		}
2130 		of_node_put(np);
2131 		lp->pcs.ops = &axienet_pcs_ops;
2132 		lp->pcs.poll = true;
2133 	}
2134 
2135 	lp->phylink_config.dev = &ndev->dev;
2136 	lp->phylink_config.type = PHYLINK_NETDEV;
2137 	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
2138 		MAC_10FD | MAC_100FD | MAC_1000FD;
2139 
2140 	__set_bit(lp->phy_mode, lp->phylink_config.supported_interfaces);
2141 	if (lp->switch_x_sgmii) {
2142 		__set_bit(PHY_INTERFACE_MODE_1000BASEX,
2143 			  lp->phylink_config.supported_interfaces);
2144 		__set_bit(PHY_INTERFACE_MODE_SGMII,
2145 			  lp->phylink_config.supported_interfaces);
2146 	}
2147 
2148 	lp->phylink = phylink_create(&lp->phylink_config, pdev->dev.fwnode,
2149 				     lp->phy_mode,
2150 				     &axienet_phylink_ops);
2151 	if (IS_ERR(lp->phylink)) {
2152 		ret = PTR_ERR(lp->phylink);
2153 		dev_err(&pdev->dev, "phylink_create error (%i)\n", ret);
2154 		goto cleanup_mdio;
2155 	}
2156 
2157 	ret = register_netdev(lp->ndev);
2158 	if (ret) {
2159 		dev_err(lp->dev, "register_netdev() error (%i)\n", ret);
2160 		goto cleanup_phylink;
2161 	}
2162 
2163 	return 0;
2164 
2165 cleanup_phylink:
2166 	phylink_destroy(lp->phylink);
2167 
2168 cleanup_mdio:
2169 	if (lp->pcs_phy)
2170 		put_device(&lp->pcs_phy->dev);
2171 	if (lp->mii_bus)
2172 		axienet_mdio_teardown(lp);
2173 cleanup_clk:
2174 	clk_bulk_disable_unprepare(XAE_NUM_MISC_CLOCKS, lp->misc_clks);
2175 	clk_disable_unprepare(lp->axi_clk);
2176 
2177 free_netdev:
2178 	free_netdev(ndev);
2179 
2180 	return ret;
2181 }
2182 
2183 static int axienet_remove(struct platform_device *pdev)
2184 {
2185 	struct net_device *ndev = platform_get_drvdata(pdev);
2186 	struct axienet_local *lp = netdev_priv(ndev);
2187 
2188 	unregister_netdev(ndev);
2189 
2190 	if (lp->phylink)
2191 		phylink_destroy(lp->phylink);
2192 
2193 	if (lp->pcs_phy)
2194 		put_device(&lp->pcs_phy->dev);
2195 
2196 	axienet_mdio_teardown(lp);
2197 
2198 	clk_bulk_disable_unprepare(XAE_NUM_MISC_CLOCKS, lp->misc_clks);
2199 	clk_disable_unprepare(lp->axi_clk);
2200 
2201 	free_netdev(ndev);
2202 
2203 	return 0;
2204 }
2205 
2206 static void axienet_shutdown(struct platform_device *pdev)
2207 {
2208 	struct net_device *ndev = platform_get_drvdata(pdev);
2209 
2210 	rtnl_lock();
2211 	netif_device_detach(ndev);
2212 
2213 	if (netif_running(ndev))
2214 		dev_close(ndev);
2215 
2216 	rtnl_unlock();
2217 }
2218 
2219 static int axienet_suspend(struct device *dev)
2220 {
2221 	struct net_device *ndev = dev_get_drvdata(dev);
2222 
2223 	if (!netif_running(ndev))
2224 		return 0;
2225 
2226 	netif_device_detach(ndev);
2227 
2228 	rtnl_lock();
2229 	axienet_stop(ndev);
2230 	rtnl_unlock();
2231 
2232 	return 0;
2233 }
2234 
2235 static int axienet_resume(struct device *dev)
2236 {
2237 	struct net_device *ndev = dev_get_drvdata(dev);
2238 
2239 	if (!netif_running(ndev))
2240 		return 0;
2241 
2242 	rtnl_lock();
2243 	axienet_open(ndev);
2244 	rtnl_unlock();
2245 
2246 	netif_device_attach(ndev);
2247 
2248 	return 0;
2249 }
2250 
2251 static DEFINE_SIMPLE_DEV_PM_OPS(axienet_pm_ops,
2252 				axienet_suspend, axienet_resume);
2253 
2254 static struct platform_driver axienet_driver = {
2255 	.probe = axienet_probe,
2256 	.remove = axienet_remove,
2257 	.shutdown = axienet_shutdown,
2258 	.driver = {
2259 		 .name = "xilinx_axienet",
2260 		 .pm = &axienet_pm_ops,
2261 		 .of_match_table = axienet_of_match,
2262 	},
2263 };
2264 
2265 module_platform_driver(axienet_driver);
2266 
2267 MODULE_DESCRIPTION("Xilinx Axi Ethernet driver");
2268 MODULE_AUTHOR("Xilinx");
2269 MODULE_LICENSE("GPL");
2270