1 /* 2 * Driver for Xilinx TEMAC Ethernet device 3 * 4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi 5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net> 6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd. 7 * 8 * This is a driver for the Xilinx ll_temac ipcore which is often used 9 * in the Virtex and Spartan series of chips. 10 * 11 * Notes: 12 * - The ll_temac hardware uses indirect access for many of the TEMAC 13 * registers, include the MDIO bus. However, indirect access to MDIO 14 * registers take considerably more clock cycles than to TEMAC registers. 15 * MDIO accesses are long, so threads doing them should probably sleep 16 * rather than busywait. However, since only one indirect access can be 17 * in progress at any given time, that means that *all* indirect accesses 18 * could end up sleeping (to wait for an MDIO access to complete). 19 * Fortunately none of the indirect accesses are on the 'hot' path for tx 20 * or rx, so this should be okay. 21 * 22 * TODO: 23 * - Factor out locallink DMA code into separate driver 24 * - Fix multicast assignment. 25 * - Fix support for hardware checksumming. 26 * - Testing. Lots and lots of testing. 27 * 28 */ 29 30 #include <linux/delay.h> 31 #include <linux/etherdevice.h> 32 #include <linux/mii.h> 33 #include <linux/module.h> 34 #include <linux/mutex.h> 35 #include <linux/netdevice.h> 36 #include <linux/of.h> 37 #include <linux/of_device.h> 38 #include <linux/of_irq.h> 39 #include <linux/of_mdio.h> 40 #include <linux/of_net.h> 41 #include <linux/of_platform.h> 42 #include <linux/of_address.h> 43 #include <linux/skbuff.h> 44 #include <linux/spinlock.h> 45 #include <linux/tcp.h> /* needed for sizeof(tcphdr) */ 46 #include <linux/udp.h> /* needed for sizeof(udphdr) */ 47 #include <linux/phy.h> 48 #include <linux/in.h> 49 #include <linux/io.h> 50 #include <linux/ip.h> 51 #include <linux/slab.h> 52 #include <linux/interrupt.h> 53 #include <linux/dma-mapping.h> 54 55 #include "ll_temac.h" 56 57 #define TX_BD_NUM 64 58 #define RX_BD_NUM 128 59 60 /* --------------------------------------------------------------------- 61 * Low level register access functions 62 */ 63 64 u32 temac_ior(struct temac_local *lp, int offset) 65 { 66 return in_be32(lp->regs + offset); 67 } 68 69 void temac_iow(struct temac_local *lp, int offset, u32 value) 70 { 71 out_be32(lp->regs + offset, value); 72 } 73 74 int temac_indirect_busywait(struct temac_local *lp) 75 { 76 unsigned long end = jiffies + 2; 77 78 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) { 79 if (time_before_eq(end, jiffies)) { 80 WARN_ON(1); 81 return -ETIMEDOUT; 82 } 83 msleep(1); 84 } 85 return 0; 86 } 87 88 /** 89 * temac_indirect_in32 90 * 91 * lp->indirect_mutex must be held when calling this function 92 */ 93 u32 temac_indirect_in32(struct temac_local *lp, int reg) 94 { 95 u32 val; 96 97 if (temac_indirect_busywait(lp)) 98 return -ETIMEDOUT; 99 temac_iow(lp, XTE_CTL0_OFFSET, reg); 100 if (temac_indirect_busywait(lp)) 101 return -ETIMEDOUT; 102 val = temac_ior(lp, XTE_LSW0_OFFSET); 103 104 return val; 105 } 106 107 /** 108 * temac_indirect_out32 109 * 110 * lp->indirect_mutex must be held when calling this function 111 */ 112 void temac_indirect_out32(struct temac_local *lp, int reg, u32 value) 113 { 114 if (temac_indirect_busywait(lp)) 115 return; 116 temac_iow(lp, XTE_LSW0_OFFSET, value); 117 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg); 118 temac_indirect_busywait(lp); 119 } 120 121 /** 122 * temac_dma_in32 - Memory mapped DMA read, this function expects a 123 * register input that is based on DCR word addresses which 124 * are then converted to memory mapped byte addresses 125 */ 126 static u32 temac_dma_in32(struct temac_local *lp, int reg) 127 { 128 return in_be32(lp->sdma_regs + (reg << 2)); 129 } 130 131 /** 132 * temac_dma_out32 - Memory mapped DMA read, this function expects a 133 * register input that is based on DCR word addresses which 134 * are then converted to memory mapped byte addresses 135 */ 136 static void temac_dma_out32(struct temac_local *lp, int reg, u32 value) 137 { 138 out_be32(lp->sdma_regs + (reg << 2), value); 139 } 140 141 /* DMA register access functions can be DCR based or memory mapped. 142 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both 143 * memory mapped. 144 */ 145 #ifdef CONFIG_PPC_DCR 146 147 /** 148 * temac_dma_dcr_in32 - DCR based DMA read 149 */ 150 static u32 temac_dma_dcr_in(struct temac_local *lp, int reg) 151 { 152 return dcr_read(lp->sdma_dcrs, reg); 153 } 154 155 /** 156 * temac_dma_dcr_out32 - DCR based DMA write 157 */ 158 static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value) 159 { 160 dcr_write(lp->sdma_dcrs, reg, value); 161 } 162 163 /** 164 * temac_dcr_setup - If the DMA is DCR based, then setup the address and 165 * I/O functions 166 */ 167 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op, 168 struct device_node *np) 169 { 170 unsigned int dcrs; 171 172 /* setup the dcr address mapping if it's in the device tree */ 173 174 dcrs = dcr_resource_start(np, 0); 175 if (dcrs != 0) { 176 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0)); 177 lp->dma_in = temac_dma_dcr_in; 178 lp->dma_out = temac_dma_dcr_out; 179 dev_dbg(&op->dev, "DCR base: %x\n", dcrs); 180 return 0; 181 } 182 /* no DCR in the device tree, indicate a failure */ 183 return -1; 184 } 185 186 #else 187 188 /* 189 * temac_dcr_setup - This is a stub for when DCR is not supported, 190 * such as with MicroBlaze 191 */ 192 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op, 193 struct device_node *np) 194 { 195 return -1; 196 } 197 198 #endif 199 200 /** 201 * temac_dma_bd_release - Release buffer descriptor rings 202 */ 203 static void temac_dma_bd_release(struct net_device *ndev) 204 { 205 struct temac_local *lp = netdev_priv(ndev); 206 int i; 207 208 /* Reset Local Link (DMA) */ 209 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST); 210 211 for (i = 0; i < RX_BD_NUM; i++) { 212 if (!lp->rx_skb[i]) 213 break; 214 else { 215 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys, 216 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE); 217 dev_kfree_skb(lp->rx_skb[i]); 218 } 219 } 220 if (lp->rx_bd_v) 221 dma_free_coherent(ndev->dev.parent, 222 sizeof(*lp->rx_bd_v) * RX_BD_NUM, 223 lp->rx_bd_v, lp->rx_bd_p); 224 if (lp->tx_bd_v) 225 dma_free_coherent(ndev->dev.parent, 226 sizeof(*lp->tx_bd_v) * TX_BD_NUM, 227 lp->tx_bd_v, lp->tx_bd_p); 228 kfree(lp->rx_skb); 229 } 230 231 /** 232 * temac_dma_bd_init - Setup buffer descriptor rings 233 */ 234 static int temac_dma_bd_init(struct net_device *ndev) 235 { 236 struct temac_local *lp = netdev_priv(ndev); 237 struct sk_buff *skb; 238 int i; 239 240 lp->rx_skb = kcalloc(RX_BD_NUM, sizeof(*lp->rx_skb), GFP_KERNEL); 241 if (!lp->rx_skb) 242 goto out; 243 244 /* allocate the tx and rx ring buffer descriptors. */ 245 /* returns a virtual address and a physical address. */ 246 lp->tx_bd_v = dma_zalloc_coherent(ndev->dev.parent, 247 sizeof(*lp->tx_bd_v) * TX_BD_NUM, 248 &lp->tx_bd_p, GFP_KERNEL); 249 if (!lp->tx_bd_v) 250 goto out; 251 252 lp->rx_bd_v = dma_zalloc_coherent(ndev->dev.parent, 253 sizeof(*lp->rx_bd_v) * RX_BD_NUM, 254 &lp->rx_bd_p, GFP_KERNEL); 255 if (!lp->rx_bd_v) 256 goto out; 257 258 for (i = 0; i < TX_BD_NUM; i++) { 259 lp->tx_bd_v[i].next = lp->tx_bd_p + 260 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM); 261 } 262 263 for (i = 0; i < RX_BD_NUM; i++) { 264 lp->rx_bd_v[i].next = lp->rx_bd_p + 265 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM); 266 267 skb = netdev_alloc_skb_ip_align(ndev, 268 XTE_MAX_JUMBO_FRAME_SIZE); 269 if (!skb) 270 goto out; 271 272 lp->rx_skb[i] = skb; 273 /* returns physical address of skb->data */ 274 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent, 275 skb->data, 276 XTE_MAX_JUMBO_FRAME_SIZE, 277 DMA_FROM_DEVICE); 278 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE; 279 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND; 280 } 281 282 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 | 283 CHNL_CTRL_IRQ_EN | 284 CHNL_CTRL_IRQ_DLY_EN | 285 CHNL_CTRL_IRQ_COAL_EN); 286 /* 0x10220483 */ 287 /* 0x00100483 */ 288 lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 | 289 CHNL_CTRL_IRQ_EN | 290 CHNL_CTRL_IRQ_DLY_EN | 291 CHNL_CTRL_IRQ_COAL_EN | 292 CHNL_CTRL_IRQ_IOE); 293 /* 0xff010283 */ 294 295 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p); 296 lp->dma_out(lp, RX_TAILDESC_PTR, 297 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1))); 298 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p); 299 300 /* Init descriptor indexes */ 301 lp->tx_bd_ci = 0; 302 lp->tx_bd_next = 0; 303 lp->tx_bd_tail = 0; 304 lp->rx_bd_ci = 0; 305 306 return 0; 307 308 out: 309 temac_dma_bd_release(ndev); 310 return -ENOMEM; 311 } 312 313 /* --------------------------------------------------------------------- 314 * net_device_ops 315 */ 316 317 static void temac_do_set_mac_address(struct net_device *ndev) 318 { 319 struct temac_local *lp = netdev_priv(ndev); 320 321 /* set up unicast MAC address filter set its mac address */ 322 mutex_lock(&lp->indirect_mutex); 323 temac_indirect_out32(lp, XTE_UAW0_OFFSET, 324 (ndev->dev_addr[0]) | 325 (ndev->dev_addr[1] << 8) | 326 (ndev->dev_addr[2] << 16) | 327 (ndev->dev_addr[3] << 24)); 328 /* There are reserved bits in EUAW1 329 * so don't affect them Set MAC bits [47:32] in EUAW1 */ 330 temac_indirect_out32(lp, XTE_UAW1_OFFSET, 331 (ndev->dev_addr[4] & 0x000000ff) | 332 (ndev->dev_addr[5] << 8)); 333 mutex_unlock(&lp->indirect_mutex); 334 } 335 336 static int temac_init_mac_address(struct net_device *ndev, const void *address) 337 { 338 memcpy(ndev->dev_addr, address, ETH_ALEN); 339 if (!is_valid_ether_addr(ndev->dev_addr)) 340 eth_hw_addr_random(ndev); 341 temac_do_set_mac_address(ndev); 342 return 0; 343 } 344 345 static int temac_set_mac_address(struct net_device *ndev, void *p) 346 { 347 struct sockaddr *addr = p; 348 349 if (!is_valid_ether_addr(addr->sa_data)) 350 return -EADDRNOTAVAIL; 351 memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN); 352 temac_do_set_mac_address(ndev); 353 return 0; 354 } 355 356 static void temac_set_multicast_list(struct net_device *ndev) 357 { 358 struct temac_local *lp = netdev_priv(ndev); 359 u32 multi_addr_msw, multi_addr_lsw, val; 360 int i; 361 362 mutex_lock(&lp->indirect_mutex); 363 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) || 364 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) { 365 /* 366 * We must make the kernel realise we had to move 367 * into promisc mode or we start all out war on 368 * the cable. If it was a promisc request the 369 * flag is already set. If not we assert it. 370 */ 371 ndev->flags |= IFF_PROMISC; 372 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK); 373 dev_info(&ndev->dev, "Promiscuous mode enabled.\n"); 374 } else if (!netdev_mc_empty(ndev)) { 375 struct netdev_hw_addr *ha; 376 377 i = 0; 378 netdev_for_each_mc_addr(ha, ndev) { 379 if (i >= MULTICAST_CAM_TABLE_NUM) 380 break; 381 multi_addr_msw = ((ha->addr[3] << 24) | 382 (ha->addr[2] << 16) | 383 (ha->addr[1] << 8) | 384 (ha->addr[0])); 385 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 386 multi_addr_msw); 387 multi_addr_lsw = ((ha->addr[5] << 8) | 388 (ha->addr[4]) | (i << 16)); 389 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 390 multi_addr_lsw); 391 i++; 392 } 393 } else { 394 val = temac_indirect_in32(lp, XTE_AFM_OFFSET); 395 temac_indirect_out32(lp, XTE_AFM_OFFSET, 396 val & ~XTE_AFM_EPPRM_MASK); 397 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0); 398 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0); 399 dev_info(&ndev->dev, "Promiscuous mode disabled.\n"); 400 } 401 mutex_unlock(&lp->indirect_mutex); 402 } 403 404 static struct temac_option { 405 int flg; 406 u32 opt; 407 u32 reg; 408 u32 m_or; 409 u32 m_and; 410 } temac_options[] = { 411 /* Turn on jumbo packet support for both Rx and Tx */ 412 { 413 .opt = XTE_OPTION_JUMBO, 414 .reg = XTE_TXC_OFFSET, 415 .m_or = XTE_TXC_TXJMBO_MASK, 416 }, 417 { 418 .opt = XTE_OPTION_JUMBO, 419 .reg = XTE_RXC1_OFFSET, 420 .m_or =XTE_RXC1_RXJMBO_MASK, 421 }, 422 /* Turn on VLAN packet support for both Rx and Tx */ 423 { 424 .opt = XTE_OPTION_VLAN, 425 .reg = XTE_TXC_OFFSET, 426 .m_or =XTE_TXC_TXVLAN_MASK, 427 }, 428 { 429 .opt = XTE_OPTION_VLAN, 430 .reg = XTE_RXC1_OFFSET, 431 .m_or =XTE_RXC1_RXVLAN_MASK, 432 }, 433 /* Turn on FCS stripping on receive packets */ 434 { 435 .opt = XTE_OPTION_FCS_STRIP, 436 .reg = XTE_RXC1_OFFSET, 437 .m_or =XTE_RXC1_RXFCS_MASK, 438 }, 439 /* Turn on FCS insertion on transmit packets */ 440 { 441 .opt = XTE_OPTION_FCS_INSERT, 442 .reg = XTE_TXC_OFFSET, 443 .m_or =XTE_TXC_TXFCS_MASK, 444 }, 445 /* Turn on length/type field checking on receive packets */ 446 { 447 .opt = XTE_OPTION_LENTYPE_ERR, 448 .reg = XTE_RXC1_OFFSET, 449 .m_or =XTE_RXC1_RXLT_MASK, 450 }, 451 /* Turn on flow control */ 452 { 453 .opt = XTE_OPTION_FLOW_CONTROL, 454 .reg = XTE_FCC_OFFSET, 455 .m_or =XTE_FCC_RXFLO_MASK, 456 }, 457 /* Turn on flow control */ 458 { 459 .opt = XTE_OPTION_FLOW_CONTROL, 460 .reg = XTE_FCC_OFFSET, 461 .m_or =XTE_FCC_TXFLO_MASK, 462 }, 463 /* Turn on promiscuous frame filtering (all frames are received ) */ 464 { 465 .opt = XTE_OPTION_PROMISC, 466 .reg = XTE_AFM_OFFSET, 467 .m_or =XTE_AFM_EPPRM_MASK, 468 }, 469 /* Enable transmitter if not already enabled */ 470 { 471 .opt = XTE_OPTION_TXEN, 472 .reg = XTE_TXC_OFFSET, 473 .m_or =XTE_TXC_TXEN_MASK, 474 }, 475 /* Enable receiver? */ 476 { 477 .opt = XTE_OPTION_RXEN, 478 .reg = XTE_RXC1_OFFSET, 479 .m_or =XTE_RXC1_RXEN_MASK, 480 }, 481 {} 482 }; 483 484 /** 485 * temac_setoptions 486 */ 487 static u32 temac_setoptions(struct net_device *ndev, u32 options) 488 { 489 struct temac_local *lp = netdev_priv(ndev); 490 struct temac_option *tp = &temac_options[0]; 491 int reg; 492 493 mutex_lock(&lp->indirect_mutex); 494 while (tp->opt) { 495 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or; 496 if (options & tp->opt) 497 reg |= tp->m_or; 498 temac_indirect_out32(lp, tp->reg, reg); 499 tp++; 500 } 501 lp->options |= options; 502 mutex_unlock(&lp->indirect_mutex); 503 504 return 0; 505 } 506 507 /* Initialize temac */ 508 static void temac_device_reset(struct net_device *ndev) 509 { 510 struct temac_local *lp = netdev_priv(ndev); 511 u32 timeout; 512 u32 val; 513 514 /* Perform a software reset */ 515 516 /* 0x300 host enable bit ? */ 517 /* reset PHY through control register ?:1 */ 518 519 dev_dbg(&ndev->dev, "%s()\n", __func__); 520 521 mutex_lock(&lp->indirect_mutex); 522 /* Reset the receiver and wait for it to finish reset */ 523 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK); 524 timeout = 1000; 525 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) { 526 udelay(1); 527 if (--timeout == 0) { 528 dev_err(&ndev->dev, 529 "temac_device_reset RX reset timeout!!\n"); 530 break; 531 } 532 } 533 534 /* Reset the transmitter and wait for it to finish reset */ 535 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK); 536 timeout = 1000; 537 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) { 538 udelay(1); 539 if (--timeout == 0) { 540 dev_err(&ndev->dev, 541 "temac_device_reset TX reset timeout!!\n"); 542 break; 543 } 544 } 545 546 /* Disable the receiver */ 547 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET); 548 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK); 549 550 /* Reset Local Link (DMA) */ 551 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST); 552 timeout = 1000; 553 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) { 554 udelay(1); 555 if (--timeout == 0) { 556 dev_err(&ndev->dev, 557 "temac_device_reset DMA reset timeout!!\n"); 558 break; 559 } 560 } 561 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE); 562 563 if (temac_dma_bd_init(ndev)) { 564 dev_err(&ndev->dev, 565 "temac_device_reset descriptor allocation failed\n"); 566 } 567 568 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0); 569 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0); 570 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0); 571 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK); 572 573 mutex_unlock(&lp->indirect_mutex); 574 575 /* Sync default options with HW 576 * but leave receiver and transmitter disabled. */ 577 temac_setoptions(ndev, 578 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN)); 579 580 temac_do_set_mac_address(ndev); 581 582 /* Set address filter table */ 583 temac_set_multicast_list(ndev); 584 if (temac_setoptions(ndev, lp->options)) 585 dev_err(&ndev->dev, "Error setting TEMAC options\n"); 586 587 /* Init Driver variable */ 588 netif_trans_update(ndev); /* prevent tx timeout */ 589 } 590 591 static void temac_adjust_link(struct net_device *ndev) 592 { 593 struct temac_local *lp = netdev_priv(ndev); 594 struct phy_device *phy = ndev->phydev; 595 u32 mii_speed; 596 int link_state; 597 598 /* hash together the state values to decide if something has changed */ 599 link_state = phy->speed | (phy->duplex << 1) | phy->link; 600 601 mutex_lock(&lp->indirect_mutex); 602 if (lp->last_link != link_state) { 603 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET); 604 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK; 605 606 switch (phy->speed) { 607 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break; 608 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break; 609 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break; 610 } 611 612 /* Write new speed setting out to TEMAC */ 613 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed); 614 lp->last_link = link_state; 615 phy_print_status(phy); 616 } 617 mutex_unlock(&lp->indirect_mutex); 618 } 619 620 static void temac_start_xmit_done(struct net_device *ndev) 621 { 622 struct temac_local *lp = netdev_priv(ndev); 623 struct cdmac_bd *cur_p; 624 unsigned int stat = 0; 625 626 cur_p = &lp->tx_bd_v[lp->tx_bd_ci]; 627 stat = cur_p->app0; 628 629 while (stat & STS_CTRL_APP0_CMPLT) { 630 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len, 631 DMA_TO_DEVICE); 632 if (cur_p->app4) 633 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4); 634 cur_p->app0 = 0; 635 cur_p->app1 = 0; 636 cur_p->app2 = 0; 637 cur_p->app3 = 0; 638 cur_p->app4 = 0; 639 640 ndev->stats.tx_packets++; 641 ndev->stats.tx_bytes += cur_p->len; 642 643 lp->tx_bd_ci++; 644 if (lp->tx_bd_ci >= TX_BD_NUM) 645 lp->tx_bd_ci = 0; 646 647 cur_p = &lp->tx_bd_v[lp->tx_bd_ci]; 648 stat = cur_p->app0; 649 } 650 651 netif_wake_queue(ndev); 652 } 653 654 static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag) 655 { 656 struct cdmac_bd *cur_p; 657 int tail; 658 659 tail = lp->tx_bd_tail; 660 cur_p = &lp->tx_bd_v[tail]; 661 662 do { 663 if (cur_p->app0) 664 return NETDEV_TX_BUSY; 665 666 tail++; 667 if (tail >= TX_BD_NUM) 668 tail = 0; 669 670 cur_p = &lp->tx_bd_v[tail]; 671 num_frag--; 672 } while (num_frag >= 0); 673 674 return 0; 675 } 676 677 static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev) 678 { 679 struct temac_local *lp = netdev_priv(ndev); 680 struct cdmac_bd *cur_p; 681 dma_addr_t start_p, tail_p; 682 int ii; 683 unsigned long num_frag; 684 skb_frag_t *frag; 685 686 num_frag = skb_shinfo(skb)->nr_frags; 687 frag = &skb_shinfo(skb)->frags[0]; 688 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail; 689 cur_p = &lp->tx_bd_v[lp->tx_bd_tail]; 690 691 if (temac_check_tx_bd_space(lp, num_frag)) { 692 if (!netif_queue_stopped(ndev)) 693 netif_stop_queue(ndev); 694 return NETDEV_TX_BUSY; 695 } 696 697 cur_p->app0 = 0; 698 if (skb->ip_summed == CHECKSUM_PARTIAL) { 699 unsigned int csum_start_off = skb_checksum_start_offset(skb); 700 unsigned int csum_index_off = csum_start_off + skb->csum_offset; 701 702 cur_p->app0 |= 1; /* TX Checksum Enabled */ 703 cur_p->app1 = (csum_start_off << 16) | csum_index_off; 704 cur_p->app2 = 0; /* initial checksum seed */ 705 } 706 707 cur_p->app0 |= STS_CTRL_APP0_SOP; 708 cur_p->len = skb_headlen(skb); 709 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data, 710 skb_headlen(skb), DMA_TO_DEVICE); 711 cur_p->app4 = (unsigned long)skb; 712 713 for (ii = 0; ii < num_frag; ii++) { 714 lp->tx_bd_tail++; 715 if (lp->tx_bd_tail >= TX_BD_NUM) 716 lp->tx_bd_tail = 0; 717 718 cur_p = &lp->tx_bd_v[lp->tx_bd_tail]; 719 cur_p->phys = dma_map_single(ndev->dev.parent, 720 skb_frag_address(frag), 721 skb_frag_size(frag), DMA_TO_DEVICE); 722 cur_p->len = skb_frag_size(frag); 723 cur_p->app0 = 0; 724 frag++; 725 } 726 cur_p->app0 |= STS_CTRL_APP0_EOP; 727 728 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail; 729 lp->tx_bd_tail++; 730 if (lp->tx_bd_tail >= TX_BD_NUM) 731 lp->tx_bd_tail = 0; 732 733 skb_tx_timestamp(skb); 734 735 /* Kick off the transfer */ 736 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */ 737 738 return NETDEV_TX_OK; 739 } 740 741 742 static void ll_temac_recv(struct net_device *ndev) 743 { 744 struct temac_local *lp = netdev_priv(ndev); 745 struct sk_buff *skb, *new_skb; 746 unsigned int bdstat; 747 struct cdmac_bd *cur_p; 748 dma_addr_t tail_p; 749 int length; 750 unsigned long flags; 751 752 spin_lock_irqsave(&lp->rx_lock, flags); 753 754 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci; 755 cur_p = &lp->rx_bd_v[lp->rx_bd_ci]; 756 757 bdstat = cur_p->app0; 758 while ((bdstat & STS_CTRL_APP0_CMPLT)) { 759 760 skb = lp->rx_skb[lp->rx_bd_ci]; 761 length = cur_p->app4 & 0x3FFF; 762 763 dma_unmap_single(ndev->dev.parent, cur_p->phys, length, 764 DMA_FROM_DEVICE); 765 766 skb_put(skb, length); 767 skb->protocol = eth_type_trans(skb, ndev); 768 skb_checksum_none_assert(skb); 769 770 /* if we're doing rx csum offload, set it up */ 771 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) && 772 (skb->protocol == htons(ETH_P_IP)) && 773 (skb->len > 64)) { 774 775 skb->csum = cur_p->app3 & 0xFFFF; 776 skb->ip_summed = CHECKSUM_COMPLETE; 777 } 778 779 if (!skb_defer_rx_timestamp(skb)) 780 netif_rx(skb); 781 782 ndev->stats.rx_packets++; 783 ndev->stats.rx_bytes += length; 784 785 new_skb = netdev_alloc_skb_ip_align(ndev, 786 XTE_MAX_JUMBO_FRAME_SIZE); 787 if (!new_skb) { 788 spin_unlock_irqrestore(&lp->rx_lock, flags); 789 return; 790 } 791 792 cur_p->app0 = STS_CTRL_APP0_IRQONEND; 793 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data, 794 XTE_MAX_JUMBO_FRAME_SIZE, 795 DMA_FROM_DEVICE); 796 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE; 797 lp->rx_skb[lp->rx_bd_ci] = new_skb; 798 799 lp->rx_bd_ci++; 800 if (lp->rx_bd_ci >= RX_BD_NUM) 801 lp->rx_bd_ci = 0; 802 803 cur_p = &lp->rx_bd_v[lp->rx_bd_ci]; 804 bdstat = cur_p->app0; 805 } 806 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p); 807 808 spin_unlock_irqrestore(&lp->rx_lock, flags); 809 } 810 811 static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev) 812 { 813 struct net_device *ndev = _ndev; 814 struct temac_local *lp = netdev_priv(ndev); 815 unsigned int status; 816 817 status = lp->dma_in(lp, TX_IRQ_REG); 818 lp->dma_out(lp, TX_IRQ_REG, status); 819 820 if (status & (IRQ_COAL | IRQ_DLY)) 821 temac_start_xmit_done(lp->ndev); 822 if (status & 0x080) 823 dev_err(&ndev->dev, "DMA error 0x%x\n", status); 824 825 return IRQ_HANDLED; 826 } 827 828 static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev) 829 { 830 struct net_device *ndev = _ndev; 831 struct temac_local *lp = netdev_priv(ndev); 832 unsigned int status; 833 834 /* Read and clear the status registers */ 835 status = lp->dma_in(lp, RX_IRQ_REG); 836 lp->dma_out(lp, RX_IRQ_REG, status); 837 838 if (status & (IRQ_COAL | IRQ_DLY)) 839 ll_temac_recv(lp->ndev); 840 841 return IRQ_HANDLED; 842 } 843 844 static int temac_open(struct net_device *ndev) 845 { 846 struct temac_local *lp = netdev_priv(ndev); 847 struct phy_device *phydev = NULL; 848 int rc; 849 850 dev_dbg(&ndev->dev, "temac_open()\n"); 851 852 if (lp->phy_node) { 853 phydev = of_phy_connect(lp->ndev, lp->phy_node, 854 temac_adjust_link, 0, 0); 855 if (!phydev) { 856 dev_err(lp->dev, "of_phy_connect() failed\n"); 857 return -ENODEV; 858 } 859 860 phy_start(phydev); 861 } 862 863 temac_device_reset(ndev); 864 865 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev); 866 if (rc) 867 goto err_tx_irq; 868 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev); 869 if (rc) 870 goto err_rx_irq; 871 872 return 0; 873 874 err_rx_irq: 875 free_irq(lp->tx_irq, ndev); 876 err_tx_irq: 877 if (phydev) 878 phy_disconnect(phydev); 879 dev_err(lp->dev, "request_irq() failed\n"); 880 return rc; 881 } 882 883 static int temac_stop(struct net_device *ndev) 884 { 885 struct temac_local *lp = netdev_priv(ndev); 886 struct phy_device *phydev = ndev->phydev; 887 888 dev_dbg(&ndev->dev, "temac_close()\n"); 889 890 free_irq(lp->tx_irq, ndev); 891 free_irq(lp->rx_irq, ndev); 892 893 if (phydev) 894 phy_disconnect(phydev); 895 896 temac_dma_bd_release(ndev); 897 898 return 0; 899 } 900 901 #ifdef CONFIG_NET_POLL_CONTROLLER 902 static void 903 temac_poll_controller(struct net_device *ndev) 904 { 905 struct temac_local *lp = netdev_priv(ndev); 906 907 disable_irq(lp->tx_irq); 908 disable_irq(lp->rx_irq); 909 910 ll_temac_rx_irq(lp->tx_irq, ndev); 911 ll_temac_tx_irq(lp->rx_irq, ndev); 912 913 enable_irq(lp->tx_irq); 914 enable_irq(lp->rx_irq); 915 } 916 #endif 917 918 static int temac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 919 { 920 if (!netif_running(ndev)) 921 return -EINVAL; 922 923 if (!ndev->phydev) 924 return -EINVAL; 925 926 return phy_mii_ioctl(ndev->phydev, rq, cmd); 927 } 928 929 static const struct net_device_ops temac_netdev_ops = { 930 .ndo_open = temac_open, 931 .ndo_stop = temac_stop, 932 .ndo_start_xmit = temac_start_xmit, 933 .ndo_set_mac_address = temac_set_mac_address, 934 .ndo_validate_addr = eth_validate_addr, 935 .ndo_do_ioctl = temac_ioctl, 936 #ifdef CONFIG_NET_POLL_CONTROLLER 937 .ndo_poll_controller = temac_poll_controller, 938 #endif 939 }; 940 941 /* --------------------------------------------------------------------- 942 * SYSFS device attributes 943 */ 944 static ssize_t temac_show_llink_regs(struct device *dev, 945 struct device_attribute *attr, char *buf) 946 { 947 struct net_device *ndev = dev_get_drvdata(dev); 948 struct temac_local *lp = netdev_priv(ndev); 949 int i, len = 0; 950 951 for (i = 0; i < 0x11; i++) 952 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i), 953 (i % 8) == 7 ? "\n" : " "); 954 len += sprintf(buf + len, "\n"); 955 956 return len; 957 } 958 959 static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL); 960 961 static struct attribute *temac_device_attrs[] = { 962 &dev_attr_llink_regs.attr, 963 NULL, 964 }; 965 966 static const struct attribute_group temac_attr_group = { 967 .attrs = temac_device_attrs, 968 }; 969 970 /* ethtool support */ 971 static const struct ethtool_ops temac_ethtool_ops = { 972 .nway_reset = phy_ethtool_nway_reset, 973 .get_link = ethtool_op_get_link, 974 .get_ts_info = ethtool_op_get_ts_info, 975 .get_link_ksettings = phy_ethtool_get_link_ksettings, 976 .set_link_ksettings = phy_ethtool_set_link_ksettings, 977 }; 978 979 static int temac_of_probe(struct platform_device *op) 980 { 981 struct device_node *np; 982 struct temac_local *lp; 983 struct net_device *ndev; 984 const void *addr; 985 __be32 *p; 986 int rc = 0; 987 988 /* Init network device structure */ 989 ndev = alloc_etherdev(sizeof(*lp)); 990 if (!ndev) 991 return -ENOMEM; 992 993 platform_set_drvdata(op, ndev); 994 SET_NETDEV_DEV(ndev, &op->dev); 995 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */ 996 ndev->features = NETIF_F_SG; 997 ndev->netdev_ops = &temac_netdev_ops; 998 ndev->ethtool_ops = &temac_ethtool_ops; 999 #if 0 1000 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */ 1001 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */ 1002 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */ 1003 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */ 1004 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; /* Transmit VLAN hw accel */ 1005 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; /* Receive VLAN hw acceleration */ 1006 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; /* Receive VLAN filtering */ 1007 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */ 1008 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */ 1009 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */ 1010 ndev->features |= NETIF_F_LRO; /* large receive offload */ 1011 #endif 1012 1013 /* setup temac private info structure */ 1014 lp = netdev_priv(ndev); 1015 lp->ndev = ndev; 1016 lp->dev = &op->dev; 1017 lp->options = XTE_OPTION_DEFAULTS; 1018 spin_lock_init(&lp->rx_lock); 1019 mutex_init(&lp->indirect_mutex); 1020 1021 /* map device registers */ 1022 lp->regs = of_iomap(op->dev.of_node, 0); 1023 if (!lp->regs) { 1024 dev_err(&op->dev, "could not map temac regs.\n"); 1025 rc = -ENOMEM; 1026 goto nodev; 1027 } 1028 1029 /* Setup checksum offload, but default to off if not specified */ 1030 lp->temac_features = 0; 1031 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL); 1032 if (p && be32_to_cpu(*p)) { 1033 lp->temac_features |= TEMAC_FEATURE_TX_CSUM; 1034 /* Can checksum TCP/UDP over IPv4. */ 1035 ndev->features |= NETIF_F_IP_CSUM; 1036 } 1037 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL); 1038 if (p && be32_to_cpu(*p)) 1039 lp->temac_features |= TEMAC_FEATURE_RX_CSUM; 1040 1041 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */ 1042 np = of_parse_phandle(op->dev.of_node, "llink-connected", 0); 1043 if (!np) { 1044 dev_err(&op->dev, "could not find DMA node\n"); 1045 rc = -ENODEV; 1046 goto err_iounmap; 1047 } 1048 1049 /* Setup the DMA register accesses, could be DCR or memory mapped */ 1050 if (temac_dcr_setup(lp, op, np)) { 1051 1052 /* no DCR in the device tree, try non-DCR */ 1053 lp->sdma_regs = of_iomap(np, 0); 1054 if (lp->sdma_regs) { 1055 lp->dma_in = temac_dma_in32; 1056 lp->dma_out = temac_dma_out32; 1057 dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs); 1058 } else { 1059 dev_err(&op->dev, "unable to map DMA registers\n"); 1060 of_node_put(np); 1061 goto err_iounmap; 1062 } 1063 } 1064 1065 lp->rx_irq = irq_of_parse_and_map(np, 0); 1066 lp->tx_irq = irq_of_parse_and_map(np, 1); 1067 1068 of_node_put(np); /* Finished with the DMA node; drop the reference */ 1069 1070 if (!lp->rx_irq || !lp->tx_irq) { 1071 dev_err(&op->dev, "could not determine irqs\n"); 1072 rc = -ENOMEM; 1073 goto err_iounmap_2; 1074 } 1075 1076 1077 /* Retrieve the MAC address */ 1078 addr = of_get_mac_address(op->dev.of_node); 1079 if (!addr) { 1080 dev_err(&op->dev, "could not find MAC address\n"); 1081 rc = -ENODEV; 1082 goto err_iounmap_2; 1083 } 1084 temac_init_mac_address(ndev, addr); 1085 1086 rc = temac_mdio_setup(lp, op->dev.of_node); 1087 if (rc) 1088 dev_warn(&op->dev, "error registering MDIO bus\n"); 1089 1090 lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0); 1091 if (lp->phy_node) 1092 dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np); 1093 1094 /* Add the device attributes */ 1095 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group); 1096 if (rc) { 1097 dev_err(lp->dev, "Error creating sysfs files\n"); 1098 goto err_iounmap_2; 1099 } 1100 1101 rc = register_netdev(lp->ndev); 1102 if (rc) { 1103 dev_err(lp->dev, "register_netdev() error (%i)\n", rc); 1104 goto err_register_ndev; 1105 } 1106 1107 return 0; 1108 1109 err_register_ndev: 1110 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group); 1111 err_iounmap_2: 1112 if (lp->sdma_regs) 1113 iounmap(lp->sdma_regs); 1114 err_iounmap: 1115 iounmap(lp->regs); 1116 nodev: 1117 free_netdev(ndev); 1118 ndev = NULL; 1119 return rc; 1120 } 1121 1122 static int temac_of_remove(struct platform_device *op) 1123 { 1124 struct net_device *ndev = platform_get_drvdata(op); 1125 struct temac_local *lp = netdev_priv(ndev); 1126 1127 temac_mdio_teardown(lp); 1128 unregister_netdev(ndev); 1129 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group); 1130 of_node_put(lp->phy_node); 1131 lp->phy_node = NULL; 1132 iounmap(lp->regs); 1133 if (lp->sdma_regs) 1134 iounmap(lp->sdma_regs); 1135 free_netdev(ndev); 1136 return 0; 1137 } 1138 1139 static const struct of_device_id temac_of_match[] = { 1140 { .compatible = "xlnx,xps-ll-temac-1.01.b", }, 1141 { .compatible = "xlnx,xps-ll-temac-2.00.a", }, 1142 { .compatible = "xlnx,xps-ll-temac-2.02.a", }, 1143 { .compatible = "xlnx,xps-ll-temac-2.03.a", }, 1144 {}, 1145 }; 1146 MODULE_DEVICE_TABLE(of, temac_of_match); 1147 1148 static struct platform_driver temac_of_driver = { 1149 .probe = temac_of_probe, 1150 .remove = temac_of_remove, 1151 .driver = { 1152 .name = "xilinx_temac", 1153 .of_match_table = temac_of_match, 1154 }, 1155 }; 1156 1157 module_platform_driver(temac_of_driver); 1158 1159 MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver"); 1160 MODULE_AUTHOR("Yoshio Kashiwagi"); 1161 MODULE_LICENSE("GPL"); 1162