1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for Xilinx TEMAC Ethernet device 4 * 5 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi 6 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net> 7 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd. 8 * 9 * This is a driver for the Xilinx ll_temac ipcore which is often used 10 * in the Virtex and Spartan series of chips. 11 * 12 * Notes: 13 * - The ll_temac hardware uses indirect access for many of the TEMAC 14 * registers, include the MDIO bus. However, indirect access to MDIO 15 * registers take considerably more clock cycles than to TEMAC registers. 16 * MDIO accesses are long, so threads doing them should probably sleep 17 * rather than busywait. However, since only one indirect access can be 18 * in progress at any given time, that means that *all* indirect accesses 19 * could end up sleeping (to wait for an MDIO access to complete). 20 * Fortunately none of the indirect accesses are on the 'hot' path for tx 21 * or rx, so this should be okay. 22 * 23 * TODO: 24 * - Factor out locallink DMA code into separate driver 25 * - Fix multicast assignment. 26 * - Fix support for hardware checksumming. 27 * - Testing. Lots and lots of testing. 28 * 29 */ 30 31 #include <linux/delay.h> 32 #include <linux/etherdevice.h> 33 #include <linux/mii.h> 34 #include <linux/module.h> 35 #include <linux/mutex.h> 36 #include <linux/netdevice.h> 37 #include <linux/if_ether.h> 38 #include <linux/of.h> 39 #include <linux/of_device.h> 40 #include <linux/of_irq.h> 41 #include <linux/of_mdio.h> 42 #include <linux/of_net.h> 43 #include <linux/of_platform.h> 44 #include <linux/of_address.h> 45 #include <linux/skbuff.h> 46 #include <linux/spinlock.h> 47 #include <linux/tcp.h> /* needed for sizeof(tcphdr) */ 48 #include <linux/udp.h> /* needed for sizeof(udphdr) */ 49 #include <linux/phy.h> 50 #include <linux/in.h> 51 #include <linux/io.h> 52 #include <linux/ip.h> 53 #include <linux/slab.h> 54 #include <linux/interrupt.h> 55 #include <linux/dma-mapping.h> 56 #include <linux/platform_data/xilinx-ll-temac.h> 57 58 #include "ll_temac.h" 59 60 #define TX_BD_NUM 64 61 #define RX_BD_NUM 128 62 63 /* --------------------------------------------------------------------- 64 * Low level register access functions 65 */ 66 67 static u32 _temac_ior_be(struct temac_local *lp, int offset) 68 { 69 return ioread32be(lp->regs + offset); 70 } 71 72 static void _temac_iow_be(struct temac_local *lp, int offset, u32 value) 73 { 74 return iowrite32be(value, lp->regs + offset); 75 } 76 77 static u32 _temac_ior_le(struct temac_local *lp, int offset) 78 { 79 return ioread32(lp->regs + offset); 80 } 81 82 static void _temac_iow_le(struct temac_local *lp, int offset, u32 value) 83 { 84 return iowrite32(value, lp->regs + offset); 85 } 86 87 int temac_indirect_busywait(struct temac_local *lp) 88 { 89 unsigned long end = jiffies + 2; 90 91 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) { 92 if (time_before_eq(end, jiffies)) { 93 WARN_ON(1); 94 return -ETIMEDOUT; 95 } 96 usleep_range(500, 1000); 97 } 98 return 0; 99 } 100 101 /** 102 * temac_indirect_in32 103 * 104 * lp->indirect_mutex must be held when calling this function 105 */ 106 u32 temac_indirect_in32(struct temac_local *lp, int reg) 107 { 108 u32 val; 109 110 if (temac_indirect_busywait(lp)) 111 return -ETIMEDOUT; 112 temac_iow(lp, XTE_CTL0_OFFSET, reg); 113 if (temac_indirect_busywait(lp)) 114 return -ETIMEDOUT; 115 val = temac_ior(lp, XTE_LSW0_OFFSET); 116 117 return val; 118 } 119 120 /** 121 * temac_indirect_out32 122 * 123 * lp->indirect_mutex must be held when calling this function 124 */ 125 void temac_indirect_out32(struct temac_local *lp, int reg, u32 value) 126 { 127 if (temac_indirect_busywait(lp)) 128 return; 129 temac_iow(lp, XTE_LSW0_OFFSET, value); 130 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg); 131 temac_indirect_busywait(lp); 132 } 133 134 /** 135 * temac_dma_in32_* - Memory mapped DMA read, these function expects a 136 * register input that is based on DCR word addresses which are then 137 * converted to memory mapped byte addresses. To be assigned to 138 * lp->dma_in32. 139 */ 140 static u32 temac_dma_in32_be(struct temac_local *lp, int reg) 141 { 142 return ioread32be(lp->sdma_regs + (reg << 2)); 143 } 144 145 static u32 temac_dma_in32_le(struct temac_local *lp, int reg) 146 { 147 return ioread32(lp->sdma_regs + (reg << 2)); 148 } 149 150 /** 151 * temac_dma_out32_* - Memory mapped DMA read, these function expects 152 * a register input that is based on DCR word addresses which are then 153 * converted to memory mapped byte addresses. To be assigned to 154 * lp->dma_out32. 155 */ 156 static void temac_dma_out32_be(struct temac_local *lp, int reg, u32 value) 157 { 158 iowrite32be(value, lp->sdma_regs + (reg << 2)); 159 } 160 161 static void temac_dma_out32_le(struct temac_local *lp, int reg, u32 value) 162 { 163 iowrite32(value, lp->sdma_regs + (reg << 2)); 164 } 165 166 /* DMA register access functions can be DCR based or memory mapped. 167 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both 168 * memory mapped. 169 */ 170 #ifdef CONFIG_PPC_DCR 171 172 /** 173 * temac_dma_dcr_in32 - DCR based DMA read 174 */ 175 static u32 temac_dma_dcr_in(struct temac_local *lp, int reg) 176 { 177 return dcr_read(lp->sdma_dcrs, reg); 178 } 179 180 /** 181 * temac_dma_dcr_out32 - DCR based DMA write 182 */ 183 static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value) 184 { 185 dcr_write(lp->sdma_dcrs, reg, value); 186 } 187 188 /** 189 * temac_dcr_setup - If the DMA is DCR based, then setup the address and 190 * I/O functions 191 */ 192 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op, 193 struct device_node *np) 194 { 195 unsigned int dcrs; 196 197 /* setup the dcr address mapping if it's in the device tree */ 198 199 dcrs = dcr_resource_start(np, 0); 200 if (dcrs != 0) { 201 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0)); 202 lp->dma_in = temac_dma_dcr_in; 203 lp->dma_out = temac_dma_dcr_out; 204 dev_dbg(&op->dev, "DCR base: %x\n", dcrs); 205 return 0; 206 } 207 /* no DCR in the device tree, indicate a failure */ 208 return -1; 209 } 210 211 #else 212 213 /* 214 * temac_dcr_setup - This is a stub for when DCR is not supported, 215 * such as with MicroBlaze and x86 216 */ 217 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op, 218 struct device_node *np) 219 { 220 return -1; 221 } 222 223 #endif 224 225 /** 226 * temac_dma_bd_release - Release buffer descriptor rings 227 */ 228 static void temac_dma_bd_release(struct net_device *ndev) 229 { 230 struct temac_local *lp = netdev_priv(ndev); 231 int i; 232 233 /* Reset Local Link (DMA) */ 234 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST); 235 236 for (i = 0; i < RX_BD_NUM; i++) { 237 if (!lp->rx_skb[i]) 238 break; 239 else { 240 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys, 241 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE); 242 dev_kfree_skb(lp->rx_skb[i]); 243 } 244 } 245 if (lp->rx_bd_v) 246 dma_free_coherent(ndev->dev.parent, 247 sizeof(*lp->rx_bd_v) * RX_BD_NUM, 248 lp->rx_bd_v, lp->rx_bd_p); 249 if (lp->tx_bd_v) 250 dma_free_coherent(ndev->dev.parent, 251 sizeof(*lp->tx_bd_v) * TX_BD_NUM, 252 lp->tx_bd_v, lp->tx_bd_p); 253 } 254 255 /** 256 * temac_dma_bd_init - Setup buffer descriptor rings 257 */ 258 static int temac_dma_bd_init(struct net_device *ndev) 259 { 260 struct temac_local *lp = netdev_priv(ndev); 261 struct sk_buff *skb; 262 dma_addr_t skb_dma_addr; 263 int i; 264 265 lp->rx_skb = devm_kcalloc(&ndev->dev, RX_BD_NUM, sizeof(*lp->rx_skb), 266 GFP_KERNEL); 267 if (!lp->rx_skb) 268 goto out; 269 270 /* allocate the tx and rx ring buffer descriptors. */ 271 /* returns a virtual address and a physical address. */ 272 lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent, 273 sizeof(*lp->tx_bd_v) * TX_BD_NUM, 274 &lp->tx_bd_p, GFP_KERNEL); 275 if (!lp->tx_bd_v) 276 goto out; 277 278 lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent, 279 sizeof(*lp->rx_bd_v) * RX_BD_NUM, 280 &lp->rx_bd_p, GFP_KERNEL); 281 if (!lp->rx_bd_v) 282 goto out; 283 284 for (i = 0; i < TX_BD_NUM; i++) { 285 lp->tx_bd_v[i].next = cpu_to_be32(lp->tx_bd_p 286 + sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM)); 287 } 288 289 for (i = 0; i < RX_BD_NUM; i++) { 290 lp->rx_bd_v[i].next = cpu_to_be32(lp->rx_bd_p 291 + sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM)); 292 293 skb = netdev_alloc_skb_ip_align(ndev, 294 XTE_MAX_JUMBO_FRAME_SIZE); 295 if (!skb) 296 goto out; 297 298 lp->rx_skb[i] = skb; 299 /* returns physical address of skb->data */ 300 skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data, 301 XTE_MAX_JUMBO_FRAME_SIZE, 302 DMA_FROM_DEVICE); 303 lp->rx_bd_v[i].phys = cpu_to_be32(skb_dma_addr); 304 lp->rx_bd_v[i].len = cpu_to_be32(XTE_MAX_JUMBO_FRAME_SIZE); 305 lp->rx_bd_v[i].app0 = cpu_to_be32(STS_CTRL_APP0_IRQONEND); 306 } 307 308 /* Configure DMA channel (irq setup) */ 309 lp->dma_out(lp, TX_CHNL_CTRL, lp->tx_chnl_ctrl | 310 0x00000400 | // Use 1 Bit Wide Counters. Currently Not Used! 311 CHNL_CTRL_IRQ_EN | CHNL_CTRL_IRQ_ERR_EN | 312 CHNL_CTRL_IRQ_DLY_EN | CHNL_CTRL_IRQ_COAL_EN); 313 lp->dma_out(lp, RX_CHNL_CTRL, lp->rx_chnl_ctrl | 314 CHNL_CTRL_IRQ_IOE | 315 CHNL_CTRL_IRQ_EN | CHNL_CTRL_IRQ_ERR_EN | 316 CHNL_CTRL_IRQ_DLY_EN | CHNL_CTRL_IRQ_COAL_EN); 317 318 /* Init descriptor indexes */ 319 lp->tx_bd_ci = 0; 320 lp->tx_bd_next = 0; 321 lp->tx_bd_tail = 0; 322 lp->rx_bd_ci = 0; 323 324 /* Enable RX DMA transfers */ 325 wmb(); 326 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p); 327 lp->dma_out(lp, RX_TAILDESC_PTR, 328 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1))); 329 330 /* Prepare for TX DMA transfer */ 331 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p); 332 333 return 0; 334 335 out: 336 temac_dma_bd_release(ndev); 337 return -ENOMEM; 338 } 339 340 /* --------------------------------------------------------------------- 341 * net_device_ops 342 */ 343 344 static void temac_do_set_mac_address(struct net_device *ndev) 345 { 346 struct temac_local *lp = netdev_priv(ndev); 347 348 /* set up unicast MAC address filter set its mac address */ 349 mutex_lock(lp->indirect_mutex); 350 temac_indirect_out32(lp, XTE_UAW0_OFFSET, 351 (ndev->dev_addr[0]) | 352 (ndev->dev_addr[1] << 8) | 353 (ndev->dev_addr[2] << 16) | 354 (ndev->dev_addr[3] << 24)); 355 /* There are reserved bits in EUAW1 356 * so don't affect them Set MAC bits [47:32] in EUAW1 */ 357 temac_indirect_out32(lp, XTE_UAW1_OFFSET, 358 (ndev->dev_addr[4] & 0x000000ff) | 359 (ndev->dev_addr[5] << 8)); 360 mutex_unlock(lp->indirect_mutex); 361 } 362 363 static int temac_init_mac_address(struct net_device *ndev, const void *address) 364 { 365 ether_addr_copy(ndev->dev_addr, address); 366 if (!is_valid_ether_addr(ndev->dev_addr)) 367 eth_hw_addr_random(ndev); 368 temac_do_set_mac_address(ndev); 369 return 0; 370 } 371 372 static int temac_set_mac_address(struct net_device *ndev, void *p) 373 { 374 struct sockaddr *addr = p; 375 376 if (!is_valid_ether_addr(addr->sa_data)) 377 return -EADDRNOTAVAIL; 378 memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN); 379 temac_do_set_mac_address(ndev); 380 return 0; 381 } 382 383 static void temac_set_multicast_list(struct net_device *ndev) 384 { 385 struct temac_local *lp = netdev_priv(ndev); 386 u32 multi_addr_msw, multi_addr_lsw, val; 387 int i; 388 389 mutex_lock(lp->indirect_mutex); 390 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) || 391 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) { 392 /* 393 * We must make the kernel realise we had to move 394 * into promisc mode or we start all out war on 395 * the cable. If it was a promisc request the 396 * flag is already set. If not we assert it. 397 */ 398 ndev->flags |= IFF_PROMISC; 399 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK); 400 dev_info(&ndev->dev, "Promiscuous mode enabled.\n"); 401 } else if (!netdev_mc_empty(ndev)) { 402 struct netdev_hw_addr *ha; 403 404 i = 0; 405 netdev_for_each_mc_addr(ha, ndev) { 406 if (i >= MULTICAST_CAM_TABLE_NUM) 407 break; 408 multi_addr_msw = ((ha->addr[3] << 24) | 409 (ha->addr[2] << 16) | 410 (ha->addr[1] << 8) | 411 (ha->addr[0])); 412 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 413 multi_addr_msw); 414 multi_addr_lsw = ((ha->addr[5] << 8) | 415 (ha->addr[4]) | (i << 16)); 416 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 417 multi_addr_lsw); 418 i++; 419 } 420 } else { 421 val = temac_indirect_in32(lp, XTE_AFM_OFFSET); 422 temac_indirect_out32(lp, XTE_AFM_OFFSET, 423 val & ~XTE_AFM_EPPRM_MASK); 424 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0); 425 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0); 426 dev_info(&ndev->dev, "Promiscuous mode disabled.\n"); 427 } 428 mutex_unlock(lp->indirect_mutex); 429 } 430 431 static struct temac_option { 432 int flg; 433 u32 opt; 434 u32 reg; 435 u32 m_or; 436 u32 m_and; 437 } temac_options[] = { 438 /* Turn on jumbo packet support for both Rx and Tx */ 439 { 440 .opt = XTE_OPTION_JUMBO, 441 .reg = XTE_TXC_OFFSET, 442 .m_or = XTE_TXC_TXJMBO_MASK, 443 }, 444 { 445 .opt = XTE_OPTION_JUMBO, 446 .reg = XTE_RXC1_OFFSET, 447 .m_or =XTE_RXC1_RXJMBO_MASK, 448 }, 449 /* Turn on VLAN packet support for both Rx and Tx */ 450 { 451 .opt = XTE_OPTION_VLAN, 452 .reg = XTE_TXC_OFFSET, 453 .m_or =XTE_TXC_TXVLAN_MASK, 454 }, 455 { 456 .opt = XTE_OPTION_VLAN, 457 .reg = XTE_RXC1_OFFSET, 458 .m_or =XTE_RXC1_RXVLAN_MASK, 459 }, 460 /* Turn on FCS stripping on receive packets */ 461 { 462 .opt = XTE_OPTION_FCS_STRIP, 463 .reg = XTE_RXC1_OFFSET, 464 .m_or =XTE_RXC1_RXFCS_MASK, 465 }, 466 /* Turn on FCS insertion on transmit packets */ 467 { 468 .opt = XTE_OPTION_FCS_INSERT, 469 .reg = XTE_TXC_OFFSET, 470 .m_or =XTE_TXC_TXFCS_MASK, 471 }, 472 /* Turn on length/type field checking on receive packets */ 473 { 474 .opt = XTE_OPTION_LENTYPE_ERR, 475 .reg = XTE_RXC1_OFFSET, 476 .m_or =XTE_RXC1_RXLT_MASK, 477 }, 478 /* Turn on flow control */ 479 { 480 .opt = XTE_OPTION_FLOW_CONTROL, 481 .reg = XTE_FCC_OFFSET, 482 .m_or =XTE_FCC_RXFLO_MASK, 483 }, 484 /* Turn on flow control */ 485 { 486 .opt = XTE_OPTION_FLOW_CONTROL, 487 .reg = XTE_FCC_OFFSET, 488 .m_or =XTE_FCC_TXFLO_MASK, 489 }, 490 /* Turn on promiscuous frame filtering (all frames are received ) */ 491 { 492 .opt = XTE_OPTION_PROMISC, 493 .reg = XTE_AFM_OFFSET, 494 .m_or =XTE_AFM_EPPRM_MASK, 495 }, 496 /* Enable transmitter if not already enabled */ 497 { 498 .opt = XTE_OPTION_TXEN, 499 .reg = XTE_TXC_OFFSET, 500 .m_or =XTE_TXC_TXEN_MASK, 501 }, 502 /* Enable receiver? */ 503 { 504 .opt = XTE_OPTION_RXEN, 505 .reg = XTE_RXC1_OFFSET, 506 .m_or =XTE_RXC1_RXEN_MASK, 507 }, 508 {} 509 }; 510 511 /** 512 * temac_setoptions 513 */ 514 static u32 temac_setoptions(struct net_device *ndev, u32 options) 515 { 516 struct temac_local *lp = netdev_priv(ndev); 517 struct temac_option *tp = &temac_options[0]; 518 int reg; 519 520 mutex_lock(lp->indirect_mutex); 521 while (tp->opt) { 522 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or; 523 if (options & tp->opt) 524 reg |= tp->m_or; 525 temac_indirect_out32(lp, tp->reg, reg); 526 tp++; 527 } 528 lp->options |= options; 529 mutex_unlock(lp->indirect_mutex); 530 531 return 0; 532 } 533 534 /* Initialize temac */ 535 static void temac_device_reset(struct net_device *ndev) 536 { 537 struct temac_local *lp = netdev_priv(ndev); 538 u32 timeout; 539 u32 val; 540 541 /* Perform a software reset */ 542 543 /* 0x300 host enable bit ? */ 544 /* reset PHY through control register ?:1 */ 545 546 dev_dbg(&ndev->dev, "%s()\n", __func__); 547 548 mutex_lock(lp->indirect_mutex); 549 /* Reset the receiver and wait for it to finish reset */ 550 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK); 551 timeout = 1000; 552 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) { 553 udelay(1); 554 if (--timeout == 0) { 555 dev_err(&ndev->dev, 556 "temac_device_reset RX reset timeout!!\n"); 557 break; 558 } 559 } 560 561 /* Reset the transmitter and wait for it to finish reset */ 562 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK); 563 timeout = 1000; 564 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) { 565 udelay(1); 566 if (--timeout == 0) { 567 dev_err(&ndev->dev, 568 "temac_device_reset TX reset timeout!!\n"); 569 break; 570 } 571 } 572 573 /* Disable the receiver */ 574 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET); 575 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK); 576 577 /* Reset Local Link (DMA) */ 578 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST); 579 timeout = 1000; 580 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) { 581 udelay(1); 582 if (--timeout == 0) { 583 dev_err(&ndev->dev, 584 "temac_device_reset DMA reset timeout!!\n"); 585 break; 586 } 587 } 588 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE); 589 590 if (temac_dma_bd_init(ndev)) { 591 dev_err(&ndev->dev, 592 "temac_device_reset descriptor allocation failed\n"); 593 } 594 595 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0); 596 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0); 597 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0); 598 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK); 599 600 mutex_unlock(lp->indirect_mutex); 601 602 /* Sync default options with HW 603 * but leave receiver and transmitter disabled. */ 604 temac_setoptions(ndev, 605 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN)); 606 607 temac_do_set_mac_address(ndev); 608 609 /* Set address filter table */ 610 temac_set_multicast_list(ndev); 611 if (temac_setoptions(ndev, lp->options)) 612 dev_err(&ndev->dev, "Error setting TEMAC options\n"); 613 614 /* Init Driver variable */ 615 netif_trans_update(ndev); /* prevent tx timeout */ 616 } 617 618 static void temac_adjust_link(struct net_device *ndev) 619 { 620 struct temac_local *lp = netdev_priv(ndev); 621 struct phy_device *phy = ndev->phydev; 622 u32 mii_speed; 623 int link_state; 624 625 /* hash together the state values to decide if something has changed */ 626 link_state = phy->speed | (phy->duplex << 1) | phy->link; 627 628 mutex_lock(lp->indirect_mutex); 629 if (lp->last_link != link_state) { 630 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET); 631 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK; 632 633 switch (phy->speed) { 634 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break; 635 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break; 636 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break; 637 } 638 639 /* Write new speed setting out to TEMAC */ 640 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed); 641 lp->last_link = link_state; 642 phy_print_status(phy); 643 } 644 mutex_unlock(lp->indirect_mutex); 645 } 646 647 #ifdef CONFIG_64BIT 648 649 static void ptr_to_txbd(void *p, struct cdmac_bd *bd) 650 { 651 bd->app3 = (u32)(((u64)p) >> 32); 652 bd->app4 = (u32)((u64)p & 0xFFFFFFFF); 653 } 654 655 static void *ptr_from_txbd(struct cdmac_bd *bd) 656 { 657 return (void *)(((u64)(bd->app3) << 32) | bd->app4); 658 } 659 660 #else 661 662 static void ptr_to_txbd(void *p, struct cdmac_bd *bd) 663 { 664 bd->app4 = (u32)p; 665 } 666 667 static void *ptr_from_txbd(struct cdmac_bd *bd) 668 { 669 return (void *)(bd->app4); 670 } 671 672 #endif 673 674 static void temac_start_xmit_done(struct net_device *ndev) 675 { 676 struct temac_local *lp = netdev_priv(ndev); 677 struct cdmac_bd *cur_p; 678 unsigned int stat = 0; 679 struct sk_buff *skb; 680 681 cur_p = &lp->tx_bd_v[lp->tx_bd_ci]; 682 stat = be32_to_cpu(cur_p->app0); 683 684 while (stat & STS_CTRL_APP0_CMPLT) { 685 dma_unmap_single(ndev->dev.parent, be32_to_cpu(cur_p->phys), 686 be32_to_cpu(cur_p->len), DMA_TO_DEVICE); 687 skb = (struct sk_buff *)ptr_from_txbd(cur_p); 688 if (skb) 689 dev_consume_skb_irq(skb); 690 cur_p->app0 = 0; 691 cur_p->app1 = 0; 692 cur_p->app2 = 0; 693 cur_p->app3 = 0; 694 cur_p->app4 = 0; 695 696 ndev->stats.tx_packets++; 697 ndev->stats.tx_bytes += be32_to_cpu(cur_p->len); 698 699 lp->tx_bd_ci++; 700 if (lp->tx_bd_ci >= TX_BD_NUM) 701 lp->tx_bd_ci = 0; 702 703 cur_p = &lp->tx_bd_v[lp->tx_bd_ci]; 704 stat = be32_to_cpu(cur_p->app0); 705 } 706 707 netif_wake_queue(ndev); 708 } 709 710 static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag) 711 { 712 struct cdmac_bd *cur_p; 713 int tail; 714 715 tail = lp->tx_bd_tail; 716 cur_p = &lp->tx_bd_v[tail]; 717 718 do { 719 if (cur_p->app0) 720 return NETDEV_TX_BUSY; 721 722 tail++; 723 if (tail >= TX_BD_NUM) 724 tail = 0; 725 726 cur_p = &lp->tx_bd_v[tail]; 727 num_frag--; 728 } while (num_frag >= 0); 729 730 return 0; 731 } 732 733 static netdev_tx_t 734 temac_start_xmit(struct sk_buff *skb, struct net_device *ndev) 735 { 736 struct temac_local *lp = netdev_priv(ndev); 737 struct cdmac_bd *cur_p; 738 dma_addr_t start_p, tail_p, skb_dma_addr; 739 int ii; 740 unsigned long num_frag; 741 skb_frag_t *frag; 742 743 num_frag = skb_shinfo(skb)->nr_frags; 744 frag = &skb_shinfo(skb)->frags[0]; 745 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail; 746 cur_p = &lp->tx_bd_v[lp->tx_bd_tail]; 747 748 if (temac_check_tx_bd_space(lp, num_frag + 1)) { 749 if (!netif_queue_stopped(ndev)) 750 netif_stop_queue(ndev); 751 return NETDEV_TX_BUSY; 752 } 753 754 cur_p->app0 = 0; 755 if (skb->ip_summed == CHECKSUM_PARTIAL) { 756 unsigned int csum_start_off = skb_checksum_start_offset(skb); 757 unsigned int csum_index_off = csum_start_off + skb->csum_offset; 758 759 cur_p->app0 |= cpu_to_be32(0x000001); /* TX Checksum Enabled */ 760 cur_p->app1 = cpu_to_be32((csum_start_off << 16) 761 | csum_index_off); 762 cur_p->app2 = 0; /* initial checksum seed */ 763 } 764 765 cur_p->app0 |= cpu_to_be32(STS_CTRL_APP0_SOP); 766 skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data, 767 skb_headlen(skb), DMA_TO_DEVICE); 768 cur_p->len = cpu_to_be32(skb_headlen(skb)); 769 cur_p->phys = cpu_to_be32(skb_dma_addr); 770 ptr_to_txbd((void *)skb, cur_p); 771 772 for (ii = 0; ii < num_frag; ii++) { 773 lp->tx_bd_tail++; 774 if (lp->tx_bd_tail >= TX_BD_NUM) 775 lp->tx_bd_tail = 0; 776 777 cur_p = &lp->tx_bd_v[lp->tx_bd_tail]; 778 skb_dma_addr = dma_map_single(ndev->dev.parent, 779 skb_frag_address(frag), 780 skb_frag_size(frag), 781 DMA_TO_DEVICE); 782 cur_p->phys = cpu_to_be32(skb_dma_addr); 783 cur_p->len = cpu_to_be32(skb_frag_size(frag)); 784 cur_p->app0 = 0; 785 frag++; 786 } 787 cur_p->app0 |= cpu_to_be32(STS_CTRL_APP0_EOP); 788 789 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail; 790 lp->tx_bd_tail++; 791 if (lp->tx_bd_tail >= TX_BD_NUM) 792 lp->tx_bd_tail = 0; 793 794 skb_tx_timestamp(skb); 795 796 /* Kick off the transfer */ 797 wmb(); 798 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */ 799 800 return NETDEV_TX_OK; 801 } 802 803 804 static void ll_temac_recv(struct net_device *ndev) 805 { 806 struct temac_local *lp = netdev_priv(ndev); 807 struct sk_buff *skb, *new_skb; 808 unsigned int bdstat; 809 struct cdmac_bd *cur_p; 810 dma_addr_t tail_p, skb_dma_addr; 811 int length; 812 unsigned long flags; 813 814 spin_lock_irqsave(&lp->rx_lock, flags); 815 816 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci; 817 cur_p = &lp->rx_bd_v[lp->rx_bd_ci]; 818 819 bdstat = be32_to_cpu(cur_p->app0); 820 while ((bdstat & STS_CTRL_APP0_CMPLT)) { 821 822 skb = lp->rx_skb[lp->rx_bd_ci]; 823 length = be32_to_cpu(cur_p->app4) & 0x3FFF; 824 825 dma_unmap_single(ndev->dev.parent, be32_to_cpu(cur_p->phys), 826 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE); 827 828 skb_put(skb, length); 829 skb->protocol = eth_type_trans(skb, ndev); 830 skb_checksum_none_assert(skb); 831 832 /* if we're doing rx csum offload, set it up */ 833 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) && 834 (skb->protocol == htons(ETH_P_IP)) && 835 (skb->len > 64)) { 836 837 /* Convert from device endianness (be32) to cpu 838 * endiannes, and if necessary swap the bytes 839 * (back) for proper IP checksum byte order 840 * (be16). 841 */ 842 skb->csum = htons(be32_to_cpu(cur_p->app3) & 0xFFFF); 843 skb->ip_summed = CHECKSUM_COMPLETE; 844 } 845 846 if (!skb_defer_rx_timestamp(skb)) 847 netif_rx(skb); 848 849 ndev->stats.rx_packets++; 850 ndev->stats.rx_bytes += length; 851 852 new_skb = netdev_alloc_skb_ip_align(ndev, 853 XTE_MAX_JUMBO_FRAME_SIZE); 854 if (!new_skb) { 855 spin_unlock_irqrestore(&lp->rx_lock, flags); 856 return; 857 } 858 859 cur_p->app0 = cpu_to_be32(STS_CTRL_APP0_IRQONEND); 860 skb_dma_addr = dma_map_single(ndev->dev.parent, new_skb->data, 861 XTE_MAX_JUMBO_FRAME_SIZE, 862 DMA_FROM_DEVICE); 863 cur_p->phys = cpu_to_be32(skb_dma_addr); 864 cur_p->len = cpu_to_be32(XTE_MAX_JUMBO_FRAME_SIZE); 865 lp->rx_skb[lp->rx_bd_ci] = new_skb; 866 867 lp->rx_bd_ci++; 868 if (lp->rx_bd_ci >= RX_BD_NUM) 869 lp->rx_bd_ci = 0; 870 871 cur_p = &lp->rx_bd_v[lp->rx_bd_ci]; 872 bdstat = be32_to_cpu(cur_p->app0); 873 } 874 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p); 875 876 spin_unlock_irqrestore(&lp->rx_lock, flags); 877 } 878 879 static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev) 880 { 881 struct net_device *ndev = _ndev; 882 struct temac_local *lp = netdev_priv(ndev); 883 unsigned int status; 884 885 status = lp->dma_in(lp, TX_IRQ_REG); 886 lp->dma_out(lp, TX_IRQ_REG, status); 887 888 if (status & (IRQ_COAL | IRQ_DLY)) 889 temac_start_xmit_done(lp->ndev); 890 if (status & (IRQ_ERR | IRQ_DMAERR)) 891 dev_err_ratelimited(&ndev->dev, 892 "TX error 0x%x TX_CHNL_STS=0x%08x\n", 893 status, lp->dma_in(lp, TX_CHNL_STS)); 894 895 return IRQ_HANDLED; 896 } 897 898 static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev) 899 { 900 struct net_device *ndev = _ndev; 901 struct temac_local *lp = netdev_priv(ndev); 902 unsigned int status; 903 904 /* Read and clear the status registers */ 905 status = lp->dma_in(lp, RX_IRQ_REG); 906 lp->dma_out(lp, RX_IRQ_REG, status); 907 908 if (status & (IRQ_COAL | IRQ_DLY)) 909 ll_temac_recv(lp->ndev); 910 if (status & (IRQ_ERR | IRQ_DMAERR)) 911 dev_err_ratelimited(&ndev->dev, 912 "RX error 0x%x RX_CHNL_STS=0x%08x\n", 913 status, lp->dma_in(lp, RX_CHNL_STS)); 914 915 return IRQ_HANDLED; 916 } 917 918 static int temac_open(struct net_device *ndev) 919 { 920 struct temac_local *lp = netdev_priv(ndev); 921 struct phy_device *phydev = NULL; 922 int rc; 923 924 dev_dbg(&ndev->dev, "temac_open()\n"); 925 926 if (lp->phy_node) { 927 phydev = of_phy_connect(lp->ndev, lp->phy_node, 928 temac_adjust_link, 0, 0); 929 if (!phydev) { 930 dev_err(lp->dev, "of_phy_connect() failed\n"); 931 return -ENODEV; 932 } 933 phy_start(phydev); 934 } else if (strlen(lp->phy_name) > 0) { 935 phydev = phy_connect(lp->ndev, lp->phy_name, temac_adjust_link, 936 lp->phy_interface); 937 if (IS_ERR(phydev)) { 938 dev_err(lp->dev, "phy_connect() failed\n"); 939 return PTR_ERR(phydev); 940 } 941 phy_start(phydev); 942 } 943 944 temac_device_reset(ndev); 945 946 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev); 947 if (rc) 948 goto err_tx_irq; 949 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev); 950 if (rc) 951 goto err_rx_irq; 952 953 return 0; 954 955 err_rx_irq: 956 free_irq(lp->tx_irq, ndev); 957 err_tx_irq: 958 if (phydev) 959 phy_disconnect(phydev); 960 dev_err(lp->dev, "request_irq() failed\n"); 961 return rc; 962 } 963 964 static int temac_stop(struct net_device *ndev) 965 { 966 struct temac_local *lp = netdev_priv(ndev); 967 struct phy_device *phydev = ndev->phydev; 968 969 dev_dbg(&ndev->dev, "temac_close()\n"); 970 971 free_irq(lp->tx_irq, ndev); 972 free_irq(lp->rx_irq, ndev); 973 974 if (phydev) 975 phy_disconnect(phydev); 976 977 temac_dma_bd_release(ndev); 978 979 return 0; 980 } 981 982 #ifdef CONFIG_NET_POLL_CONTROLLER 983 static void 984 temac_poll_controller(struct net_device *ndev) 985 { 986 struct temac_local *lp = netdev_priv(ndev); 987 988 disable_irq(lp->tx_irq); 989 disable_irq(lp->rx_irq); 990 991 ll_temac_rx_irq(lp->tx_irq, ndev); 992 ll_temac_tx_irq(lp->rx_irq, ndev); 993 994 enable_irq(lp->tx_irq); 995 enable_irq(lp->rx_irq); 996 } 997 #endif 998 999 static int temac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 1000 { 1001 if (!netif_running(ndev)) 1002 return -EINVAL; 1003 1004 if (!ndev->phydev) 1005 return -EINVAL; 1006 1007 return phy_mii_ioctl(ndev->phydev, rq, cmd); 1008 } 1009 1010 static const struct net_device_ops temac_netdev_ops = { 1011 .ndo_open = temac_open, 1012 .ndo_stop = temac_stop, 1013 .ndo_start_xmit = temac_start_xmit, 1014 .ndo_set_mac_address = temac_set_mac_address, 1015 .ndo_validate_addr = eth_validate_addr, 1016 .ndo_do_ioctl = temac_ioctl, 1017 #ifdef CONFIG_NET_POLL_CONTROLLER 1018 .ndo_poll_controller = temac_poll_controller, 1019 #endif 1020 }; 1021 1022 /* --------------------------------------------------------------------- 1023 * SYSFS device attributes 1024 */ 1025 static ssize_t temac_show_llink_regs(struct device *dev, 1026 struct device_attribute *attr, char *buf) 1027 { 1028 struct net_device *ndev = dev_get_drvdata(dev); 1029 struct temac_local *lp = netdev_priv(ndev); 1030 int i, len = 0; 1031 1032 for (i = 0; i < 0x11; i++) 1033 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i), 1034 (i % 8) == 7 ? "\n" : " "); 1035 len += sprintf(buf + len, "\n"); 1036 1037 return len; 1038 } 1039 1040 static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL); 1041 1042 static struct attribute *temac_device_attrs[] = { 1043 &dev_attr_llink_regs.attr, 1044 NULL, 1045 }; 1046 1047 static const struct attribute_group temac_attr_group = { 1048 .attrs = temac_device_attrs, 1049 }; 1050 1051 /* ethtool support */ 1052 static const struct ethtool_ops temac_ethtool_ops = { 1053 .nway_reset = phy_ethtool_nway_reset, 1054 .get_link = ethtool_op_get_link, 1055 .get_ts_info = ethtool_op_get_ts_info, 1056 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1057 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1058 }; 1059 1060 static int temac_probe(struct platform_device *pdev) 1061 { 1062 struct ll_temac_platform_data *pdata = dev_get_platdata(&pdev->dev); 1063 struct device_node *temac_np = dev_of_node(&pdev->dev), *dma_np; 1064 struct temac_local *lp; 1065 struct net_device *ndev; 1066 struct resource *res; 1067 const void *addr; 1068 __be32 *p; 1069 bool little_endian; 1070 int rc = 0; 1071 1072 /* Init network device structure */ 1073 ndev = devm_alloc_etherdev(&pdev->dev, sizeof(*lp)); 1074 if (!ndev) 1075 return -ENOMEM; 1076 1077 platform_set_drvdata(pdev, ndev); 1078 SET_NETDEV_DEV(ndev, &pdev->dev); 1079 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */ 1080 ndev->features = NETIF_F_SG; 1081 ndev->netdev_ops = &temac_netdev_ops; 1082 ndev->ethtool_ops = &temac_ethtool_ops; 1083 #if 0 1084 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */ 1085 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */ 1086 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */ 1087 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */ 1088 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; /* Transmit VLAN hw accel */ 1089 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; /* Receive VLAN hw acceleration */ 1090 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; /* Receive VLAN filtering */ 1091 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */ 1092 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */ 1093 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */ 1094 ndev->features |= NETIF_F_LRO; /* large receive offload */ 1095 #endif 1096 1097 /* setup temac private info structure */ 1098 lp = netdev_priv(ndev); 1099 lp->ndev = ndev; 1100 lp->dev = &pdev->dev; 1101 lp->options = XTE_OPTION_DEFAULTS; 1102 spin_lock_init(&lp->rx_lock); 1103 1104 /* Setup mutex for synchronization of indirect register access */ 1105 if (pdata) { 1106 if (!pdata->indirect_mutex) { 1107 dev_err(&pdev->dev, 1108 "indirect_mutex missing in platform_data\n"); 1109 return -EINVAL; 1110 } 1111 lp->indirect_mutex = pdata->indirect_mutex; 1112 } else { 1113 lp->indirect_mutex = devm_kmalloc(&pdev->dev, 1114 sizeof(*lp->indirect_mutex), 1115 GFP_KERNEL); 1116 mutex_init(lp->indirect_mutex); 1117 } 1118 1119 /* map device registers */ 1120 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1121 lp->regs = devm_ioremap_nocache(&pdev->dev, res->start, 1122 resource_size(res)); 1123 if (IS_ERR(lp->regs)) { 1124 dev_err(&pdev->dev, "could not map TEMAC registers\n"); 1125 return PTR_ERR(lp->regs); 1126 } 1127 1128 /* Select register access functions with the specified 1129 * endianness mode. Default for OF devices is big-endian. 1130 */ 1131 little_endian = false; 1132 if (temac_np) { 1133 if (of_get_property(temac_np, "little-endian", NULL)) 1134 little_endian = true; 1135 } else if (pdata) { 1136 little_endian = pdata->reg_little_endian; 1137 } 1138 if (little_endian) { 1139 lp->temac_ior = _temac_ior_le; 1140 lp->temac_iow = _temac_iow_le; 1141 } else { 1142 lp->temac_ior = _temac_ior_be; 1143 lp->temac_iow = _temac_iow_be; 1144 } 1145 1146 /* Setup checksum offload, but default to off if not specified */ 1147 lp->temac_features = 0; 1148 if (temac_np) { 1149 p = (__be32 *)of_get_property(temac_np, "xlnx,txcsum", NULL); 1150 if (p && be32_to_cpu(*p)) 1151 lp->temac_features |= TEMAC_FEATURE_TX_CSUM; 1152 p = (__be32 *)of_get_property(temac_np, "xlnx,rxcsum", NULL); 1153 if (p && be32_to_cpu(*p)) 1154 lp->temac_features |= TEMAC_FEATURE_RX_CSUM; 1155 } else if (pdata) { 1156 if (pdata->txcsum) 1157 lp->temac_features |= TEMAC_FEATURE_TX_CSUM; 1158 if (pdata->rxcsum) 1159 lp->temac_features |= TEMAC_FEATURE_RX_CSUM; 1160 } 1161 if (lp->temac_features & TEMAC_FEATURE_TX_CSUM) 1162 /* Can checksum TCP/UDP over IPv4. */ 1163 ndev->features |= NETIF_F_IP_CSUM; 1164 1165 /* Setup LocalLink DMA */ 1166 if (temac_np) { 1167 /* Find the DMA node, map the DMA registers, and 1168 * decode the DMA IRQs. 1169 */ 1170 dma_np = of_parse_phandle(temac_np, "llink-connected", 0); 1171 if (!dma_np) { 1172 dev_err(&pdev->dev, "could not find DMA node\n"); 1173 return -ENODEV; 1174 } 1175 1176 /* Setup the DMA register accesses, could be DCR or 1177 * memory mapped. 1178 */ 1179 if (temac_dcr_setup(lp, pdev, dma_np)) { 1180 /* no DCR in the device tree, try non-DCR */ 1181 lp->sdma_regs = devm_of_iomap(&pdev->dev, dma_np, 0, 1182 NULL); 1183 if (IS_ERR(lp->sdma_regs)) { 1184 dev_err(&pdev->dev, 1185 "unable to map DMA registers\n"); 1186 of_node_put(dma_np); 1187 return PTR_ERR(lp->sdma_regs); 1188 } 1189 if (of_get_property(dma_np, "little-endian", NULL)) { 1190 lp->dma_in = temac_dma_in32_le; 1191 lp->dma_out = temac_dma_out32_le; 1192 } else { 1193 lp->dma_in = temac_dma_in32_be; 1194 lp->dma_out = temac_dma_out32_be; 1195 } 1196 dev_dbg(&pdev->dev, "MEM base: %p\n", lp->sdma_regs); 1197 } 1198 1199 /* Get DMA RX and TX interrupts */ 1200 lp->rx_irq = irq_of_parse_and_map(dma_np, 0); 1201 lp->tx_irq = irq_of_parse_and_map(dma_np, 1); 1202 1203 /* Use defaults for IRQ delay/coalescing setup. These 1204 * are configuration values, so does not belong in 1205 * device-tree. 1206 */ 1207 lp->tx_chnl_ctrl = 0x10220000; 1208 lp->rx_chnl_ctrl = 0xff070000; 1209 1210 /* Finished with the DMA node; drop the reference */ 1211 of_node_put(dma_np); 1212 } else if (pdata) { 1213 /* 2nd memory resource specifies DMA registers */ 1214 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1215 lp->sdma_regs = devm_ioremap_nocache(&pdev->dev, res->start, 1216 resource_size(res)); 1217 if (IS_ERR(lp->sdma_regs)) { 1218 dev_err(&pdev->dev, 1219 "could not map DMA registers\n"); 1220 return PTR_ERR(lp->sdma_regs); 1221 } 1222 if (pdata->dma_little_endian) { 1223 lp->dma_in = temac_dma_in32_le; 1224 lp->dma_out = temac_dma_out32_le; 1225 } else { 1226 lp->dma_in = temac_dma_in32_be; 1227 lp->dma_out = temac_dma_out32_be; 1228 } 1229 1230 /* Get DMA RX and TX interrupts */ 1231 lp->rx_irq = platform_get_irq(pdev, 0); 1232 lp->tx_irq = platform_get_irq(pdev, 1); 1233 1234 /* IRQ delay/coalescing setup */ 1235 if (pdata->tx_irq_timeout || pdata->tx_irq_count) 1236 lp->tx_chnl_ctrl = (pdata->tx_irq_timeout << 24) | 1237 (pdata->tx_irq_count << 16); 1238 else 1239 lp->tx_chnl_ctrl = 0x10220000; 1240 if (pdata->rx_irq_timeout || pdata->rx_irq_count) 1241 lp->rx_chnl_ctrl = (pdata->rx_irq_timeout << 24) | 1242 (pdata->rx_irq_count << 16); 1243 else 1244 lp->rx_chnl_ctrl = 0xff070000; 1245 } 1246 1247 /* Error handle returned DMA RX and TX interrupts */ 1248 if (lp->rx_irq < 0) { 1249 if (lp->rx_irq != -EPROBE_DEFER) 1250 dev_err(&pdev->dev, "could not get DMA RX irq\n"); 1251 return lp->rx_irq; 1252 } 1253 if (lp->tx_irq < 0) { 1254 if (lp->tx_irq != -EPROBE_DEFER) 1255 dev_err(&pdev->dev, "could not get DMA TX irq\n"); 1256 return lp->tx_irq; 1257 } 1258 1259 if (temac_np) { 1260 /* Retrieve the MAC address */ 1261 addr = of_get_mac_address(temac_np); 1262 if (IS_ERR(addr)) { 1263 dev_err(&pdev->dev, "could not find MAC address\n"); 1264 return -ENODEV; 1265 } 1266 temac_init_mac_address(ndev, addr); 1267 } else if (pdata) { 1268 temac_init_mac_address(ndev, pdata->mac_addr); 1269 } 1270 1271 rc = temac_mdio_setup(lp, pdev); 1272 if (rc) 1273 dev_warn(&pdev->dev, "error registering MDIO bus\n"); 1274 1275 if (temac_np) { 1276 lp->phy_node = of_parse_phandle(temac_np, "phy-handle", 0); 1277 if (lp->phy_node) 1278 dev_dbg(lp->dev, "using PHY node %pOF\n", temac_np); 1279 } else if (pdata) { 1280 snprintf(lp->phy_name, sizeof(lp->phy_name), 1281 PHY_ID_FMT, lp->mii_bus->id, pdata->phy_addr); 1282 lp->phy_interface = pdata->phy_interface; 1283 } 1284 1285 /* Add the device attributes */ 1286 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group); 1287 if (rc) { 1288 dev_err(lp->dev, "Error creating sysfs files\n"); 1289 goto err_sysfs_create; 1290 } 1291 1292 rc = register_netdev(lp->ndev); 1293 if (rc) { 1294 dev_err(lp->dev, "register_netdev() error (%i)\n", rc); 1295 goto err_register_ndev; 1296 } 1297 1298 return 0; 1299 1300 err_register_ndev: 1301 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group); 1302 err_sysfs_create: 1303 if (lp->phy_node) 1304 of_node_put(lp->phy_node); 1305 temac_mdio_teardown(lp); 1306 return rc; 1307 } 1308 1309 static int temac_remove(struct platform_device *pdev) 1310 { 1311 struct net_device *ndev = platform_get_drvdata(pdev); 1312 struct temac_local *lp = netdev_priv(ndev); 1313 1314 unregister_netdev(ndev); 1315 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group); 1316 if (lp->phy_node) 1317 of_node_put(lp->phy_node); 1318 temac_mdio_teardown(lp); 1319 return 0; 1320 } 1321 1322 static const struct of_device_id temac_of_match[] = { 1323 { .compatible = "xlnx,xps-ll-temac-1.01.b", }, 1324 { .compatible = "xlnx,xps-ll-temac-2.00.a", }, 1325 { .compatible = "xlnx,xps-ll-temac-2.02.a", }, 1326 { .compatible = "xlnx,xps-ll-temac-2.03.a", }, 1327 {}, 1328 }; 1329 MODULE_DEVICE_TABLE(of, temac_of_match); 1330 1331 static struct platform_driver temac_driver = { 1332 .probe = temac_probe, 1333 .remove = temac_remove, 1334 .driver = { 1335 .name = "xilinx_temac", 1336 .of_match_table = temac_of_match, 1337 }, 1338 }; 1339 1340 module_platform_driver(temac_driver); 1341 1342 MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver"); 1343 MODULE_AUTHOR("Yoshio Kashiwagi"); 1344 MODULE_LICENSE("GPL"); 1345