1 /* 2 * Driver for Xilinx TEMAC Ethernet device 3 * 4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi 5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net> 6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd. 7 * 8 * This is a driver for the Xilinx ll_temac ipcore which is often used 9 * in the Virtex and Spartan series of chips. 10 * 11 * Notes: 12 * - The ll_temac hardware uses indirect access for many of the TEMAC 13 * registers, include the MDIO bus. However, indirect access to MDIO 14 * registers take considerably more clock cycles than to TEMAC registers. 15 * MDIO accesses are long, so threads doing them should probably sleep 16 * rather than busywait. However, since only one indirect access can be 17 * in progress at any given time, that means that *all* indirect accesses 18 * could end up sleeping (to wait for an MDIO access to complete). 19 * Fortunately none of the indirect accesses are on the 'hot' path for tx 20 * or rx, so this should be okay. 21 * 22 * TODO: 23 * - Factor out locallink DMA code into separate driver 24 * - Fix multicast assignment. 25 * - Fix support for hardware checksumming. 26 * - Testing. Lots and lots of testing. 27 * 28 */ 29 30 #include <linux/delay.h> 31 #include <linux/etherdevice.h> 32 #include <linux/init.h> 33 #include <linux/mii.h> 34 #include <linux/module.h> 35 #include <linux/mutex.h> 36 #include <linux/netdevice.h> 37 #include <linux/of.h> 38 #include <linux/of_device.h> 39 #include <linux/of_irq.h> 40 #include <linux/of_mdio.h> 41 #include <linux/of_platform.h> 42 #include <linux/of_address.h> 43 #include <linux/skbuff.h> 44 #include <linux/spinlock.h> 45 #include <linux/tcp.h> /* needed for sizeof(tcphdr) */ 46 #include <linux/udp.h> /* needed for sizeof(udphdr) */ 47 #include <linux/phy.h> 48 #include <linux/in.h> 49 #include <linux/io.h> 50 #include <linux/ip.h> 51 #include <linux/slab.h> 52 #include <linux/interrupt.h> 53 #include <linux/dma-mapping.h> 54 55 #include "ll_temac.h" 56 57 #define TX_BD_NUM 64 58 #define RX_BD_NUM 128 59 60 /* --------------------------------------------------------------------- 61 * Low level register access functions 62 */ 63 64 u32 temac_ior(struct temac_local *lp, int offset) 65 { 66 return in_be32((u32 *)(lp->regs + offset)); 67 } 68 69 void temac_iow(struct temac_local *lp, int offset, u32 value) 70 { 71 out_be32((u32 *) (lp->regs + offset), value); 72 } 73 74 int temac_indirect_busywait(struct temac_local *lp) 75 { 76 long end = jiffies + 2; 77 78 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) { 79 if (end - jiffies <= 0) { 80 WARN_ON(1); 81 return -ETIMEDOUT; 82 } 83 msleep(1); 84 } 85 return 0; 86 } 87 88 /** 89 * temac_indirect_in32 90 * 91 * lp->indirect_mutex must be held when calling this function 92 */ 93 u32 temac_indirect_in32(struct temac_local *lp, int reg) 94 { 95 u32 val; 96 97 if (temac_indirect_busywait(lp)) 98 return -ETIMEDOUT; 99 temac_iow(lp, XTE_CTL0_OFFSET, reg); 100 if (temac_indirect_busywait(lp)) 101 return -ETIMEDOUT; 102 val = temac_ior(lp, XTE_LSW0_OFFSET); 103 104 return val; 105 } 106 107 /** 108 * temac_indirect_out32 109 * 110 * lp->indirect_mutex must be held when calling this function 111 */ 112 void temac_indirect_out32(struct temac_local *lp, int reg, u32 value) 113 { 114 if (temac_indirect_busywait(lp)) 115 return; 116 temac_iow(lp, XTE_LSW0_OFFSET, value); 117 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg); 118 temac_indirect_busywait(lp); 119 } 120 121 /** 122 * temac_dma_in32 - Memory mapped DMA read, this function expects a 123 * register input that is based on DCR word addresses which 124 * are then converted to memory mapped byte addresses 125 */ 126 static u32 temac_dma_in32(struct temac_local *lp, int reg) 127 { 128 return in_be32((u32 *)(lp->sdma_regs + (reg << 2))); 129 } 130 131 /** 132 * temac_dma_out32 - Memory mapped DMA read, this function expects a 133 * register input that is based on DCR word addresses which 134 * are then converted to memory mapped byte addresses 135 */ 136 static void temac_dma_out32(struct temac_local *lp, int reg, u32 value) 137 { 138 out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value); 139 } 140 141 /* DMA register access functions can be DCR based or memory mapped. 142 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both 143 * memory mapped. 144 */ 145 #ifdef CONFIG_PPC_DCR 146 147 /** 148 * temac_dma_dcr_in32 - DCR based DMA read 149 */ 150 static u32 temac_dma_dcr_in(struct temac_local *lp, int reg) 151 { 152 return dcr_read(lp->sdma_dcrs, reg); 153 } 154 155 /** 156 * temac_dma_dcr_out32 - DCR based DMA write 157 */ 158 static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value) 159 { 160 dcr_write(lp->sdma_dcrs, reg, value); 161 } 162 163 /** 164 * temac_dcr_setup - If the DMA is DCR based, then setup the address and 165 * I/O functions 166 */ 167 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op, 168 struct device_node *np) 169 { 170 unsigned int dcrs; 171 172 /* setup the dcr address mapping if it's in the device tree */ 173 174 dcrs = dcr_resource_start(np, 0); 175 if (dcrs != 0) { 176 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0)); 177 lp->dma_in = temac_dma_dcr_in; 178 lp->dma_out = temac_dma_dcr_out; 179 dev_dbg(&op->dev, "DCR base: %x\n", dcrs); 180 return 0; 181 } 182 /* no DCR in the device tree, indicate a failure */ 183 return -1; 184 } 185 186 #else 187 188 /* 189 * temac_dcr_setup - This is a stub for when DCR is not supported, 190 * such as with MicroBlaze 191 */ 192 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op, 193 struct device_node *np) 194 { 195 return -1; 196 } 197 198 #endif 199 200 /** 201 * temac_dma_bd_release - Release buffer descriptor rings 202 */ 203 static void temac_dma_bd_release(struct net_device *ndev) 204 { 205 struct temac_local *lp = netdev_priv(ndev); 206 int i; 207 208 /* Reset Local Link (DMA) */ 209 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST); 210 211 for (i = 0; i < RX_BD_NUM; i++) { 212 if (!lp->rx_skb[i]) 213 break; 214 else { 215 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys, 216 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE); 217 dev_kfree_skb(lp->rx_skb[i]); 218 } 219 } 220 if (lp->rx_bd_v) 221 dma_free_coherent(ndev->dev.parent, 222 sizeof(*lp->rx_bd_v) * RX_BD_NUM, 223 lp->rx_bd_v, lp->rx_bd_p); 224 if (lp->tx_bd_v) 225 dma_free_coherent(ndev->dev.parent, 226 sizeof(*lp->tx_bd_v) * TX_BD_NUM, 227 lp->tx_bd_v, lp->tx_bd_p); 228 if (lp->rx_skb) 229 kfree(lp->rx_skb); 230 } 231 232 /** 233 * temac_dma_bd_init - Setup buffer descriptor rings 234 */ 235 static int temac_dma_bd_init(struct net_device *ndev) 236 { 237 struct temac_local *lp = netdev_priv(ndev); 238 struct sk_buff *skb; 239 int i; 240 241 lp->rx_skb = kcalloc(RX_BD_NUM, sizeof(*lp->rx_skb), GFP_KERNEL); 242 if (!lp->rx_skb) 243 goto out; 244 245 /* allocate the tx and rx ring buffer descriptors. */ 246 /* returns a virtual address and a physical address. */ 247 lp->tx_bd_v = dma_zalloc_coherent(ndev->dev.parent, 248 sizeof(*lp->tx_bd_v) * TX_BD_NUM, 249 &lp->tx_bd_p, GFP_KERNEL); 250 if (!lp->tx_bd_v) 251 goto out; 252 253 lp->rx_bd_v = dma_zalloc_coherent(ndev->dev.parent, 254 sizeof(*lp->rx_bd_v) * RX_BD_NUM, 255 &lp->rx_bd_p, GFP_KERNEL); 256 if (!lp->rx_bd_v) 257 goto out; 258 259 for (i = 0; i < TX_BD_NUM; i++) { 260 lp->tx_bd_v[i].next = lp->tx_bd_p + 261 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM); 262 } 263 264 for (i = 0; i < RX_BD_NUM; i++) { 265 lp->rx_bd_v[i].next = lp->rx_bd_p + 266 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM); 267 268 skb = netdev_alloc_skb_ip_align(ndev, 269 XTE_MAX_JUMBO_FRAME_SIZE); 270 if (!skb) 271 goto out; 272 273 lp->rx_skb[i] = skb; 274 /* returns physical address of skb->data */ 275 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent, 276 skb->data, 277 XTE_MAX_JUMBO_FRAME_SIZE, 278 DMA_FROM_DEVICE); 279 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE; 280 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND; 281 } 282 283 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 | 284 CHNL_CTRL_IRQ_EN | 285 CHNL_CTRL_IRQ_DLY_EN | 286 CHNL_CTRL_IRQ_COAL_EN); 287 /* 0x10220483 */ 288 /* 0x00100483 */ 289 lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 | 290 CHNL_CTRL_IRQ_EN | 291 CHNL_CTRL_IRQ_DLY_EN | 292 CHNL_CTRL_IRQ_COAL_EN | 293 CHNL_CTRL_IRQ_IOE); 294 /* 0xff010283 */ 295 296 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p); 297 lp->dma_out(lp, RX_TAILDESC_PTR, 298 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1))); 299 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p); 300 301 return 0; 302 303 out: 304 temac_dma_bd_release(ndev); 305 return -ENOMEM; 306 } 307 308 /* --------------------------------------------------------------------- 309 * net_device_ops 310 */ 311 312 static void temac_do_set_mac_address(struct net_device *ndev) 313 { 314 struct temac_local *lp = netdev_priv(ndev); 315 316 /* set up unicast MAC address filter set its mac address */ 317 mutex_lock(&lp->indirect_mutex); 318 temac_indirect_out32(lp, XTE_UAW0_OFFSET, 319 (ndev->dev_addr[0]) | 320 (ndev->dev_addr[1] << 8) | 321 (ndev->dev_addr[2] << 16) | 322 (ndev->dev_addr[3] << 24)); 323 /* There are reserved bits in EUAW1 324 * so don't affect them Set MAC bits [47:32] in EUAW1 */ 325 temac_indirect_out32(lp, XTE_UAW1_OFFSET, 326 (ndev->dev_addr[4] & 0x000000ff) | 327 (ndev->dev_addr[5] << 8)); 328 mutex_unlock(&lp->indirect_mutex); 329 } 330 331 static int temac_init_mac_address(struct net_device *ndev, void *address) 332 { 333 memcpy(ndev->dev_addr, address, ETH_ALEN); 334 if (!is_valid_ether_addr(ndev->dev_addr)) 335 eth_hw_addr_random(ndev); 336 temac_do_set_mac_address(ndev); 337 return 0; 338 } 339 340 static int temac_set_mac_address(struct net_device *ndev, void *p) 341 { 342 struct sockaddr *addr = p; 343 344 if (!is_valid_ether_addr(addr->sa_data)) 345 return -EADDRNOTAVAIL; 346 memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN); 347 temac_do_set_mac_address(ndev); 348 return 0; 349 } 350 351 static void temac_set_multicast_list(struct net_device *ndev) 352 { 353 struct temac_local *lp = netdev_priv(ndev); 354 u32 multi_addr_msw, multi_addr_lsw, val; 355 int i; 356 357 mutex_lock(&lp->indirect_mutex); 358 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) || 359 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) { 360 /* 361 * We must make the kernel realise we had to move 362 * into promisc mode or we start all out war on 363 * the cable. If it was a promisc request the 364 * flag is already set. If not we assert it. 365 */ 366 ndev->flags |= IFF_PROMISC; 367 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK); 368 dev_info(&ndev->dev, "Promiscuous mode enabled.\n"); 369 } else if (!netdev_mc_empty(ndev)) { 370 struct netdev_hw_addr *ha; 371 372 i = 0; 373 netdev_for_each_mc_addr(ha, ndev) { 374 if (i >= MULTICAST_CAM_TABLE_NUM) 375 break; 376 multi_addr_msw = ((ha->addr[3] << 24) | 377 (ha->addr[2] << 16) | 378 (ha->addr[1] << 8) | 379 (ha->addr[0])); 380 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 381 multi_addr_msw); 382 multi_addr_lsw = ((ha->addr[5] << 8) | 383 (ha->addr[4]) | (i << 16)); 384 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 385 multi_addr_lsw); 386 i++; 387 } 388 } else { 389 val = temac_indirect_in32(lp, XTE_AFM_OFFSET); 390 temac_indirect_out32(lp, XTE_AFM_OFFSET, 391 val & ~XTE_AFM_EPPRM_MASK); 392 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0); 393 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0); 394 dev_info(&ndev->dev, "Promiscuous mode disabled.\n"); 395 } 396 mutex_unlock(&lp->indirect_mutex); 397 } 398 399 struct temac_option { 400 int flg; 401 u32 opt; 402 u32 reg; 403 u32 m_or; 404 u32 m_and; 405 } temac_options[] = { 406 /* Turn on jumbo packet support for both Rx and Tx */ 407 { 408 .opt = XTE_OPTION_JUMBO, 409 .reg = XTE_TXC_OFFSET, 410 .m_or = XTE_TXC_TXJMBO_MASK, 411 }, 412 { 413 .opt = XTE_OPTION_JUMBO, 414 .reg = XTE_RXC1_OFFSET, 415 .m_or =XTE_RXC1_RXJMBO_MASK, 416 }, 417 /* Turn on VLAN packet support for both Rx and Tx */ 418 { 419 .opt = XTE_OPTION_VLAN, 420 .reg = XTE_TXC_OFFSET, 421 .m_or =XTE_TXC_TXVLAN_MASK, 422 }, 423 { 424 .opt = XTE_OPTION_VLAN, 425 .reg = XTE_RXC1_OFFSET, 426 .m_or =XTE_RXC1_RXVLAN_MASK, 427 }, 428 /* Turn on FCS stripping on receive packets */ 429 { 430 .opt = XTE_OPTION_FCS_STRIP, 431 .reg = XTE_RXC1_OFFSET, 432 .m_or =XTE_RXC1_RXFCS_MASK, 433 }, 434 /* Turn on FCS insertion on transmit packets */ 435 { 436 .opt = XTE_OPTION_FCS_INSERT, 437 .reg = XTE_TXC_OFFSET, 438 .m_or =XTE_TXC_TXFCS_MASK, 439 }, 440 /* Turn on length/type field checking on receive packets */ 441 { 442 .opt = XTE_OPTION_LENTYPE_ERR, 443 .reg = XTE_RXC1_OFFSET, 444 .m_or =XTE_RXC1_RXLT_MASK, 445 }, 446 /* Turn on flow control */ 447 { 448 .opt = XTE_OPTION_FLOW_CONTROL, 449 .reg = XTE_FCC_OFFSET, 450 .m_or =XTE_FCC_RXFLO_MASK, 451 }, 452 /* Turn on flow control */ 453 { 454 .opt = XTE_OPTION_FLOW_CONTROL, 455 .reg = XTE_FCC_OFFSET, 456 .m_or =XTE_FCC_TXFLO_MASK, 457 }, 458 /* Turn on promiscuous frame filtering (all frames are received ) */ 459 { 460 .opt = XTE_OPTION_PROMISC, 461 .reg = XTE_AFM_OFFSET, 462 .m_or =XTE_AFM_EPPRM_MASK, 463 }, 464 /* Enable transmitter if not already enabled */ 465 { 466 .opt = XTE_OPTION_TXEN, 467 .reg = XTE_TXC_OFFSET, 468 .m_or =XTE_TXC_TXEN_MASK, 469 }, 470 /* Enable receiver? */ 471 { 472 .opt = XTE_OPTION_RXEN, 473 .reg = XTE_RXC1_OFFSET, 474 .m_or =XTE_RXC1_RXEN_MASK, 475 }, 476 {} 477 }; 478 479 /** 480 * temac_setoptions 481 */ 482 static u32 temac_setoptions(struct net_device *ndev, u32 options) 483 { 484 struct temac_local *lp = netdev_priv(ndev); 485 struct temac_option *tp = &temac_options[0]; 486 int reg; 487 488 mutex_lock(&lp->indirect_mutex); 489 while (tp->opt) { 490 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or; 491 if (options & tp->opt) 492 reg |= tp->m_or; 493 temac_indirect_out32(lp, tp->reg, reg); 494 tp++; 495 } 496 lp->options |= options; 497 mutex_unlock(&lp->indirect_mutex); 498 499 return 0; 500 } 501 502 /* Initialize temac */ 503 static void temac_device_reset(struct net_device *ndev) 504 { 505 struct temac_local *lp = netdev_priv(ndev); 506 u32 timeout; 507 u32 val; 508 509 /* Perform a software reset */ 510 511 /* 0x300 host enable bit ? */ 512 /* reset PHY through control register ?:1 */ 513 514 dev_dbg(&ndev->dev, "%s()\n", __func__); 515 516 mutex_lock(&lp->indirect_mutex); 517 /* Reset the receiver and wait for it to finish reset */ 518 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK); 519 timeout = 1000; 520 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) { 521 udelay(1); 522 if (--timeout == 0) { 523 dev_err(&ndev->dev, 524 "temac_device_reset RX reset timeout!!\n"); 525 break; 526 } 527 } 528 529 /* Reset the transmitter and wait for it to finish reset */ 530 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK); 531 timeout = 1000; 532 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) { 533 udelay(1); 534 if (--timeout == 0) { 535 dev_err(&ndev->dev, 536 "temac_device_reset TX reset timeout!!\n"); 537 break; 538 } 539 } 540 541 /* Disable the receiver */ 542 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET); 543 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK); 544 545 /* Reset Local Link (DMA) */ 546 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST); 547 timeout = 1000; 548 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) { 549 udelay(1); 550 if (--timeout == 0) { 551 dev_err(&ndev->dev, 552 "temac_device_reset DMA reset timeout!!\n"); 553 break; 554 } 555 } 556 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE); 557 558 if (temac_dma_bd_init(ndev)) { 559 dev_err(&ndev->dev, 560 "temac_device_reset descriptor allocation failed\n"); 561 } 562 563 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0); 564 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0); 565 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0); 566 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK); 567 568 mutex_unlock(&lp->indirect_mutex); 569 570 /* Sync default options with HW 571 * but leave receiver and transmitter disabled. */ 572 temac_setoptions(ndev, 573 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN)); 574 575 temac_do_set_mac_address(ndev); 576 577 /* Set address filter table */ 578 temac_set_multicast_list(ndev); 579 if (temac_setoptions(ndev, lp->options)) 580 dev_err(&ndev->dev, "Error setting TEMAC options\n"); 581 582 /* Init Driver variable */ 583 ndev->trans_start = jiffies; /* prevent tx timeout */ 584 } 585 586 void temac_adjust_link(struct net_device *ndev) 587 { 588 struct temac_local *lp = netdev_priv(ndev); 589 struct phy_device *phy = lp->phy_dev; 590 u32 mii_speed; 591 int link_state; 592 593 /* hash together the state values to decide if something has changed */ 594 link_state = phy->speed | (phy->duplex << 1) | phy->link; 595 596 mutex_lock(&lp->indirect_mutex); 597 if (lp->last_link != link_state) { 598 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET); 599 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK; 600 601 switch (phy->speed) { 602 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break; 603 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break; 604 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break; 605 } 606 607 /* Write new speed setting out to TEMAC */ 608 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed); 609 lp->last_link = link_state; 610 phy_print_status(phy); 611 } 612 mutex_unlock(&lp->indirect_mutex); 613 } 614 615 static void temac_start_xmit_done(struct net_device *ndev) 616 { 617 struct temac_local *lp = netdev_priv(ndev); 618 struct cdmac_bd *cur_p; 619 unsigned int stat = 0; 620 621 cur_p = &lp->tx_bd_v[lp->tx_bd_ci]; 622 stat = cur_p->app0; 623 624 while (stat & STS_CTRL_APP0_CMPLT) { 625 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len, 626 DMA_TO_DEVICE); 627 if (cur_p->app4) 628 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4); 629 cur_p->app0 = 0; 630 cur_p->app1 = 0; 631 cur_p->app2 = 0; 632 cur_p->app3 = 0; 633 cur_p->app4 = 0; 634 635 ndev->stats.tx_packets++; 636 ndev->stats.tx_bytes += cur_p->len; 637 638 lp->tx_bd_ci++; 639 if (lp->tx_bd_ci >= TX_BD_NUM) 640 lp->tx_bd_ci = 0; 641 642 cur_p = &lp->tx_bd_v[lp->tx_bd_ci]; 643 stat = cur_p->app0; 644 } 645 646 netif_wake_queue(ndev); 647 } 648 649 static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag) 650 { 651 struct cdmac_bd *cur_p; 652 int tail; 653 654 tail = lp->tx_bd_tail; 655 cur_p = &lp->tx_bd_v[tail]; 656 657 do { 658 if (cur_p->app0) 659 return NETDEV_TX_BUSY; 660 661 tail++; 662 if (tail >= TX_BD_NUM) 663 tail = 0; 664 665 cur_p = &lp->tx_bd_v[tail]; 666 num_frag--; 667 } while (num_frag >= 0); 668 669 return 0; 670 } 671 672 static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev) 673 { 674 struct temac_local *lp = netdev_priv(ndev); 675 struct cdmac_bd *cur_p; 676 dma_addr_t start_p, tail_p; 677 int ii; 678 unsigned long num_frag; 679 skb_frag_t *frag; 680 681 num_frag = skb_shinfo(skb)->nr_frags; 682 frag = &skb_shinfo(skb)->frags[0]; 683 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail; 684 cur_p = &lp->tx_bd_v[lp->tx_bd_tail]; 685 686 if (temac_check_tx_bd_space(lp, num_frag)) { 687 if (!netif_queue_stopped(ndev)) { 688 netif_stop_queue(ndev); 689 return NETDEV_TX_BUSY; 690 } 691 return NETDEV_TX_BUSY; 692 } 693 694 cur_p->app0 = 0; 695 if (skb->ip_summed == CHECKSUM_PARTIAL) { 696 unsigned int csum_start_off = skb_checksum_start_offset(skb); 697 unsigned int csum_index_off = csum_start_off + skb->csum_offset; 698 699 cur_p->app0 |= 1; /* TX Checksum Enabled */ 700 cur_p->app1 = (csum_start_off << 16) | csum_index_off; 701 cur_p->app2 = 0; /* initial checksum seed */ 702 } 703 704 cur_p->app0 |= STS_CTRL_APP0_SOP; 705 cur_p->len = skb_headlen(skb); 706 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data, skb->len, 707 DMA_TO_DEVICE); 708 cur_p->app4 = (unsigned long)skb; 709 710 for (ii = 0; ii < num_frag; ii++) { 711 lp->tx_bd_tail++; 712 if (lp->tx_bd_tail >= TX_BD_NUM) 713 lp->tx_bd_tail = 0; 714 715 cur_p = &lp->tx_bd_v[lp->tx_bd_tail]; 716 cur_p->phys = dma_map_single(ndev->dev.parent, 717 skb_frag_address(frag), 718 skb_frag_size(frag), DMA_TO_DEVICE); 719 cur_p->len = skb_frag_size(frag); 720 cur_p->app0 = 0; 721 frag++; 722 } 723 cur_p->app0 |= STS_CTRL_APP0_EOP; 724 725 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail; 726 lp->tx_bd_tail++; 727 if (lp->tx_bd_tail >= TX_BD_NUM) 728 lp->tx_bd_tail = 0; 729 730 skb_tx_timestamp(skb); 731 732 /* Kick off the transfer */ 733 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */ 734 735 return NETDEV_TX_OK; 736 } 737 738 739 static void ll_temac_recv(struct net_device *ndev) 740 { 741 struct temac_local *lp = netdev_priv(ndev); 742 struct sk_buff *skb, *new_skb; 743 unsigned int bdstat; 744 struct cdmac_bd *cur_p; 745 dma_addr_t tail_p; 746 int length; 747 unsigned long flags; 748 749 spin_lock_irqsave(&lp->rx_lock, flags); 750 751 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci; 752 cur_p = &lp->rx_bd_v[lp->rx_bd_ci]; 753 754 bdstat = cur_p->app0; 755 while ((bdstat & STS_CTRL_APP0_CMPLT)) { 756 757 skb = lp->rx_skb[lp->rx_bd_ci]; 758 length = cur_p->app4 & 0x3FFF; 759 760 dma_unmap_single(ndev->dev.parent, cur_p->phys, length, 761 DMA_FROM_DEVICE); 762 763 skb_put(skb, length); 764 skb->protocol = eth_type_trans(skb, ndev); 765 skb_checksum_none_assert(skb); 766 767 /* if we're doing rx csum offload, set it up */ 768 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) && 769 (skb->protocol == __constant_htons(ETH_P_IP)) && 770 (skb->len > 64)) { 771 772 skb->csum = cur_p->app3 & 0xFFFF; 773 skb->ip_summed = CHECKSUM_COMPLETE; 774 } 775 776 if (!skb_defer_rx_timestamp(skb)) 777 netif_rx(skb); 778 779 ndev->stats.rx_packets++; 780 ndev->stats.rx_bytes += length; 781 782 new_skb = netdev_alloc_skb_ip_align(ndev, 783 XTE_MAX_JUMBO_FRAME_SIZE); 784 if (!new_skb) { 785 spin_unlock_irqrestore(&lp->rx_lock, flags); 786 return; 787 } 788 789 cur_p->app0 = STS_CTRL_APP0_IRQONEND; 790 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data, 791 XTE_MAX_JUMBO_FRAME_SIZE, 792 DMA_FROM_DEVICE); 793 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE; 794 lp->rx_skb[lp->rx_bd_ci] = new_skb; 795 796 lp->rx_bd_ci++; 797 if (lp->rx_bd_ci >= RX_BD_NUM) 798 lp->rx_bd_ci = 0; 799 800 cur_p = &lp->rx_bd_v[lp->rx_bd_ci]; 801 bdstat = cur_p->app0; 802 } 803 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p); 804 805 spin_unlock_irqrestore(&lp->rx_lock, flags); 806 } 807 808 static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev) 809 { 810 struct net_device *ndev = _ndev; 811 struct temac_local *lp = netdev_priv(ndev); 812 unsigned int status; 813 814 status = lp->dma_in(lp, TX_IRQ_REG); 815 lp->dma_out(lp, TX_IRQ_REG, status); 816 817 if (status & (IRQ_COAL | IRQ_DLY)) 818 temac_start_xmit_done(lp->ndev); 819 if (status & 0x080) 820 dev_err(&ndev->dev, "DMA error 0x%x\n", status); 821 822 return IRQ_HANDLED; 823 } 824 825 static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev) 826 { 827 struct net_device *ndev = _ndev; 828 struct temac_local *lp = netdev_priv(ndev); 829 unsigned int status; 830 831 /* Read and clear the status registers */ 832 status = lp->dma_in(lp, RX_IRQ_REG); 833 lp->dma_out(lp, RX_IRQ_REG, status); 834 835 if (status & (IRQ_COAL | IRQ_DLY)) 836 ll_temac_recv(lp->ndev); 837 838 return IRQ_HANDLED; 839 } 840 841 static int temac_open(struct net_device *ndev) 842 { 843 struct temac_local *lp = netdev_priv(ndev); 844 int rc; 845 846 dev_dbg(&ndev->dev, "temac_open()\n"); 847 848 if (lp->phy_node) { 849 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node, 850 temac_adjust_link, 0, 0); 851 if (!lp->phy_dev) { 852 dev_err(lp->dev, "of_phy_connect() failed\n"); 853 return -ENODEV; 854 } 855 856 phy_start(lp->phy_dev); 857 } 858 859 temac_device_reset(ndev); 860 861 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev); 862 if (rc) 863 goto err_tx_irq; 864 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev); 865 if (rc) 866 goto err_rx_irq; 867 868 return 0; 869 870 err_rx_irq: 871 free_irq(lp->tx_irq, ndev); 872 err_tx_irq: 873 if (lp->phy_dev) 874 phy_disconnect(lp->phy_dev); 875 lp->phy_dev = NULL; 876 dev_err(lp->dev, "request_irq() failed\n"); 877 return rc; 878 } 879 880 static int temac_stop(struct net_device *ndev) 881 { 882 struct temac_local *lp = netdev_priv(ndev); 883 884 dev_dbg(&ndev->dev, "temac_close()\n"); 885 886 free_irq(lp->tx_irq, ndev); 887 free_irq(lp->rx_irq, ndev); 888 889 if (lp->phy_dev) 890 phy_disconnect(lp->phy_dev); 891 lp->phy_dev = NULL; 892 893 temac_dma_bd_release(ndev); 894 895 return 0; 896 } 897 898 #ifdef CONFIG_NET_POLL_CONTROLLER 899 static void 900 temac_poll_controller(struct net_device *ndev) 901 { 902 struct temac_local *lp = netdev_priv(ndev); 903 904 disable_irq(lp->tx_irq); 905 disable_irq(lp->rx_irq); 906 907 ll_temac_rx_irq(lp->tx_irq, ndev); 908 ll_temac_tx_irq(lp->rx_irq, ndev); 909 910 enable_irq(lp->tx_irq); 911 enable_irq(lp->rx_irq); 912 } 913 #endif 914 915 static int temac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 916 { 917 struct temac_local *lp = netdev_priv(ndev); 918 919 if (!netif_running(ndev)) 920 return -EINVAL; 921 922 if (!lp->phy_dev) 923 return -EINVAL; 924 925 return phy_mii_ioctl(lp->phy_dev, rq, cmd); 926 } 927 928 static const struct net_device_ops temac_netdev_ops = { 929 .ndo_open = temac_open, 930 .ndo_stop = temac_stop, 931 .ndo_start_xmit = temac_start_xmit, 932 .ndo_set_mac_address = temac_set_mac_address, 933 .ndo_validate_addr = eth_validate_addr, 934 .ndo_do_ioctl = temac_ioctl, 935 #ifdef CONFIG_NET_POLL_CONTROLLER 936 .ndo_poll_controller = temac_poll_controller, 937 #endif 938 }; 939 940 /* --------------------------------------------------------------------- 941 * SYSFS device attributes 942 */ 943 static ssize_t temac_show_llink_regs(struct device *dev, 944 struct device_attribute *attr, char *buf) 945 { 946 struct net_device *ndev = dev_get_drvdata(dev); 947 struct temac_local *lp = netdev_priv(ndev); 948 int i, len = 0; 949 950 for (i = 0; i < 0x11; i++) 951 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i), 952 (i % 8) == 7 ? "\n" : " "); 953 len += sprintf(buf + len, "\n"); 954 955 return len; 956 } 957 958 static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL); 959 960 static struct attribute *temac_device_attrs[] = { 961 &dev_attr_llink_regs.attr, 962 NULL, 963 }; 964 965 static const struct attribute_group temac_attr_group = { 966 .attrs = temac_device_attrs, 967 }; 968 969 /* ethtool support */ 970 static int temac_get_settings(struct net_device *ndev, struct ethtool_cmd *cmd) 971 { 972 struct temac_local *lp = netdev_priv(ndev); 973 return phy_ethtool_gset(lp->phy_dev, cmd); 974 } 975 976 static int temac_set_settings(struct net_device *ndev, struct ethtool_cmd *cmd) 977 { 978 struct temac_local *lp = netdev_priv(ndev); 979 return phy_ethtool_sset(lp->phy_dev, cmd); 980 } 981 982 static int temac_nway_reset(struct net_device *ndev) 983 { 984 struct temac_local *lp = netdev_priv(ndev); 985 return phy_start_aneg(lp->phy_dev); 986 } 987 988 static const struct ethtool_ops temac_ethtool_ops = { 989 .get_settings = temac_get_settings, 990 .set_settings = temac_set_settings, 991 .nway_reset = temac_nway_reset, 992 .get_link = ethtool_op_get_link, 993 .get_ts_info = ethtool_op_get_ts_info, 994 }; 995 996 static int temac_of_probe(struct platform_device *op) 997 { 998 struct device_node *np; 999 struct temac_local *lp; 1000 struct net_device *ndev; 1001 const void *addr; 1002 __be32 *p; 1003 int size, rc = 0; 1004 1005 /* Init network device structure */ 1006 ndev = alloc_etherdev(sizeof(*lp)); 1007 if (!ndev) 1008 return -ENOMEM; 1009 1010 ether_setup(ndev); 1011 platform_set_drvdata(op, ndev); 1012 SET_NETDEV_DEV(ndev, &op->dev); 1013 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */ 1014 ndev->features = NETIF_F_SG | NETIF_F_FRAGLIST; 1015 ndev->netdev_ops = &temac_netdev_ops; 1016 ndev->ethtool_ops = &temac_ethtool_ops; 1017 #if 0 1018 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */ 1019 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */ 1020 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */ 1021 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */ 1022 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; /* Transmit VLAN hw accel */ 1023 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; /* Receive VLAN hw acceleration */ 1024 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; /* Receive VLAN filtering */ 1025 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */ 1026 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */ 1027 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */ 1028 ndev->features |= NETIF_F_LRO; /* large receive offload */ 1029 #endif 1030 1031 /* setup temac private info structure */ 1032 lp = netdev_priv(ndev); 1033 lp->ndev = ndev; 1034 lp->dev = &op->dev; 1035 lp->options = XTE_OPTION_DEFAULTS; 1036 spin_lock_init(&lp->rx_lock); 1037 mutex_init(&lp->indirect_mutex); 1038 1039 /* map device registers */ 1040 lp->regs = of_iomap(op->dev.of_node, 0); 1041 if (!lp->regs) { 1042 dev_err(&op->dev, "could not map temac regs.\n"); 1043 goto nodev; 1044 } 1045 1046 /* Setup checksum offload, but default to off if not specified */ 1047 lp->temac_features = 0; 1048 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL); 1049 if (p && be32_to_cpu(*p)) { 1050 lp->temac_features |= TEMAC_FEATURE_TX_CSUM; 1051 /* Can checksum TCP/UDP over IPv4. */ 1052 ndev->features |= NETIF_F_IP_CSUM; 1053 } 1054 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL); 1055 if (p && be32_to_cpu(*p)) 1056 lp->temac_features |= TEMAC_FEATURE_RX_CSUM; 1057 1058 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */ 1059 np = of_parse_phandle(op->dev.of_node, "llink-connected", 0); 1060 if (!np) { 1061 dev_err(&op->dev, "could not find DMA node\n"); 1062 goto err_iounmap; 1063 } 1064 1065 /* Setup the DMA register accesses, could be DCR or memory mapped */ 1066 if (temac_dcr_setup(lp, op, np)) { 1067 1068 /* no DCR in the device tree, try non-DCR */ 1069 lp->sdma_regs = of_iomap(np, 0); 1070 if (lp->sdma_regs) { 1071 lp->dma_in = temac_dma_in32; 1072 lp->dma_out = temac_dma_out32; 1073 dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs); 1074 } else { 1075 dev_err(&op->dev, "unable to map DMA registers\n"); 1076 of_node_put(np); 1077 goto err_iounmap; 1078 } 1079 } 1080 1081 lp->rx_irq = irq_of_parse_and_map(np, 0); 1082 lp->tx_irq = irq_of_parse_and_map(np, 1); 1083 1084 of_node_put(np); /* Finished with the DMA node; drop the reference */ 1085 1086 if (!lp->rx_irq || !lp->tx_irq) { 1087 dev_err(&op->dev, "could not determine irqs\n"); 1088 rc = -ENOMEM; 1089 goto err_iounmap_2; 1090 } 1091 1092 1093 /* Retrieve the MAC address */ 1094 addr = of_get_property(op->dev.of_node, "local-mac-address", &size); 1095 if ((!addr) || (size != 6)) { 1096 dev_err(&op->dev, "could not find MAC address\n"); 1097 rc = -ENODEV; 1098 goto err_iounmap_2; 1099 } 1100 temac_init_mac_address(ndev, (void *)addr); 1101 1102 rc = temac_mdio_setup(lp, op->dev.of_node); 1103 if (rc) 1104 dev_warn(&op->dev, "error registering MDIO bus\n"); 1105 1106 lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0); 1107 if (lp->phy_node) 1108 dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np); 1109 1110 /* Add the device attributes */ 1111 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group); 1112 if (rc) { 1113 dev_err(lp->dev, "Error creating sysfs files\n"); 1114 goto err_iounmap_2; 1115 } 1116 1117 rc = register_netdev(lp->ndev); 1118 if (rc) { 1119 dev_err(lp->dev, "register_netdev() error (%i)\n", rc); 1120 goto err_register_ndev; 1121 } 1122 1123 return 0; 1124 1125 err_register_ndev: 1126 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group); 1127 err_iounmap_2: 1128 if (lp->sdma_regs) 1129 iounmap(lp->sdma_regs); 1130 err_iounmap: 1131 iounmap(lp->regs); 1132 nodev: 1133 free_netdev(ndev); 1134 ndev = NULL; 1135 return rc; 1136 } 1137 1138 static int temac_of_remove(struct platform_device *op) 1139 { 1140 struct net_device *ndev = platform_get_drvdata(op); 1141 struct temac_local *lp = netdev_priv(ndev); 1142 1143 temac_mdio_teardown(lp); 1144 unregister_netdev(ndev); 1145 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group); 1146 if (lp->phy_node) 1147 of_node_put(lp->phy_node); 1148 lp->phy_node = NULL; 1149 iounmap(lp->regs); 1150 if (lp->sdma_regs) 1151 iounmap(lp->sdma_regs); 1152 free_netdev(ndev); 1153 return 0; 1154 } 1155 1156 static struct of_device_id temac_of_match[] = { 1157 { .compatible = "xlnx,xps-ll-temac-1.01.b", }, 1158 { .compatible = "xlnx,xps-ll-temac-2.00.a", }, 1159 { .compatible = "xlnx,xps-ll-temac-2.02.a", }, 1160 { .compatible = "xlnx,xps-ll-temac-2.03.a", }, 1161 {}, 1162 }; 1163 MODULE_DEVICE_TABLE(of, temac_of_match); 1164 1165 static struct platform_driver temac_of_driver = { 1166 .probe = temac_of_probe, 1167 .remove = temac_of_remove, 1168 .driver = { 1169 .owner = THIS_MODULE, 1170 .name = "xilinx_temac", 1171 .of_match_table = temac_of_match, 1172 }, 1173 }; 1174 1175 module_platform_driver(temac_of_driver); 1176 1177 MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver"); 1178 MODULE_AUTHOR("Yoshio Kashiwagi"); 1179 MODULE_LICENSE("GPL"); 1180