1 /* 2 * Ethernet driver for the WIZnet W5100 chip. 3 * 4 * Copyright (C) 2006-2008 WIZnet Co.,Ltd. 5 * Copyright (C) 2012 Mike Sinkovsky <msink@permonline.ru> 6 * 7 * Licensed under the GPL-2 or later. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/platform_device.h> 15 #include <linux/platform_data/wiznet.h> 16 #include <linux/ethtool.h> 17 #include <linux/skbuff.h> 18 #include <linux/types.h> 19 #include <linux/errno.h> 20 #include <linux/delay.h> 21 #include <linux/slab.h> 22 #include <linux/spinlock.h> 23 #include <linux/io.h> 24 #include <linux/ioport.h> 25 #include <linux/interrupt.h> 26 #include <linux/irq.h> 27 #include <linux/gpio.h> 28 29 #include "w5100.h" 30 31 #define DRV_NAME "w5100" 32 #define DRV_VERSION "2012-04-04" 33 34 MODULE_DESCRIPTION("WIZnet W5100 Ethernet driver v"DRV_VERSION); 35 MODULE_AUTHOR("Mike Sinkovsky <msink@permonline.ru>"); 36 MODULE_ALIAS("platform:"DRV_NAME); 37 MODULE_LICENSE("GPL"); 38 39 /* 40 * W5100/W5200/W5500 common registers 41 */ 42 #define W5100_COMMON_REGS 0x0000 43 #define W5100_MR 0x0000 /* Mode Register */ 44 #define MR_RST 0x80 /* S/W reset */ 45 #define MR_PB 0x10 /* Ping block */ 46 #define MR_AI 0x02 /* Address Auto-Increment */ 47 #define MR_IND 0x01 /* Indirect mode */ 48 #define W5100_SHAR 0x0009 /* Source MAC address */ 49 #define W5100_IR 0x0015 /* Interrupt Register */ 50 #define W5100_COMMON_REGS_LEN 0x0040 51 52 #define W5100_Sn_MR 0x0000 /* Sn Mode Register */ 53 #define W5100_Sn_CR 0x0001 /* Sn Command Register */ 54 #define W5100_Sn_IR 0x0002 /* Sn Interrupt Register */ 55 #define W5100_Sn_SR 0x0003 /* Sn Status Register */ 56 #define W5100_Sn_TX_FSR 0x0020 /* Sn Transmit free memory size */ 57 #define W5100_Sn_TX_RD 0x0022 /* Sn Transmit memory read pointer */ 58 #define W5100_Sn_TX_WR 0x0024 /* Sn Transmit memory write pointer */ 59 #define W5100_Sn_RX_RSR 0x0026 /* Sn Receive free memory size */ 60 #define W5100_Sn_RX_RD 0x0028 /* Sn Receive memory read pointer */ 61 62 #define S0_REGS(priv) ((priv)->s0_regs) 63 64 #define W5100_S0_MR(priv) (S0_REGS(priv) + W5100_Sn_MR) 65 #define S0_MR_MACRAW 0x04 /* MAC RAW mode */ 66 #define S0_MR_MF 0x40 /* MAC Filter for W5100 and W5200 */ 67 #define W5500_S0_MR_MF 0x80 /* MAC Filter for W5500 */ 68 #define W5100_S0_CR(priv) (S0_REGS(priv) + W5100_Sn_CR) 69 #define S0_CR_OPEN 0x01 /* OPEN command */ 70 #define S0_CR_CLOSE 0x10 /* CLOSE command */ 71 #define S0_CR_SEND 0x20 /* SEND command */ 72 #define S0_CR_RECV 0x40 /* RECV command */ 73 #define W5100_S0_IR(priv) (S0_REGS(priv) + W5100_Sn_IR) 74 #define S0_IR_SENDOK 0x10 /* complete sending */ 75 #define S0_IR_RECV 0x04 /* receiving data */ 76 #define W5100_S0_SR(priv) (S0_REGS(priv) + W5100_Sn_SR) 77 #define S0_SR_MACRAW 0x42 /* mac raw mode */ 78 #define W5100_S0_TX_FSR(priv) (S0_REGS(priv) + W5100_Sn_TX_FSR) 79 #define W5100_S0_TX_RD(priv) (S0_REGS(priv) + W5100_Sn_TX_RD) 80 #define W5100_S0_TX_WR(priv) (S0_REGS(priv) + W5100_Sn_TX_WR) 81 #define W5100_S0_RX_RSR(priv) (S0_REGS(priv) + W5100_Sn_RX_RSR) 82 #define W5100_S0_RX_RD(priv) (S0_REGS(priv) + W5100_Sn_RX_RD) 83 84 #define W5100_S0_REGS_LEN 0x0040 85 86 /* 87 * W5100 and W5200 common registers 88 */ 89 #define W5100_IMR 0x0016 /* Interrupt Mask Register */ 90 #define IR_S0 0x01 /* S0 interrupt */ 91 #define W5100_RTR 0x0017 /* Retry Time-value Register */ 92 #define RTR_DEFAULT 2000 /* =0x07d0 (2000) */ 93 94 /* 95 * W5100 specific register and memory 96 */ 97 #define W5100_RMSR 0x001a /* Receive Memory Size */ 98 #define W5100_TMSR 0x001b /* Transmit Memory Size */ 99 100 #define W5100_S0_REGS 0x0400 101 102 #define W5100_TX_MEM_START 0x4000 103 #define W5100_TX_MEM_SIZE 0x2000 104 #define W5100_RX_MEM_START 0x6000 105 #define W5100_RX_MEM_SIZE 0x2000 106 107 /* 108 * W5200 specific register and memory 109 */ 110 #define W5200_S0_REGS 0x4000 111 112 #define W5200_Sn_RXMEM_SIZE(n) (0x401e + (n) * 0x0100) /* Sn RX Memory Size */ 113 #define W5200_Sn_TXMEM_SIZE(n) (0x401f + (n) * 0x0100) /* Sn TX Memory Size */ 114 115 #define W5200_TX_MEM_START 0x8000 116 #define W5200_TX_MEM_SIZE 0x4000 117 #define W5200_RX_MEM_START 0xc000 118 #define W5200_RX_MEM_SIZE 0x4000 119 120 /* 121 * W5500 specific register and memory 122 * 123 * W5500 register and memory are organized by multiple blocks. Each one is 124 * selected by 16bits offset address and 5bits block select bits. So we 125 * encode it into 32bits address. (lower 16bits is offset address and 126 * upper 16bits is block select bits) 127 */ 128 #define W5500_SIMR 0x0018 /* Socket Interrupt Mask Register */ 129 #define W5500_RTR 0x0019 /* Retry Time-value Register */ 130 131 #define W5500_S0_REGS 0x10000 132 133 #define W5500_Sn_RXMEM_SIZE(n) \ 134 (0x1001e + (n) * 0x40000) /* Sn RX Memory Size */ 135 #define W5500_Sn_TXMEM_SIZE(n) \ 136 (0x1001f + (n) * 0x40000) /* Sn TX Memory Size */ 137 138 #define W5500_TX_MEM_START 0x20000 139 #define W5500_TX_MEM_SIZE 0x04000 140 #define W5500_RX_MEM_START 0x30000 141 #define W5500_RX_MEM_SIZE 0x04000 142 143 /* 144 * Device driver private data structure 145 */ 146 147 struct w5100_priv { 148 const struct w5100_ops *ops; 149 150 /* Socket 0 register offset address */ 151 u32 s0_regs; 152 /* Socket 0 TX buffer offset address and size */ 153 u32 s0_tx_buf; 154 u16 s0_tx_buf_size; 155 /* Socket 0 RX buffer offset address and size */ 156 u32 s0_rx_buf; 157 u16 s0_rx_buf_size; 158 159 int irq; 160 int link_irq; 161 int link_gpio; 162 163 struct napi_struct napi; 164 struct net_device *ndev; 165 bool promisc; 166 u32 msg_enable; 167 168 struct workqueue_struct *xfer_wq; 169 struct work_struct rx_work; 170 struct sk_buff *tx_skb; 171 struct work_struct tx_work; 172 struct work_struct setrx_work; 173 struct work_struct restart_work; 174 }; 175 176 /************************************************************************ 177 * 178 * Lowlevel I/O functions 179 * 180 ***********************************************************************/ 181 182 struct w5100_mmio_priv { 183 void __iomem *base; 184 /* Serialize access in indirect address mode */ 185 spinlock_t reg_lock; 186 }; 187 188 static inline struct w5100_mmio_priv *w5100_mmio_priv(struct net_device *dev) 189 { 190 return w5100_ops_priv(dev); 191 } 192 193 static inline void __iomem *w5100_mmio(struct net_device *ndev) 194 { 195 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev); 196 197 return mmio_priv->base; 198 } 199 200 /* 201 * In direct address mode host system can directly access W5100 registers 202 * after mapping to Memory-Mapped I/O space. 203 * 204 * 0x8000 bytes are required for memory space. 205 */ 206 static inline int w5100_read_direct(struct net_device *ndev, u32 addr) 207 { 208 return ioread8(w5100_mmio(ndev) + (addr << CONFIG_WIZNET_BUS_SHIFT)); 209 } 210 211 static inline int __w5100_write_direct(struct net_device *ndev, u32 addr, 212 u8 data) 213 { 214 iowrite8(data, w5100_mmio(ndev) + (addr << CONFIG_WIZNET_BUS_SHIFT)); 215 216 return 0; 217 } 218 219 static inline int w5100_write_direct(struct net_device *ndev, u32 addr, u8 data) 220 { 221 __w5100_write_direct(ndev, addr, data); 222 223 return 0; 224 } 225 226 static int w5100_read16_direct(struct net_device *ndev, u32 addr) 227 { 228 u16 data; 229 data = w5100_read_direct(ndev, addr) << 8; 230 data |= w5100_read_direct(ndev, addr + 1); 231 return data; 232 } 233 234 static int w5100_write16_direct(struct net_device *ndev, u32 addr, u16 data) 235 { 236 __w5100_write_direct(ndev, addr, data >> 8); 237 __w5100_write_direct(ndev, addr + 1, data); 238 239 return 0; 240 } 241 242 static int w5100_readbulk_direct(struct net_device *ndev, u32 addr, u8 *buf, 243 int len) 244 { 245 int i; 246 247 for (i = 0; i < len; i++, addr++) 248 *buf++ = w5100_read_direct(ndev, addr); 249 250 return 0; 251 } 252 253 static int w5100_writebulk_direct(struct net_device *ndev, u32 addr, 254 const u8 *buf, int len) 255 { 256 int i; 257 258 for (i = 0; i < len; i++, addr++) 259 __w5100_write_direct(ndev, addr, *buf++); 260 261 return 0; 262 } 263 264 static int w5100_mmio_init(struct net_device *ndev) 265 { 266 struct platform_device *pdev = to_platform_device(ndev->dev.parent); 267 struct w5100_priv *priv = netdev_priv(ndev); 268 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev); 269 struct resource *mem; 270 271 spin_lock_init(&mmio_priv->reg_lock); 272 273 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 274 mmio_priv->base = devm_ioremap_resource(&pdev->dev, mem); 275 if (IS_ERR(mmio_priv->base)) 276 return PTR_ERR(mmio_priv->base); 277 278 netdev_info(ndev, "at 0x%llx irq %d\n", (u64)mem->start, priv->irq); 279 280 return 0; 281 } 282 283 static const struct w5100_ops w5100_mmio_direct_ops = { 284 .chip_id = W5100, 285 .read = w5100_read_direct, 286 .write = w5100_write_direct, 287 .read16 = w5100_read16_direct, 288 .write16 = w5100_write16_direct, 289 .readbulk = w5100_readbulk_direct, 290 .writebulk = w5100_writebulk_direct, 291 .init = w5100_mmio_init, 292 }; 293 294 /* 295 * In indirect address mode host system indirectly accesses registers by 296 * using Indirect Mode Address Register (IDM_AR) and Indirect Mode Data 297 * Register (IDM_DR), which are directly mapped to Memory-Mapped I/O space. 298 * Mode Register (MR) is directly accessible. 299 * 300 * Only 0x04 bytes are required for memory space. 301 */ 302 #define W5100_IDM_AR 0x01 /* Indirect Mode Address Register */ 303 #define W5100_IDM_DR 0x03 /* Indirect Mode Data Register */ 304 305 static int w5100_read_indirect(struct net_device *ndev, u32 addr) 306 { 307 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev); 308 unsigned long flags; 309 u8 data; 310 311 spin_lock_irqsave(&mmio_priv->reg_lock, flags); 312 w5100_write16_direct(ndev, W5100_IDM_AR, addr); 313 data = w5100_read_direct(ndev, W5100_IDM_DR); 314 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags); 315 316 return data; 317 } 318 319 static int w5100_write_indirect(struct net_device *ndev, u32 addr, u8 data) 320 { 321 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev); 322 unsigned long flags; 323 324 spin_lock_irqsave(&mmio_priv->reg_lock, flags); 325 w5100_write16_direct(ndev, W5100_IDM_AR, addr); 326 w5100_write_direct(ndev, W5100_IDM_DR, data); 327 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags); 328 329 return 0; 330 } 331 332 static int w5100_read16_indirect(struct net_device *ndev, u32 addr) 333 { 334 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev); 335 unsigned long flags; 336 u16 data; 337 338 spin_lock_irqsave(&mmio_priv->reg_lock, flags); 339 w5100_write16_direct(ndev, W5100_IDM_AR, addr); 340 data = w5100_read_direct(ndev, W5100_IDM_DR) << 8; 341 data |= w5100_read_direct(ndev, W5100_IDM_DR); 342 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags); 343 344 return data; 345 } 346 347 static int w5100_write16_indirect(struct net_device *ndev, u32 addr, u16 data) 348 { 349 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev); 350 unsigned long flags; 351 352 spin_lock_irqsave(&mmio_priv->reg_lock, flags); 353 w5100_write16_direct(ndev, W5100_IDM_AR, addr); 354 __w5100_write_direct(ndev, W5100_IDM_DR, data >> 8); 355 w5100_write_direct(ndev, W5100_IDM_DR, data); 356 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags); 357 358 return 0; 359 } 360 361 static int w5100_readbulk_indirect(struct net_device *ndev, u32 addr, u8 *buf, 362 int len) 363 { 364 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev); 365 unsigned long flags; 366 int i; 367 368 spin_lock_irqsave(&mmio_priv->reg_lock, flags); 369 w5100_write16_direct(ndev, W5100_IDM_AR, addr); 370 371 for (i = 0; i < len; i++) 372 *buf++ = w5100_read_direct(ndev, W5100_IDM_DR); 373 374 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags); 375 376 return 0; 377 } 378 379 static int w5100_writebulk_indirect(struct net_device *ndev, u32 addr, 380 const u8 *buf, int len) 381 { 382 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev); 383 unsigned long flags; 384 int i; 385 386 spin_lock_irqsave(&mmio_priv->reg_lock, flags); 387 w5100_write16_direct(ndev, W5100_IDM_AR, addr); 388 389 for (i = 0; i < len; i++) 390 __w5100_write_direct(ndev, W5100_IDM_DR, *buf++); 391 392 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags); 393 394 return 0; 395 } 396 397 static int w5100_reset_indirect(struct net_device *ndev) 398 { 399 w5100_write_direct(ndev, W5100_MR, MR_RST); 400 mdelay(5); 401 w5100_write_direct(ndev, W5100_MR, MR_PB | MR_AI | MR_IND); 402 403 return 0; 404 } 405 406 static const struct w5100_ops w5100_mmio_indirect_ops = { 407 .chip_id = W5100, 408 .read = w5100_read_indirect, 409 .write = w5100_write_indirect, 410 .read16 = w5100_read16_indirect, 411 .write16 = w5100_write16_indirect, 412 .readbulk = w5100_readbulk_indirect, 413 .writebulk = w5100_writebulk_indirect, 414 .init = w5100_mmio_init, 415 .reset = w5100_reset_indirect, 416 }; 417 418 #if defined(CONFIG_WIZNET_BUS_DIRECT) 419 420 static int w5100_read(struct w5100_priv *priv, u32 addr) 421 { 422 return w5100_read_direct(priv->ndev, addr); 423 } 424 425 static int w5100_write(struct w5100_priv *priv, u32 addr, u8 data) 426 { 427 return w5100_write_direct(priv->ndev, addr, data); 428 } 429 430 static int w5100_read16(struct w5100_priv *priv, u32 addr) 431 { 432 return w5100_read16_direct(priv->ndev, addr); 433 } 434 435 static int w5100_write16(struct w5100_priv *priv, u32 addr, u16 data) 436 { 437 return w5100_write16_direct(priv->ndev, addr, data); 438 } 439 440 static int w5100_readbulk(struct w5100_priv *priv, u32 addr, u8 *buf, int len) 441 { 442 return w5100_readbulk_direct(priv->ndev, addr, buf, len); 443 } 444 445 static int w5100_writebulk(struct w5100_priv *priv, u32 addr, const u8 *buf, 446 int len) 447 { 448 return w5100_writebulk_direct(priv->ndev, addr, buf, len); 449 } 450 451 #elif defined(CONFIG_WIZNET_BUS_INDIRECT) 452 453 static int w5100_read(struct w5100_priv *priv, u32 addr) 454 { 455 return w5100_read_indirect(priv->ndev, addr); 456 } 457 458 static int w5100_write(struct w5100_priv *priv, u32 addr, u8 data) 459 { 460 return w5100_write_indirect(priv->ndev, addr, data); 461 } 462 463 static int w5100_read16(struct w5100_priv *priv, u32 addr) 464 { 465 return w5100_read16_indirect(priv->ndev, addr); 466 } 467 468 static int w5100_write16(struct w5100_priv *priv, u32 addr, u16 data) 469 { 470 return w5100_write16_indirect(priv->ndev, addr, data); 471 } 472 473 static int w5100_readbulk(struct w5100_priv *priv, u32 addr, u8 *buf, int len) 474 { 475 return w5100_readbulk_indirect(priv->ndev, addr, buf, len); 476 } 477 478 static int w5100_writebulk(struct w5100_priv *priv, u32 addr, const u8 *buf, 479 int len) 480 { 481 return w5100_writebulk_indirect(priv->ndev, addr, buf, len); 482 } 483 484 #else /* CONFIG_WIZNET_BUS_ANY */ 485 486 static int w5100_read(struct w5100_priv *priv, u32 addr) 487 { 488 return priv->ops->read(priv->ndev, addr); 489 } 490 491 static int w5100_write(struct w5100_priv *priv, u32 addr, u8 data) 492 { 493 return priv->ops->write(priv->ndev, addr, data); 494 } 495 496 static int w5100_read16(struct w5100_priv *priv, u32 addr) 497 { 498 return priv->ops->read16(priv->ndev, addr); 499 } 500 501 static int w5100_write16(struct w5100_priv *priv, u32 addr, u16 data) 502 { 503 return priv->ops->write16(priv->ndev, addr, data); 504 } 505 506 static int w5100_readbulk(struct w5100_priv *priv, u32 addr, u8 *buf, int len) 507 { 508 return priv->ops->readbulk(priv->ndev, addr, buf, len); 509 } 510 511 static int w5100_writebulk(struct w5100_priv *priv, u32 addr, const u8 *buf, 512 int len) 513 { 514 return priv->ops->writebulk(priv->ndev, addr, buf, len); 515 } 516 517 #endif 518 519 static int w5100_readbuf(struct w5100_priv *priv, u16 offset, u8 *buf, int len) 520 { 521 u32 addr; 522 int remain = 0; 523 int ret; 524 const u32 mem_start = priv->s0_rx_buf; 525 const u16 mem_size = priv->s0_rx_buf_size; 526 527 offset %= mem_size; 528 addr = mem_start + offset; 529 530 if (offset + len > mem_size) { 531 remain = (offset + len) % mem_size; 532 len = mem_size - offset; 533 } 534 535 ret = w5100_readbulk(priv, addr, buf, len); 536 if (ret || !remain) 537 return ret; 538 539 return w5100_readbulk(priv, mem_start, buf + len, remain); 540 } 541 542 static int w5100_writebuf(struct w5100_priv *priv, u16 offset, const u8 *buf, 543 int len) 544 { 545 u32 addr; 546 int ret; 547 int remain = 0; 548 const u32 mem_start = priv->s0_tx_buf; 549 const u16 mem_size = priv->s0_tx_buf_size; 550 551 offset %= mem_size; 552 addr = mem_start + offset; 553 554 if (offset + len > mem_size) { 555 remain = (offset + len) % mem_size; 556 len = mem_size - offset; 557 } 558 559 ret = w5100_writebulk(priv, addr, buf, len); 560 if (ret || !remain) 561 return ret; 562 563 return w5100_writebulk(priv, mem_start, buf + len, remain); 564 } 565 566 static int w5100_reset(struct w5100_priv *priv) 567 { 568 if (priv->ops->reset) 569 return priv->ops->reset(priv->ndev); 570 571 w5100_write(priv, W5100_MR, MR_RST); 572 mdelay(5); 573 w5100_write(priv, W5100_MR, MR_PB); 574 575 return 0; 576 } 577 578 static int w5100_command(struct w5100_priv *priv, u16 cmd) 579 { 580 unsigned long timeout; 581 582 w5100_write(priv, W5100_S0_CR(priv), cmd); 583 584 timeout = jiffies + msecs_to_jiffies(100); 585 586 while (w5100_read(priv, W5100_S0_CR(priv)) != 0) { 587 if (time_after(jiffies, timeout)) 588 return -EIO; 589 cpu_relax(); 590 } 591 592 return 0; 593 } 594 595 static void w5100_write_macaddr(struct w5100_priv *priv) 596 { 597 struct net_device *ndev = priv->ndev; 598 599 w5100_writebulk(priv, W5100_SHAR, ndev->dev_addr, ETH_ALEN); 600 } 601 602 static void w5100_socket_intr_mask(struct w5100_priv *priv, u8 mask) 603 { 604 u32 imr; 605 606 if (priv->ops->chip_id == W5500) 607 imr = W5500_SIMR; 608 else 609 imr = W5100_IMR; 610 611 w5100_write(priv, imr, mask); 612 } 613 614 static void w5100_enable_intr(struct w5100_priv *priv) 615 { 616 w5100_socket_intr_mask(priv, IR_S0); 617 } 618 619 static void w5100_disable_intr(struct w5100_priv *priv) 620 { 621 w5100_socket_intr_mask(priv, 0); 622 } 623 624 static void w5100_memory_configure(struct w5100_priv *priv) 625 { 626 /* Configure 16K of internal memory 627 * as 8K RX buffer and 8K TX buffer 628 */ 629 w5100_write(priv, W5100_RMSR, 0x03); 630 w5100_write(priv, W5100_TMSR, 0x03); 631 } 632 633 static void w5200_memory_configure(struct w5100_priv *priv) 634 { 635 int i; 636 637 /* Configure internal RX memory as 16K RX buffer and 638 * internal TX memory as 16K TX buffer 639 */ 640 w5100_write(priv, W5200_Sn_RXMEM_SIZE(0), 0x10); 641 w5100_write(priv, W5200_Sn_TXMEM_SIZE(0), 0x10); 642 643 for (i = 1; i < 8; i++) { 644 w5100_write(priv, W5200_Sn_RXMEM_SIZE(i), 0); 645 w5100_write(priv, W5200_Sn_TXMEM_SIZE(i), 0); 646 } 647 } 648 649 static void w5500_memory_configure(struct w5100_priv *priv) 650 { 651 int i; 652 653 /* Configure internal RX memory as 16K RX buffer and 654 * internal TX memory as 16K TX buffer 655 */ 656 w5100_write(priv, W5500_Sn_RXMEM_SIZE(0), 0x10); 657 w5100_write(priv, W5500_Sn_TXMEM_SIZE(0), 0x10); 658 659 for (i = 1; i < 8; i++) { 660 w5100_write(priv, W5500_Sn_RXMEM_SIZE(i), 0); 661 w5100_write(priv, W5500_Sn_TXMEM_SIZE(i), 0); 662 } 663 } 664 665 static int w5100_hw_reset(struct w5100_priv *priv) 666 { 667 u32 rtr; 668 669 w5100_reset(priv); 670 671 w5100_disable_intr(priv); 672 w5100_write_macaddr(priv); 673 674 switch (priv->ops->chip_id) { 675 case W5100: 676 w5100_memory_configure(priv); 677 rtr = W5100_RTR; 678 break; 679 case W5200: 680 w5200_memory_configure(priv); 681 rtr = W5100_RTR; 682 break; 683 case W5500: 684 w5500_memory_configure(priv); 685 rtr = W5500_RTR; 686 break; 687 default: 688 return -EINVAL; 689 } 690 691 if (w5100_read16(priv, rtr) != RTR_DEFAULT) 692 return -ENODEV; 693 694 return 0; 695 } 696 697 static void w5100_hw_start(struct w5100_priv *priv) 698 { 699 u8 mode = S0_MR_MACRAW; 700 701 if (!priv->promisc) { 702 if (priv->ops->chip_id == W5500) 703 mode |= W5500_S0_MR_MF; 704 else 705 mode |= S0_MR_MF; 706 } 707 708 w5100_write(priv, W5100_S0_MR(priv), mode); 709 w5100_command(priv, S0_CR_OPEN); 710 w5100_enable_intr(priv); 711 } 712 713 static void w5100_hw_close(struct w5100_priv *priv) 714 { 715 w5100_disable_intr(priv); 716 w5100_command(priv, S0_CR_CLOSE); 717 } 718 719 /*********************************************************************** 720 * 721 * Device driver functions / callbacks 722 * 723 ***********************************************************************/ 724 725 static void w5100_get_drvinfo(struct net_device *ndev, 726 struct ethtool_drvinfo *info) 727 { 728 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 729 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 730 strlcpy(info->bus_info, dev_name(ndev->dev.parent), 731 sizeof(info->bus_info)); 732 } 733 734 static u32 w5100_get_link(struct net_device *ndev) 735 { 736 struct w5100_priv *priv = netdev_priv(ndev); 737 738 if (gpio_is_valid(priv->link_gpio)) 739 return !!gpio_get_value(priv->link_gpio); 740 741 return 1; 742 } 743 744 static u32 w5100_get_msglevel(struct net_device *ndev) 745 { 746 struct w5100_priv *priv = netdev_priv(ndev); 747 748 return priv->msg_enable; 749 } 750 751 static void w5100_set_msglevel(struct net_device *ndev, u32 value) 752 { 753 struct w5100_priv *priv = netdev_priv(ndev); 754 755 priv->msg_enable = value; 756 } 757 758 static int w5100_get_regs_len(struct net_device *ndev) 759 { 760 return W5100_COMMON_REGS_LEN + W5100_S0_REGS_LEN; 761 } 762 763 static void w5100_get_regs(struct net_device *ndev, 764 struct ethtool_regs *regs, void *buf) 765 { 766 struct w5100_priv *priv = netdev_priv(ndev); 767 768 regs->version = 1; 769 w5100_readbulk(priv, W5100_COMMON_REGS, buf, W5100_COMMON_REGS_LEN); 770 buf += W5100_COMMON_REGS_LEN; 771 w5100_readbulk(priv, S0_REGS(priv), buf, W5100_S0_REGS_LEN); 772 } 773 774 static void w5100_restart(struct net_device *ndev) 775 { 776 struct w5100_priv *priv = netdev_priv(ndev); 777 778 netif_stop_queue(ndev); 779 w5100_hw_reset(priv); 780 w5100_hw_start(priv); 781 ndev->stats.tx_errors++; 782 netif_trans_update(ndev); 783 netif_wake_queue(ndev); 784 } 785 786 static void w5100_restart_work(struct work_struct *work) 787 { 788 struct w5100_priv *priv = container_of(work, struct w5100_priv, 789 restart_work); 790 791 w5100_restart(priv->ndev); 792 } 793 794 static void w5100_tx_timeout(struct net_device *ndev) 795 { 796 struct w5100_priv *priv = netdev_priv(ndev); 797 798 if (priv->ops->may_sleep) 799 schedule_work(&priv->restart_work); 800 else 801 w5100_restart(ndev); 802 } 803 804 static void w5100_tx_skb(struct net_device *ndev, struct sk_buff *skb) 805 { 806 struct w5100_priv *priv = netdev_priv(ndev); 807 u16 offset; 808 809 offset = w5100_read16(priv, W5100_S0_TX_WR(priv)); 810 w5100_writebuf(priv, offset, skb->data, skb->len); 811 w5100_write16(priv, W5100_S0_TX_WR(priv), offset + skb->len); 812 ndev->stats.tx_bytes += skb->len; 813 ndev->stats.tx_packets++; 814 dev_kfree_skb(skb); 815 816 w5100_command(priv, S0_CR_SEND); 817 } 818 819 static void w5100_tx_work(struct work_struct *work) 820 { 821 struct w5100_priv *priv = container_of(work, struct w5100_priv, 822 tx_work); 823 struct sk_buff *skb = priv->tx_skb; 824 825 priv->tx_skb = NULL; 826 827 if (WARN_ON(!skb)) 828 return; 829 w5100_tx_skb(priv->ndev, skb); 830 } 831 832 static netdev_tx_t w5100_start_tx(struct sk_buff *skb, struct net_device *ndev) 833 { 834 struct w5100_priv *priv = netdev_priv(ndev); 835 836 netif_stop_queue(ndev); 837 838 if (priv->ops->may_sleep) { 839 WARN_ON(priv->tx_skb); 840 priv->tx_skb = skb; 841 queue_work(priv->xfer_wq, &priv->tx_work); 842 } else { 843 w5100_tx_skb(ndev, skb); 844 } 845 846 return NETDEV_TX_OK; 847 } 848 849 static struct sk_buff *w5100_rx_skb(struct net_device *ndev) 850 { 851 struct w5100_priv *priv = netdev_priv(ndev); 852 struct sk_buff *skb; 853 u16 rx_len; 854 u16 offset; 855 u8 header[2]; 856 u16 rx_buf_len = w5100_read16(priv, W5100_S0_RX_RSR(priv)); 857 858 if (rx_buf_len == 0) 859 return NULL; 860 861 offset = w5100_read16(priv, W5100_S0_RX_RD(priv)); 862 w5100_readbuf(priv, offset, header, 2); 863 rx_len = get_unaligned_be16(header) - 2; 864 865 skb = netdev_alloc_skb_ip_align(ndev, rx_len); 866 if (unlikely(!skb)) { 867 w5100_write16(priv, W5100_S0_RX_RD(priv), offset + rx_buf_len); 868 w5100_command(priv, S0_CR_RECV); 869 ndev->stats.rx_dropped++; 870 return NULL; 871 } 872 873 skb_put(skb, rx_len); 874 w5100_readbuf(priv, offset + 2, skb->data, rx_len); 875 w5100_write16(priv, W5100_S0_RX_RD(priv), offset + 2 + rx_len); 876 w5100_command(priv, S0_CR_RECV); 877 skb->protocol = eth_type_trans(skb, ndev); 878 879 ndev->stats.rx_packets++; 880 ndev->stats.rx_bytes += rx_len; 881 882 return skb; 883 } 884 885 static void w5100_rx_work(struct work_struct *work) 886 { 887 struct w5100_priv *priv = container_of(work, struct w5100_priv, 888 rx_work); 889 struct sk_buff *skb; 890 891 while ((skb = w5100_rx_skb(priv->ndev))) 892 netif_rx_ni(skb); 893 894 w5100_enable_intr(priv); 895 } 896 897 static int w5100_napi_poll(struct napi_struct *napi, int budget) 898 { 899 struct w5100_priv *priv = container_of(napi, struct w5100_priv, napi); 900 int rx_count; 901 902 for (rx_count = 0; rx_count < budget; rx_count++) { 903 struct sk_buff *skb = w5100_rx_skb(priv->ndev); 904 905 if (skb) 906 netif_receive_skb(skb); 907 else 908 break; 909 } 910 911 if (rx_count < budget) { 912 napi_complete_done(napi, rx_count); 913 w5100_enable_intr(priv); 914 } 915 916 return rx_count; 917 } 918 919 static irqreturn_t w5100_interrupt(int irq, void *ndev_instance) 920 { 921 struct net_device *ndev = ndev_instance; 922 struct w5100_priv *priv = netdev_priv(ndev); 923 924 int ir = w5100_read(priv, W5100_S0_IR(priv)); 925 if (!ir) 926 return IRQ_NONE; 927 w5100_write(priv, W5100_S0_IR(priv), ir); 928 929 if (ir & S0_IR_SENDOK) { 930 netif_dbg(priv, tx_done, ndev, "tx done\n"); 931 netif_wake_queue(ndev); 932 } 933 934 if (ir & S0_IR_RECV) { 935 w5100_disable_intr(priv); 936 937 if (priv->ops->may_sleep) 938 queue_work(priv->xfer_wq, &priv->rx_work); 939 else if (napi_schedule_prep(&priv->napi)) 940 __napi_schedule(&priv->napi); 941 } 942 943 return IRQ_HANDLED; 944 } 945 946 static irqreturn_t w5100_detect_link(int irq, void *ndev_instance) 947 { 948 struct net_device *ndev = ndev_instance; 949 struct w5100_priv *priv = netdev_priv(ndev); 950 951 if (netif_running(ndev)) { 952 if (gpio_get_value(priv->link_gpio) != 0) { 953 netif_info(priv, link, ndev, "link is up\n"); 954 netif_carrier_on(ndev); 955 } else { 956 netif_info(priv, link, ndev, "link is down\n"); 957 netif_carrier_off(ndev); 958 } 959 } 960 961 return IRQ_HANDLED; 962 } 963 964 static void w5100_setrx_work(struct work_struct *work) 965 { 966 struct w5100_priv *priv = container_of(work, struct w5100_priv, 967 setrx_work); 968 969 w5100_hw_start(priv); 970 } 971 972 static void w5100_set_rx_mode(struct net_device *ndev) 973 { 974 struct w5100_priv *priv = netdev_priv(ndev); 975 bool set_promisc = (ndev->flags & IFF_PROMISC) != 0; 976 977 if (priv->promisc != set_promisc) { 978 priv->promisc = set_promisc; 979 980 if (priv->ops->may_sleep) 981 schedule_work(&priv->setrx_work); 982 else 983 w5100_hw_start(priv); 984 } 985 } 986 987 static int w5100_set_macaddr(struct net_device *ndev, void *addr) 988 { 989 struct w5100_priv *priv = netdev_priv(ndev); 990 struct sockaddr *sock_addr = addr; 991 992 if (!is_valid_ether_addr(sock_addr->sa_data)) 993 return -EADDRNOTAVAIL; 994 memcpy(ndev->dev_addr, sock_addr->sa_data, ETH_ALEN); 995 w5100_write_macaddr(priv); 996 return 0; 997 } 998 999 static int w5100_open(struct net_device *ndev) 1000 { 1001 struct w5100_priv *priv = netdev_priv(ndev); 1002 1003 netif_info(priv, ifup, ndev, "enabling\n"); 1004 w5100_hw_start(priv); 1005 napi_enable(&priv->napi); 1006 netif_start_queue(ndev); 1007 if (!gpio_is_valid(priv->link_gpio) || 1008 gpio_get_value(priv->link_gpio) != 0) 1009 netif_carrier_on(ndev); 1010 return 0; 1011 } 1012 1013 static int w5100_stop(struct net_device *ndev) 1014 { 1015 struct w5100_priv *priv = netdev_priv(ndev); 1016 1017 netif_info(priv, ifdown, ndev, "shutting down\n"); 1018 w5100_hw_close(priv); 1019 netif_carrier_off(ndev); 1020 netif_stop_queue(ndev); 1021 napi_disable(&priv->napi); 1022 return 0; 1023 } 1024 1025 static const struct ethtool_ops w5100_ethtool_ops = { 1026 .get_drvinfo = w5100_get_drvinfo, 1027 .get_msglevel = w5100_get_msglevel, 1028 .set_msglevel = w5100_set_msglevel, 1029 .get_link = w5100_get_link, 1030 .get_regs_len = w5100_get_regs_len, 1031 .get_regs = w5100_get_regs, 1032 }; 1033 1034 static const struct net_device_ops w5100_netdev_ops = { 1035 .ndo_open = w5100_open, 1036 .ndo_stop = w5100_stop, 1037 .ndo_start_xmit = w5100_start_tx, 1038 .ndo_tx_timeout = w5100_tx_timeout, 1039 .ndo_set_rx_mode = w5100_set_rx_mode, 1040 .ndo_set_mac_address = w5100_set_macaddr, 1041 .ndo_validate_addr = eth_validate_addr, 1042 }; 1043 1044 static int w5100_mmio_probe(struct platform_device *pdev) 1045 { 1046 struct wiznet_platform_data *data = dev_get_platdata(&pdev->dev); 1047 const void *mac_addr = NULL; 1048 struct resource *mem; 1049 const struct w5100_ops *ops; 1050 int irq; 1051 1052 if (data && is_valid_ether_addr(data->mac_addr)) 1053 mac_addr = data->mac_addr; 1054 1055 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1056 if (resource_size(mem) < W5100_BUS_DIRECT_SIZE) 1057 ops = &w5100_mmio_indirect_ops; 1058 else 1059 ops = &w5100_mmio_direct_ops; 1060 1061 irq = platform_get_irq(pdev, 0); 1062 if (irq < 0) 1063 return irq; 1064 1065 return w5100_probe(&pdev->dev, ops, sizeof(struct w5100_mmio_priv), 1066 mac_addr, irq, data ? data->link_gpio : -EINVAL); 1067 } 1068 1069 static int w5100_mmio_remove(struct platform_device *pdev) 1070 { 1071 return w5100_remove(&pdev->dev); 1072 } 1073 1074 void *w5100_ops_priv(const struct net_device *ndev) 1075 { 1076 return netdev_priv(ndev) + 1077 ALIGN(sizeof(struct w5100_priv), NETDEV_ALIGN); 1078 } 1079 EXPORT_SYMBOL_GPL(w5100_ops_priv); 1080 1081 int w5100_probe(struct device *dev, const struct w5100_ops *ops, 1082 int sizeof_ops_priv, const void *mac_addr, int irq, 1083 int link_gpio) 1084 { 1085 struct w5100_priv *priv; 1086 struct net_device *ndev; 1087 int err; 1088 size_t alloc_size; 1089 1090 alloc_size = sizeof(*priv); 1091 if (sizeof_ops_priv) { 1092 alloc_size = ALIGN(alloc_size, NETDEV_ALIGN); 1093 alloc_size += sizeof_ops_priv; 1094 } 1095 alloc_size += NETDEV_ALIGN - 1; 1096 1097 ndev = alloc_etherdev(alloc_size); 1098 if (!ndev) 1099 return -ENOMEM; 1100 SET_NETDEV_DEV(ndev, dev); 1101 dev_set_drvdata(dev, ndev); 1102 priv = netdev_priv(ndev); 1103 1104 switch (ops->chip_id) { 1105 case W5100: 1106 priv->s0_regs = W5100_S0_REGS; 1107 priv->s0_tx_buf = W5100_TX_MEM_START; 1108 priv->s0_tx_buf_size = W5100_TX_MEM_SIZE; 1109 priv->s0_rx_buf = W5100_RX_MEM_START; 1110 priv->s0_rx_buf_size = W5100_RX_MEM_SIZE; 1111 break; 1112 case W5200: 1113 priv->s0_regs = W5200_S0_REGS; 1114 priv->s0_tx_buf = W5200_TX_MEM_START; 1115 priv->s0_tx_buf_size = W5200_TX_MEM_SIZE; 1116 priv->s0_rx_buf = W5200_RX_MEM_START; 1117 priv->s0_rx_buf_size = W5200_RX_MEM_SIZE; 1118 break; 1119 case W5500: 1120 priv->s0_regs = W5500_S0_REGS; 1121 priv->s0_tx_buf = W5500_TX_MEM_START; 1122 priv->s0_tx_buf_size = W5500_TX_MEM_SIZE; 1123 priv->s0_rx_buf = W5500_RX_MEM_START; 1124 priv->s0_rx_buf_size = W5500_RX_MEM_SIZE; 1125 break; 1126 default: 1127 err = -EINVAL; 1128 goto err_register; 1129 } 1130 1131 priv->ndev = ndev; 1132 priv->ops = ops; 1133 priv->irq = irq; 1134 priv->link_gpio = link_gpio; 1135 1136 ndev->netdev_ops = &w5100_netdev_ops; 1137 ndev->ethtool_ops = &w5100_ethtool_ops; 1138 netif_napi_add(ndev, &priv->napi, w5100_napi_poll, 16); 1139 1140 /* This chip doesn't support VLAN packets with normal MTU, 1141 * so disable VLAN for this device. 1142 */ 1143 ndev->features |= NETIF_F_VLAN_CHALLENGED; 1144 1145 err = register_netdev(ndev); 1146 if (err < 0) 1147 goto err_register; 1148 1149 priv->xfer_wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 0, 1150 netdev_name(ndev)); 1151 if (!priv->xfer_wq) { 1152 err = -ENOMEM; 1153 goto err_wq; 1154 } 1155 1156 INIT_WORK(&priv->rx_work, w5100_rx_work); 1157 INIT_WORK(&priv->tx_work, w5100_tx_work); 1158 INIT_WORK(&priv->setrx_work, w5100_setrx_work); 1159 INIT_WORK(&priv->restart_work, w5100_restart_work); 1160 1161 if (!IS_ERR_OR_NULL(mac_addr)) 1162 memcpy(ndev->dev_addr, mac_addr, ETH_ALEN); 1163 else 1164 eth_hw_addr_random(ndev); 1165 1166 if (priv->ops->init) { 1167 err = priv->ops->init(priv->ndev); 1168 if (err) 1169 goto err_hw; 1170 } 1171 1172 err = w5100_hw_reset(priv); 1173 if (err) 1174 goto err_hw; 1175 1176 if (ops->may_sleep) { 1177 err = request_threaded_irq(priv->irq, NULL, w5100_interrupt, 1178 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1179 netdev_name(ndev), ndev); 1180 } else { 1181 err = request_irq(priv->irq, w5100_interrupt, 1182 IRQF_TRIGGER_LOW, netdev_name(ndev), ndev); 1183 } 1184 if (err) 1185 goto err_hw; 1186 1187 if (gpio_is_valid(priv->link_gpio)) { 1188 char *link_name = devm_kzalloc(dev, 16, GFP_KERNEL); 1189 1190 if (!link_name) { 1191 err = -ENOMEM; 1192 goto err_gpio; 1193 } 1194 snprintf(link_name, 16, "%s-link", netdev_name(ndev)); 1195 priv->link_irq = gpio_to_irq(priv->link_gpio); 1196 if (request_any_context_irq(priv->link_irq, w5100_detect_link, 1197 IRQF_TRIGGER_RISING | 1198 IRQF_TRIGGER_FALLING, 1199 link_name, priv->ndev) < 0) 1200 priv->link_gpio = -EINVAL; 1201 } 1202 1203 return 0; 1204 1205 err_gpio: 1206 free_irq(priv->irq, ndev); 1207 err_hw: 1208 destroy_workqueue(priv->xfer_wq); 1209 err_wq: 1210 unregister_netdev(ndev); 1211 err_register: 1212 free_netdev(ndev); 1213 return err; 1214 } 1215 EXPORT_SYMBOL_GPL(w5100_probe); 1216 1217 int w5100_remove(struct device *dev) 1218 { 1219 struct net_device *ndev = dev_get_drvdata(dev); 1220 struct w5100_priv *priv = netdev_priv(ndev); 1221 1222 w5100_hw_reset(priv); 1223 free_irq(priv->irq, ndev); 1224 if (gpio_is_valid(priv->link_gpio)) 1225 free_irq(priv->link_irq, ndev); 1226 1227 flush_work(&priv->setrx_work); 1228 flush_work(&priv->restart_work); 1229 destroy_workqueue(priv->xfer_wq); 1230 1231 unregister_netdev(ndev); 1232 free_netdev(ndev); 1233 return 0; 1234 } 1235 EXPORT_SYMBOL_GPL(w5100_remove); 1236 1237 #ifdef CONFIG_PM_SLEEP 1238 static int w5100_suspend(struct device *dev) 1239 { 1240 struct net_device *ndev = dev_get_drvdata(dev); 1241 struct w5100_priv *priv = netdev_priv(ndev); 1242 1243 if (netif_running(ndev)) { 1244 netif_carrier_off(ndev); 1245 netif_device_detach(ndev); 1246 1247 w5100_hw_close(priv); 1248 } 1249 return 0; 1250 } 1251 1252 static int w5100_resume(struct device *dev) 1253 { 1254 struct net_device *ndev = dev_get_drvdata(dev); 1255 struct w5100_priv *priv = netdev_priv(ndev); 1256 1257 if (netif_running(ndev)) { 1258 w5100_hw_reset(priv); 1259 w5100_hw_start(priv); 1260 1261 netif_device_attach(ndev); 1262 if (!gpio_is_valid(priv->link_gpio) || 1263 gpio_get_value(priv->link_gpio) != 0) 1264 netif_carrier_on(ndev); 1265 } 1266 return 0; 1267 } 1268 #endif /* CONFIG_PM_SLEEP */ 1269 1270 SIMPLE_DEV_PM_OPS(w5100_pm_ops, w5100_suspend, w5100_resume); 1271 EXPORT_SYMBOL_GPL(w5100_pm_ops); 1272 1273 static struct platform_driver w5100_mmio_driver = { 1274 .driver = { 1275 .name = DRV_NAME, 1276 .pm = &w5100_pm_ops, 1277 }, 1278 .probe = w5100_mmio_probe, 1279 .remove = w5100_mmio_remove, 1280 }; 1281 module_platform_driver(w5100_mmio_driver); 1282