1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Ethernet driver for the WIZnet W5100/W5200/W5500 chip.
4  *
5  * Copyright (C) 2016 Akinobu Mita <akinobu.mita@gmail.com>
6  *
7  * Datasheet:
8  * http://www.wiznet.co.kr/wp-content/uploads/wiznethome/Chip/W5100/Document/W5100_Datasheet_v1.2.6.pdf
9  * http://wiznethome.cafe24.com/wp-content/uploads/wiznethome/Chip/W5200/Documents/W5200_DS_V140E.pdf
10  * http://wizwiki.net/wiki/lib/exe/fetch.php?media=products:w5500:w5500_ds_v106e_141230.pdf
11  */
12 
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/delay.h>
16 #include <linux/netdevice.h>
17 #include <linux/of_net.h>
18 #include <linux/spi/spi.h>
19 
20 #include "w5100.h"
21 
22 #define W5100_SPI_WRITE_OPCODE 0xf0
23 #define W5100_SPI_READ_OPCODE 0x0f
24 
25 static int w5100_spi_read(struct net_device *ndev, u32 addr)
26 {
27 	struct spi_device *spi = to_spi_device(ndev->dev.parent);
28 	u8 cmd[3] = { W5100_SPI_READ_OPCODE, addr >> 8, addr & 0xff };
29 	u8 data;
30 	int ret;
31 
32 	ret = spi_write_then_read(spi, cmd, sizeof(cmd), &data, 1);
33 
34 	return ret ? ret : data;
35 }
36 
37 static int w5100_spi_write(struct net_device *ndev, u32 addr, u8 data)
38 {
39 	struct spi_device *spi = to_spi_device(ndev->dev.parent);
40 	u8 cmd[4] = { W5100_SPI_WRITE_OPCODE, addr >> 8, addr & 0xff, data};
41 
42 	return spi_write_then_read(spi, cmd, sizeof(cmd), NULL, 0);
43 }
44 
45 static int w5100_spi_read16(struct net_device *ndev, u32 addr)
46 {
47 	u16 data;
48 	int ret;
49 
50 	ret = w5100_spi_read(ndev, addr);
51 	if (ret < 0)
52 		return ret;
53 	data = ret << 8;
54 	ret = w5100_spi_read(ndev, addr + 1);
55 
56 	return ret < 0 ? ret : data | ret;
57 }
58 
59 static int w5100_spi_write16(struct net_device *ndev, u32 addr, u16 data)
60 {
61 	int ret;
62 
63 	ret = w5100_spi_write(ndev, addr, data >> 8);
64 	if (ret)
65 		return ret;
66 
67 	return w5100_spi_write(ndev, addr + 1, data & 0xff);
68 }
69 
70 static int w5100_spi_readbulk(struct net_device *ndev, u32 addr, u8 *buf,
71 			      int len)
72 {
73 	int i;
74 
75 	for (i = 0; i < len; i++) {
76 		int ret = w5100_spi_read(ndev, addr + i);
77 
78 		if (ret < 0)
79 			return ret;
80 		buf[i] = ret;
81 	}
82 
83 	return 0;
84 }
85 
86 static int w5100_spi_writebulk(struct net_device *ndev, u32 addr, const u8 *buf,
87 			       int len)
88 {
89 	int i;
90 
91 	for (i = 0; i < len; i++) {
92 		int ret = w5100_spi_write(ndev, addr + i, buf[i]);
93 
94 		if (ret)
95 			return ret;
96 	}
97 
98 	return 0;
99 }
100 
101 static const struct w5100_ops w5100_spi_ops = {
102 	.may_sleep = true,
103 	.chip_id = W5100,
104 	.read = w5100_spi_read,
105 	.write = w5100_spi_write,
106 	.read16 = w5100_spi_read16,
107 	.write16 = w5100_spi_write16,
108 	.readbulk = w5100_spi_readbulk,
109 	.writebulk = w5100_spi_writebulk,
110 };
111 
112 #define W5200_SPI_WRITE_OPCODE 0x80
113 
114 struct w5200_spi_priv {
115 	/* Serialize access to cmd_buf */
116 	struct mutex cmd_lock;
117 
118 	/* DMA (thus cache coherency maintenance) requires the
119 	 * transfer buffers to live in their own cache lines.
120 	 */
121 	u8 cmd_buf[4] ____cacheline_aligned;
122 };
123 
124 static struct w5200_spi_priv *w5200_spi_priv(struct net_device *ndev)
125 {
126 	return w5100_ops_priv(ndev);
127 }
128 
129 static int w5200_spi_init(struct net_device *ndev)
130 {
131 	struct w5200_spi_priv *spi_priv = w5200_spi_priv(ndev);
132 
133 	mutex_init(&spi_priv->cmd_lock);
134 
135 	return 0;
136 }
137 
138 static int w5200_spi_read(struct net_device *ndev, u32 addr)
139 {
140 	struct spi_device *spi = to_spi_device(ndev->dev.parent);
141 	u8 cmd[4] = { addr >> 8, addr & 0xff, 0, 1 };
142 	u8 data;
143 	int ret;
144 
145 	ret = spi_write_then_read(spi, cmd, sizeof(cmd), &data, 1);
146 
147 	return ret ? ret : data;
148 }
149 
150 static int w5200_spi_write(struct net_device *ndev, u32 addr, u8 data)
151 {
152 	struct spi_device *spi = to_spi_device(ndev->dev.parent);
153 	u8 cmd[5] = { addr >> 8, addr & 0xff, W5200_SPI_WRITE_OPCODE, 1, data };
154 
155 	return spi_write_then_read(spi, cmd, sizeof(cmd), NULL, 0);
156 }
157 
158 static int w5200_spi_read16(struct net_device *ndev, u32 addr)
159 {
160 	struct spi_device *spi = to_spi_device(ndev->dev.parent);
161 	u8 cmd[4] = { addr >> 8, addr & 0xff, 0, 2 };
162 	__be16 data;
163 	int ret;
164 
165 	ret = spi_write_then_read(spi, cmd, sizeof(cmd), &data, sizeof(data));
166 
167 	return ret ? ret : be16_to_cpu(data);
168 }
169 
170 static int w5200_spi_write16(struct net_device *ndev, u32 addr, u16 data)
171 {
172 	struct spi_device *spi = to_spi_device(ndev->dev.parent);
173 	u8 cmd[6] = {
174 		addr >> 8, addr & 0xff,
175 		W5200_SPI_WRITE_OPCODE, 2,
176 		data >> 8, data & 0xff
177 	};
178 
179 	return spi_write_then_read(spi, cmd, sizeof(cmd), NULL, 0);
180 }
181 
182 static int w5200_spi_readbulk(struct net_device *ndev, u32 addr, u8 *buf,
183 			      int len)
184 {
185 	struct spi_device *spi = to_spi_device(ndev->dev.parent);
186 	struct w5200_spi_priv *spi_priv = w5200_spi_priv(ndev);
187 	struct spi_transfer xfer[] = {
188 		{
189 			.tx_buf = spi_priv->cmd_buf,
190 			.len = sizeof(spi_priv->cmd_buf),
191 		},
192 		{
193 			.rx_buf = buf,
194 			.len = len,
195 		},
196 	};
197 	int ret;
198 
199 	mutex_lock(&spi_priv->cmd_lock);
200 
201 	spi_priv->cmd_buf[0] = addr >> 8;
202 	spi_priv->cmd_buf[1] = addr;
203 	spi_priv->cmd_buf[2] = len >> 8;
204 	spi_priv->cmd_buf[3] = len;
205 	ret = spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
206 
207 	mutex_unlock(&spi_priv->cmd_lock);
208 
209 	return ret;
210 }
211 
212 static int w5200_spi_writebulk(struct net_device *ndev, u32 addr, const u8 *buf,
213 			       int len)
214 {
215 	struct spi_device *spi = to_spi_device(ndev->dev.parent);
216 	struct w5200_spi_priv *spi_priv = w5200_spi_priv(ndev);
217 	struct spi_transfer xfer[] = {
218 		{
219 			.tx_buf = spi_priv->cmd_buf,
220 			.len = sizeof(spi_priv->cmd_buf),
221 		},
222 		{
223 			.tx_buf = buf,
224 			.len = len,
225 		},
226 	};
227 	int ret;
228 
229 	mutex_lock(&spi_priv->cmd_lock);
230 
231 	spi_priv->cmd_buf[0] = addr >> 8;
232 	spi_priv->cmd_buf[1] = addr;
233 	spi_priv->cmd_buf[2] = W5200_SPI_WRITE_OPCODE | (len >> 8);
234 	spi_priv->cmd_buf[3] = len;
235 	ret = spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
236 
237 	mutex_unlock(&spi_priv->cmd_lock);
238 
239 	return ret;
240 }
241 
242 static const struct w5100_ops w5200_ops = {
243 	.may_sleep = true,
244 	.chip_id = W5200,
245 	.read = w5200_spi_read,
246 	.write = w5200_spi_write,
247 	.read16 = w5200_spi_read16,
248 	.write16 = w5200_spi_write16,
249 	.readbulk = w5200_spi_readbulk,
250 	.writebulk = w5200_spi_writebulk,
251 	.init = w5200_spi_init,
252 };
253 
254 #define W5500_SPI_BLOCK_SELECT(addr) (((addr) >> 16) & 0x1f)
255 #define W5500_SPI_READ_CONTROL(addr) (W5500_SPI_BLOCK_SELECT(addr) << 3)
256 #define W5500_SPI_WRITE_CONTROL(addr)	\
257 	((W5500_SPI_BLOCK_SELECT(addr) << 3) | BIT(2))
258 
259 struct w5500_spi_priv {
260 	/* Serialize access to cmd_buf */
261 	struct mutex cmd_lock;
262 
263 	/* DMA (thus cache coherency maintenance) requires the
264 	 * transfer buffers to live in their own cache lines.
265 	 */
266 	u8 cmd_buf[3] ____cacheline_aligned;
267 };
268 
269 static struct w5500_spi_priv *w5500_spi_priv(struct net_device *ndev)
270 {
271 	return w5100_ops_priv(ndev);
272 }
273 
274 static int w5500_spi_init(struct net_device *ndev)
275 {
276 	struct w5500_spi_priv *spi_priv = w5500_spi_priv(ndev);
277 
278 	mutex_init(&spi_priv->cmd_lock);
279 
280 	return 0;
281 }
282 
283 static int w5500_spi_read(struct net_device *ndev, u32 addr)
284 {
285 	struct spi_device *spi = to_spi_device(ndev->dev.parent);
286 	u8 cmd[3] = {
287 		addr >> 8,
288 		addr,
289 		W5500_SPI_READ_CONTROL(addr)
290 	};
291 	u8 data;
292 	int ret;
293 
294 	ret = spi_write_then_read(spi, cmd, sizeof(cmd), &data, 1);
295 
296 	return ret ? ret : data;
297 }
298 
299 static int w5500_spi_write(struct net_device *ndev, u32 addr, u8 data)
300 {
301 	struct spi_device *spi = to_spi_device(ndev->dev.parent);
302 	u8 cmd[4] = {
303 		addr >> 8,
304 		addr,
305 		W5500_SPI_WRITE_CONTROL(addr),
306 		data
307 	};
308 
309 	return spi_write_then_read(spi, cmd, sizeof(cmd), NULL, 0);
310 }
311 
312 static int w5500_spi_read16(struct net_device *ndev, u32 addr)
313 {
314 	struct spi_device *spi = to_spi_device(ndev->dev.parent);
315 	u8 cmd[3] = {
316 		addr >> 8,
317 		addr,
318 		W5500_SPI_READ_CONTROL(addr)
319 	};
320 	__be16 data;
321 	int ret;
322 
323 	ret = spi_write_then_read(spi, cmd, sizeof(cmd), &data, sizeof(data));
324 
325 	return ret ? ret : be16_to_cpu(data);
326 }
327 
328 static int w5500_spi_write16(struct net_device *ndev, u32 addr, u16 data)
329 {
330 	struct spi_device *spi = to_spi_device(ndev->dev.parent);
331 	u8 cmd[5] = {
332 		addr >> 8,
333 		addr,
334 		W5500_SPI_WRITE_CONTROL(addr),
335 		data >> 8,
336 		data
337 	};
338 
339 	return spi_write_then_read(spi, cmd, sizeof(cmd), NULL, 0);
340 }
341 
342 static int w5500_spi_readbulk(struct net_device *ndev, u32 addr, u8 *buf,
343 			      int len)
344 {
345 	struct spi_device *spi = to_spi_device(ndev->dev.parent);
346 	struct w5500_spi_priv *spi_priv = w5500_spi_priv(ndev);
347 	struct spi_transfer xfer[] = {
348 		{
349 			.tx_buf = spi_priv->cmd_buf,
350 			.len = sizeof(spi_priv->cmd_buf),
351 		},
352 		{
353 			.rx_buf = buf,
354 			.len = len,
355 		},
356 	};
357 	int ret;
358 
359 	mutex_lock(&spi_priv->cmd_lock);
360 
361 	spi_priv->cmd_buf[0] = addr >> 8;
362 	spi_priv->cmd_buf[1] = addr;
363 	spi_priv->cmd_buf[2] = W5500_SPI_READ_CONTROL(addr);
364 	ret = spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
365 
366 	mutex_unlock(&spi_priv->cmd_lock);
367 
368 	return ret;
369 }
370 
371 static int w5500_spi_writebulk(struct net_device *ndev, u32 addr, const u8 *buf,
372 			       int len)
373 {
374 	struct spi_device *spi = to_spi_device(ndev->dev.parent);
375 	struct w5500_spi_priv *spi_priv = w5500_spi_priv(ndev);
376 	struct spi_transfer xfer[] = {
377 		{
378 			.tx_buf = spi_priv->cmd_buf,
379 			.len = sizeof(spi_priv->cmd_buf),
380 		},
381 		{
382 			.tx_buf = buf,
383 			.len = len,
384 		},
385 	};
386 	int ret;
387 
388 	mutex_lock(&spi_priv->cmd_lock);
389 
390 	spi_priv->cmd_buf[0] = addr >> 8;
391 	spi_priv->cmd_buf[1] = addr;
392 	spi_priv->cmd_buf[2] = W5500_SPI_WRITE_CONTROL(addr);
393 	ret = spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
394 
395 	mutex_unlock(&spi_priv->cmd_lock);
396 
397 	return ret;
398 }
399 
400 static const struct w5100_ops w5500_ops = {
401 	.may_sleep = true,
402 	.chip_id = W5500,
403 	.read = w5500_spi_read,
404 	.write = w5500_spi_write,
405 	.read16 = w5500_spi_read16,
406 	.write16 = w5500_spi_write16,
407 	.readbulk = w5500_spi_readbulk,
408 	.writebulk = w5500_spi_writebulk,
409 	.init = w5500_spi_init,
410 };
411 
412 static int w5100_spi_probe(struct spi_device *spi)
413 {
414 	const struct spi_device_id *id = spi_get_device_id(spi);
415 	const struct w5100_ops *ops;
416 	int priv_size;
417 	const void *mac = of_get_mac_address(spi->dev.of_node);
418 
419 	switch (id->driver_data) {
420 	case W5100:
421 		ops = &w5100_spi_ops;
422 		priv_size = 0;
423 		break;
424 	case W5200:
425 		ops = &w5200_ops;
426 		priv_size = sizeof(struct w5200_spi_priv);
427 		break;
428 	case W5500:
429 		ops = &w5500_ops;
430 		priv_size = sizeof(struct w5500_spi_priv);
431 		break;
432 	default:
433 		return -EINVAL;
434 	}
435 
436 	return w5100_probe(&spi->dev, ops, priv_size, mac, spi->irq, -EINVAL);
437 }
438 
439 static int w5100_spi_remove(struct spi_device *spi)
440 {
441 	return w5100_remove(&spi->dev);
442 }
443 
444 static const struct spi_device_id w5100_spi_ids[] = {
445 	{ "w5100", W5100 },
446 	{ "w5200", W5200 },
447 	{ "w5500", W5500 },
448 	{}
449 };
450 MODULE_DEVICE_TABLE(spi, w5100_spi_ids);
451 
452 static struct spi_driver w5100_spi_driver = {
453 	.driver		= {
454 		.name	= "w5100",
455 		.pm	= &w5100_pm_ops,
456 	},
457 	.probe		= w5100_spi_probe,
458 	.remove		= w5100_spi_remove,
459 	.id_table	= w5100_spi_ids,
460 };
461 module_spi_driver(w5100_spi_driver);
462 
463 MODULE_DESCRIPTION("WIZnet W5100/W5200/W5500 Ethernet driver for SPI mode");
464 MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>");
465 MODULE_LICENSE("GPL");
466