1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2015 - 2023 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/gpio/machine.h> 5 #include <linux/gpio/driver.h> 6 #include <linux/gpio/property.h> 7 #include <linux/clk-provider.h> 8 #include <linux/clkdev.h> 9 #include <linux/i2c.h> 10 #include <linux/pci.h> 11 #include <linux/platform_device.h> 12 #include <linux/regmap.h> 13 #include <linux/pcs/pcs-xpcs.h> 14 #include <linux/phylink.h> 15 16 #include "../libwx/wx_type.h" 17 #include "../libwx/wx_lib.h" 18 #include "../libwx/wx_hw.h" 19 #include "txgbe_type.h" 20 #include "txgbe_phy.h" 21 22 static int txgbe_swnodes_register(struct txgbe *txgbe) 23 { 24 struct txgbe_nodes *nodes = &txgbe->nodes; 25 struct pci_dev *pdev = txgbe->wx->pdev; 26 struct software_node *swnodes; 27 u32 id; 28 29 id = (pdev->bus->number << 8) | pdev->devfn; 30 31 snprintf(nodes->gpio_name, sizeof(nodes->gpio_name), "txgbe_gpio-%x", id); 32 snprintf(nodes->i2c_name, sizeof(nodes->i2c_name), "txgbe_i2c-%x", id); 33 snprintf(nodes->sfp_name, sizeof(nodes->sfp_name), "txgbe_sfp-%x", id); 34 snprintf(nodes->phylink_name, sizeof(nodes->phylink_name), "txgbe_phylink-%x", id); 35 36 swnodes = nodes->swnodes; 37 38 /* GPIO 0: tx fault 39 * GPIO 1: tx disable 40 * GPIO 2: sfp module absent 41 * GPIO 3: rx signal lost 42 * GPIO 4: rate select, 1G(0) 10G(1) 43 * GPIO 5: rate select, 1G(0) 10G(1) 44 */ 45 nodes->gpio_props[0] = PROPERTY_ENTRY_STRING("pinctrl-names", "default"); 46 swnodes[SWNODE_GPIO] = NODE_PROP(nodes->gpio_name, nodes->gpio_props); 47 nodes->gpio0_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 0, GPIO_ACTIVE_HIGH); 48 nodes->gpio1_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 1, GPIO_ACTIVE_HIGH); 49 nodes->gpio2_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 2, GPIO_ACTIVE_LOW); 50 nodes->gpio3_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 3, GPIO_ACTIVE_HIGH); 51 nodes->gpio4_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 4, GPIO_ACTIVE_HIGH); 52 nodes->gpio5_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 5, GPIO_ACTIVE_HIGH); 53 54 nodes->i2c_props[0] = PROPERTY_ENTRY_STRING("compatible", "snps,designware-i2c"); 55 nodes->i2c_props[1] = PROPERTY_ENTRY_BOOL("wx,i2c-snps-model"); 56 nodes->i2c_props[2] = PROPERTY_ENTRY_U32("clock-frequency", I2C_MAX_STANDARD_MODE_FREQ); 57 swnodes[SWNODE_I2C] = NODE_PROP(nodes->i2c_name, nodes->i2c_props); 58 nodes->i2c_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_I2C]); 59 60 nodes->sfp_props[0] = PROPERTY_ENTRY_STRING("compatible", "sff,sfp"); 61 nodes->sfp_props[1] = PROPERTY_ENTRY_REF_ARRAY("i2c-bus", nodes->i2c_ref); 62 nodes->sfp_props[2] = PROPERTY_ENTRY_REF_ARRAY("tx-fault-gpios", nodes->gpio0_ref); 63 nodes->sfp_props[3] = PROPERTY_ENTRY_REF_ARRAY("tx-disable-gpios", nodes->gpio1_ref); 64 nodes->sfp_props[4] = PROPERTY_ENTRY_REF_ARRAY("mod-def0-gpios", nodes->gpio2_ref); 65 nodes->sfp_props[5] = PROPERTY_ENTRY_REF_ARRAY("los-gpios", nodes->gpio3_ref); 66 nodes->sfp_props[6] = PROPERTY_ENTRY_REF_ARRAY("rate-select1-gpios", nodes->gpio4_ref); 67 nodes->sfp_props[7] = PROPERTY_ENTRY_REF_ARRAY("rate-select0-gpios", nodes->gpio5_ref); 68 swnodes[SWNODE_SFP] = NODE_PROP(nodes->sfp_name, nodes->sfp_props); 69 nodes->sfp_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_SFP]); 70 71 nodes->phylink_props[0] = PROPERTY_ENTRY_STRING("managed", "in-band-status"); 72 nodes->phylink_props[1] = PROPERTY_ENTRY_REF_ARRAY("sfp", nodes->sfp_ref); 73 swnodes[SWNODE_PHYLINK] = NODE_PROP(nodes->phylink_name, nodes->phylink_props); 74 75 nodes->group[SWNODE_GPIO] = &swnodes[SWNODE_GPIO]; 76 nodes->group[SWNODE_I2C] = &swnodes[SWNODE_I2C]; 77 nodes->group[SWNODE_SFP] = &swnodes[SWNODE_SFP]; 78 nodes->group[SWNODE_PHYLINK] = &swnodes[SWNODE_PHYLINK]; 79 80 return software_node_register_node_group(nodes->group); 81 } 82 83 static int txgbe_pcs_read(struct mii_bus *bus, int addr, int devnum, int regnum) 84 { 85 struct wx *wx = bus->priv; 86 u32 offset, val; 87 88 if (addr) 89 return -EOPNOTSUPP; 90 91 offset = devnum << 16 | regnum; 92 93 /* Set the LAN port indicator to IDA_ADDR */ 94 wr32(wx, TXGBE_XPCS_IDA_ADDR, offset); 95 96 /* Read the data from IDA_DATA register */ 97 val = rd32(wx, TXGBE_XPCS_IDA_DATA); 98 99 return (u16)val; 100 } 101 102 static int txgbe_pcs_write(struct mii_bus *bus, int addr, int devnum, int regnum, u16 val) 103 { 104 struct wx *wx = bus->priv; 105 u32 offset; 106 107 if (addr) 108 return -EOPNOTSUPP; 109 110 offset = devnum << 16 | regnum; 111 112 /* Set the LAN port indicator to IDA_ADDR */ 113 wr32(wx, TXGBE_XPCS_IDA_ADDR, offset); 114 115 /* Write the data to IDA_DATA register */ 116 wr32(wx, TXGBE_XPCS_IDA_DATA, val); 117 118 return 0; 119 } 120 121 static int txgbe_mdio_pcs_init(struct txgbe *txgbe) 122 { 123 struct mii_bus *mii_bus; 124 struct dw_xpcs *xpcs; 125 struct pci_dev *pdev; 126 struct wx *wx; 127 int ret = 0; 128 129 wx = txgbe->wx; 130 pdev = wx->pdev; 131 132 mii_bus = devm_mdiobus_alloc(&pdev->dev); 133 if (!mii_bus) 134 return -ENOMEM; 135 136 mii_bus->name = "txgbe_pcs_mdio_bus"; 137 mii_bus->read_c45 = &txgbe_pcs_read; 138 mii_bus->write_c45 = &txgbe_pcs_write; 139 mii_bus->parent = &pdev->dev; 140 mii_bus->phy_mask = ~0; 141 mii_bus->priv = wx; 142 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "txgbe_pcs-%x", 143 (pdev->bus->number << 8) | pdev->devfn); 144 145 ret = devm_mdiobus_register(&pdev->dev, mii_bus); 146 if (ret) 147 return ret; 148 149 xpcs = xpcs_create_mdiodev(mii_bus, 0, PHY_INTERFACE_MODE_10GBASER); 150 if (IS_ERR(xpcs)) 151 return PTR_ERR(xpcs); 152 153 txgbe->xpcs = xpcs; 154 155 return 0; 156 } 157 158 static struct phylink_pcs *txgbe_phylink_mac_select(struct phylink_config *config, 159 phy_interface_t interface) 160 { 161 struct txgbe *txgbe = netdev_to_txgbe(to_net_dev(config->dev)); 162 163 return &txgbe->xpcs->pcs; 164 } 165 166 static void txgbe_mac_config(struct phylink_config *config, unsigned int mode, 167 const struct phylink_link_state *state) 168 { 169 } 170 171 static void txgbe_mac_link_down(struct phylink_config *config, 172 unsigned int mode, phy_interface_t interface) 173 { 174 struct wx *wx = netdev_priv(to_net_dev(config->dev)); 175 176 wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0); 177 } 178 179 static void txgbe_mac_link_up(struct phylink_config *config, 180 struct phy_device *phy, 181 unsigned int mode, phy_interface_t interface, 182 int speed, int duplex, 183 bool tx_pause, bool rx_pause) 184 { 185 struct wx *wx = netdev_priv(to_net_dev(config->dev)); 186 u32 txcfg, wdg; 187 188 txcfg = rd32(wx, WX_MAC_TX_CFG); 189 txcfg &= ~WX_MAC_TX_CFG_SPEED_MASK; 190 191 switch (speed) { 192 case SPEED_10000: 193 txcfg |= WX_MAC_TX_CFG_SPEED_10G; 194 break; 195 case SPEED_1000: 196 case SPEED_100: 197 case SPEED_10: 198 txcfg |= WX_MAC_TX_CFG_SPEED_1G; 199 break; 200 default: 201 break; 202 } 203 204 wr32(wx, WX_MAC_TX_CFG, txcfg | WX_MAC_TX_CFG_TE); 205 206 /* Re configure MAC Rx */ 207 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE); 208 wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR); 209 wdg = rd32(wx, WX_MAC_WDG_TIMEOUT); 210 wr32(wx, WX_MAC_WDG_TIMEOUT, wdg); 211 } 212 213 static const struct phylink_mac_ops txgbe_mac_ops = { 214 .mac_select_pcs = txgbe_phylink_mac_select, 215 .mac_config = txgbe_mac_config, 216 .mac_link_down = txgbe_mac_link_down, 217 .mac_link_up = txgbe_mac_link_up, 218 }; 219 220 static int txgbe_phylink_init(struct txgbe *txgbe) 221 { 222 struct phylink_config *config; 223 struct fwnode_handle *fwnode; 224 struct wx *wx = txgbe->wx; 225 phy_interface_t phy_mode; 226 struct phylink *phylink; 227 228 config = devm_kzalloc(&wx->pdev->dev, sizeof(*config), GFP_KERNEL); 229 if (!config) 230 return -ENOMEM; 231 232 config->dev = &wx->netdev->dev; 233 config->type = PHYLINK_NETDEV; 234 config->mac_capabilities = MAC_10000FD | MAC_1000FD | MAC_SYM_PAUSE | MAC_ASYM_PAUSE; 235 phy_mode = PHY_INTERFACE_MODE_10GBASER; 236 __set_bit(PHY_INTERFACE_MODE_10GBASER, config->supported_interfaces); 237 fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_PHYLINK]); 238 phylink = phylink_create(config, fwnode, phy_mode, &txgbe_mac_ops); 239 if (IS_ERR(phylink)) 240 return PTR_ERR(phylink); 241 242 txgbe->phylink = phylink; 243 244 return 0; 245 } 246 247 static int txgbe_gpio_get(struct gpio_chip *chip, unsigned int offset) 248 { 249 struct wx *wx = gpiochip_get_data(chip); 250 int val; 251 252 val = rd32m(wx, WX_GPIO_EXT, BIT(offset)); 253 254 return !!(val & BIT(offset)); 255 } 256 257 static int txgbe_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 258 { 259 struct wx *wx = gpiochip_get_data(chip); 260 u32 val; 261 262 val = rd32(wx, WX_GPIO_DDR); 263 if (BIT(offset) & val) 264 return GPIO_LINE_DIRECTION_OUT; 265 266 return GPIO_LINE_DIRECTION_IN; 267 } 268 269 static int txgbe_gpio_direction_in(struct gpio_chip *chip, unsigned int offset) 270 { 271 struct wx *wx = gpiochip_get_data(chip); 272 unsigned long flags; 273 274 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 275 wr32m(wx, WX_GPIO_DDR, BIT(offset), 0); 276 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 277 278 return 0; 279 } 280 281 static int txgbe_gpio_direction_out(struct gpio_chip *chip, unsigned int offset, 282 int val) 283 { 284 struct wx *wx = gpiochip_get_data(chip); 285 unsigned long flags; 286 u32 set; 287 288 set = val ? BIT(offset) : 0; 289 290 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 291 wr32m(wx, WX_GPIO_DR, BIT(offset), set); 292 wr32m(wx, WX_GPIO_DDR, BIT(offset), BIT(offset)); 293 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 294 295 return 0; 296 } 297 298 static void txgbe_gpio_irq_ack(struct irq_data *d) 299 { 300 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 301 irq_hw_number_t hwirq = irqd_to_hwirq(d); 302 struct wx *wx = gpiochip_get_data(gc); 303 unsigned long flags; 304 305 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 306 wr32(wx, WX_GPIO_EOI, BIT(hwirq)); 307 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 308 } 309 310 static void txgbe_gpio_irq_mask(struct irq_data *d) 311 { 312 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 313 irq_hw_number_t hwirq = irqd_to_hwirq(d); 314 struct wx *wx = gpiochip_get_data(gc); 315 unsigned long flags; 316 317 gpiochip_disable_irq(gc, hwirq); 318 319 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 320 wr32m(wx, WX_GPIO_INTMASK, BIT(hwirq), BIT(hwirq)); 321 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 322 } 323 324 static void txgbe_gpio_irq_unmask(struct irq_data *d) 325 { 326 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 327 irq_hw_number_t hwirq = irqd_to_hwirq(d); 328 struct wx *wx = gpiochip_get_data(gc); 329 unsigned long flags; 330 331 gpiochip_enable_irq(gc, hwirq); 332 333 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 334 wr32m(wx, WX_GPIO_INTMASK, BIT(hwirq), 0); 335 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 336 } 337 338 static void txgbe_toggle_trigger(struct gpio_chip *gc, unsigned int offset) 339 { 340 struct wx *wx = gpiochip_get_data(gc); 341 u32 pol, val; 342 343 pol = rd32(wx, WX_GPIO_POLARITY); 344 val = rd32(wx, WX_GPIO_EXT); 345 346 if (val & BIT(offset)) 347 pol &= ~BIT(offset); 348 else 349 pol |= BIT(offset); 350 351 wr32(wx, WX_GPIO_POLARITY, pol); 352 } 353 354 static int txgbe_gpio_set_type(struct irq_data *d, unsigned int type) 355 { 356 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 357 irq_hw_number_t hwirq = irqd_to_hwirq(d); 358 struct wx *wx = gpiochip_get_data(gc); 359 u32 level, polarity, mask; 360 unsigned long flags; 361 362 mask = BIT(hwirq); 363 364 if (type & IRQ_TYPE_LEVEL_MASK) { 365 level = 0; 366 irq_set_handler_locked(d, handle_level_irq); 367 } else { 368 level = mask; 369 irq_set_handler_locked(d, handle_edge_irq); 370 } 371 372 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) 373 polarity = mask; 374 else 375 polarity = 0; 376 377 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 378 379 wr32m(wx, WX_GPIO_INTEN, mask, mask); 380 wr32m(wx, WX_GPIO_INTTYPE_LEVEL, mask, level); 381 if (type == IRQ_TYPE_EDGE_BOTH) 382 txgbe_toggle_trigger(gc, hwirq); 383 else 384 wr32m(wx, WX_GPIO_POLARITY, mask, polarity); 385 386 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 387 388 return 0; 389 } 390 391 static const struct irq_chip txgbe_gpio_irq_chip = { 392 .name = "txgbe_gpio_irq", 393 .irq_ack = txgbe_gpio_irq_ack, 394 .irq_mask = txgbe_gpio_irq_mask, 395 .irq_unmask = txgbe_gpio_irq_unmask, 396 .irq_set_type = txgbe_gpio_set_type, 397 .flags = IRQCHIP_IMMUTABLE, 398 GPIOCHIP_IRQ_RESOURCE_HELPERS, 399 }; 400 401 static void txgbe_irq_handler(struct irq_desc *desc) 402 { 403 struct irq_chip *chip = irq_desc_get_chip(desc); 404 struct wx *wx = irq_desc_get_handler_data(desc); 405 struct txgbe *txgbe = wx->priv; 406 irq_hw_number_t hwirq; 407 unsigned long gpioirq; 408 struct gpio_chip *gc; 409 unsigned long flags; 410 u32 eicr; 411 412 eicr = wx_misc_isb(wx, WX_ISB_MISC); 413 414 chained_irq_enter(chip, desc); 415 416 gpioirq = rd32(wx, WX_GPIO_INTSTATUS); 417 418 gc = txgbe->gpio; 419 for_each_set_bit(hwirq, &gpioirq, gc->ngpio) { 420 int gpio = irq_find_mapping(gc->irq.domain, hwirq); 421 u32 irq_type = irq_get_trigger_type(gpio); 422 423 generic_handle_domain_irq(gc->irq.domain, hwirq); 424 425 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 426 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 427 txgbe_toggle_trigger(gc, hwirq); 428 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 429 } 430 } 431 432 chained_irq_exit(chip, desc); 433 434 if (eicr & (TXGBE_PX_MISC_ETH_LK | TXGBE_PX_MISC_ETH_LKDN)) { 435 u32 reg = rd32(wx, TXGBE_CFG_PORT_ST); 436 437 phylink_mac_change(txgbe->phylink, !!(reg & TXGBE_CFG_PORT_ST_LINK_UP)); 438 } 439 440 /* unmask interrupt */ 441 wx_intr_enable(wx, TXGBE_INTR_MISC(wx)); 442 } 443 444 static int txgbe_gpio_init(struct txgbe *txgbe) 445 { 446 struct gpio_irq_chip *girq; 447 struct gpio_chip *gc; 448 struct device *dev; 449 struct wx *wx; 450 int ret; 451 452 wx = txgbe->wx; 453 dev = &wx->pdev->dev; 454 455 raw_spin_lock_init(&wx->gpio_lock); 456 457 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 458 if (!gc) 459 return -ENOMEM; 460 461 gc->label = devm_kasprintf(dev, GFP_KERNEL, "txgbe_gpio-%x", 462 (wx->pdev->bus->number << 8) | wx->pdev->devfn); 463 if (!gc->label) 464 return -ENOMEM; 465 466 gc->base = -1; 467 gc->ngpio = 6; 468 gc->owner = THIS_MODULE; 469 gc->parent = dev; 470 gc->fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_GPIO]); 471 gc->get = txgbe_gpio_get; 472 gc->get_direction = txgbe_gpio_get_direction; 473 gc->direction_input = txgbe_gpio_direction_in; 474 gc->direction_output = txgbe_gpio_direction_out; 475 476 girq = &gc->irq; 477 gpio_irq_chip_set_chip(girq, &txgbe_gpio_irq_chip); 478 girq->parent_handler = txgbe_irq_handler; 479 girq->parent_handler_data = wx; 480 girq->num_parents = 1; 481 girq->parents = devm_kcalloc(dev, girq->num_parents, 482 sizeof(*girq->parents), GFP_KERNEL); 483 if (!girq->parents) 484 return -ENOMEM; 485 girq->parents[0] = wx->msix_entries[wx->num_q_vectors].vector; 486 girq->default_type = IRQ_TYPE_NONE; 487 girq->handler = handle_bad_irq; 488 489 ret = devm_gpiochip_add_data(dev, gc, wx); 490 if (ret) 491 return ret; 492 493 txgbe->gpio = gc; 494 495 return 0; 496 } 497 498 static int txgbe_clock_register(struct txgbe *txgbe) 499 { 500 struct pci_dev *pdev = txgbe->wx->pdev; 501 struct clk_lookup *clock; 502 char clk_name[32]; 503 struct clk *clk; 504 505 snprintf(clk_name, sizeof(clk_name), "i2c_designware.%d", 506 (pdev->bus->number << 8) | pdev->devfn); 507 508 clk = clk_register_fixed_rate(NULL, clk_name, NULL, 0, 156250000); 509 if (IS_ERR(clk)) 510 return PTR_ERR(clk); 511 512 clock = clkdev_create(clk, NULL, clk_name); 513 if (!clock) { 514 clk_unregister(clk); 515 return -ENOMEM; 516 } 517 518 txgbe->clk = clk; 519 txgbe->clock = clock; 520 521 return 0; 522 } 523 524 static int txgbe_i2c_read(void *context, unsigned int reg, unsigned int *val) 525 { 526 struct wx *wx = context; 527 528 *val = rd32(wx, reg + TXGBE_I2C_BASE); 529 530 return 0; 531 } 532 533 static int txgbe_i2c_write(void *context, unsigned int reg, unsigned int val) 534 { 535 struct wx *wx = context; 536 537 wr32(wx, reg + TXGBE_I2C_BASE, val); 538 539 return 0; 540 } 541 542 static const struct regmap_config i2c_regmap_config = { 543 .reg_bits = 32, 544 .val_bits = 32, 545 .reg_read = txgbe_i2c_read, 546 .reg_write = txgbe_i2c_write, 547 .fast_io = true, 548 }; 549 550 static int txgbe_i2c_register(struct txgbe *txgbe) 551 { 552 struct platform_device_info info = {}; 553 struct platform_device *i2c_dev; 554 struct regmap *i2c_regmap; 555 struct pci_dev *pdev; 556 struct wx *wx; 557 558 wx = txgbe->wx; 559 pdev = wx->pdev; 560 i2c_regmap = devm_regmap_init(&pdev->dev, NULL, wx, &i2c_regmap_config); 561 if (IS_ERR(i2c_regmap)) { 562 wx_err(wx, "failed to init I2C regmap\n"); 563 return PTR_ERR(i2c_regmap); 564 } 565 566 info.parent = &pdev->dev; 567 info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_I2C]); 568 info.name = "i2c_designware"; 569 info.id = (pdev->bus->number << 8) | pdev->devfn; 570 571 info.res = &DEFINE_RES_IRQ(pdev->irq); 572 info.num_res = 1; 573 i2c_dev = platform_device_register_full(&info); 574 if (IS_ERR(i2c_dev)) 575 return PTR_ERR(i2c_dev); 576 577 txgbe->i2c_dev = i2c_dev; 578 579 return 0; 580 } 581 582 static int txgbe_sfp_register(struct txgbe *txgbe) 583 { 584 struct pci_dev *pdev = txgbe->wx->pdev; 585 struct platform_device_info info = {}; 586 struct platform_device *sfp_dev; 587 588 info.parent = &pdev->dev; 589 info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_SFP]); 590 info.name = "sfp"; 591 info.id = (pdev->bus->number << 8) | pdev->devfn; 592 sfp_dev = platform_device_register_full(&info); 593 if (IS_ERR(sfp_dev)) 594 return PTR_ERR(sfp_dev); 595 596 txgbe->sfp_dev = sfp_dev; 597 598 return 0; 599 } 600 601 int txgbe_init_phy(struct txgbe *txgbe) 602 { 603 int ret; 604 605 ret = txgbe_swnodes_register(txgbe); 606 if (ret) { 607 wx_err(txgbe->wx, "failed to register software nodes\n"); 608 return ret; 609 } 610 611 ret = txgbe_mdio_pcs_init(txgbe); 612 if (ret) { 613 wx_err(txgbe->wx, "failed to init mdio pcs: %d\n", ret); 614 goto err_unregister_swnode; 615 } 616 617 ret = txgbe_phylink_init(txgbe); 618 if (ret) { 619 wx_err(txgbe->wx, "failed to init phylink\n"); 620 goto err_destroy_xpcs; 621 } 622 623 ret = txgbe_gpio_init(txgbe); 624 if (ret) { 625 wx_err(txgbe->wx, "failed to init gpio\n"); 626 goto err_destroy_phylink; 627 } 628 629 ret = txgbe_clock_register(txgbe); 630 if (ret) { 631 wx_err(txgbe->wx, "failed to register clock: %d\n", ret); 632 goto err_destroy_phylink; 633 } 634 635 ret = txgbe_i2c_register(txgbe); 636 if (ret) { 637 wx_err(txgbe->wx, "failed to init i2c interface: %d\n", ret); 638 goto err_unregister_clk; 639 } 640 641 ret = txgbe_sfp_register(txgbe); 642 if (ret) { 643 wx_err(txgbe->wx, "failed to register sfp\n"); 644 goto err_unregister_i2c; 645 } 646 647 return 0; 648 649 err_unregister_i2c: 650 platform_device_unregister(txgbe->i2c_dev); 651 err_unregister_clk: 652 clkdev_drop(txgbe->clock); 653 clk_unregister(txgbe->clk); 654 err_destroy_phylink: 655 phylink_destroy(txgbe->phylink); 656 err_destroy_xpcs: 657 xpcs_destroy(txgbe->xpcs); 658 err_unregister_swnode: 659 software_node_unregister_node_group(txgbe->nodes.group); 660 661 return ret; 662 } 663 664 void txgbe_remove_phy(struct txgbe *txgbe) 665 { 666 platform_device_unregister(txgbe->sfp_dev); 667 platform_device_unregister(txgbe->i2c_dev); 668 clkdev_drop(txgbe->clock); 669 clk_unregister(txgbe->clk); 670 phylink_destroy(txgbe->phylink); 671 xpcs_destroy(txgbe->xpcs); 672 software_node_unregister_node_group(txgbe->nodes.group); 673 } 674