1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2015 - 2023 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/gpio/machine.h> 5 #include <linux/gpio/driver.h> 6 #include <linux/gpio/property.h> 7 #include <linux/clk-provider.h> 8 #include <linux/clkdev.h> 9 #include <linux/i2c.h> 10 #include <linux/pci.h> 11 #include <linux/platform_device.h> 12 #include <linux/regmap.h> 13 #include <linux/pcs/pcs-xpcs.h> 14 #include <linux/phylink.h> 15 16 #include "../libwx/wx_type.h" 17 #include "../libwx/wx_lib.h" 18 #include "../libwx/wx_hw.h" 19 #include "txgbe_type.h" 20 #include "txgbe_phy.h" 21 #include "txgbe_hw.h" 22 23 #define TXGBE_I2C_CLK_DEV_NAME "i2c_dw" 24 25 static int txgbe_swnodes_register(struct txgbe *txgbe) 26 { 27 struct txgbe_nodes *nodes = &txgbe->nodes; 28 struct pci_dev *pdev = txgbe->wx->pdev; 29 struct software_node *swnodes; 30 u32 id; 31 32 id = pci_dev_id(pdev); 33 34 snprintf(nodes->gpio_name, sizeof(nodes->gpio_name), "txgbe_gpio-%x", id); 35 snprintf(nodes->i2c_name, sizeof(nodes->i2c_name), "txgbe_i2c-%x", id); 36 snprintf(nodes->sfp_name, sizeof(nodes->sfp_name), "txgbe_sfp-%x", id); 37 snprintf(nodes->phylink_name, sizeof(nodes->phylink_name), "txgbe_phylink-%x", id); 38 39 swnodes = nodes->swnodes; 40 41 /* GPIO 0: tx fault 42 * GPIO 1: tx disable 43 * GPIO 2: sfp module absent 44 * GPIO 3: rx signal lost 45 * GPIO 4: rate select, 1G(0) 10G(1) 46 * GPIO 5: rate select, 1G(0) 10G(1) 47 */ 48 nodes->gpio_props[0] = PROPERTY_ENTRY_STRING("pinctrl-names", "default"); 49 swnodes[SWNODE_GPIO] = NODE_PROP(nodes->gpio_name, nodes->gpio_props); 50 nodes->gpio0_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 0, GPIO_ACTIVE_HIGH); 51 nodes->gpio1_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 1, GPIO_ACTIVE_HIGH); 52 nodes->gpio2_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 2, GPIO_ACTIVE_LOW); 53 nodes->gpio3_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 3, GPIO_ACTIVE_HIGH); 54 nodes->gpio4_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 4, GPIO_ACTIVE_HIGH); 55 nodes->gpio5_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 5, GPIO_ACTIVE_HIGH); 56 57 nodes->i2c_props[0] = PROPERTY_ENTRY_STRING("compatible", "snps,designware-i2c"); 58 nodes->i2c_props[1] = PROPERTY_ENTRY_BOOL("wx,i2c-snps-model"); 59 nodes->i2c_props[2] = PROPERTY_ENTRY_U32("clock-frequency", I2C_MAX_STANDARD_MODE_FREQ); 60 swnodes[SWNODE_I2C] = NODE_PROP(nodes->i2c_name, nodes->i2c_props); 61 nodes->i2c_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_I2C]); 62 63 nodes->sfp_props[0] = PROPERTY_ENTRY_STRING("compatible", "sff,sfp"); 64 nodes->sfp_props[1] = PROPERTY_ENTRY_REF_ARRAY("i2c-bus", nodes->i2c_ref); 65 nodes->sfp_props[2] = PROPERTY_ENTRY_REF_ARRAY("tx-fault-gpios", nodes->gpio0_ref); 66 nodes->sfp_props[3] = PROPERTY_ENTRY_REF_ARRAY("tx-disable-gpios", nodes->gpio1_ref); 67 nodes->sfp_props[4] = PROPERTY_ENTRY_REF_ARRAY("mod-def0-gpios", nodes->gpio2_ref); 68 nodes->sfp_props[5] = PROPERTY_ENTRY_REF_ARRAY("los-gpios", nodes->gpio3_ref); 69 nodes->sfp_props[6] = PROPERTY_ENTRY_REF_ARRAY("rate-select1-gpios", nodes->gpio4_ref); 70 nodes->sfp_props[7] = PROPERTY_ENTRY_REF_ARRAY("rate-select0-gpios", nodes->gpio5_ref); 71 swnodes[SWNODE_SFP] = NODE_PROP(nodes->sfp_name, nodes->sfp_props); 72 nodes->sfp_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_SFP]); 73 74 nodes->phylink_props[0] = PROPERTY_ENTRY_STRING("managed", "in-band-status"); 75 nodes->phylink_props[1] = PROPERTY_ENTRY_REF_ARRAY("sfp", nodes->sfp_ref); 76 swnodes[SWNODE_PHYLINK] = NODE_PROP(nodes->phylink_name, nodes->phylink_props); 77 78 nodes->group[SWNODE_GPIO] = &swnodes[SWNODE_GPIO]; 79 nodes->group[SWNODE_I2C] = &swnodes[SWNODE_I2C]; 80 nodes->group[SWNODE_SFP] = &swnodes[SWNODE_SFP]; 81 nodes->group[SWNODE_PHYLINK] = &swnodes[SWNODE_PHYLINK]; 82 83 return software_node_register_node_group(nodes->group); 84 } 85 86 static int txgbe_pcs_read(struct mii_bus *bus, int addr, int devnum, int regnum) 87 { 88 struct wx *wx = bus->priv; 89 u32 offset, val; 90 91 if (addr) 92 return -EOPNOTSUPP; 93 94 offset = devnum << 16 | regnum; 95 96 /* Set the LAN port indicator to IDA_ADDR */ 97 wr32(wx, TXGBE_XPCS_IDA_ADDR, offset); 98 99 /* Read the data from IDA_DATA register */ 100 val = rd32(wx, TXGBE_XPCS_IDA_DATA); 101 102 return (u16)val; 103 } 104 105 static int txgbe_pcs_write(struct mii_bus *bus, int addr, int devnum, int regnum, u16 val) 106 { 107 struct wx *wx = bus->priv; 108 u32 offset; 109 110 if (addr) 111 return -EOPNOTSUPP; 112 113 offset = devnum << 16 | regnum; 114 115 /* Set the LAN port indicator to IDA_ADDR */ 116 wr32(wx, TXGBE_XPCS_IDA_ADDR, offset); 117 118 /* Write the data to IDA_DATA register */ 119 wr32(wx, TXGBE_XPCS_IDA_DATA, val); 120 121 return 0; 122 } 123 124 static int txgbe_mdio_pcs_init(struct txgbe *txgbe) 125 { 126 struct mii_bus *mii_bus; 127 struct dw_xpcs *xpcs; 128 struct pci_dev *pdev; 129 struct wx *wx; 130 int ret = 0; 131 132 wx = txgbe->wx; 133 pdev = wx->pdev; 134 135 mii_bus = devm_mdiobus_alloc(&pdev->dev); 136 if (!mii_bus) 137 return -ENOMEM; 138 139 mii_bus->name = "txgbe_pcs_mdio_bus"; 140 mii_bus->read_c45 = &txgbe_pcs_read; 141 mii_bus->write_c45 = &txgbe_pcs_write; 142 mii_bus->parent = &pdev->dev; 143 mii_bus->phy_mask = ~0; 144 mii_bus->priv = wx; 145 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "txgbe_pcs-%x", 146 pci_dev_id(pdev)); 147 148 ret = devm_mdiobus_register(&pdev->dev, mii_bus); 149 if (ret) 150 return ret; 151 152 xpcs = xpcs_create_mdiodev(mii_bus, 0, PHY_INTERFACE_MODE_10GBASER); 153 if (IS_ERR(xpcs)) 154 return PTR_ERR(xpcs); 155 156 txgbe->xpcs = xpcs; 157 158 return 0; 159 } 160 161 static struct phylink_pcs *txgbe_phylink_mac_select(struct phylink_config *config, 162 phy_interface_t interface) 163 { 164 struct txgbe *txgbe = netdev_to_txgbe(to_net_dev(config->dev)); 165 166 if (interface == PHY_INTERFACE_MODE_10GBASER) 167 return &txgbe->xpcs->pcs; 168 169 return NULL; 170 } 171 172 static void txgbe_mac_config(struct phylink_config *config, unsigned int mode, 173 const struct phylink_link_state *state) 174 { 175 } 176 177 static void txgbe_mac_link_down(struct phylink_config *config, 178 unsigned int mode, phy_interface_t interface) 179 { 180 struct wx *wx = netdev_priv(to_net_dev(config->dev)); 181 182 wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0); 183 } 184 185 static void txgbe_mac_link_up(struct phylink_config *config, 186 struct phy_device *phy, 187 unsigned int mode, phy_interface_t interface, 188 int speed, int duplex, 189 bool tx_pause, bool rx_pause) 190 { 191 struct wx *wx = netdev_priv(to_net_dev(config->dev)); 192 u32 txcfg, wdg; 193 194 txcfg = rd32(wx, WX_MAC_TX_CFG); 195 txcfg &= ~WX_MAC_TX_CFG_SPEED_MASK; 196 197 switch (speed) { 198 case SPEED_10000: 199 txcfg |= WX_MAC_TX_CFG_SPEED_10G; 200 break; 201 case SPEED_1000: 202 case SPEED_100: 203 case SPEED_10: 204 txcfg |= WX_MAC_TX_CFG_SPEED_1G; 205 break; 206 default: 207 break; 208 } 209 210 wr32(wx, WX_MAC_TX_CFG, txcfg | WX_MAC_TX_CFG_TE); 211 212 /* Re configure MAC Rx */ 213 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE); 214 wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR); 215 wdg = rd32(wx, WX_MAC_WDG_TIMEOUT); 216 wr32(wx, WX_MAC_WDG_TIMEOUT, wdg); 217 } 218 219 static int txgbe_mac_prepare(struct phylink_config *config, unsigned int mode, 220 phy_interface_t interface) 221 { 222 struct wx *wx = netdev_priv(to_net_dev(config->dev)); 223 224 wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0); 225 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, 0); 226 227 return txgbe_disable_sec_tx_path(wx); 228 } 229 230 static int txgbe_mac_finish(struct phylink_config *config, unsigned int mode, 231 phy_interface_t interface) 232 { 233 struct wx *wx = netdev_priv(to_net_dev(config->dev)); 234 235 txgbe_enable_sec_tx_path(wx); 236 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE); 237 238 return 0; 239 } 240 241 static const struct phylink_mac_ops txgbe_mac_ops = { 242 .mac_select_pcs = txgbe_phylink_mac_select, 243 .mac_prepare = txgbe_mac_prepare, 244 .mac_finish = txgbe_mac_finish, 245 .mac_config = txgbe_mac_config, 246 .mac_link_down = txgbe_mac_link_down, 247 .mac_link_up = txgbe_mac_link_up, 248 }; 249 250 static int txgbe_phylink_init(struct txgbe *txgbe) 251 { 252 struct fwnode_handle *fwnode = NULL; 253 struct phylink_config *config; 254 struct wx *wx = txgbe->wx; 255 phy_interface_t phy_mode; 256 struct phylink *phylink; 257 258 config = devm_kzalloc(&wx->pdev->dev, sizeof(*config), GFP_KERNEL); 259 if (!config) 260 return -ENOMEM; 261 262 config->dev = &wx->netdev->dev; 263 config->type = PHYLINK_NETDEV; 264 config->mac_capabilities = MAC_10000FD | MAC_1000FD | MAC_100FD | 265 MAC_SYM_PAUSE | MAC_ASYM_PAUSE; 266 267 if (wx->media_type == sp_media_copper) { 268 phy_mode = PHY_INTERFACE_MODE_XAUI; 269 __set_bit(PHY_INTERFACE_MODE_XAUI, config->supported_interfaces); 270 } else { 271 phy_mode = PHY_INTERFACE_MODE_10GBASER; 272 fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_PHYLINK]); 273 __set_bit(PHY_INTERFACE_MODE_10GBASER, config->supported_interfaces); 274 __set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces); 275 __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); 276 } 277 278 phylink = phylink_create(config, fwnode, phy_mode, &txgbe_mac_ops); 279 if (IS_ERR(phylink)) 280 return PTR_ERR(phylink); 281 282 if (wx->phydev) { 283 int ret; 284 285 ret = phylink_connect_phy(phylink, wx->phydev); 286 if (ret) { 287 phylink_destroy(phylink); 288 return ret; 289 } 290 } 291 292 txgbe->phylink = phylink; 293 294 return 0; 295 } 296 297 static int txgbe_gpio_get(struct gpio_chip *chip, unsigned int offset) 298 { 299 struct wx *wx = gpiochip_get_data(chip); 300 int val; 301 302 val = rd32m(wx, WX_GPIO_EXT, BIT(offset)); 303 304 return !!(val & BIT(offset)); 305 } 306 307 static int txgbe_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 308 { 309 struct wx *wx = gpiochip_get_data(chip); 310 u32 val; 311 312 val = rd32(wx, WX_GPIO_DDR); 313 if (BIT(offset) & val) 314 return GPIO_LINE_DIRECTION_OUT; 315 316 return GPIO_LINE_DIRECTION_IN; 317 } 318 319 static int txgbe_gpio_direction_in(struct gpio_chip *chip, unsigned int offset) 320 { 321 struct wx *wx = gpiochip_get_data(chip); 322 unsigned long flags; 323 324 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 325 wr32m(wx, WX_GPIO_DDR, BIT(offset), 0); 326 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 327 328 return 0; 329 } 330 331 static int txgbe_gpio_direction_out(struct gpio_chip *chip, unsigned int offset, 332 int val) 333 { 334 struct wx *wx = gpiochip_get_data(chip); 335 unsigned long flags; 336 u32 set; 337 338 set = val ? BIT(offset) : 0; 339 340 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 341 wr32m(wx, WX_GPIO_DR, BIT(offset), set); 342 wr32m(wx, WX_GPIO_DDR, BIT(offset), BIT(offset)); 343 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 344 345 return 0; 346 } 347 348 static void txgbe_gpio_irq_ack(struct irq_data *d) 349 { 350 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 351 irq_hw_number_t hwirq = irqd_to_hwirq(d); 352 struct wx *wx = gpiochip_get_data(gc); 353 unsigned long flags; 354 355 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 356 wr32(wx, WX_GPIO_EOI, BIT(hwirq)); 357 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 358 } 359 360 static void txgbe_gpio_irq_mask(struct irq_data *d) 361 { 362 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 363 irq_hw_number_t hwirq = irqd_to_hwirq(d); 364 struct wx *wx = gpiochip_get_data(gc); 365 unsigned long flags; 366 367 gpiochip_disable_irq(gc, hwirq); 368 369 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 370 wr32m(wx, WX_GPIO_INTMASK, BIT(hwirq), BIT(hwirq)); 371 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 372 } 373 374 static void txgbe_gpio_irq_unmask(struct irq_data *d) 375 { 376 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 377 irq_hw_number_t hwirq = irqd_to_hwirq(d); 378 struct wx *wx = gpiochip_get_data(gc); 379 unsigned long flags; 380 381 gpiochip_enable_irq(gc, hwirq); 382 383 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 384 wr32m(wx, WX_GPIO_INTMASK, BIT(hwirq), 0); 385 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 386 } 387 388 static void txgbe_toggle_trigger(struct gpio_chip *gc, unsigned int offset) 389 { 390 struct wx *wx = gpiochip_get_data(gc); 391 u32 pol, val; 392 393 pol = rd32(wx, WX_GPIO_POLARITY); 394 val = rd32(wx, WX_GPIO_EXT); 395 396 if (val & BIT(offset)) 397 pol &= ~BIT(offset); 398 else 399 pol |= BIT(offset); 400 401 wr32(wx, WX_GPIO_POLARITY, pol); 402 } 403 404 static int txgbe_gpio_set_type(struct irq_data *d, unsigned int type) 405 { 406 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 407 irq_hw_number_t hwirq = irqd_to_hwirq(d); 408 struct wx *wx = gpiochip_get_data(gc); 409 u32 level, polarity, mask; 410 unsigned long flags; 411 412 mask = BIT(hwirq); 413 414 if (type & IRQ_TYPE_LEVEL_MASK) { 415 level = 0; 416 irq_set_handler_locked(d, handle_level_irq); 417 } else { 418 level = mask; 419 irq_set_handler_locked(d, handle_edge_irq); 420 } 421 422 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) 423 polarity = mask; 424 else 425 polarity = 0; 426 427 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 428 429 wr32m(wx, WX_GPIO_INTEN, mask, mask); 430 wr32m(wx, WX_GPIO_INTTYPE_LEVEL, mask, level); 431 if (type == IRQ_TYPE_EDGE_BOTH) 432 txgbe_toggle_trigger(gc, hwirq); 433 else 434 wr32m(wx, WX_GPIO_POLARITY, mask, polarity); 435 436 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 437 438 return 0; 439 } 440 441 static const struct irq_chip txgbe_gpio_irq_chip = { 442 .name = "txgbe_gpio_irq", 443 .irq_ack = txgbe_gpio_irq_ack, 444 .irq_mask = txgbe_gpio_irq_mask, 445 .irq_unmask = txgbe_gpio_irq_unmask, 446 .irq_set_type = txgbe_gpio_set_type, 447 .flags = IRQCHIP_IMMUTABLE, 448 GPIOCHIP_IRQ_RESOURCE_HELPERS, 449 }; 450 451 static void txgbe_irq_handler(struct irq_desc *desc) 452 { 453 struct irq_chip *chip = irq_desc_get_chip(desc); 454 struct wx *wx = irq_desc_get_handler_data(desc); 455 struct txgbe *txgbe = wx->priv; 456 irq_hw_number_t hwirq; 457 unsigned long gpioirq; 458 struct gpio_chip *gc; 459 unsigned long flags; 460 u32 eicr; 461 462 eicr = wx_misc_isb(wx, WX_ISB_MISC); 463 464 chained_irq_enter(chip, desc); 465 466 gpioirq = rd32(wx, WX_GPIO_INTSTATUS); 467 468 gc = txgbe->gpio; 469 for_each_set_bit(hwirq, &gpioirq, gc->ngpio) { 470 int gpio = irq_find_mapping(gc->irq.domain, hwirq); 471 u32 irq_type = irq_get_trigger_type(gpio); 472 473 generic_handle_domain_irq(gc->irq.domain, hwirq); 474 475 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 476 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 477 txgbe_toggle_trigger(gc, hwirq); 478 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 479 } 480 } 481 482 chained_irq_exit(chip, desc); 483 484 if (eicr & (TXGBE_PX_MISC_ETH_LK | TXGBE_PX_MISC_ETH_LKDN | 485 TXGBE_PX_MISC_ETH_AN)) { 486 u32 reg = rd32(wx, TXGBE_CFG_PORT_ST); 487 488 phylink_mac_change(txgbe->phylink, !!(reg & TXGBE_CFG_PORT_ST_LINK_UP)); 489 } 490 491 /* unmask interrupt */ 492 wx_intr_enable(wx, TXGBE_INTR_MISC(wx)); 493 } 494 495 static int txgbe_gpio_init(struct txgbe *txgbe) 496 { 497 struct gpio_irq_chip *girq; 498 struct gpio_chip *gc; 499 struct device *dev; 500 struct wx *wx; 501 int ret; 502 503 wx = txgbe->wx; 504 dev = &wx->pdev->dev; 505 506 raw_spin_lock_init(&wx->gpio_lock); 507 508 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 509 if (!gc) 510 return -ENOMEM; 511 512 gc->label = devm_kasprintf(dev, GFP_KERNEL, "txgbe_gpio-%x", 513 pci_dev_id(wx->pdev)); 514 if (!gc->label) 515 return -ENOMEM; 516 517 gc->base = -1; 518 gc->ngpio = 6; 519 gc->owner = THIS_MODULE; 520 gc->parent = dev; 521 gc->fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_GPIO]); 522 gc->get = txgbe_gpio_get; 523 gc->get_direction = txgbe_gpio_get_direction; 524 gc->direction_input = txgbe_gpio_direction_in; 525 gc->direction_output = txgbe_gpio_direction_out; 526 527 girq = &gc->irq; 528 gpio_irq_chip_set_chip(girq, &txgbe_gpio_irq_chip); 529 girq->parent_handler = txgbe_irq_handler; 530 girq->parent_handler_data = wx; 531 girq->num_parents = 1; 532 girq->parents = devm_kcalloc(dev, girq->num_parents, 533 sizeof(*girq->parents), GFP_KERNEL); 534 if (!girq->parents) 535 return -ENOMEM; 536 girq->parents[0] = wx->msix_entries[wx->num_q_vectors].vector; 537 girq->default_type = IRQ_TYPE_NONE; 538 girq->handler = handle_bad_irq; 539 540 ret = devm_gpiochip_add_data(dev, gc, wx); 541 if (ret) 542 return ret; 543 544 txgbe->gpio = gc; 545 546 return 0; 547 } 548 549 static int txgbe_clock_register(struct txgbe *txgbe) 550 { 551 struct pci_dev *pdev = txgbe->wx->pdev; 552 struct clk_lookup *clock; 553 char clk_name[32]; 554 struct clk *clk; 555 556 snprintf(clk_name, sizeof(clk_name), "%s.%d", 557 TXGBE_I2C_CLK_DEV_NAME, pci_dev_id(pdev)); 558 559 clk = clk_register_fixed_rate(NULL, clk_name, NULL, 0, 156250000); 560 if (IS_ERR(clk)) 561 return PTR_ERR(clk); 562 563 clock = clkdev_create(clk, NULL, clk_name); 564 if (!clock) { 565 clk_unregister(clk); 566 return -ENOMEM; 567 } 568 569 txgbe->clk = clk; 570 txgbe->clock = clock; 571 572 return 0; 573 } 574 575 static int txgbe_i2c_read(void *context, unsigned int reg, unsigned int *val) 576 { 577 struct wx *wx = context; 578 579 *val = rd32(wx, reg + TXGBE_I2C_BASE); 580 581 return 0; 582 } 583 584 static int txgbe_i2c_write(void *context, unsigned int reg, unsigned int val) 585 { 586 struct wx *wx = context; 587 588 wr32(wx, reg + TXGBE_I2C_BASE, val); 589 590 return 0; 591 } 592 593 static const struct regmap_config i2c_regmap_config = { 594 .reg_bits = 32, 595 .val_bits = 32, 596 .reg_read = txgbe_i2c_read, 597 .reg_write = txgbe_i2c_write, 598 .fast_io = true, 599 }; 600 601 static int txgbe_i2c_register(struct txgbe *txgbe) 602 { 603 struct platform_device_info info = {}; 604 struct platform_device *i2c_dev; 605 struct regmap *i2c_regmap; 606 struct pci_dev *pdev; 607 struct wx *wx; 608 609 wx = txgbe->wx; 610 pdev = wx->pdev; 611 i2c_regmap = devm_regmap_init(&pdev->dev, NULL, wx, &i2c_regmap_config); 612 if (IS_ERR(i2c_regmap)) { 613 wx_err(wx, "failed to init I2C regmap\n"); 614 return PTR_ERR(i2c_regmap); 615 } 616 617 info.parent = &pdev->dev; 618 info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_I2C]); 619 info.name = TXGBE_I2C_CLK_DEV_NAME; 620 info.id = pci_dev_id(pdev); 621 622 info.res = &DEFINE_RES_IRQ(pdev->irq); 623 info.num_res = 1; 624 i2c_dev = platform_device_register_full(&info); 625 if (IS_ERR(i2c_dev)) 626 return PTR_ERR(i2c_dev); 627 628 txgbe->i2c_dev = i2c_dev; 629 630 return 0; 631 } 632 633 static int txgbe_sfp_register(struct txgbe *txgbe) 634 { 635 struct pci_dev *pdev = txgbe->wx->pdev; 636 struct platform_device_info info = {}; 637 struct platform_device *sfp_dev; 638 639 info.parent = &pdev->dev; 640 info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_SFP]); 641 info.name = "sfp"; 642 info.id = pci_dev_id(pdev); 643 sfp_dev = platform_device_register_full(&info); 644 if (IS_ERR(sfp_dev)) 645 return PTR_ERR(sfp_dev); 646 647 txgbe->sfp_dev = sfp_dev; 648 649 return 0; 650 } 651 652 static int txgbe_phy_read(struct mii_bus *bus, int phy_addr, 653 int devnum, int regnum) 654 { 655 struct wx *wx = bus->priv; 656 u32 val, command; 657 int ret; 658 659 /* setup and write the address cycle command */ 660 command = WX_MSCA_RA(regnum) | 661 WX_MSCA_PA(phy_addr) | 662 WX_MSCA_DA(devnum); 663 wr32(wx, WX_MSCA, command); 664 665 command = WX_MSCC_CMD(WX_MSCA_CMD_READ) | WX_MSCC_BUSY; 666 wr32(wx, WX_MSCC, command); 667 668 /* wait to complete */ 669 ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000, 670 100000, false, wx, WX_MSCC); 671 if (ret) { 672 wx_err(wx, "Mdio read c45 command did not complete.\n"); 673 return ret; 674 } 675 676 return (u16)rd32(wx, WX_MSCC); 677 } 678 679 static int txgbe_phy_write(struct mii_bus *bus, int phy_addr, 680 int devnum, int regnum, u16 value) 681 { 682 struct wx *wx = bus->priv; 683 int ret, command; 684 u16 val; 685 686 /* setup and write the address cycle command */ 687 command = WX_MSCA_RA(regnum) | 688 WX_MSCA_PA(phy_addr) | 689 WX_MSCA_DA(devnum); 690 wr32(wx, WX_MSCA, command); 691 692 command = value | WX_MSCC_CMD(WX_MSCA_CMD_WRITE) | WX_MSCC_BUSY; 693 wr32(wx, WX_MSCC, command); 694 695 /* wait to complete */ 696 ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000, 697 100000, false, wx, WX_MSCC); 698 if (ret) 699 wx_err(wx, "Mdio write c45 command did not complete.\n"); 700 701 return ret; 702 } 703 704 static int txgbe_ext_phy_init(struct txgbe *txgbe) 705 { 706 struct phy_device *phydev; 707 struct mii_bus *mii_bus; 708 struct pci_dev *pdev; 709 struct wx *wx; 710 int ret = 0; 711 712 wx = txgbe->wx; 713 pdev = wx->pdev; 714 715 mii_bus = devm_mdiobus_alloc(&pdev->dev); 716 if (!mii_bus) 717 return -ENOMEM; 718 719 mii_bus->name = "txgbe_mii_bus"; 720 mii_bus->read_c45 = &txgbe_phy_read; 721 mii_bus->write_c45 = &txgbe_phy_write; 722 mii_bus->parent = &pdev->dev; 723 mii_bus->phy_mask = GENMASK(31, 1); 724 mii_bus->priv = wx; 725 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "txgbe-%x", 726 (pdev->bus->number << 8) | pdev->devfn); 727 728 ret = devm_mdiobus_register(&pdev->dev, mii_bus); 729 if (ret) { 730 wx_err(wx, "failed to register MDIO bus: %d\n", ret); 731 return ret; 732 } 733 734 phydev = phy_find_first(mii_bus); 735 if (!phydev) { 736 wx_err(wx, "no PHY found\n"); 737 return -ENODEV; 738 } 739 740 phy_attached_info(phydev); 741 742 wx->link = 0; 743 wx->speed = 0; 744 wx->duplex = 0; 745 wx->phydev = phydev; 746 747 ret = txgbe_phylink_init(txgbe); 748 if (ret) { 749 wx_err(wx, "failed to init phylink: %d\n", ret); 750 return ret; 751 } 752 753 return 0; 754 } 755 756 int txgbe_init_phy(struct txgbe *txgbe) 757 { 758 int ret; 759 760 if (txgbe->wx->media_type == sp_media_copper) 761 return txgbe_ext_phy_init(txgbe); 762 763 ret = txgbe_swnodes_register(txgbe); 764 if (ret) { 765 wx_err(txgbe->wx, "failed to register software nodes\n"); 766 return ret; 767 } 768 769 ret = txgbe_mdio_pcs_init(txgbe); 770 if (ret) { 771 wx_err(txgbe->wx, "failed to init mdio pcs: %d\n", ret); 772 goto err_unregister_swnode; 773 } 774 775 ret = txgbe_phylink_init(txgbe); 776 if (ret) { 777 wx_err(txgbe->wx, "failed to init phylink\n"); 778 goto err_destroy_xpcs; 779 } 780 781 ret = txgbe_gpio_init(txgbe); 782 if (ret) { 783 wx_err(txgbe->wx, "failed to init gpio\n"); 784 goto err_destroy_phylink; 785 } 786 787 ret = txgbe_clock_register(txgbe); 788 if (ret) { 789 wx_err(txgbe->wx, "failed to register clock: %d\n", ret); 790 goto err_destroy_phylink; 791 } 792 793 ret = txgbe_i2c_register(txgbe); 794 if (ret) { 795 wx_err(txgbe->wx, "failed to init i2c interface: %d\n", ret); 796 goto err_unregister_clk; 797 } 798 799 ret = txgbe_sfp_register(txgbe); 800 if (ret) { 801 wx_err(txgbe->wx, "failed to register sfp\n"); 802 goto err_unregister_i2c; 803 } 804 805 return 0; 806 807 err_unregister_i2c: 808 platform_device_unregister(txgbe->i2c_dev); 809 err_unregister_clk: 810 clkdev_drop(txgbe->clock); 811 clk_unregister(txgbe->clk); 812 err_destroy_phylink: 813 phylink_destroy(txgbe->phylink); 814 err_destroy_xpcs: 815 xpcs_destroy(txgbe->xpcs); 816 err_unregister_swnode: 817 software_node_unregister_node_group(txgbe->nodes.group); 818 819 return ret; 820 } 821 822 void txgbe_remove_phy(struct txgbe *txgbe) 823 { 824 if (txgbe->wx->media_type == sp_media_copper) { 825 phylink_disconnect_phy(txgbe->phylink); 826 phylink_destroy(txgbe->phylink); 827 return; 828 } 829 830 platform_device_unregister(txgbe->sfp_dev); 831 platform_device_unregister(txgbe->i2c_dev); 832 clkdev_drop(txgbe->clock); 833 clk_unregister(txgbe->clk); 834 phylink_destroy(txgbe->phylink); 835 xpcs_destroy(txgbe->xpcs); 836 software_node_unregister_node_group(txgbe->nodes.group); 837 } 838