1c3e382adSJiawen Wu // SPDX-License-Identifier: GPL-2.0
2c3e382adSJiawen Wu /* Copyright (c) 2015 - 2023 Beijing WangXun Technology Co., Ltd. */
3c3e382adSJiawen Wu
4b83c3731SJiawen Wu #include <linux/gpio/machine.h>
5b83c3731SJiawen Wu #include <linux/gpio/driver.h>
6c3e382adSJiawen Wu #include <linux/gpio/property.h>
7b63f2048SJiawen Wu #include <linux/clk-provider.h>
8b63f2048SJiawen Wu #include <linux/clkdev.h>
9c3e382adSJiawen Wu #include <linux/i2c.h>
10c3e382adSJiawen Wu #include <linux/pci.h>
11c625e725SJiawen Wu #include <linux/platform_device.h>
12c625e725SJiawen Wu #include <linux/regmap.h>
13854cace6SJiawen Wu #include <linux/pcs/pcs-xpcs.h>
1408f08f93SJiawen Wu #include <linux/phylink.h>
15c3e382adSJiawen Wu
16c3e382adSJiawen Wu #include "../libwx/wx_type.h"
1708f08f93SJiawen Wu #include "../libwx/wx_lib.h"
18b83c3731SJiawen Wu #include "../libwx/wx_hw.h"
19c3e382adSJiawen Wu #include "txgbe_type.h"
20c3e382adSJiawen Wu #include "txgbe_phy.h"
21a4414dd1SJiawen Wu #include "txgbe_hw.h"
22c3e382adSJiawen Wu
txgbe_swnodes_register(struct txgbe * txgbe)23c3e382adSJiawen Wu static int txgbe_swnodes_register(struct txgbe *txgbe)
24c3e382adSJiawen Wu {
25c3e382adSJiawen Wu struct txgbe_nodes *nodes = &txgbe->nodes;
26c3e382adSJiawen Wu struct pci_dev *pdev = txgbe->wx->pdev;
27c3e382adSJiawen Wu struct software_node *swnodes;
28c3e382adSJiawen Wu u32 id;
29c3e382adSJiawen Wu
30d8c21ef7SXiongfeng Wang id = pci_dev_id(pdev);
31c3e382adSJiawen Wu
32c3e382adSJiawen Wu snprintf(nodes->gpio_name, sizeof(nodes->gpio_name), "txgbe_gpio-%x", id);
33c3e382adSJiawen Wu snprintf(nodes->i2c_name, sizeof(nodes->i2c_name), "txgbe_i2c-%x", id);
34c3e382adSJiawen Wu snprintf(nodes->sfp_name, sizeof(nodes->sfp_name), "txgbe_sfp-%x", id);
35c3e382adSJiawen Wu snprintf(nodes->phylink_name, sizeof(nodes->phylink_name), "txgbe_phylink-%x", id);
36c3e382adSJiawen Wu
37c3e382adSJiawen Wu swnodes = nodes->swnodes;
38c3e382adSJiawen Wu
39c3e382adSJiawen Wu /* GPIO 0: tx fault
40c3e382adSJiawen Wu * GPIO 1: tx disable
41c3e382adSJiawen Wu * GPIO 2: sfp module absent
42c3e382adSJiawen Wu * GPIO 3: rx signal lost
43c3e382adSJiawen Wu * GPIO 4: rate select, 1G(0) 10G(1)
44c3e382adSJiawen Wu * GPIO 5: rate select, 1G(0) 10G(1)
45c3e382adSJiawen Wu */
46c3e382adSJiawen Wu nodes->gpio_props[0] = PROPERTY_ENTRY_STRING("pinctrl-names", "default");
47c3e382adSJiawen Wu swnodes[SWNODE_GPIO] = NODE_PROP(nodes->gpio_name, nodes->gpio_props);
48c3e382adSJiawen Wu nodes->gpio0_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 0, GPIO_ACTIVE_HIGH);
49c3e382adSJiawen Wu nodes->gpio1_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 1, GPIO_ACTIVE_HIGH);
50c3e382adSJiawen Wu nodes->gpio2_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 2, GPIO_ACTIVE_LOW);
51c3e382adSJiawen Wu nodes->gpio3_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 3, GPIO_ACTIVE_HIGH);
52c3e382adSJiawen Wu nodes->gpio4_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 4, GPIO_ACTIVE_HIGH);
53c3e382adSJiawen Wu nodes->gpio5_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 5, GPIO_ACTIVE_HIGH);
54c3e382adSJiawen Wu
55c3e382adSJiawen Wu nodes->i2c_props[0] = PROPERTY_ENTRY_STRING("compatible", "snps,designware-i2c");
56c3e382adSJiawen Wu nodes->i2c_props[1] = PROPERTY_ENTRY_BOOL("wx,i2c-snps-model");
57c3e382adSJiawen Wu nodes->i2c_props[2] = PROPERTY_ENTRY_U32("clock-frequency", I2C_MAX_STANDARD_MODE_FREQ);
58c3e382adSJiawen Wu swnodes[SWNODE_I2C] = NODE_PROP(nodes->i2c_name, nodes->i2c_props);
59c3e382adSJiawen Wu nodes->i2c_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_I2C]);
60c3e382adSJiawen Wu
61c3e382adSJiawen Wu nodes->sfp_props[0] = PROPERTY_ENTRY_STRING("compatible", "sff,sfp");
62c3e382adSJiawen Wu nodes->sfp_props[1] = PROPERTY_ENTRY_REF_ARRAY("i2c-bus", nodes->i2c_ref);
63c3e382adSJiawen Wu nodes->sfp_props[2] = PROPERTY_ENTRY_REF_ARRAY("tx-fault-gpios", nodes->gpio0_ref);
64c3e382adSJiawen Wu nodes->sfp_props[3] = PROPERTY_ENTRY_REF_ARRAY("tx-disable-gpios", nodes->gpio1_ref);
65c3e382adSJiawen Wu nodes->sfp_props[4] = PROPERTY_ENTRY_REF_ARRAY("mod-def0-gpios", nodes->gpio2_ref);
66c3e382adSJiawen Wu nodes->sfp_props[5] = PROPERTY_ENTRY_REF_ARRAY("los-gpios", nodes->gpio3_ref);
67c3e382adSJiawen Wu nodes->sfp_props[6] = PROPERTY_ENTRY_REF_ARRAY("rate-select1-gpios", nodes->gpio4_ref);
68c3e382adSJiawen Wu nodes->sfp_props[7] = PROPERTY_ENTRY_REF_ARRAY("rate-select0-gpios", nodes->gpio5_ref);
69c3e382adSJiawen Wu swnodes[SWNODE_SFP] = NODE_PROP(nodes->sfp_name, nodes->sfp_props);
70c3e382adSJiawen Wu nodes->sfp_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_SFP]);
71c3e382adSJiawen Wu
72c3e382adSJiawen Wu nodes->phylink_props[0] = PROPERTY_ENTRY_STRING("managed", "in-band-status");
73c3e382adSJiawen Wu nodes->phylink_props[1] = PROPERTY_ENTRY_REF_ARRAY("sfp", nodes->sfp_ref);
74c3e382adSJiawen Wu swnodes[SWNODE_PHYLINK] = NODE_PROP(nodes->phylink_name, nodes->phylink_props);
75c3e382adSJiawen Wu
76c3e382adSJiawen Wu nodes->group[SWNODE_GPIO] = &swnodes[SWNODE_GPIO];
77c3e382adSJiawen Wu nodes->group[SWNODE_I2C] = &swnodes[SWNODE_I2C];
78c3e382adSJiawen Wu nodes->group[SWNODE_SFP] = &swnodes[SWNODE_SFP];
79c3e382adSJiawen Wu nodes->group[SWNODE_PHYLINK] = &swnodes[SWNODE_PHYLINK];
80c3e382adSJiawen Wu
81c3e382adSJiawen Wu return software_node_register_node_group(nodes->group);
82c3e382adSJiawen Wu }
83c3e382adSJiawen Wu
txgbe_pcs_read(struct mii_bus * bus,int addr,int devnum,int regnum)84854cace6SJiawen Wu static int txgbe_pcs_read(struct mii_bus *bus, int addr, int devnum, int regnum)
85854cace6SJiawen Wu {
86854cace6SJiawen Wu struct wx *wx = bus->priv;
87854cace6SJiawen Wu u32 offset, val;
88854cace6SJiawen Wu
89854cace6SJiawen Wu if (addr)
90854cace6SJiawen Wu return -EOPNOTSUPP;
91854cace6SJiawen Wu
92854cace6SJiawen Wu offset = devnum << 16 | regnum;
93854cace6SJiawen Wu
94854cace6SJiawen Wu /* Set the LAN port indicator to IDA_ADDR */
95854cace6SJiawen Wu wr32(wx, TXGBE_XPCS_IDA_ADDR, offset);
96854cace6SJiawen Wu
97854cace6SJiawen Wu /* Read the data from IDA_DATA register */
98854cace6SJiawen Wu val = rd32(wx, TXGBE_XPCS_IDA_DATA);
99854cace6SJiawen Wu
100854cace6SJiawen Wu return (u16)val;
101854cace6SJiawen Wu }
102854cace6SJiawen Wu
txgbe_pcs_write(struct mii_bus * bus,int addr,int devnum,int regnum,u16 val)103854cace6SJiawen Wu static int txgbe_pcs_write(struct mii_bus *bus, int addr, int devnum, int regnum, u16 val)
104854cace6SJiawen Wu {
105854cace6SJiawen Wu struct wx *wx = bus->priv;
106854cace6SJiawen Wu u32 offset;
107854cace6SJiawen Wu
108854cace6SJiawen Wu if (addr)
109854cace6SJiawen Wu return -EOPNOTSUPP;
110854cace6SJiawen Wu
111854cace6SJiawen Wu offset = devnum << 16 | regnum;
112854cace6SJiawen Wu
113854cace6SJiawen Wu /* Set the LAN port indicator to IDA_ADDR */
114854cace6SJiawen Wu wr32(wx, TXGBE_XPCS_IDA_ADDR, offset);
115854cace6SJiawen Wu
116854cace6SJiawen Wu /* Write the data to IDA_DATA register */
117854cace6SJiawen Wu wr32(wx, TXGBE_XPCS_IDA_DATA, val);
118854cace6SJiawen Wu
119854cace6SJiawen Wu return 0;
120854cace6SJiawen Wu }
121854cace6SJiawen Wu
txgbe_mdio_pcs_init(struct txgbe * txgbe)122854cace6SJiawen Wu static int txgbe_mdio_pcs_init(struct txgbe *txgbe)
123854cace6SJiawen Wu {
124854cace6SJiawen Wu struct mii_bus *mii_bus;
125854cace6SJiawen Wu struct dw_xpcs *xpcs;
126854cace6SJiawen Wu struct pci_dev *pdev;
127854cace6SJiawen Wu struct wx *wx;
128854cace6SJiawen Wu int ret = 0;
129854cace6SJiawen Wu
130854cace6SJiawen Wu wx = txgbe->wx;
131854cace6SJiawen Wu pdev = wx->pdev;
132854cace6SJiawen Wu
133854cace6SJiawen Wu mii_bus = devm_mdiobus_alloc(&pdev->dev);
134854cace6SJiawen Wu if (!mii_bus)
135854cace6SJiawen Wu return -ENOMEM;
136854cace6SJiawen Wu
137854cace6SJiawen Wu mii_bus->name = "txgbe_pcs_mdio_bus";
138854cace6SJiawen Wu mii_bus->read_c45 = &txgbe_pcs_read;
139854cace6SJiawen Wu mii_bus->write_c45 = &txgbe_pcs_write;
140854cace6SJiawen Wu mii_bus->parent = &pdev->dev;
141854cace6SJiawen Wu mii_bus->phy_mask = ~0;
142854cace6SJiawen Wu mii_bus->priv = wx;
143854cace6SJiawen Wu snprintf(mii_bus->id, MII_BUS_ID_SIZE, "txgbe_pcs-%x",
144d8c21ef7SXiongfeng Wang pci_dev_id(pdev));
145854cace6SJiawen Wu
146854cace6SJiawen Wu ret = devm_mdiobus_register(&pdev->dev, mii_bus);
147854cace6SJiawen Wu if (ret)
148854cace6SJiawen Wu return ret;
149854cace6SJiawen Wu
150854cace6SJiawen Wu xpcs = xpcs_create_mdiodev(mii_bus, 0, PHY_INTERFACE_MODE_10GBASER);
151854cace6SJiawen Wu if (IS_ERR(xpcs))
152854cace6SJiawen Wu return PTR_ERR(xpcs);
153854cace6SJiawen Wu
154854cace6SJiawen Wu txgbe->xpcs = xpcs;
155854cace6SJiawen Wu
156854cace6SJiawen Wu return 0;
157854cace6SJiawen Wu }
158854cace6SJiawen Wu
txgbe_phylink_mac_select(struct phylink_config * config,phy_interface_t interface)15908f08f93SJiawen Wu static struct phylink_pcs *txgbe_phylink_mac_select(struct phylink_config *config,
16008f08f93SJiawen Wu phy_interface_t interface)
16108f08f93SJiawen Wu {
16208f08f93SJiawen Wu struct txgbe *txgbe = netdev_to_txgbe(to_net_dev(config->dev));
16308f08f93SJiawen Wu
16402b2a6f9SJiawen Wu if (interface == PHY_INTERFACE_MODE_10GBASER)
16508f08f93SJiawen Wu return &txgbe->xpcs->pcs;
16602b2a6f9SJiawen Wu
16702b2a6f9SJiawen Wu return NULL;
16808f08f93SJiawen Wu }
16908f08f93SJiawen Wu
txgbe_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)17008f08f93SJiawen Wu static void txgbe_mac_config(struct phylink_config *config, unsigned int mode,
17108f08f93SJiawen Wu const struct phylink_link_state *state)
17208f08f93SJiawen Wu {
17308f08f93SJiawen Wu }
17408f08f93SJiawen Wu
txgbe_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)17508f08f93SJiawen Wu static void txgbe_mac_link_down(struct phylink_config *config,
17608f08f93SJiawen Wu unsigned int mode, phy_interface_t interface)
17708f08f93SJiawen Wu {
17808f08f93SJiawen Wu struct wx *wx = netdev_priv(to_net_dev(config->dev));
17908f08f93SJiawen Wu
18008f08f93SJiawen Wu wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0);
18108f08f93SJiawen Wu }
18208f08f93SJiawen Wu
txgbe_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)18308f08f93SJiawen Wu static void txgbe_mac_link_up(struct phylink_config *config,
18408f08f93SJiawen Wu struct phy_device *phy,
18508f08f93SJiawen Wu unsigned int mode, phy_interface_t interface,
18608f08f93SJiawen Wu int speed, int duplex,
18708f08f93SJiawen Wu bool tx_pause, bool rx_pause)
18808f08f93SJiawen Wu {
18908f08f93SJiawen Wu struct wx *wx = netdev_priv(to_net_dev(config->dev));
19008f08f93SJiawen Wu u32 txcfg, wdg;
19108f08f93SJiawen Wu
19208f08f93SJiawen Wu txcfg = rd32(wx, WX_MAC_TX_CFG);
19308f08f93SJiawen Wu txcfg &= ~WX_MAC_TX_CFG_SPEED_MASK;
19408f08f93SJiawen Wu
19508f08f93SJiawen Wu switch (speed) {
19608f08f93SJiawen Wu case SPEED_10000:
19708f08f93SJiawen Wu txcfg |= WX_MAC_TX_CFG_SPEED_10G;
19808f08f93SJiawen Wu break;
19908f08f93SJiawen Wu case SPEED_1000:
20008f08f93SJiawen Wu case SPEED_100:
20108f08f93SJiawen Wu case SPEED_10:
20208f08f93SJiawen Wu txcfg |= WX_MAC_TX_CFG_SPEED_1G;
20308f08f93SJiawen Wu break;
20408f08f93SJiawen Wu default:
20508f08f93SJiawen Wu break;
20608f08f93SJiawen Wu }
20708f08f93SJiawen Wu
20808f08f93SJiawen Wu wr32(wx, WX_MAC_TX_CFG, txcfg | WX_MAC_TX_CFG_TE);
20908f08f93SJiawen Wu
21008f08f93SJiawen Wu /* Re configure MAC Rx */
21108f08f93SJiawen Wu wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE);
21208f08f93SJiawen Wu wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR);
21308f08f93SJiawen Wu wdg = rd32(wx, WX_MAC_WDG_TIMEOUT);
21408f08f93SJiawen Wu wr32(wx, WX_MAC_WDG_TIMEOUT, wdg);
21508f08f93SJiawen Wu }
21608f08f93SJiawen Wu
txgbe_mac_prepare(struct phylink_config * config,unsigned int mode,phy_interface_t interface)217a4414dd1SJiawen Wu static int txgbe_mac_prepare(struct phylink_config *config, unsigned int mode,
218a4414dd1SJiawen Wu phy_interface_t interface)
219a4414dd1SJiawen Wu {
220a4414dd1SJiawen Wu struct wx *wx = netdev_priv(to_net_dev(config->dev));
221a4414dd1SJiawen Wu
222a4414dd1SJiawen Wu wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0);
223a4414dd1SJiawen Wu wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, 0);
224a4414dd1SJiawen Wu
225a4414dd1SJiawen Wu return txgbe_disable_sec_tx_path(wx);
226a4414dd1SJiawen Wu }
227a4414dd1SJiawen Wu
txgbe_mac_finish(struct phylink_config * config,unsigned int mode,phy_interface_t interface)228a4414dd1SJiawen Wu static int txgbe_mac_finish(struct phylink_config *config, unsigned int mode,
229a4414dd1SJiawen Wu phy_interface_t interface)
230a4414dd1SJiawen Wu {
231a4414dd1SJiawen Wu struct wx *wx = netdev_priv(to_net_dev(config->dev));
232a4414dd1SJiawen Wu
233a4414dd1SJiawen Wu txgbe_enable_sec_tx_path(wx);
234a4414dd1SJiawen Wu wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE);
235a4414dd1SJiawen Wu
236a4414dd1SJiawen Wu return 0;
237a4414dd1SJiawen Wu }
238a4414dd1SJiawen Wu
23908f08f93SJiawen Wu static const struct phylink_mac_ops txgbe_mac_ops = {
24008f08f93SJiawen Wu .mac_select_pcs = txgbe_phylink_mac_select,
241a4414dd1SJiawen Wu .mac_prepare = txgbe_mac_prepare,
242a4414dd1SJiawen Wu .mac_finish = txgbe_mac_finish,
24308f08f93SJiawen Wu .mac_config = txgbe_mac_config,
24408f08f93SJiawen Wu .mac_link_down = txgbe_mac_link_down,
24508f08f93SJiawen Wu .mac_link_up = txgbe_mac_link_up,
24608f08f93SJiawen Wu };
24708f08f93SJiawen Wu
txgbe_phylink_init(struct txgbe * txgbe)24808f08f93SJiawen Wu static int txgbe_phylink_init(struct txgbe *txgbe)
24908f08f93SJiawen Wu {
25002b2a6f9SJiawen Wu struct fwnode_handle *fwnode = NULL;
25108f08f93SJiawen Wu struct phylink_config *config;
25208f08f93SJiawen Wu struct wx *wx = txgbe->wx;
25308f08f93SJiawen Wu phy_interface_t phy_mode;
25408f08f93SJiawen Wu struct phylink *phylink;
25508f08f93SJiawen Wu
25608f08f93SJiawen Wu config = devm_kzalloc(&wx->pdev->dev, sizeof(*config), GFP_KERNEL);
25708f08f93SJiawen Wu if (!config)
25808f08f93SJiawen Wu return -ENOMEM;
25908f08f93SJiawen Wu
26008f08f93SJiawen Wu config->dev = &wx->netdev->dev;
26108f08f93SJiawen Wu config->type = PHYLINK_NETDEV;
26202b2a6f9SJiawen Wu config->mac_capabilities = MAC_10000FD | MAC_1000FD | MAC_100FD |
26302b2a6f9SJiawen Wu MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
26402b2a6f9SJiawen Wu
26502b2a6f9SJiawen Wu if (wx->media_type == sp_media_copper) {
26602b2a6f9SJiawen Wu phy_mode = PHY_INTERFACE_MODE_XAUI;
26702b2a6f9SJiawen Wu __set_bit(PHY_INTERFACE_MODE_XAUI, config->supported_interfaces);
26802b2a6f9SJiawen Wu } else {
26908f08f93SJiawen Wu phy_mode = PHY_INTERFACE_MODE_10GBASER;
27002b2a6f9SJiawen Wu fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_PHYLINK]);
27108f08f93SJiawen Wu __set_bit(PHY_INTERFACE_MODE_10GBASER, config->supported_interfaces);
272a4414dd1SJiawen Wu __set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces);
273a4414dd1SJiawen Wu __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces);
27402b2a6f9SJiawen Wu }
27502b2a6f9SJiawen Wu
27608f08f93SJiawen Wu phylink = phylink_create(config, fwnode, phy_mode, &txgbe_mac_ops);
27708f08f93SJiawen Wu if (IS_ERR(phylink))
27808f08f93SJiawen Wu return PTR_ERR(phylink);
27908f08f93SJiawen Wu
28002b2a6f9SJiawen Wu if (wx->phydev) {
28102b2a6f9SJiawen Wu int ret;
28202b2a6f9SJiawen Wu
28302b2a6f9SJiawen Wu ret = phylink_connect_phy(phylink, wx->phydev);
28402b2a6f9SJiawen Wu if (ret) {
28502b2a6f9SJiawen Wu phylink_destroy(phylink);
28602b2a6f9SJiawen Wu return ret;
28702b2a6f9SJiawen Wu }
28802b2a6f9SJiawen Wu }
28902b2a6f9SJiawen Wu
29008f08f93SJiawen Wu txgbe->phylink = phylink;
29108f08f93SJiawen Wu
29208f08f93SJiawen Wu return 0;
29308f08f93SJiawen Wu }
29408f08f93SJiawen Wu
txgbe_gpio_get(struct gpio_chip * chip,unsigned int offset)295b83c3731SJiawen Wu static int txgbe_gpio_get(struct gpio_chip *chip, unsigned int offset)
296b83c3731SJiawen Wu {
297b83c3731SJiawen Wu struct wx *wx = gpiochip_get_data(chip);
298b83c3731SJiawen Wu int val;
299b83c3731SJiawen Wu
300b83c3731SJiawen Wu val = rd32m(wx, WX_GPIO_EXT, BIT(offset));
301b83c3731SJiawen Wu
302b83c3731SJiawen Wu return !!(val & BIT(offset));
303b83c3731SJiawen Wu }
304b83c3731SJiawen Wu
txgbe_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)305b83c3731SJiawen Wu static int txgbe_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
306b83c3731SJiawen Wu {
307b83c3731SJiawen Wu struct wx *wx = gpiochip_get_data(chip);
308b83c3731SJiawen Wu u32 val;
309b83c3731SJiawen Wu
310b83c3731SJiawen Wu val = rd32(wx, WX_GPIO_DDR);
311b83c3731SJiawen Wu if (BIT(offset) & val)
312b83c3731SJiawen Wu return GPIO_LINE_DIRECTION_OUT;
313b83c3731SJiawen Wu
314b83c3731SJiawen Wu return GPIO_LINE_DIRECTION_IN;
315b83c3731SJiawen Wu }
316b83c3731SJiawen Wu
txgbe_gpio_direction_in(struct gpio_chip * chip,unsigned int offset)317b83c3731SJiawen Wu static int txgbe_gpio_direction_in(struct gpio_chip *chip, unsigned int offset)
318b83c3731SJiawen Wu {
319b83c3731SJiawen Wu struct wx *wx = gpiochip_get_data(chip);
320b83c3731SJiawen Wu unsigned long flags;
321b83c3731SJiawen Wu
322b83c3731SJiawen Wu raw_spin_lock_irqsave(&wx->gpio_lock, flags);
323b83c3731SJiawen Wu wr32m(wx, WX_GPIO_DDR, BIT(offset), 0);
324b83c3731SJiawen Wu raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
325b83c3731SJiawen Wu
326b83c3731SJiawen Wu return 0;
327b83c3731SJiawen Wu }
328b83c3731SJiawen Wu
txgbe_gpio_direction_out(struct gpio_chip * chip,unsigned int offset,int val)329b83c3731SJiawen Wu static int txgbe_gpio_direction_out(struct gpio_chip *chip, unsigned int offset,
330b83c3731SJiawen Wu int val)
331b83c3731SJiawen Wu {
332b83c3731SJiawen Wu struct wx *wx = gpiochip_get_data(chip);
333b83c3731SJiawen Wu unsigned long flags;
334b83c3731SJiawen Wu u32 set;
335b83c3731SJiawen Wu
336b83c3731SJiawen Wu set = val ? BIT(offset) : 0;
337b83c3731SJiawen Wu
338b83c3731SJiawen Wu raw_spin_lock_irqsave(&wx->gpio_lock, flags);
339b83c3731SJiawen Wu wr32m(wx, WX_GPIO_DR, BIT(offset), set);
340b83c3731SJiawen Wu wr32m(wx, WX_GPIO_DDR, BIT(offset), BIT(offset));
341b83c3731SJiawen Wu raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
342b83c3731SJiawen Wu
343b83c3731SJiawen Wu return 0;
344b83c3731SJiawen Wu }
345b83c3731SJiawen Wu
txgbe_gpio_irq_ack(struct irq_data * d)346b83c3731SJiawen Wu static void txgbe_gpio_irq_ack(struct irq_data *d)
347b83c3731SJiawen Wu {
348b83c3731SJiawen Wu struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
349b83c3731SJiawen Wu irq_hw_number_t hwirq = irqd_to_hwirq(d);
350b83c3731SJiawen Wu struct wx *wx = gpiochip_get_data(gc);
351b83c3731SJiawen Wu unsigned long flags;
352b83c3731SJiawen Wu
353b83c3731SJiawen Wu raw_spin_lock_irqsave(&wx->gpio_lock, flags);
354b83c3731SJiawen Wu wr32(wx, WX_GPIO_EOI, BIT(hwirq));
355b83c3731SJiawen Wu raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
356b83c3731SJiawen Wu }
357b83c3731SJiawen Wu
txgbe_gpio_irq_mask(struct irq_data * d)358b83c3731SJiawen Wu static void txgbe_gpio_irq_mask(struct irq_data *d)
359b83c3731SJiawen Wu {
360b83c3731SJiawen Wu struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
361b83c3731SJiawen Wu irq_hw_number_t hwirq = irqd_to_hwirq(d);
362b83c3731SJiawen Wu struct wx *wx = gpiochip_get_data(gc);
363b83c3731SJiawen Wu unsigned long flags;
364b83c3731SJiawen Wu
365b83c3731SJiawen Wu gpiochip_disable_irq(gc, hwirq);
366b83c3731SJiawen Wu
367b83c3731SJiawen Wu raw_spin_lock_irqsave(&wx->gpio_lock, flags);
368b83c3731SJiawen Wu wr32m(wx, WX_GPIO_INTMASK, BIT(hwirq), BIT(hwirq));
369b83c3731SJiawen Wu raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
370b83c3731SJiawen Wu }
371b83c3731SJiawen Wu
txgbe_gpio_irq_unmask(struct irq_data * d)372b83c3731SJiawen Wu static void txgbe_gpio_irq_unmask(struct irq_data *d)
373b83c3731SJiawen Wu {
374b83c3731SJiawen Wu struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
375b83c3731SJiawen Wu irq_hw_number_t hwirq = irqd_to_hwirq(d);
376b83c3731SJiawen Wu struct wx *wx = gpiochip_get_data(gc);
377b83c3731SJiawen Wu unsigned long flags;
378b83c3731SJiawen Wu
379b83c3731SJiawen Wu gpiochip_enable_irq(gc, hwirq);
380b83c3731SJiawen Wu
381b83c3731SJiawen Wu raw_spin_lock_irqsave(&wx->gpio_lock, flags);
382b83c3731SJiawen Wu wr32m(wx, WX_GPIO_INTMASK, BIT(hwirq), 0);
383b83c3731SJiawen Wu raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
384b83c3731SJiawen Wu }
385b83c3731SJiawen Wu
txgbe_toggle_trigger(struct gpio_chip * gc,unsigned int offset)386b83c3731SJiawen Wu static void txgbe_toggle_trigger(struct gpio_chip *gc, unsigned int offset)
387b83c3731SJiawen Wu {
388b83c3731SJiawen Wu struct wx *wx = gpiochip_get_data(gc);
389b83c3731SJiawen Wu u32 pol, val;
390b83c3731SJiawen Wu
391b83c3731SJiawen Wu pol = rd32(wx, WX_GPIO_POLARITY);
392b83c3731SJiawen Wu val = rd32(wx, WX_GPIO_EXT);
393b83c3731SJiawen Wu
394b83c3731SJiawen Wu if (val & BIT(offset))
395b83c3731SJiawen Wu pol &= ~BIT(offset);
396b83c3731SJiawen Wu else
397b83c3731SJiawen Wu pol |= BIT(offset);
398b83c3731SJiawen Wu
399b83c3731SJiawen Wu wr32(wx, WX_GPIO_POLARITY, pol);
400b83c3731SJiawen Wu }
401b83c3731SJiawen Wu
txgbe_gpio_set_type(struct irq_data * d,unsigned int type)402b83c3731SJiawen Wu static int txgbe_gpio_set_type(struct irq_data *d, unsigned int type)
403b83c3731SJiawen Wu {
404b83c3731SJiawen Wu struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
405b83c3731SJiawen Wu irq_hw_number_t hwirq = irqd_to_hwirq(d);
406b83c3731SJiawen Wu struct wx *wx = gpiochip_get_data(gc);
407b83c3731SJiawen Wu u32 level, polarity, mask;
408b83c3731SJiawen Wu unsigned long flags;
409b83c3731SJiawen Wu
410b83c3731SJiawen Wu mask = BIT(hwirq);
411b83c3731SJiawen Wu
412b83c3731SJiawen Wu if (type & IRQ_TYPE_LEVEL_MASK) {
413b83c3731SJiawen Wu level = 0;
414b83c3731SJiawen Wu irq_set_handler_locked(d, handle_level_irq);
415b83c3731SJiawen Wu } else {
416b83c3731SJiawen Wu level = mask;
417b83c3731SJiawen Wu irq_set_handler_locked(d, handle_edge_irq);
418b83c3731SJiawen Wu }
419b83c3731SJiawen Wu
420b83c3731SJiawen Wu if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
421b83c3731SJiawen Wu polarity = mask;
422b83c3731SJiawen Wu else
423b83c3731SJiawen Wu polarity = 0;
424b83c3731SJiawen Wu
425b83c3731SJiawen Wu raw_spin_lock_irqsave(&wx->gpio_lock, flags);
426b83c3731SJiawen Wu
427b83c3731SJiawen Wu wr32m(wx, WX_GPIO_INTEN, mask, mask);
428b83c3731SJiawen Wu wr32m(wx, WX_GPIO_INTTYPE_LEVEL, mask, level);
429b83c3731SJiawen Wu if (type == IRQ_TYPE_EDGE_BOTH)
430b83c3731SJiawen Wu txgbe_toggle_trigger(gc, hwirq);
431b83c3731SJiawen Wu else
432b83c3731SJiawen Wu wr32m(wx, WX_GPIO_POLARITY, mask, polarity);
433b83c3731SJiawen Wu
434b83c3731SJiawen Wu raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
435b83c3731SJiawen Wu
436b83c3731SJiawen Wu return 0;
437b83c3731SJiawen Wu }
438b83c3731SJiawen Wu
439b83c3731SJiawen Wu static const struct irq_chip txgbe_gpio_irq_chip = {
440b83c3731SJiawen Wu .name = "txgbe_gpio_irq",
441b83c3731SJiawen Wu .irq_ack = txgbe_gpio_irq_ack,
442b83c3731SJiawen Wu .irq_mask = txgbe_gpio_irq_mask,
443b83c3731SJiawen Wu .irq_unmask = txgbe_gpio_irq_unmask,
444b83c3731SJiawen Wu .irq_set_type = txgbe_gpio_set_type,
445b83c3731SJiawen Wu .flags = IRQCHIP_IMMUTABLE,
446b83c3731SJiawen Wu GPIOCHIP_IRQ_RESOURCE_HELPERS,
447b83c3731SJiawen Wu };
448b83c3731SJiawen Wu
txgbe_irq_handler(struct irq_desc * desc)449b83c3731SJiawen Wu static void txgbe_irq_handler(struct irq_desc *desc)
450b83c3731SJiawen Wu {
451b83c3731SJiawen Wu struct irq_chip *chip = irq_desc_get_chip(desc);
452b83c3731SJiawen Wu struct wx *wx = irq_desc_get_handler_data(desc);
453b83c3731SJiawen Wu struct txgbe *txgbe = wx->priv;
454b83c3731SJiawen Wu irq_hw_number_t hwirq;
455b83c3731SJiawen Wu unsigned long gpioirq;
456b83c3731SJiawen Wu struct gpio_chip *gc;
457b83c3731SJiawen Wu unsigned long flags;
45808f08f93SJiawen Wu u32 eicr;
45908f08f93SJiawen Wu
46008f08f93SJiawen Wu eicr = wx_misc_isb(wx, WX_ISB_MISC);
461b83c3731SJiawen Wu
462b83c3731SJiawen Wu chained_irq_enter(chip, desc);
463b83c3731SJiawen Wu
464b83c3731SJiawen Wu gpioirq = rd32(wx, WX_GPIO_INTSTATUS);
465b83c3731SJiawen Wu
466b83c3731SJiawen Wu gc = txgbe->gpio;
467b83c3731SJiawen Wu for_each_set_bit(hwirq, &gpioirq, gc->ngpio) {
468b83c3731SJiawen Wu int gpio = irq_find_mapping(gc->irq.domain, hwirq);
469b83c3731SJiawen Wu u32 irq_type = irq_get_trigger_type(gpio);
470b83c3731SJiawen Wu
471b83c3731SJiawen Wu generic_handle_domain_irq(gc->irq.domain, hwirq);
472b83c3731SJiawen Wu
473b83c3731SJiawen Wu if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
474b83c3731SJiawen Wu raw_spin_lock_irqsave(&wx->gpio_lock, flags);
475b83c3731SJiawen Wu txgbe_toggle_trigger(gc, hwirq);
476b83c3731SJiawen Wu raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
477b83c3731SJiawen Wu }
478b83c3731SJiawen Wu }
479b83c3731SJiawen Wu
480b83c3731SJiawen Wu chained_irq_exit(chip, desc);
481b83c3731SJiawen Wu
482a4414dd1SJiawen Wu if (eicr & (TXGBE_PX_MISC_ETH_LK | TXGBE_PX_MISC_ETH_LKDN |
483a4414dd1SJiawen Wu TXGBE_PX_MISC_ETH_AN)) {
48408f08f93SJiawen Wu u32 reg = rd32(wx, TXGBE_CFG_PORT_ST);
48508f08f93SJiawen Wu
48608f08f93SJiawen Wu phylink_mac_change(txgbe->phylink, !!(reg & TXGBE_CFG_PORT_ST_LINK_UP));
48708f08f93SJiawen Wu }
48808f08f93SJiawen Wu
489b83c3731SJiawen Wu /* unmask interrupt */
490b83c3731SJiawen Wu wx_intr_enable(wx, TXGBE_INTR_MISC(wx));
491b83c3731SJiawen Wu }
492b83c3731SJiawen Wu
txgbe_gpio_init(struct txgbe * txgbe)493b83c3731SJiawen Wu static int txgbe_gpio_init(struct txgbe *txgbe)
494b83c3731SJiawen Wu {
495b83c3731SJiawen Wu struct gpio_irq_chip *girq;
496b83c3731SJiawen Wu struct gpio_chip *gc;
497b83c3731SJiawen Wu struct device *dev;
498b83c3731SJiawen Wu struct wx *wx;
499b83c3731SJiawen Wu int ret;
500b83c3731SJiawen Wu
501b83c3731SJiawen Wu wx = txgbe->wx;
502b83c3731SJiawen Wu dev = &wx->pdev->dev;
503b83c3731SJiawen Wu
504b83c3731SJiawen Wu raw_spin_lock_init(&wx->gpio_lock);
505b83c3731SJiawen Wu
506b83c3731SJiawen Wu gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
507b83c3731SJiawen Wu if (!gc)
508b83c3731SJiawen Wu return -ENOMEM;
509b83c3731SJiawen Wu
510b83c3731SJiawen Wu gc->label = devm_kasprintf(dev, GFP_KERNEL, "txgbe_gpio-%x",
511d8c21ef7SXiongfeng Wang pci_dev_id(wx->pdev));
512b83c3731SJiawen Wu if (!gc->label)
513b83c3731SJiawen Wu return -ENOMEM;
514b83c3731SJiawen Wu
515b83c3731SJiawen Wu gc->base = -1;
516b83c3731SJiawen Wu gc->ngpio = 6;
517b83c3731SJiawen Wu gc->owner = THIS_MODULE;
518b83c3731SJiawen Wu gc->parent = dev;
519b83c3731SJiawen Wu gc->fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_GPIO]);
520b83c3731SJiawen Wu gc->get = txgbe_gpio_get;
521b83c3731SJiawen Wu gc->get_direction = txgbe_gpio_get_direction;
522b83c3731SJiawen Wu gc->direction_input = txgbe_gpio_direction_in;
523b83c3731SJiawen Wu gc->direction_output = txgbe_gpio_direction_out;
524b83c3731SJiawen Wu
525b83c3731SJiawen Wu girq = &gc->irq;
526b83c3731SJiawen Wu gpio_irq_chip_set_chip(girq, &txgbe_gpio_irq_chip);
527b83c3731SJiawen Wu girq->parent_handler = txgbe_irq_handler;
528b83c3731SJiawen Wu girq->parent_handler_data = wx;
529b83c3731SJiawen Wu girq->num_parents = 1;
530b83c3731SJiawen Wu girq->parents = devm_kcalloc(dev, girq->num_parents,
531b83c3731SJiawen Wu sizeof(*girq->parents), GFP_KERNEL);
532b83c3731SJiawen Wu if (!girq->parents)
533b83c3731SJiawen Wu return -ENOMEM;
534b83c3731SJiawen Wu girq->parents[0] = wx->msix_entries[wx->num_q_vectors].vector;
535b83c3731SJiawen Wu girq->default_type = IRQ_TYPE_NONE;
536b83c3731SJiawen Wu girq->handler = handle_bad_irq;
537b83c3731SJiawen Wu
538b83c3731SJiawen Wu ret = devm_gpiochip_add_data(dev, gc, wx);
539b83c3731SJiawen Wu if (ret)
540b83c3731SJiawen Wu return ret;
541b83c3731SJiawen Wu
542b83c3731SJiawen Wu txgbe->gpio = gc;
543b83c3731SJiawen Wu
544b83c3731SJiawen Wu return 0;
545b83c3731SJiawen Wu }
546b83c3731SJiawen Wu
txgbe_clock_register(struct txgbe * txgbe)547b63f2048SJiawen Wu static int txgbe_clock_register(struct txgbe *txgbe)
548b63f2048SJiawen Wu {
549b63f2048SJiawen Wu struct pci_dev *pdev = txgbe->wx->pdev;
550b63f2048SJiawen Wu struct clk_lookup *clock;
551b63f2048SJiawen Wu char clk_name[32];
552b63f2048SJiawen Wu struct clk *clk;
553b63f2048SJiawen Wu
554d4ed9984SDuanqiang Wen snprintf(clk_name, sizeof(clk_name), "i2c_designware.%d",
555d6a20073SDuanqiang Wen pci_dev_id(pdev));
556b63f2048SJiawen Wu
557b63f2048SJiawen Wu clk = clk_register_fixed_rate(NULL, clk_name, NULL, 0, 156250000);
558b63f2048SJiawen Wu if (IS_ERR(clk))
559b63f2048SJiawen Wu return PTR_ERR(clk);
560b63f2048SJiawen Wu
561b63f2048SJiawen Wu clock = clkdev_create(clk, NULL, clk_name);
562b63f2048SJiawen Wu if (!clock) {
563b63f2048SJiawen Wu clk_unregister(clk);
564b63f2048SJiawen Wu return -ENOMEM;
565b63f2048SJiawen Wu }
566b63f2048SJiawen Wu
567b63f2048SJiawen Wu txgbe->clk = clk;
568b63f2048SJiawen Wu txgbe->clock = clock;
569b63f2048SJiawen Wu
570b63f2048SJiawen Wu return 0;
571b63f2048SJiawen Wu }
572b63f2048SJiawen Wu
txgbe_i2c_read(void * context,unsigned int reg,unsigned int * val)573c625e725SJiawen Wu static int txgbe_i2c_read(void *context, unsigned int reg, unsigned int *val)
574c625e725SJiawen Wu {
575c625e725SJiawen Wu struct wx *wx = context;
576c625e725SJiawen Wu
577c625e725SJiawen Wu *val = rd32(wx, reg + TXGBE_I2C_BASE);
578c625e725SJiawen Wu
579c625e725SJiawen Wu return 0;
580c625e725SJiawen Wu }
581c625e725SJiawen Wu
txgbe_i2c_write(void * context,unsigned int reg,unsigned int val)582c625e725SJiawen Wu static int txgbe_i2c_write(void *context, unsigned int reg, unsigned int val)
583c625e725SJiawen Wu {
584c625e725SJiawen Wu struct wx *wx = context;
585c625e725SJiawen Wu
586c625e725SJiawen Wu wr32(wx, reg + TXGBE_I2C_BASE, val);
587c625e725SJiawen Wu
588c625e725SJiawen Wu return 0;
589c625e725SJiawen Wu }
590c625e725SJiawen Wu
591c625e725SJiawen Wu static const struct regmap_config i2c_regmap_config = {
592c625e725SJiawen Wu .reg_bits = 32,
593c625e725SJiawen Wu .val_bits = 32,
594c625e725SJiawen Wu .reg_read = txgbe_i2c_read,
595c625e725SJiawen Wu .reg_write = txgbe_i2c_write,
596c625e725SJiawen Wu .fast_io = true,
597c625e725SJiawen Wu };
598c625e725SJiawen Wu
txgbe_i2c_register(struct txgbe * txgbe)599c625e725SJiawen Wu static int txgbe_i2c_register(struct txgbe *txgbe)
600c625e725SJiawen Wu {
601c625e725SJiawen Wu struct platform_device_info info = {};
602c625e725SJiawen Wu struct platform_device *i2c_dev;
603c625e725SJiawen Wu struct regmap *i2c_regmap;
604c625e725SJiawen Wu struct pci_dev *pdev;
605c625e725SJiawen Wu struct wx *wx;
606c625e725SJiawen Wu
607c625e725SJiawen Wu wx = txgbe->wx;
608c625e725SJiawen Wu pdev = wx->pdev;
609c625e725SJiawen Wu i2c_regmap = devm_regmap_init(&pdev->dev, NULL, wx, &i2c_regmap_config);
610c625e725SJiawen Wu if (IS_ERR(i2c_regmap)) {
611c625e725SJiawen Wu wx_err(wx, "failed to init I2C regmap\n");
612c625e725SJiawen Wu return PTR_ERR(i2c_regmap);
613c625e725SJiawen Wu }
614c625e725SJiawen Wu
615c625e725SJiawen Wu info.parent = &pdev->dev;
616c625e725SJiawen Wu info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_I2C]);
617d6a20073SDuanqiang Wen info.name = "i2c_designware";
618d8c21ef7SXiongfeng Wang info.id = pci_dev_id(pdev);
619c625e725SJiawen Wu
620c625e725SJiawen Wu info.res = &DEFINE_RES_IRQ(pdev->irq);
621c625e725SJiawen Wu info.num_res = 1;
622c625e725SJiawen Wu i2c_dev = platform_device_register_full(&info);
623c625e725SJiawen Wu if (IS_ERR(i2c_dev))
624c625e725SJiawen Wu return PTR_ERR(i2c_dev);
625c625e725SJiawen Wu
626c625e725SJiawen Wu txgbe->i2c_dev = i2c_dev;
627c625e725SJiawen Wu
628c625e725SJiawen Wu return 0;
629c625e725SJiawen Wu }
630c625e725SJiawen Wu
txgbe_sfp_register(struct txgbe * txgbe)63104d94236SJiawen Wu static int txgbe_sfp_register(struct txgbe *txgbe)
63204d94236SJiawen Wu {
63304d94236SJiawen Wu struct pci_dev *pdev = txgbe->wx->pdev;
63404d94236SJiawen Wu struct platform_device_info info = {};
63504d94236SJiawen Wu struct platform_device *sfp_dev;
63604d94236SJiawen Wu
63704d94236SJiawen Wu info.parent = &pdev->dev;
63804d94236SJiawen Wu info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_SFP]);
63904d94236SJiawen Wu info.name = "sfp";
640d8c21ef7SXiongfeng Wang info.id = pci_dev_id(pdev);
64104d94236SJiawen Wu sfp_dev = platform_device_register_full(&info);
64204d94236SJiawen Wu if (IS_ERR(sfp_dev))
64304d94236SJiawen Wu return PTR_ERR(sfp_dev);
64404d94236SJiawen Wu
64504d94236SJiawen Wu txgbe->sfp_dev = sfp_dev;
64604d94236SJiawen Wu
64704d94236SJiawen Wu return 0;
64804d94236SJiawen Wu }
64904d94236SJiawen Wu
txgbe_phy_read(struct mii_bus * bus,int phy_addr,int devnum,int regnum)65002b2a6f9SJiawen Wu static int txgbe_phy_read(struct mii_bus *bus, int phy_addr,
65102b2a6f9SJiawen Wu int devnum, int regnum)
65202b2a6f9SJiawen Wu {
65302b2a6f9SJiawen Wu struct wx *wx = bus->priv;
65402b2a6f9SJiawen Wu u32 val, command;
65502b2a6f9SJiawen Wu int ret;
65602b2a6f9SJiawen Wu
65702b2a6f9SJiawen Wu /* setup and write the address cycle command */
65802b2a6f9SJiawen Wu command = WX_MSCA_RA(regnum) |
65902b2a6f9SJiawen Wu WX_MSCA_PA(phy_addr) |
66002b2a6f9SJiawen Wu WX_MSCA_DA(devnum);
66102b2a6f9SJiawen Wu wr32(wx, WX_MSCA, command);
66202b2a6f9SJiawen Wu
66302b2a6f9SJiawen Wu command = WX_MSCC_CMD(WX_MSCA_CMD_READ) | WX_MSCC_BUSY;
66402b2a6f9SJiawen Wu wr32(wx, WX_MSCC, command);
66502b2a6f9SJiawen Wu
66602b2a6f9SJiawen Wu /* wait to complete */
66702b2a6f9SJiawen Wu ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000,
66802b2a6f9SJiawen Wu 100000, false, wx, WX_MSCC);
66902b2a6f9SJiawen Wu if (ret) {
67002b2a6f9SJiawen Wu wx_err(wx, "Mdio read c45 command did not complete.\n");
67102b2a6f9SJiawen Wu return ret;
67202b2a6f9SJiawen Wu }
67302b2a6f9SJiawen Wu
67402b2a6f9SJiawen Wu return (u16)rd32(wx, WX_MSCC);
67502b2a6f9SJiawen Wu }
67602b2a6f9SJiawen Wu
txgbe_phy_write(struct mii_bus * bus,int phy_addr,int devnum,int regnum,u16 value)67702b2a6f9SJiawen Wu static int txgbe_phy_write(struct mii_bus *bus, int phy_addr,
67802b2a6f9SJiawen Wu int devnum, int regnum, u16 value)
67902b2a6f9SJiawen Wu {
68002b2a6f9SJiawen Wu struct wx *wx = bus->priv;
68102b2a6f9SJiawen Wu int ret, command;
68202b2a6f9SJiawen Wu u16 val;
68302b2a6f9SJiawen Wu
68402b2a6f9SJiawen Wu /* setup and write the address cycle command */
68502b2a6f9SJiawen Wu command = WX_MSCA_RA(regnum) |
68602b2a6f9SJiawen Wu WX_MSCA_PA(phy_addr) |
68702b2a6f9SJiawen Wu WX_MSCA_DA(devnum);
68802b2a6f9SJiawen Wu wr32(wx, WX_MSCA, command);
68902b2a6f9SJiawen Wu
69002b2a6f9SJiawen Wu command = value | WX_MSCC_CMD(WX_MSCA_CMD_WRITE) | WX_MSCC_BUSY;
69102b2a6f9SJiawen Wu wr32(wx, WX_MSCC, command);
69202b2a6f9SJiawen Wu
69302b2a6f9SJiawen Wu /* wait to complete */
69402b2a6f9SJiawen Wu ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000,
69502b2a6f9SJiawen Wu 100000, false, wx, WX_MSCC);
69602b2a6f9SJiawen Wu if (ret)
69702b2a6f9SJiawen Wu wx_err(wx, "Mdio write c45 command did not complete.\n");
69802b2a6f9SJiawen Wu
69902b2a6f9SJiawen Wu return ret;
70002b2a6f9SJiawen Wu }
70102b2a6f9SJiawen Wu
txgbe_ext_phy_init(struct txgbe * txgbe)70202b2a6f9SJiawen Wu static int txgbe_ext_phy_init(struct txgbe *txgbe)
70302b2a6f9SJiawen Wu {
70402b2a6f9SJiawen Wu struct phy_device *phydev;
70502b2a6f9SJiawen Wu struct mii_bus *mii_bus;
70602b2a6f9SJiawen Wu struct pci_dev *pdev;
70702b2a6f9SJiawen Wu struct wx *wx;
70802b2a6f9SJiawen Wu int ret = 0;
70902b2a6f9SJiawen Wu
71002b2a6f9SJiawen Wu wx = txgbe->wx;
71102b2a6f9SJiawen Wu pdev = wx->pdev;
71202b2a6f9SJiawen Wu
71302b2a6f9SJiawen Wu mii_bus = devm_mdiobus_alloc(&pdev->dev);
71402b2a6f9SJiawen Wu if (!mii_bus)
71502b2a6f9SJiawen Wu return -ENOMEM;
71602b2a6f9SJiawen Wu
71702b2a6f9SJiawen Wu mii_bus->name = "txgbe_mii_bus";
71802b2a6f9SJiawen Wu mii_bus->read_c45 = &txgbe_phy_read;
71902b2a6f9SJiawen Wu mii_bus->write_c45 = &txgbe_phy_write;
72002b2a6f9SJiawen Wu mii_bus->parent = &pdev->dev;
72102b2a6f9SJiawen Wu mii_bus->phy_mask = GENMASK(31, 1);
72202b2a6f9SJiawen Wu mii_bus->priv = wx;
72302b2a6f9SJiawen Wu snprintf(mii_bus->id, MII_BUS_ID_SIZE, "txgbe-%x",
72402b2a6f9SJiawen Wu (pdev->bus->number << 8) | pdev->devfn);
72502b2a6f9SJiawen Wu
72602b2a6f9SJiawen Wu ret = devm_mdiobus_register(&pdev->dev, mii_bus);
72702b2a6f9SJiawen Wu if (ret) {
72802b2a6f9SJiawen Wu wx_err(wx, "failed to register MDIO bus: %d\n", ret);
72902b2a6f9SJiawen Wu return ret;
73002b2a6f9SJiawen Wu }
73102b2a6f9SJiawen Wu
73202b2a6f9SJiawen Wu phydev = phy_find_first(mii_bus);
73302b2a6f9SJiawen Wu if (!phydev) {
73402b2a6f9SJiawen Wu wx_err(wx, "no PHY found\n");
73502b2a6f9SJiawen Wu return -ENODEV;
73602b2a6f9SJiawen Wu }
73702b2a6f9SJiawen Wu
73802b2a6f9SJiawen Wu phy_attached_info(phydev);
73902b2a6f9SJiawen Wu
74002b2a6f9SJiawen Wu wx->link = 0;
74102b2a6f9SJiawen Wu wx->speed = 0;
74202b2a6f9SJiawen Wu wx->duplex = 0;
74302b2a6f9SJiawen Wu wx->phydev = phydev;
74402b2a6f9SJiawen Wu
74502b2a6f9SJiawen Wu ret = txgbe_phylink_init(txgbe);
74602b2a6f9SJiawen Wu if (ret) {
74702b2a6f9SJiawen Wu wx_err(wx, "failed to init phylink: %d\n", ret);
74802b2a6f9SJiawen Wu return ret;
74902b2a6f9SJiawen Wu }
75002b2a6f9SJiawen Wu
75102b2a6f9SJiawen Wu return 0;
75202b2a6f9SJiawen Wu }
75302b2a6f9SJiawen Wu
txgbe_init_phy(struct txgbe * txgbe)754c3e382adSJiawen Wu int txgbe_init_phy(struct txgbe *txgbe)
755c3e382adSJiawen Wu {
756c3e382adSJiawen Wu int ret;
757c3e382adSJiawen Wu
75802b2a6f9SJiawen Wu if (txgbe->wx->media_type == sp_media_copper)
75902b2a6f9SJiawen Wu return txgbe_ext_phy_init(txgbe);
76002b2a6f9SJiawen Wu
761c3e382adSJiawen Wu ret = txgbe_swnodes_register(txgbe);
762c3e382adSJiawen Wu if (ret) {
763c3e382adSJiawen Wu wx_err(txgbe->wx, "failed to register software nodes\n");
764c3e382adSJiawen Wu return ret;
765c3e382adSJiawen Wu }
766c3e382adSJiawen Wu
767854cace6SJiawen Wu ret = txgbe_mdio_pcs_init(txgbe);
768854cace6SJiawen Wu if (ret) {
769854cace6SJiawen Wu wx_err(txgbe->wx, "failed to init mdio pcs: %d\n", ret);
770854cace6SJiawen Wu goto err_unregister_swnode;
771854cace6SJiawen Wu }
772854cace6SJiawen Wu
77308f08f93SJiawen Wu ret = txgbe_phylink_init(txgbe);
77408f08f93SJiawen Wu if (ret) {
77508f08f93SJiawen Wu wx_err(txgbe->wx, "failed to init phylink\n");
77608f08f93SJiawen Wu goto err_destroy_xpcs;
77708f08f93SJiawen Wu }
77808f08f93SJiawen Wu
779b83c3731SJiawen Wu ret = txgbe_gpio_init(txgbe);
780b83c3731SJiawen Wu if (ret) {
781b83c3731SJiawen Wu wx_err(txgbe->wx, "failed to init gpio\n");
78208f08f93SJiawen Wu goto err_destroy_phylink;
783b83c3731SJiawen Wu }
784b83c3731SJiawen Wu
785b63f2048SJiawen Wu ret = txgbe_clock_register(txgbe);
786b63f2048SJiawen Wu if (ret) {
787b63f2048SJiawen Wu wx_err(txgbe->wx, "failed to register clock: %d\n", ret);
78808f08f93SJiawen Wu goto err_destroy_phylink;
789b63f2048SJiawen Wu }
790b63f2048SJiawen Wu
791c625e725SJiawen Wu ret = txgbe_i2c_register(txgbe);
792c625e725SJiawen Wu if (ret) {
793c625e725SJiawen Wu wx_err(txgbe->wx, "failed to init i2c interface: %d\n", ret);
794c625e725SJiawen Wu goto err_unregister_clk;
795c625e725SJiawen Wu }
796c625e725SJiawen Wu
79704d94236SJiawen Wu ret = txgbe_sfp_register(txgbe);
79804d94236SJiawen Wu if (ret) {
79904d94236SJiawen Wu wx_err(txgbe->wx, "failed to register sfp\n");
80004d94236SJiawen Wu goto err_unregister_i2c;
80104d94236SJiawen Wu }
80204d94236SJiawen Wu
803c3e382adSJiawen Wu return 0;
804b63f2048SJiawen Wu
80504d94236SJiawen Wu err_unregister_i2c:
80604d94236SJiawen Wu platform_device_unregister(txgbe->i2c_dev);
807c625e725SJiawen Wu err_unregister_clk:
808c625e725SJiawen Wu clkdev_drop(txgbe->clock);
809c625e725SJiawen Wu clk_unregister(txgbe->clk);
81008f08f93SJiawen Wu err_destroy_phylink:
81108f08f93SJiawen Wu phylink_destroy(txgbe->phylink);
812854cace6SJiawen Wu err_destroy_xpcs:
813854cace6SJiawen Wu xpcs_destroy(txgbe->xpcs);
814b63f2048SJiawen Wu err_unregister_swnode:
815b63f2048SJiawen Wu software_node_unregister_node_group(txgbe->nodes.group);
816b63f2048SJiawen Wu
817b63f2048SJiawen Wu return ret;
818c3e382adSJiawen Wu }
819c3e382adSJiawen Wu
txgbe_remove_phy(struct txgbe * txgbe)820c3e382adSJiawen Wu void txgbe_remove_phy(struct txgbe *txgbe)
821c3e382adSJiawen Wu {
82202b2a6f9SJiawen Wu if (txgbe->wx->media_type == sp_media_copper) {
82302b2a6f9SJiawen Wu phylink_disconnect_phy(txgbe->phylink);
82402b2a6f9SJiawen Wu phylink_destroy(txgbe->phylink);
82502b2a6f9SJiawen Wu return;
82602b2a6f9SJiawen Wu }
82702b2a6f9SJiawen Wu
82804d94236SJiawen Wu platform_device_unregister(txgbe->sfp_dev);
829c625e725SJiawen Wu platform_device_unregister(txgbe->i2c_dev);
830b63f2048SJiawen Wu clkdev_drop(txgbe->clock);
831b63f2048SJiawen Wu clk_unregister(txgbe->clk);
83208f08f93SJiawen Wu phylink_destroy(txgbe->phylink);
833854cace6SJiawen Wu xpcs_destroy(txgbe->xpcs);
834c3e382adSJiawen Wu software_node_unregister_node_group(txgbe->nodes.group);
835c3e382adSJiawen Wu }
836