1c3e382adSJiawen Wu // SPDX-License-Identifier: GPL-2.0 2c3e382adSJiawen Wu /* Copyright (c) 2015 - 2023 Beijing WangXun Technology Co., Ltd. */ 3c3e382adSJiawen Wu 4*b83c3731SJiawen Wu #include <linux/gpio/machine.h> 5*b83c3731SJiawen Wu #include <linux/gpio/driver.h> 6c3e382adSJiawen Wu #include <linux/gpio/property.h> 7b63f2048SJiawen Wu #include <linux/clk-provider.h> 8b63f2048SJiawen Wu #include <linux/clkdev.h> 9c3e382adSJiawen Wu #include <linux/i2c.h> 10c3e382adSJiawen Wu #include <linux/pci.h> 11c625e725SJiawen Wu #include <linux/platform_device.h> 12c625e725SJiawen Wu #include <linux/regmap.h> 13c3e382adSJiawen Wu 14c3e382adSJiawen Wu #include "../libwx/wx_type.h" 15*b83c3731SJiawen Wu #include "../libwx/wx_hw.h" 16c3e382adSJiawen Wu #include "txgbe_type.h" 17c3e382adSJiawen Wu #include "txgbe_phy.h" 18c3e382adSJiawen Wu 19c3e382adSJiawen Wu static int txgbe_swnodes_register(struct txgbe *txgbe) 20c3e382adSJiawen Wu { 21c3e382adSJiawen Wu struct txgbe_nodes *nodes = &txgbe->nodes; 22c3e382adSJiawen Wu struct pci_dev *pdev = txgbe->wx->pdev; 23c3e382adSJiawen Wu struct software_node *swnodes; 24c3e382adSJiawen Wu u32 id; 25c3e382adSJiawen Wu 26c3e382adSJiawen Wu id = (pdev->bus->number << 8) | pdev->devfn; 27c3e382adSJiawen Wu 28c3e382adSJiawen Wu snprintf(nodes->gpio_name, sizeof(nodes->gpio_name), "txgbe_gpio-%x", id); 29c3e382adSJiawen Wu snprintf(nodes->i2c_name, sizeof(nodes->i2c_name), "txgbe_i2c-%x", id); 30c3e382adSJiawen Wu snprintf(nodes->sfp_name, sizeof(nodes->sfp_name), "txgbe_sfp-%x", id); 31c3e382adSJiawen Wu snprintf(nodes->phylink_name, sizeof(nodes->phylink_name), "txgbe_phylink-%x", id); 32c3e382adSJiawen Wu 33c3e382adSJiawen Wu swnodes = nodes->swnodes; 34c3e382adSJiawen Wu 35c3e382adSJiawen Wu /* GPIO 0: tx fault 36c3e382adSJiawen Wu * GPIO 1: tx disable 37c3e382adSJiawen Wu * GPIO 2: sfp module absent 38c3e382adSJiawen Wu * GPIO 3: rx signal lost 39c3e382adSJiawen Wu * GPIO 4: rate select, 1G(0) 10G(1) 40c3e382adSJiawen Wu * GPIO 5: rate select, 1G(0) 10G(1) 41c3e382adSJiawen Wu */ 42c3e382adSJiawen Wu nodes->gpio_props[0] = PROPERTY_ENTRY_STRING("pinctrl-names", "default"); 43c3e382adSJiawen Wu swnodes[SWNODE_GPIO] = NODE_PROP(nodes->gpio_name, nodes->gpio_props); 44c3e382adSJiawen Wu nodes->gpio0_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 0, GPIO_ACTIVE_HIGH); 45c3e382adSJiawen Wu nodes->gpio1_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 1, GPIO_ACTIVE_HIGH); 46c3e382adSJiawen Wu nodes->gpio2_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 2, GPIO_ACTIVE_LOW); 47c3e382adSJiawen Wu nodes->gpio3_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 3, GPIO_ACTIVE_HIGH); 48c3e382adSJiawen Wu nodes->gpio4_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 4, GPIO_ACTIVE_HIGH); 49c3e382adSJiawen Wu nodes->gpio5_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 5, GPIO_ACTIVE_HIGH); 50c3e382adSJiawen Wu 51c3e382adSJiawen Wu nodes->i2c_props[0] = PROPERTY_ENTRY_STRING("compatible", "snps,designware-i2c"); 52c3e382adSJiawen Wu nodes->i2c_props[1] = PROPERTY_ENTRY_BOOL("wx,i2c-snps-model"); 53c3e382adSJiawen Wu nodes->i2c_props[2] = PROPERTY_ENTRY_U32("clock-frequency", I2C_MAX_STANDARD_MODE_FREQ); 54c3e382adSJiawen Wu swnodes[SWNODE_I2C] = NODE_PROP(nodes->i2c_name, nodes->i2c_props); 55c3e382adSJiawen Wu nodes->i2c_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_I2C]); 56c3e382adSJiawen Wu 57c3e382adSJiawen Wu nodes->sfp_props[0] = PROPERTY_ENTRY_STRING("compatible", "sff,sfp"); 58c3e382adSJiawen Wu nodes->sfp_props[1] = PROPERTY_ENTRY_REF_ARRAY("i2c-bus", nodes->i2c_ref); 59c3e382adSJiawen Wu nodes->sfp_props[2] = PROPERTY_ENTRY_REF_ARRAY("tx-fault-gpios", nodes->gpio0_ref); 60c3e382adSJiawen Wu nodes->sfp_props[3] = PROPERTY_ENTRY_REF_ARRAY("tx-disable-gpios", nodes->gpio1_ref); 61c3e382adSJiawen Wu nodes->sfp_props[4] = PROPERTY_ENTRY_REF_ARRAY("mod-def0-gpios", nodes->gpio2_ref); 62c3e382adSJiawen Wu nodes->sfp_props[5] = PROPERTY_ENTRY_REF_ARRAY("los-gpios", nodes->gpio3_ref); 63c3e382adSJiawen Wu nodes->sfp_props[6] = PROPERTY_ENTRY_REF_ARRAY("rate-select1-gpios", nodes->gpio4_ref); 64c3e382adSJiawen Wu nodes->sfp_props[7] = PROPERTY_ENTRY_REF_ARRAY("rate-select0-gpios", nodes->gpio5_ref); 65c3e382adSJiawen Wu swnodes[SWNODE_SFP] = NODE_PROP(nodes->sfp_name, nodes->sfp_props); 66c3e382adSJiawen Wu nodes->sfp_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_SFP]); 67c3e382adSJiawen Wu 68c3e382adSJiawen Wu nodes->phylink_props[0] = PROPERTY_ENTRY_STRING("managed", "in-band-status"); 69c3e382adSJiawen Wu nodes->phylink_props[1] = PROPERTY_ENTRY_REF_ARRAY("sfp", nodes->sfp_ref); 70c3e382adSJiawen Wu swnodes[SWNODE_PHYLINK] = NODE_PROP(nodes->phylink_name, nodes->phylink_props); 71c3e382adSJiawen Wu 72c3e382adSJiawen Wu nodes->group[SWNODE_GPIO] = &swnodes[SWNODE_GPIO]; 73c3e382adSJiawen Wu nodes->group[SWNODE_I2C] = &swnodes[SWNODE_I2C]; 74c3e382adSJiawen Wu nodes->group[SWNODE_SFP] = &swnodes[SWNODE_SFP]; 75c3e382adSJiawen Wu nodes->group[SWNODE_PHYLINK] = &swnodes[SWNODE_PHYLINK]; 76c3e382adSJiawen Wu 77c3e382adSJiawen Wu return software_node_register_node_group(nodes->group); 78c3e382adSJiawen Wu } 79c3e382adSJiawen Wu 80*b83c3731SJiawen Wu static int txgbe_gpio_get(struct gpio_chip *chip, unsigned int offset) 81*b83c3731SJiawen Wu { 82*b83c3731SJiawen Wu struct wx *wx = gpiochip_get_data(chip); 83*b83c3731SJiawen Wu int val; 84*b83c3731SJiawen Wu 85*b83c3731SJiawen Wu val = rd32m(wx, WX_GPIO_EXT, BIT(offset)); 86*b83c3731SJiawen Wu 87*b83c3731SJiawen Wu return !!(val & BIT(offset)); 88*b83c3731SJiawen Wu } 89*b83c3731SJiawen Wu 90*b83c3731SJiawen Wu static int txgbe_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 91*b83c3731SJiawen Wu { 92*b83c3731SJiawen Wu struct wx *wx = gpiochip_get_data(chip); 93*b83c3731SJiawen Wu u32 val; 94*b83c3731SJiawen Wu 95*b83c3731SJiawen Wu val = rd32(wx, WX_GPIO_DDR); 96*b83c3731SJiawen Wu if (BIT(offset) & val) 97*b83c3731SJiawen Wu return GPIO_LINE_DIRECTION_OUT; 98*b83c3731SJiawen Wu 99*b83c3731SJiawen Wu return GPIO_LINE_DIRECTION_IN; 100*b83c3731SJiawen Wu } 101*b83c3731SJiawen Wu 102*b83c3731SJiawen Wu static int txgbe_gpio_direction_in(struct gpio_chip *chip, unsigned int offset) 103*b83c3731SJiawen Wu { 104*b83c3731SJiawen Wu struct wx *wx = gpiochip_get_data(chip); 105*b83c3731SJiawen Wu unsigned long flags; 106*b83c3731SJiawen Wu 107*b83c3731SJiawen Wu raw_spin_lock_irqsave(&wx->gpio_lock, flags); 108*b83c3731SJiawen Wu wr32m(wx, WX_GPIO_DDR, BIT(offset), 0); 109*b83c3731SJiawen Wu raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 110*b83c3731SJiawen Wu 111*b83c3731SJiawen Wu return 0; 112*b83c3731SJiawen Wu } 113*b83c3731SJiawen Wu 114*b83c3731SJiawen Wu static int txgbe_gpio_direction_out(struct gpio_chip *chip, unsigned int offset, 115*b83c3731SJiawen Wu int val) 116*b83c3731SJiawen Wu { 117*b83c3731SJiawen Wu struct wx *wx = gpiochip_get_data(chip); 118*b83c3731SJiawen Wu unsigned long flags; 119*b83c3731SJiawen Wu u32 set; 120*b83c3731SJiawen Wu 121*b83c3731SJiawen Wu set = val ? BIT(offset) : 0; 122*b83c3731SJiawen Wu 123*b83c3731SJiawen Wu raw_spin_lock_irqsave(&wx->gpio_lock, flags); 124*b83c3731SJiawen Wu wr32m(wx, WX_GPIO_DR, BIT(offset), set); 125*b83c3731SJiawen Wu wr32m(wx, WX_GPIO_DDR, BIT(offset), BIT(offset)); 126*b83c3731SJiawen Wu raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 127*b83c3731SJiawen Wu 128*b83c3731SJiawen Wu return 0; 129*b83c3731SJiawen Wu } 130*b83c3731SJiawen Wu 131*b83c3731SJiawen Wu static void txgbe_gpio_irq_ack(struct irq_data *d) 132*b83c3731SJiawen Wu { 133*b83c3731SJiawen Wu struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 134*b83c3731SJiawen Wu irq_hw_number_t hwirq = irqd_to_hwirq(d); 135*b83c3731SJiawen Wu struct wx *wx = gpiochip_get_data(gc); 136*b83c3731SJiawen Wu unsigned long flags; 137*b83c3731SJiawen Wu 138*b83c3731SJiawen Wu raw_spin_lock_irqsave(&wx->gpio_lock, flags); 139*b83c3731SJiawen Wu wr32(wx, WX_GPIO_EOI, BIT(hwirq)); 140*b83c3731SJiawen Wu raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 141*b83c3731SJiawen Wu } 142*b83c3731SJiawen Wu 143*b83c3731SJiawen Wu static void txgbe_gpio_irq_mask(struct irq_data *d) 144*b83c3731SJiawen Wu { 145*b83c3731SJiawen Wu struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 146*b83c3731SJiawen Wu irq_hw_number_t hwirq = irqd_to_hwirq(d); 147*b83c3731SJiawen Wu struct wx *wx = gpiochip_get_data(gc); 148*b83c3731SJiawen Wu unsigned long flags; 149*b83c3731SJiawen Wu 150*b83c3731SJiawen Wu gpiochip_disable_irq(gc, hwirq); 151*b83c3731SJiawen Wu 152*b83c3731SJiawen Wu raw_spin_lock_irqsave(&wx->gpio_lock, flags); 153*b83c3731SJiawen Wu wr32m(wx, WX_GPIO_INTMASK, BIT(hwirq), BIT(hwirq)); 154*b83c3731SJiawen Wu raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 155*b83c3731SJiawen Wu } 156*b83c3731SJiawen Wu 157*b83c3731SJiawen Wu static void txgbe_gpio_irq_unmask(struct irq_data *d) 158*b83c3731SJiawen Wu { 159*b83c3731SJiawen Wu struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 160*b83c3731SJiawen Wu irq_hw_number_t hwirq = irqd_to_hwirq(d); 161*b83c3731SJiawen Wu struct wx *wx = gpiochip_get_data(gc); 162*b83c3731SJiawen Wu unsigned long flags; 163*b83c3731SJiawen Wu 164*b83c3731SJiawen Wu gpiochip_enable_irq(gc, hwirq); 165*b83c3731SJiawen Wu 166*b83c3731SJiawen Wu raw_spin_lock_irqsave(&wx->gpio_lock, flags); 167*b83c3731SJiawen Wu wr32m(wx, WX_GPIO_INTMASK, BIT(hwirq), 0); 168*b83c3731SJiawen Wu raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 169*b83c3731SJiawen Wu } 170*b83c3731SJiawen Wu 171*b83c3731SJiawen Wu static void txgbe_toggle_trigger(struct gpio_chip *gc, unsigned int offset) 172*b83c3731SJiawen Wu { 173*b83c3731SJiawen Wu struct wx *wx = gpiochip_get_data(gc); 174*b83c3731SJiawen Wu u32 pol, val; 175*b83c3731SJiawen Wu 176*b83c3731SJiawen Wu pol = rd32(wx, WX_GPIO_POLARITY); 177*b83c3731SJiawen Wu val = rd32(wx, WX_GPIO_EXT); 178*b83c3731SJiawen Wu 179*b83c3731SJiawen Wu if (val & BIT(offset)) 180*b83c3731SJiawen Wu pol &= ~BIT(offset); 181*b83c3731SJiawen Wu else 182*b83c3731SJiawen Wu pol |= BIT(offset); 183*b83c3731SJiawen Wu 184*b83c3731SJiawen Wu wr32(wx, WX_GPIO_POLARITY, pol); 185*b83c3731SJiawen Wu } 186*b83c3731SJiawen Wu 187*b83c3731SJiawen Wu static int txgbe_gpio_set_type(struct irq_data *d, unsigned int type) 188*b83c3731SJiawen Wu { 189*b83c3731SJiawen Wu struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 190*b83c3731SJiawen Wu irq_hw_number_t hwirq = irqd_to_hwirq(d); 191*b83c3731SJiawen Wu struct wx *wx = gpiochip_get_data(gc); 192*b83c3731SJiawen Wu u32 level, polarity, mask; 193*b83c3731SJiawen Wu unsigned long flags; 194*b83c3731SJiawen Wu 195*b83c3731SJiawen Wu mask = BIT(hwirq); 196*b83c3731SJiawen Wu 197*b83c3731SJiawen Wu if (type & IRQ_TYPE_LEVEL_MASK) { 198*b83c3731SJiawen Wu level = 0; 199*b83c3731SJiawen Wu irq_set_handler_locked(d, handle_level_irq); 200*b83c3731SJiawen Wu } else { 201*b83c3731SJiawen Wu level = mask; 202*b83c3731SJiawen Wu irq_set_handler_locked(d, handle_edge_irq); 203*b83c3731SJiawen Wu } 204*b83c3731SJiawen Wu 205*b83c3731SJiawen Wu if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) 206*b83c3731SJiawen Wu polarity = mask; 207*b83c3731SJiawen Wu else 208*b83c3731SJiawen Wu polarity = 0; 209*b83c3731SJiawen Wu 210*b83c3731SJiawen Wu raw_spin_lock_irqsave(&wx->gpio_lock, flags); 211*b83c3731SJiawen Wu 212*b83c3731SJiawen Wu wr32m(wx, WX_GPIO_INTEN, mask, mask); 213*b83c3731SJiawen Wu wr32m(wx, WX_GPIO_INTTYPE_LEVEL, mask, level); 214*b83c3731SJiawen Wu if (type == IRQ_TYPE_EDGE_BOTH) 215*b83c3731SJiawen Wu txgbe_toggle_trigger(gc, hwirq); 216*b83c3731SJiawen Wu else 217*b83c3731SJiawen Wu wr32m(wx, WX_GPIO_POLARITY, mask, polarity); 218*b83c3731SJiawen Wu 219*b83c3731SJiawen Wu raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 220*b83c3731SJiawen Wu 221*b83c3731SJiawen Wu return 0; 222*b83c3731SJiawen Wu } 223*b83c3731SJiawen Wu 224*b83c3731SJiawen Wu static const struct irq_chip txgbe_gpio_irq_chip = { 225*b83c3731SJiawen Wu .name = "txgbe_gpio_irq", 226*b83c3731SJiawen Wu .irq_ack = txgbe_gpio_irq_ack, 227*b83c3731SJiawen Wu .irq_mask = txgbe_gpio_irq_mask, 228*b83c3731SJiawen Wu .irq_unmask = txgbe_gpio_irq_unmask, 229*b83c3731SJiawen Wu .irq_set_type = txgbe_gpio_set_type, 230*b83c3731SJiawen Wu .flags = IRQCHIP_IMMUTABLE, 231*b83c3731SJiawen Wu GPIOCHIP_IRQ_RESOURCE_HELPERS, 232*b83c3731SJiawen Wu }; 233*b83c3731SJiawen Wu 234*b83c3731SJiawen Wu static void txgbe_irq_handler(struct irq_desc *desc) 235*b83c3731SJiawen Wu { 236*b83c3731SJiawen Wu struct irq_chip *chip = irq_desc_get_chip(desc); 237*b83c3731SJiawen Wu struct wx *wx = irq_desc_get_handler_data(desc); 238*b83c3731SJiawen Wu struct txgbe *txgbe = wx->priv; 239*b83c3731SJiawen Wu irq_hw_number_t hwirq; 240*b83c3731SJiawen Wu unsigned long gpioirq; 241*b83c3731SJiawen Wu struct gpio_chip *gc; 242*b83c3731SJiawen Wu unsigned long flags; 243*b83c3731SJiawen Wu 244*b83c3731SJiawen Wu chained_irq_enter(chip, desc); 245*b83c3731SJiawen Wu 246*b83c3731SJiawen Wu gpioirq = rd32(wx, WX_GPIO_INTSTATUS); 247*b83c3731SJiawen Wu 248*b83c3731SJiawen Wu gc = txgbe->gpio; 249*b83c3731SJiawen Wu for_each_set_bit(hwirq, &gpioirq, gc->ngpio) { 250*b83c3731SJiawen Wu int gpio = irq_find_mapping(gc->irq.domain, hwirq); 251*b83c3731SJiawen Wu u32 irq_type = irq_get_trigger_type(gpio); 252*b83c3731SJiawen Wu 253*b83c3731SJiawen Wu generic_handle_domain_irq(gc->irq.domain, hwirq); 254*b83c3731SJiawen Wu 255*b83c3731SJiawen Wu if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 256*b83c3731SJiawen Wu raw_spin_lock_irqsave(&wx->gpio_lock, flags); 257*b83c3731SJiawen Wu txgbe_toggle_trigger(gc, hwirq); 258*b83c3731SJiawen Wu raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 259*b83c3731SJiawen Wu } 260*b83c3731SJiawen Wu } 261*b83c3731SJiawen Wu 262*b83c3731SJiawen Wu chained_irq_exit(chip, desc); 263*b83c3731SJiawen Wu 264*b83c3731SJiawen Wu /* unmask interrupt */ 265*b83c3731SJiawen Wu wx_intr_enable(wx, TXGBE_INTR_MISC(wx)); 266*b83c3731SJiawen Wu } 267*b83c3731SJiawen Wu 268*b83c3731SJiawen Wu static int txgbe_gpio_init(struct txgbe *txgbe) 269*b83c3731SJiawen Wu { 270*b83c3731SJiawen Wu struct gpio_irq_chip *girq; 271*b83c3731SJiawen Wu struct gpio_chip *gc; 272*b83c3731SJiawen Wu struct device *dev; 273*b83c3731SJiawen Wu struct wx *wx; 274*b83c3731SJiawen Wu int ret; 275*b83c3731SJiawen Wu 276*b83c3731SJiawen Wu wx = txgbe->wx; 277*b83c3731SJiawen Wu dev = &wx->pdev->dev; 278*b83c3731SJiawen Wu 279*b83c3731SJiawen Wu raw_spin_lock_init(&wx->gpio_lock); 280*b83c3731SJiawen Wu 281*b83c3731SJiawen Wu gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 282*b83c3731SJiawen Wu if (!gc) 283*b83c3731SJiawen Wu return -ENOMEM; 284*b83c3731SJiawen Wu 285*b83c3731SJiawen Wu gc->label = devm_kasprintf(dev, GFP_KERNEL, "txgbe_gpio-%x", 286*b83c3731SJiawen Wu (wx->pdev->bus->number << 8) | wx->pdev->devfn); 287*b83c3731SJiawen Wu if (!gc->label) 288*b83c3731SJiawen Wu return -ENOMEM; 289*b83c3731SJiawen Wu 290*b83c3731SJiawen Wu gc->base = -1; 291*b83c3731SJiawen Wu gc->ngpio = 6; 292*b83c3731SJiawen Wu gc->owner = THIS_MODULE; 293*b83c3731SJiawen Wu gc->parent = dev; 294*b83c3731SJiawen Wu gc->fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_GPIO]); 295*b83c3731SJiawen Wu gc->get = txgbe_gpio_get; 296*b83c3731SJiawen Wu gc->get_direction = txgbe_gpio_get_direction; 297*b83c3731SJiawen Wu gc->direction_input = txgbe_gpio_direction_in; 298*b83c3731SJiawen Wu gc->direction_output = txgbe_gpio_direction_out; 299*b83c3731SJiawen Wu 300*b83c3731SJiawen Wu girq = &gc->irq; 301*b83c3731SJiawen Wu gpio_irq_chip_set_chip(girq, &txgbe_gpio_irq_chip); 302*b83c3731SJiawen Wu girq->parent_handler = txgbe_irq_handler; 303*b83c3731SJiawen Wu girq->parent_handler_data = wx; 304*b83c3731SJiawen Wu girq->num_parents = 1; 305*b83c3731SJiawen Wu girq->parents = devm_kcalloc(dev, girq->num_parents, 306*b83c3731SJiawen Wu sizeof(*girq->parents), GFP_KERNEL); 307*b83c3731SJiawen Wu if (!girq->parents) 308*b83c3731SJiawen Wu return -ENOMEM; 309*b83c3731SJiawen Wu girq->parents[0] = wx->msix_entries[wx->num_q_vectors].vector; 310*b83c3731SJiawen Wu girq->default_type = IRQ_TYPE_NONE; 311*b83c3731SJiawen Wu girq->handler = handle_bad_irq; 312*b83c3731SJiawen Wu 313*b83c3731SJiawen Wu ret = devm_gpiochip_add_data(dev, gc, wx); 314*b83c3731SJiawen Wu if (ret) 315*b83c3731SJiawen Wu return ret; 316*b83c3731SJiawen Wu 317*b83c3731SJiawen Wu txgbe->gpio = gc; 318*b83c3731SJiawen Wu 319*b83c3731SJiawen Wu return 0; 320*b83c3731SJiawen Wu } 321*b83c3731SJiawen Wu 322b63f2048SJiawen Wu static int txgbe_clock_register(struct txgbe *txgbe) 323b63f2048SJiawen Wu { 324b63f2048SJiawen Wu struct pci_dev *pdev = txgbe->wx->pdev; 325b63f2048SJiawen Wu struct clk_lookup *clock; 326b63f2048SJiawen Wu char clk_name[32]; 327b63f2048SJiawen Wu struct clk *clk; 328b63f2048SJiawen Wu 329b63f2048SJiawen Wu snprintf(clk_name, sizeof(clk_name), "i2c_designware.%d", 330b63f2048SJiawen Wu (pdev->bus->number << 8) | pdev->devfn); 331b63f2048SJiawen Wu 332b63f2048SJiawen Wu clk = clk_register_fixed_rate(NULL, clk_name, NULL, 0, 156250000); 333b63f2048SJiawen Wu if (IS_ERR(clk)) 334b63f2048SJiawen Wu return PTR_ERR(clk); 335b63f2048SJiawen Wu 336b63f2048SJiawen Wu clock = clkdev_create(clk, NULL, clk_name); 337b63f2048SJiawen Wu if (!clock) { 338b63f2048SJiawen Wu clk_unregister(clk); 339b63f2048SJiawen Wu return -ENOMEM; 340b63f2048SJiawen Wu } 341b63f2048SJiawen Wu 342b63f2048SJiawen Wu txgbe->clk = clk; 343b63f2048SJiawen Wu txgbe->clock = clock; 344b63f2048SJiawen Wu 345b63f2048SJiawen Wu return 0; 346b63f2048SJiawen Wu } 347b63f2048SJiawen Wu 348c625e725SJiawen Wu static int txgbe_i2c_read(void *context, unsigned int reg, unsigned int *val) 349c625e725SJiawen Wu { 350c625e725SJiawen Wu struct wx *wx = context; 351c625e725SJiawen Wu 352c625e725SJiawen Wu *val = rd32(wx, reg + TXGBE_I2C_BASE); 353c625e725SJiawen Wu 354c625e725SJiawen Wu return 0; 355c625e725SJiawen Wu } 356c625e725SJiawen Wu 357c625e725SJiawen Wu static int txgbe_i2c_write(void *context, unsigned int reg, unsigned int val) 358c625e725SJiawen Wu { 359c625e725SJiawen Wu struct wx *wx = context; 360c625e725SJiawen Wu 361c625e725SJiawen Wu wr32(wx, reg + TXGBE_I2C_BASE, val); 362c625e725SJiawen Wu 363c625e725SJiawen Wu return 0; 364c625e725SJiawen Wu } 365c625e725SJiawen Wu 366c625e725SJiawen Wu static const struct regmap_config i2c_regmap_config = { 367c625e725SJiawen Wu .reg_bits = 32, 368c625e725SJiawen Wu .val_bits = 32, 369c625e725SJiawen Wu .reg_read = txgbe_i2c_read, 370c625e725SJiawen Wu .reg_write = txgbe_i2c_write, 371c625e725SJiawen Wu .fast_io = true, 372c625e725SJiawen Wu }; 373c625e725SJiawen Wu 374c625e725SJiawen Wu static int txgbe_i2c_register(struct txgbe *txgbe) 375c625e725SJiawen Wu { 376c625e725SJiawen Wu struct platform_device_info info = {}; 377c625e725SJiawen Wu struct platform_device *i2c_dev; 378c625e725SJiawen Wu struct regmap *i2c_regmap; 379c625e725SJiawen Wu struct pci_dev *pdev; 380c625e725SJiawen Wu struct wx *wx; 381c625e725SJiawen Wu 382c625e725SJiawen Wu wx = txgbe->wx; 383c625e725SJiawen Wu pdev = wx->pdev; 384c625e725SJiawen Wu i2c_regmap = devm_regmap_init(&pdev->dev, NULL, wx, &i2c_regmap_config); 385c625e725SJiawen Wu if (IS_ERR(i2c_regmap)) { 386c625e725SJiawen Wu wx_err(wx, "failed to init I2C regmap\n"); 387c625e725SJiawen Wu return PTR_ERR(i2c_regmap); 388c625e725SJiawen Wu } 389c625e725SJiawen Wu 390c625e725SJiawen Wu info.parent = &pdev->dev; 391c625e725SJiawen Wu info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_I2C]); 392c625e725SJiawen Wu info.name = "i2c_designware"; 393c625e725SJiawen Wu info.id = (pdev->bus->number << 8) | pdev->devfn; 394c625e725SJiawen Wu 395c625e725SJiawen Wu info.res = &DEFINE_RES_IRQ(pdev->irq); 396c625e725SJiawen Wu info.num_res = 1; 397c625e725SJiawen Wu i2c_dev = platform_device_register_full(&info); 398c625e725SJiawen Wu if (IS_ERR(i2c_dev)) 399c625e725SJiawen Wu return PTR_ERR(i2c_dev); 400c625e725SJiawen Wu 401c625e725SJiawen Wu txgbe->i2c_dev = i2c_dev; 402c625e725SJiawen Wu 403c625e725SJiawen Wu return 0; 404c625e725SJiawen Wu } 405c625e725SJiawen Wu 40604d94236SJiawen Wu static int txgbe_sfp_register(struct txgbe *txgbe) 40704d94236SJiawen Wu { 40804d94236SJiawen Wu struct pci_dev *pdev = txgbe->wx->pdev; 40904d94236SJiawen Wu struct platform_device_info info = {}; 41004d94236SJiawen Wu struct platform_device *sfp_dev; 41104d94236SJiawen Wu 41204d94236SJiawen Wu info.parent = &pdev->dev; 41304d94236SJiawen Wu info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_SFP]); 41404d94236SJiawen Wu info.name = "sfp"; 41504d94236SJiawen Wu info.id = (pdev->bus->number << 8) | pdev->devfn; 41604d94236SJiawen Wu sfp_dev = platform_device_register_full(&info); 41704d94236SJiawen Wu if (IS_ERR(sfp_dev)) 41804d94236SJiawen Wu return PTR_ERR(sfp_dev); 41904d94236SJiawen Wu 42004d94236SJiawen Wu txgbe->sfp_dev = sfp_dev; 42104d94236SJiawen Wu 42204d94236SJiawen Wu return 0; 42304d94236SJiawen Wu } 42404d94236SJiawen Wu 425c3e382adSJiawen Wu int txgbe_init_phy(struct txgbe *txgbe) 426c3e382adSJiawen Wu { 427c3e382adSJiawen Wu int ret; 428c3e382adSJiawen Wu 429c3e382adSJiawen Wu ret = txgbe_swnodes_register(txgbe); 430c3e382adSJiawen Wu if (ret) { 431c3e382adSJiawen Wu wx_err(txgbe->wx, "failed to register software nodes\n"); 432c3e382adSJiawen Wu return ret; 433c3e382adSJiawen Wu } 434c3e382adSJiawen Wu 435*b83c3731SJiawen Wu ret = txgbe_gpio_init(txgbe); 436*b83c3731SJiawen Wu if (ret) { 437*b83c3731SJiawen Wu wx_err(txgbe->wx, "failed to init gpio\n"); 438*b83c3731SJiawen Wu goto err_unregister_swnode; 439*b83c3731SJiawen Wu } 440*b83c3731SJiawen Wu 441b63f2048SJiawen Wu ret = txgbe_clock_register(txgbe); 442b63f2048SJiawen Wu if (ret) { 443b63f2048SJiawen Wu wx_err(txgbe->wx, "failed to register clock: %d\n", ret); 444b63f2048SJiawen Wu goto err_unregister_swnode; 445b63f2048SJiawen Wu } 446b63f2048SJiawen Wu 447c625e725SJiawen Wu ret = txgbe_i2c_register(txgbe); 448c625e725SJiawen Wu if (ret) { 449c625e725SJiawen Wu wx_err(txgbe->wx, "failed to init i2c interface: %d\n", ret); 450c625e725SJiawen Wu goto err_unregister_clk; 451c625e725SJiawen Wu } 452c625e725SJiawen Wu 45304d94236SJiawen Wu ret = txgbe_sfp_register(txgbe); 45404d94236SJiawen Wu if (ret) { 45504d94236SJiawen Wu wx_err(txgbe->wx, "failed to register sfp\n"); 45604d94236SJiawen Wu goto err_unregister_i2c; 45704d94236SJiawen Wu } 45804d94236SJiawen Wu 459c3e382adSJiawen Wu return 0; 460b63f2048SJiawen Wu 46104d94236SJiawen Wu err_unregister_i2c: 46204d94236SJiawen Wu platform_device_unregister(txgbe->i2c_dev); 463c625e725SJiawen Wu err_unregister_clk: 464c625e725SJiawen Wu clkdev_drop(txgbe->clock); 465c625e725SJiawen Wu clk_unregister(txgbe->clk); 466b63f2048SJiawen Wu err_unregister_swnode: 467b63f2048SJiawen Wu software_node_unregister_node_group(txgbe->nodes.group); 468b63f2048SJiawen Wu 469b63f2048SJiawen Wu return ret; 470c3e382adSJiawen Wu } 471c3e382adSJiawen Wu 472c3e382adSJiawen Wu void txgbe_remove_phy(struct txgbe *txgbe) 473c3e382adSJiawen Wu { 47404d94236SJiawen Wu platform_device_unregister(txgbe->sfp_dev); 475c625e725SJiawen Wu platform_device_unregister(txgbe->i2c_dev); 476b63f2048SJiawen Wu clkdev_drop(txgbe->clock); 477b63f2048SJiawen Wu clk_unregister(txgbe->clk); 478c3e382adSJiawen Wu software_node_unregister_node_group(txgbe->nodes.group); 479c3e382adSJiawen Wu } 480