1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #ifndef _NGBE_TYPE_H_ 5 #define _NGBE_TYPE_H_ 6 7 #include <linux/types.h> 8 #include <linux/netdevice.h> 9 10 /************ NGBE_register.h ************/ 11 /* Device IDs */ 12 #define NGBE_DEV_ID_EM_WX1860AL_W 0x0100 13 #define NGBE_DEV_ID_EM_WX1860A2 0x0101 14 #define NGBE_DEV_ID_EM_WX1860A2S 0x0102 15 #define NGBE_DEV_ID_EM_WX1860A4 0x0103 16 #define NGBE_DEV_ID_EM_WX1860A4S 0x0104 17 #define NGBE_DEV_ID_EM_WX1860AL2 0x0105 18 #define NGBE_DEV_ID_EM_WX1860AL2S 0x0106 19 #define NGBE_DEV_ID_EM_WX1860AL4 0x0107 20 #define NGBE_DEV_ID_EM_WX1860AL4S 0x0108 21 #define NGBE_DEV_ID_EM_WX1860LC 0x0109 22 #define NGBE_DEV_ID_EM_WX1860A1 0x010a 23 #define NGBE_DEV_ID_EM_WX1860A1L 0x010b 24 25 /* Subsystem ID */ 26 #define NGBE_SUBID_M88E1512_SFP 0x0003 27 #define NGBE_SUBID_OCP_CARD 0x0040 28 #define NGBE_SUBID_LY_M88E1512_SFP 0x0050 29 #define NGBE_SUBID_M88E1512_RJ45 0x0051 30 #define NGBE_SUBID_M88E1512_MIX 0x0052 31 #define NGBE_SUBID_YT8521S_SFP 0x0060 32 #define NGBE_SUBID_INTERNAL_YT8521S_SFP 0x0061 33 #define NGBE_SUBID_YT8521S_SFP_GPIO 0x0062 34 #define NGBE_SUBID_INTERNAL_YT8521S_SFP_GPIO 0x0064 35 #define NGBE_SUBID_LY_YT8521S_SFP 0x0070 36 #define NGBE_SUBID_RGMII_FPGA 0x0080 37 38 #define NGBE_OEM_MASK 0x00FF 39 40 #define NGBE_NCSI_SUP 0x8000 41 #define NGBE_NCSI_MASK 0x8000 42 #define NGBE_WOL_SUP 0x4000 43 #define NGBE_WOL_MASK 0x4000 44 45 /**************** EM Registers ****************************/ 46 /* chip control Registers */ 47 #define NGBE_MIS_PRB_CTL 0x10010 48 /* FMGR Registers */ 49 #define NGBE_SPI_ILDR_STATUS 0x10120 50 #define NGBE_SPI_ILDR_STATUS_PERST BIT(0) /* PCIE_PERST is done */ 51 #define NGBE_SPI_ILDR_STATUS_PWRRST BIT(1) /* Power on reset is done */ 52 #define NGBE_SPI_ILDR_STATUS_LAN_SW_RST(_i) BIT((_i) + 9) /* lan soft reset done */ 53 54 /* Checksum and EEPROM pointers */ 55 #define NGBE_CALSUM_COMMAND 0xE9 56 #define NGBE_CALSUM_CAP_STATUS 0x10224 57 #define NGBE_EEPROM_VERSION_STORE_REG 0x1022C 58 #define NGBE_SAN_MAC_ADDR_PTR 0x18 59 #define NGBE_DEVICE_CAPS 0x1C 60 #define NGBE_EEPROM_VERSION_L 0x1D 61 #define NGBE_EEPROM_VERSION_H 0x1E 62 63 /* mdio access */ 64 #define NGBE_MSCA 0x11200 65 #define NGBE_MSCA_RA(v) ((0xFFFF & (v))) 66 #define NGBE_MSCA_PA(v) ((0x1F & (v)) << 16) 67 #define NGBE_MSCA_DA(v) ((0x1F & (v)) << 21) 68 #define NGBE_MSCC 0x11204 69 #define NGBE_MSCC_DATA(v) ((0xFFFF & (v))) 70 #define NGBE_MSCC_CMD(v) ((0x3 & (v)) << 16) 71 72 enum NGBE_MSCA_CMD_value { 73 NGBE_MSCA_CMD_RSV = 0, 74 NGBE_MSCA_CMD_WRITE, 75 NGBE_MSCA_CMD_POST_READ, 76 NGBE_MSCA_CMD_READ, 77 }; 78 79 #define NGBE_MSCC_SADDR BIT(18) 80 #define NGBE_MSCC_BUSY BIT(22) 81 #define NGBE_MDIO_CLK(v) ((0x7 & (v)) << 19) 82 83 /* Media-dependent registers. */ 84 #define NGBE_MDIO_CLAUSE_SELECT 0x11220 85 86 /* GPIO Registers */ 87 #define NGBE_GPIO_DR 0x14800 88 #define NGBE_GPIO_DDR 0x14804 89 /*GPIO bit */ 90 #define NGBE_GPIO_DR_0 BIT(0) /* SDP0 Data Value */ 91 #define NGBE_GPIO_DR_1 BIT(1) /* SDP1 Data Value */ 92 #define NGBE_GPIO_DDR_0 BIT(0) /* SDP0 IO direction */ 93 #define NGBE_GPIO_DDR_1 BIT(1) /* SDP1 IO direction */ 94 95 #define NGBE_PHY_CONFIG(reg_offset) (0x14000 + ((reg_offset) * 4)) 96 #define NGBE_CFG_LAN_SPEED 0x14440 97 #define NGBE_CFG_PORT_ST 0x14404 98 99 /* Wake up registers */ 100 #define NGBE_PSR_WKUP_CTL 0x15B80 101 /* Wake Up Filter Control Bit */ 102 #define NGBE_PSR_WKUP_CTL_LNKC BIT(0) /* Link Status Change Wakeup Enable*/ 103 #define NGBE_PSR_WKUP_CTL_MAG BIT(1) /* Magic Packet Wakeup Enable */ 104 #define NGBE_PSR_WKUP_CTL_EX BIT(2) /* Directed Exact Wakeup Enable */ 105 #define NGBE_PSR_WKUP_CTL_MC BIT(3) /* Directed Multicast Wakeup Enable*/ 106 #define NGBE_PSR_WKUP_CTL_BC BIT(4) /* Broadcast Wakeup Enable */ 107 #define NGBE_PSR_WKUP_CTL_ARP BIT(5) /* ARP Request Packet Wakeup Enable*/ 108 #define NGBE_PSR_WKUP_CTL_IPV4 BIT(6) /* Directed IPv4 Pkt Wakeup Enable */ 109 #define NGBE_PSR_WKUP_CTL_IPV6 BIT(7) /* Directed IPv6 Pkt Wakeup Enable */ 110 111 #define NGBE_FW_EEPROM_CHECKSUM_CMD 0xE9 112 #define NGBE_FW_NVM_DATA_OFFSET 3 113 #define NGBE_FW_CMD_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ 114 #define NGBE_FW_CMD_ST_PASS 0x80658383 115 #define NGBE_FW_CMD_ST_FAIL 0x70657376 116 117 #define NGBE_MAX_FDIR_INDICES 7 118 119 #define NGBE_MAX_RX_QUEUES (NGBE_MAX_FDIR_INDICES + 1) 120 #define NGBE_MAX_TX_QUEUES (NGBE_MAX_FDIR_INDICES + 1) 121 122 #define NGBE_ETH_LENGTH_OF_ADDRESS 6 123 #define NGBE_MAX_MSIX_VECTORS 0x09 124 #define NGBE_RAR_ENTRIES 32 125 126 /* TX/RX descriptor defines */ 127 #define NGBE_DEFAULT_TXD 512 /* default ring size */ 128 #define NGBE_DEFAULT_TX_WORK 256 129 #define NGBE_MAX_TXD 8192 130 #define NGBE_MIN_TXD 128 131 132 #define NGBE_DEFAULT_RXD 512 /* default ring size */ 133 #define NGBE_DEFAULT_RX_WORK 256 134 #define NGBE_MAX_RXD 8192 135 #define NGBE_MIN_RXD 128 136 137 extern char ngbe_driver_name[]; 138 139 #endif /* _NGBE_TYPE_H_ */ 140