1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #ifndef _NGBE_TYPE_H_ 5 #define _NGBE_TYPE_H_ 6 7 #include <linux/types.h> 8 #include <linux/netdevice.h> 9 10 /************ NGBE_register.h ************/ 11 /* Device IDs */ 12 #define NGBE_DEV_ID_EM_WX1860AL_W 0x0100 13 #define NGBE_DEV_ID_EM_WX1860A2 0x0101 14 #define NGBE_DEV_ID_EM_WX1860A2S 0x0102 15 #define NGBE_DEV_ID_EM_WX1860A4 0x0103 16 #define NGBE_DEV_ID_EM_WX1860A4S 0x0104 17 #define NGBE_DEV_ID_EM_WX1860AL2 0x0105 18 #define NGBE_DEV_ID_EM_WX1860AL2S 0x0106 19 #define NGBE_DEV_ID_EM_WX1860AL4 0x0107 20 #define NGBE_DEV_ID_EM_WX1860AL4S 0x0108 21 #define NGBE_DEV_ID_EM_WX1860LC 0x0109 22 #define NGBE_DEV_ID_EM_WX1860A1 0x010a 23 #define NGBE_DEV_ID_EM_WX1860A1L 0x010b 24 25 /* Subsystem ID */ 26 #define NGBE_SUBID_M88E1512_SFP 0x0003 27 #define NGBE_SUBID_OCP_CARD 0x0040 28 #define NGBE_SUBID_LY_M88E1512_SFP 0x0050 29 #define NGBE_SUBID_M88E1512_RJ45 0x0051 30 #define NGBE_SUBID_M88E1512_MIX 0x0052 31 #define NGBE_SUBID_YT8521S_SFP 0x0060 32 #define NGBE_SUBID_INTERNAL_YT8521S_SFP 0x0061 33 #define NGBE_SUBID_YT8521S_SFP_GPIO 0x0062 34 #define NGBE_SUBID_INTERNAL_YT8521S_SFP_GPIO 0x0064 35 #define NGBE_SUBID_LY_YT8521S_SFP 0x0070 36 #define NGBE_SUBID_RGMII_FPGA 0x0080 37 38 #define NGBE_OEM_MASK 0x00FF 39 40 #define NGBE_NCSI_SUP 0x8000 41 #define NGBE_NCSI_MASK 0x8000 42 #define NGBE_WOL_SUP 0x4000 43 #define NGBE_WOL_MASK 0x4000 44 45 /**************** EM Registers ****************************/ 46 /* chip control Registers */ 47 #define NGBE_MIS_PRB_CTL 0x10010 48 /* FMGR Registers */ 49 #define NGBE_SPI_ILDR_STATUS 0x10120 50 #define NGBE_SPI_ILDR_STATUS_PERST BIT(0) /* PCIE_PERST is done */ 51 #define NGBE_SPI_ILDR_STATUS_PWRRST BIT(1) /* Power on reset is done */ 52 #define NGBE_SPI_ILDR_STATUS_LAN_SW_RST(_i) BIT((_i) + 9) /* lan soft reset done */ 53 54 /* Checksum and EEPROM pointers */ 55 #define NGBE_CALSUM_COMMAND 0xE9 56 #define NGBE_CALSUM_CAP_STATUS 0x10224 57 #define NGBE_EEPROM_VERSION_STORE_REG 0x1022C 58 #define NGBE_SAN_MAC_ADDR_PTR 0x18 59 #define NGBE_DEVICE_CAPS 0x1C 60 #define NGBE_EEPROM_VERSION_L 0x1D 61 #define NGBE_EEPROM_VERSION_H 0x1E 62 63 /* Media-dependent registers. */ 64 #define NGBE_MDIO_CLAUSE_SELECT 0x11220 65 66 /* GPIO Registers */ 67 #define NGBE_GPIO_DR 0x14800 68 #define NGBE_GPIO_DDR 0x14804 69 /*GPIO bit */ 70 #define NGBE_GPIO_DR_0 BIT(0) /* SDP0 Data Value */ 71 #define NGBE_GPIO_DR_1 BIT(1) /* SDP1 Data Value */ 72 #define NGBE_GPIO_DDR_0 BIT(0) /* SDP0 IO direction */ 73 #define NGBE_GPIO_DDR_1 BIT(1) /* SDP1 IO direction */ 74 75 /* Wake up registers */ 76 #define NGBE_PSR_WKUP_CTL 0x15B80 77 /* Wake Up Filter Control Bit */ 78 #define NGBE_PSR_WKUP_CTL_LNKC BIT(0) /* Link Status Change Wakeup Enable*/ 79 #define NGBE_PSR_WKUP_CTL_MAG BIT(1) /* Magic Packet Wakeup Enable */ 80 #define NGBE_PSR_WKUP_CTL_EX BIT(2) /* Directed Exact Wakeup Enable */ 81 #define NGBE_PSR_WKUP_CTL_MC BIT(3) /* Directed Multicast Wakeup Enable*/ 82 #define NGBE_PSR_WKUP_CTL_BC BIT(4) /* Broadcast Wakeup Enable */ 83 #define NGBE_PSR_WKUP_CTL_ARP BIT(5) /* ARP Request Packet Wakeup Enable*/ 84 #define NGBE_PSR_WKUP_CTL_IPV4 BIT(6) /* Directed IPv4 Pkt Wakeup Enable */ 85 #define NGBE_PSR_WKUP_CTL_IPV6 BIT(7) /* Directed IPv6 Pkt Wakeup Enable */ 86 87 #define NGBE_FW_EEPROM_CHECKSUM_CMD 0xE9 88 #define NGBE_FW_NVM_DATA_OFFSET 3 89 #define NGBE_FW_CMD_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ 90 #define NGBE_FW_CMD_ST_PASS 0x80658383 91 #define NGBE_FW_CMD_ST_FAIL 0x70657376 92 93 enum ngbe_phy_type { 94 ngbe_phy_unknown = 0, 95 ngbe_phy_none, 96 ngbe_phy_internal, 97 ngbe_phy_m88e1512, 98 ngbe_phy_m88e1512_sfi, 99 ngbe_phy_m88e1512_unknown, 100 ngbe_phy_yt8521s, 101 ngbe_phy_yt8521s_sfi, 102 ngbe_phy_internal_yt8521s_sfi, 103 ngbe_phy_generic 104 }; 105 106 enum ngbe_media_type { 107 ngbe_media_type_unknown = 0, 108 ngbe_media_type_fiber, 109 ngbe_media_type_copper, 110 ngbe_media_type_backplane, 111 }; 112 113 enum ngbe_mac_type { 114 ngbe_mac_type_unknown = 0, 115 ngbe_mac_type_mdi, 116 ngbe_mac_type_rgmii 117 }; 118 119 struct ngbe_phy_info { 120 enum ngbe_phy_type type; 121 enum ngbe_media_type media_type; 122 123 u32 addr; 124 u32 id; 125 126 bool reset_if_overtemp; 127 128 }; 129 130 struct ngbe_mac_addr { 131 u8 addr[ETH_ALEN]; 132 u16 state; /* bitmask */ 133 u64 pools; 134 }; 135 136 /* board specific private data structure */ 137 struct ngbe_adapter { 138 u8 __iomem *io_addr; /* Mainly for iounmap use */ 139 /* OS defined structs */ 140 struct net_device *netdev; 141 struct pci_dev *pdev; 142 143 struct wx_hw wxhw; 144 struct ngbe_phy_info phy; 145 enum ngbe_mac_type mac_type; 146 147 bool wol_enabled; 148 bool ncsi_enabled; 149 bool gpio_ctrl; 150 151 struct ngbe_mac_addr *mac_table; 152 u16 msg_enable; 153 154 /* Tx fast path data */ 155 int num_tx_queues; 156 u16 tx_itr_setting; 157 u16 tx_work_limit; 158 159 /* Rx fast path data */ 160 int num_rx_queues; 161 u16 rx_itr_setting; 162 u16 rx_work_limit; 163 164 int num_q_vectors; /* current number of q_vectors for device */ 165 int max_q_vectors; /* upper limit of q_vectors for device */ 166 167 u32 tx_ring_count; 168 u32 rx_ring_count; 169 170 #define NGBE_MAX_RETA_ENTRIES 128 171 u8 rss_indir_tbl[NGBE_MAX_RETA_ENTRIES]; 172 173 #define NGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */ 174 u32 *rss_key; 175 u32 wol; 176 177 u16 bd_number; 178 }; 179 180 #endif /* _NGBE_TYPE_H_ */ 181