1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #ifndef _NGBE_TYPE_H_ 5 #define _NGBE_TYPE_H_ 6 7 #include <linux/types.h> 8 #include <linux/netdevice.h> 9 10 /************ NGBE_register.h ************/ 11 /* Device IDs */ 12 #define NGBE_DEV_ID_EM_WX1860AL_W 0x0100 13 #define NGBE_DEV_ID_EM_WX1860A2 0x0101 14 #define NGBE_DEV_ID_EM_WX1860A2S 0x0102 15 #define NGBE_DEV_ID_EM_WX1860A4 0x0103 16 #define NGBE_DEV_ID_EM_WX1860A4S 0x0104 17 #define NGBE_DEV_ID_EM_WX1860AL2 0x0105 18 #define NGBE_DEV_ID_EM_WX1860AL2S 0x0106 19 #define NGBE_DEV_ID_EM_WX1860AL4 0x0107 20 #define NGBE_DEV_ID_EM_WX1860AL4S 0x0108 21 #define NGBE_DEV_ID_EM_WX1860LC 0x0109 22 #define NGBE_DEV_ID_EM_WX1860A1 0x010a 23 #define NGBE_DEV_ID_EM_WX1860A1L 0x010b 24 25 /* Subsystem ID */ 26 #define NGBE_SUBID_M88E1512_SFP 0x0003 27 #define NGBE_SUBID_OCP_CARD 0x0040 28 #define NGBE_SUBID_LY_M88E1512_SFP 0x0050 29 #define NGBE_SUBID_M88E1512_RJ45 0x0051 30 #define NGBE_SUBID_M88E1512_MIX 0x0052 31 #define NGBE_SUBID_YT8521S_SFP 0x0060 32 #define NGBE_SUBID_INTERNAL_YT8521S_SFP 0x0061 33 #define NGBE_SUBID_YT8521S_SFP_GPIO 0x0062 34 #define NGBE_SUBID_INTERNAL_YT8521S_SFP_GPIO 0x0064 35 #define NGBE_SUBID_LY_YT8521S_SFP 0x0070 36 #define NGBE_SUBID_RGMII_FPGA 0x0080 37 38 #define NGBE_OEM_MASK 0x00FF 39 40 #define NGBE_NCSI_SUP 0x8000 41 #define NGBE_NCSI_MASK 0x8000 42 #define NGBE_WOL_SUP 0x4000 43 #define NGBE_WOL_MASK 0x4000 44 45 /**************** EM Registers ****************************/ 46 /* chip control Registers */ 47 #define NGBE_MIS_PRB_CTL 0x10010 48 /* FMGR Registers */ 49 #define NGBE_SPI_ILDR_STATUS 0x10120 50 #define NGBE_SPI_ILDR_STATUS_PERST BIT(0) /* PCIE_PERST is done */ 51 #define NGBE_SPI_ILDR_STATUS_PWRRST BIT(1) /* Power on reset is done */ 52 53 /* Checksum and EEPROM pointers */ 54 #define NGBE_CALSUM_COMMAND 0xE9 55 #define NGBE_CALSUM_CAP_STATUS 0x10224 56 #define NGBE_EEPROM_VERSION_STORE_REG 0x1022C 57 #define NGBE_SAN_MAC_ADDR_PTR 0x18 58 #define NGBE_DEVICE_CAPS 0x1C 59 #define NGBE_EEPROM_VERSION_L 0x1D 60 #define NGBE_EEPROM_VERSION_H 0x1E 61 62 /* mdio access */ 63 #define NGBE_MSCA 0x11200 64 #define NGBE_MSCA_RA(v) FIELD_PREP(U16_MAX, v) 65 #define NGBE_MSCA_PA(v) FIELD_PREP(GENMASK(20, 16), v) 66 #define NGBE_MSCA_DA(v) FIELD_PREP(GENMASK(25, 21), v) 67 #define NGBE_MSCC 0x11204 68 #define NGBE_MSCC_CMD(v) FIELD_PREP(GENMASK(17, 16), v) 69 70 enum NGBE_MSCA_CMD_value { 71 NGBE_MSCA_CMD_RSV = 0, 72 NGBE_MSCA_CMD_WRITE, 73 NGBE_MSCA_CMD_POST_READ, 74 NGBE_MSCA_CMD_READ, 75 }; 76 77 #define NGBE_MSCC_SADDR BIT(18) 78 #define NGBE_MSCC_BUSY BIT(22) 79 #define NGBE_MDIO_CLK(v) FIELD_PREP(GENMASK(21, 19), v) 80 81 /* Media-dependent registers. */ 82 #define NGBE_MDIO_CLAUSE_SELECT 0x11220 83 84 /* GPIO Registers */ 85 #define NGBE_GPIO_DR 0x14800 86 #define NGBE_GPIO_DDR 0x14804 87 /*GPIO bit */ 88 #define NGBE_GPIO_DR_0 BIT(0) /* SDP0 Data Value */ 89 #define NGBE_GPIO_DR_1 BIT(1) /* SDP1 Data Value */ 90 #define NGBE_GPIO_DDR_0 BIT(0) /* SDP0 IO direction */ 91 #define NGBE_GPIO_DDR_1 BIT(1) /* SDP1 IO direction */ 92 93 /* Extended Interrupt Enable Set */ 94 #define NGBE_PX_MISC_IEN_DEV_RST BIT(10) 95 #define NGBE_PX_MISC_IEN_ETH_LK BIT(18) 96 #define NGBE_PX_MISC_IEN_INT_ERR BIT(20) 97 #define NGBE_PX_MISC_IEN_GPIO BIT(26) 98 #define NGBE_PX_MISC_IEN_MASK ( \ 99 NGBE_PX_MISC_IEN_DEV_RST | \ 100 NGBE_PX_MISC_IEN_ETH_LK | \ 101 NGBE_PX_MISC_IEN_INT_ERR | \ 102 NGBE_PX_MISC_IEN_GPIO) 103 104 #define NGBE_INTR_ALL 0x1FF 105 #define NGBE_INTR_MISC(A) BIT((A)->num_q_vectors) 106 107 #define NGBE_PHY_CONFIG(reg_offset) (0x14000 + ((reg_offset) * 4)) 108 #define NGBE_CFG_LAN_SPEED 0x14440 109 #define NGBE_CFG_PORT_ST 0x14404 110 111 /* Wake up registers */ 112 #define NGBE_PSR_WKUP_CTL 0x15B80 113 /* Wake Up Filter Control Bit */ 114 #define NGBE_PSR_WKUP_CTL_LNKC BIT(0) /* Link Status Change Wakeup Enable*/ 115 #define NGBE_PSR_WKUP_CTL_MAG BIT(1) /* Magic Packet Wakeup Enable */ 116 #define NGBE_PSR_WKUP_CTL_EX BIT(2) /* Directed Exact Wakeup Enable */ 117 #define NGBE_PSR_WKUP_CTL_MC BIT(3) /* Directed Multicast Wakeup Enable*/ 118 #define NGBE_PSR_WKUP_CTL_BC BIT(4) /* Broadcast Wakeup Enable */ 119 #define NGBE_PSR_WKUP_CTL_ARP BIT(5) /* ARP Request Packet Wakeup Enable*/ 120 #define NGBE_PSR_WKUP_CTL_IPV4 BIT(6) /* Directed IPv4 Pkt Wakeup Enable */ 121 #define NGBE_PSR_WKUP_CTL_IPV6 BIT(7) /* Directed IPv6 Pkt Wakeup Enable */ 122 123 #define NGBE_FW_EEPROM_CHECKSUM_CMD 0xE9 124 #define NGBE_FW_NVM_DATA_OFFSET 3 125 #define NGBE_FW_CMD_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ 126 #define NGBE_FW_CMD_ST_PASS 0x80658383 127 #define NGBE_FW_CMD_ST_FAIL 0x70657376 128 129 #define NGBE_MAX_FDIR_INDICES 7 130 131 #define NGBE_MAX_RX_QUEUES (NGBE_MAX_FDIR_INDICES + 1) 132 #define NGBE_MAX_TX_QUEUES (NGBE_MAX_FDIR_INDICES + 1) 133 134 #define NGBE_ETH_LENGTH_OF_ADDRESS 6 135 #define NGBE_MAX_MSIX_VECTORS 0x09 136 #define NGBE_RAR_ENTRIES 32 137 #define NGBE_RX_PB_SIZE 42 138 #define NGBE_MC_TBL_SIZE 128 139 #define NGBE_TDB_PB_SZ (20 * 1024) /* 160KB Packet Buffer */ 140 141 /* TX/RX descriptor defines */ 142 #define NGBE_DEFAULT_TXD 512 /* default ring size */ 143 #define NGBE_DEFAULT_TX_WORK 256 144 #define NGBE_MAX_TXD 8192 145 #define NGBE_MIN_TXD 128 146 147 #define NGBE_DEFAULT_RXD 512 /* default ring size */ 148 #define NGBE_DEFAULT_RX_WORK 256 149 #define NGBE_MAX_RXD 8192 150 #define NGBE_MIN_RXD 128 151 152 extern char ngbe_driver_name[]; 153 154 #endif /* _NGBE_TYPE_H_ */ 155