1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #ifndef _WX_TYPE_H_ 5 #define _WX_TYPE_H_ 6 7 /* Vendor ID */ 8 #ifndef PCI_VENDOR_ID_WANGXUN 9 #define PCI_VENDOR_ID_WANGXUN 0x8088 10 #endif 11 12 #define WX_NCSI_SUP 0x8000 13 #define WX_NCSI_MASK 0x8000 14 #define WX_WOL_SUP 0x4000 15 #define WX_WOL_MASK 0x4000 16 17 /* MSI-X capability fields masks */ 18 #define WX_PCIE_MSIX_TBL_SZ_MASK 0x7FF 19 #define WX_PCI_LINK_STATUS 0xB2 20 21 /**************** Global Registers ****************************/ 22 /* chip control Registers */ 23 #define WX_MIS_PWR 0x10000 24 #define WX_MIS_RST 0x1000C 25 #define WX_MIS_RST_LAN_RST(_i) BIT((_i) + 1) 26 #define WX_MIS_RST_SW_RST BIT(0) 27 #define WX_MIS_ST 0x10028 28 #define WX_MIS_ST_MNG_INIT_DN BIT(0) 29 #define WX_MIS_SWSM 0x1002C 30 #define WX_MIS_SWSM_SMBI BIT(0) 31 #define WX_MIS_RST_ST 0x10030 32 #define WX_MIS_RST_ST_RST_INI_SHIFT 8 33 #define WX_MIS_RST_ST_RST_INIT (0xFF << WX_MIS_RST_ST_RST_INI_SHIFT) 34 35 /* FMGR Registers */ 36 #define WX_SPI_CMD 0x10104 37 #define WX_SPI_CMD_READ_DWORD 0x1 38 #define WX_SPI_CLK_DIV 0x3 39 #define WX_SPI_CMD_CMD(_v) (((_v) & 0x7) << 28) 40 #define WX_SPI_CMD_CLK(_v) (((_v) & 0x7) << 25) 41 #define WX_SPI_CMD_ADDR(_v) (((_v) & 0xFFFFFF)) 42 #define WX_SPI_DATA 0x10108 43 #define WX_SPI_DATA_BYPASS BIT(31) 44 #define WX_SPI_DATA_STATUS(_v) (((_v) & 0xFF) << 16) 45 #define WX_SPI_DATA_OP_DONE BIT(0) 46 #define WX_SPI_STATUS 0x1010C 47 #define WX_SPI_STATUS_OPDONE BIT(0) 48 #define WX_SPI_STATUS_FLASH_BYPASS BIT(31) 49 #define WX_SPI_ILDR_STATUS 0x10120 50 51 /* Sensors for PVT(Process Voltage Temperature) */ 52 #define WX_TS_EN 0x10304 53 #define WX_TS_EN_ENA BIT(0) 54 #define WX_TS_ALARM_THRE 0x1030C 55 #define WX_TS_DALARM_THRE 0x10310 56 #define WX_TS_INT_EN 0x10314 57 #define WX_TS_INT_EN_DALARM_INT_EN BIT(1) 58 #define WX_TS_INT_EN_ALARM_INT_EN BIT(0) 59 #define WX_TS_ALARM_ST 0x10318 60 #define WX_TS_ALARM_ST_DALARM BIT(1) 61 #define WX_TS_ALARM_ST_ALARM BIT(0) 62 63 /************************* Port Registers ************************************/ 64 /* port cfg Registers */ 65 #define WX_CFG_PORT_CTL 0x14400 66 #define WX_CFG_PORT_CTL_DRV_LOAD BIT(3) 67 68 /*********************** Transmit DMA registers **************************/ 69 /* transmit global control */ 70 #define WX_TDM_CTL 0x18000 71 /* TDM CTL BIT */ 72 #define WX_TDM_CTL_TE BIT(0) /* Transmit Enable */ 73 74 /***************************** RDB registers *********************************/ 75 /* receive packet buffer */ 76 #define WX_RDB_PB_CTL 0x19000 77 #define WX_RDB_PB_CTL_RXEN BIT(31) /* Enable Receiver */ 78 #define WX_RDB_PB_CTL_DISABLED BIT(0) 79 /* statistic */ 80 #define WX_RDB_PFCMACDAL 0x19210 81 #define WX_RDB_PFCMACDAH 0x19214 82 83 /******************************* PSR Registers *******************************/ 84 /* psr control */ 85 #define WX_PSR_CTL 0x15000 86 /* Header split receive */ 87 #define WX_PSR_CTL_SW_EN BIT(18) 88 #define WX_PSR_CTL_RSC_ACK BIT(17) 89 #define WX_PSR_CTL_RSC_DIS BIT(16) 90 #define WX_PSR_CTL_PCSD BIT(13) 91 #define WX_PSR_CTL_IPPCSE BIT(12) 92 #define WX_PSR_CTL_BAM BIT(10) 93 #define WX_PSR_CTL_UPE BIT(9) 94 #define WX_PSR_CTL_MPE BIT(8) 95 #define WX_PSR_CTL_MFE BIT(7) 96 #define WX_PSR_CTL_MO_SHIFT 5 97 #define WX_PSR_CTL_MO (0x3 << WX_PSR_CTL_MO_SHIFT) 98 #define WX_PSR_CTL_TPE BIT(4) 99 /* mcasst/ucast overflow tbl */ 100 #define WX_PSR_MC_TBL(_i) (0x15200 + ((_i) * 4)) 101 #define WX_PSR_UC_TBL(_i) (0x15400 + ((_i) * 4)) 102 103 /* Management */ 104 #define WX_PSR_MNG_FLEX_SEL 0x1582C 105 #define WX_PSR_MNG_FLEX_DW_L(_i) (0x15A00 + ((_i) * 16)) 106 #define WX_PSR_MNG_FLEX_DW_H(_i) (0x15A04 + ((_i) * 16)) 107 #define WX_PSR_MNG_FLEX_MSK(_i) (0x15A08 + ((_i) * 16)) 108 #define WX_PSR_LAN_FLEX_SEL 0x15B8C 109 #define WX_PSR_LAN_FLEX_DW_L(_i) (0x15C00 + ((_i) * 16)) 110 #define WX_PSR_LAN_FLEX_DW_H(_i) (0x15C04 + ((_i) * 16)) 111 #define WX_PSR_LAN_FLEX_MSK(_i) (0x15C08 + ((_i) * 16)) 112 113 /* mac switcher */ 114 #define WX_PSR_MAC_SWC_AD_L 0x16200 115 #define WX_PSR_MAC_SWC_AD_H 0x16204 116 #define WX_PSR_MAC_SWC_AD_H_AD(v) (((v) & 0xFFFF)) 117 #define WX_PSR_MAC_SWC_AD_H_ADTYPE(v) (((v) & 0x1) << 30) 118 #define WX_PSR_MAC_SWC_AD_H_AV BIT(31) 119 #define WX_PSR_MAC_SWC_VM_L 0x16208 120 #define WX_PSR_MAC_SWC_VM_H 0x1620C 121 #define WX_PSR_MAC_SWC_IDX 0x16210 122 #define WX_CLEAR_VMDQ_ALL 0xFFFFFFFFU 123 124 /************************************** MNG ********************************/ 125 #define WX_MNG_SWFW_SYNC 0x1E008 126 #define WX_MNG_SWFW_SYNC_SW_MB BIT(2) 127 #define WX_MNG_SWFW_SYNC_SW_FLASH BIT(3) 128 #define WX_MNG_MBOX 0x1E100 129 #define WX_MNG_MBOX_CTL 0x1E044 130 #define WX_MNG_MBOX_CTL_SWRDY BIT(0) 131 #define WX_MNG_MBOX_CTL_FWRDY BIT(2) 132 133 /************************************* ETH MAC *****************************/ 134 #define WX_MAC_TX_CFG 0x11000 135 #define WX_MAC_TX_CFG_TE BIT(0) 136 #define WX_MAC_RX_CFG 0x11004 137 #define WX_MAC_RX_CFG_RE BIT(0) 138 #define WX_MAC_RX_CFG_JE BIT(8) 139 #define WX_MAC_PKT_FLT 0x11008 140 #define WX_MAC_PKT_FLT_PR BIT(0) /* promiscuous mode */ 141 #define WX_MAC_RX_FLOW_CTRL 0x11090 142 #define WX_MAC_RX_FLOW_CTRL_RFE BIT(0) /* receive fc enable */ 143 #define WX_MMC_CONTROL 0x11800 144 #define WX_MMC_CONTROL_RSTONRD BIT(2) /* reset on read */ 145 146 /********************************* BAR registers ***************************/ 147 /* Interrupt Registers */ 148 #define WX_BME_CTL 0x12020 149 #define WX_PX_MISC_IC 0x100 150 #define WX_PX_IMS(_i) (0x140 + (_i) * 4) 151 #define WX_PX_TRANSACTION_PENDING 0x168 152 153 /* transmit DMA Registers */ 154 #define WX_PX_TR_CFG(_i) (0x03010 + ((_i) * 0x40)) 155 /* Transmit Config masks */ 156 #define WX_PX_TR_CFG_ENABLE BIT(0) /* Ena specific Tx Queue */ 157 #define WX_PX_TR_CFG_TR_SIZE_SHIFT 1 /* tx desc number per ring */ 158 #define WX_PX_TR_CFG_SWFLSH BIT(26) /* Tx Desc. wr-bk flushing */ 159 #define WX_PX_TR_CFG_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ 160 #define WX_PX_TR_CFG_THRE_SHIFT 8 161 162 /* Receive DMA Registers */ 163 #define WX_PX_RR_CFG(_i) (0x01010 + ((_i) * 0x40)) 164 /* PX_RR_CFG bit definitions */ 165 #define WX_PX_RR_CFG_RR_EN BIT(0) 166 167 /* Number of 80 microseconds we wait for PCI Express master disable */ 168 #define WX_PCI_MASTER_DISABLE_TIMEOUT 80000 169 170 /****************** Manageablility Host Interface defines ********************/ 171 #define WX_HI_MAX_BLOCK_BYTE_LENGTH 256 /* Num of bytes in range */ 172 #define WX_HI_COMMAND_TIMEOUT 1000 /* Process HI command limit */ 173 174 #define FW_READ_SHADOW_RAM_CMD 0x31 175 #define FW_READ_SHADOW_RAM_LEN 0x6 176 #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ 177 #define FW_NVM_DATA_OFFSET 3 178 #define FW_MAX_READ_BUFFER_SIZE 244 179 #define FW_RESET_CMD 0xDF 180 #define FW_RESET_LEN 0x2 181 #define FW_CEM_HDR_LEN 0x4 182 #define FW_CEM_CMD_RESERVED 0X0 183 #define FW_CEM_MAX_RETRIES 3 184 #define FW_CEM_RESP_STATUS_SUCCESS 0x1 185 186 #define WX_SW_REGION_PTR 0x1C 187 188 /* Host Interface Command Structures */ 189 struct wx_hic_hdr { 190 u8 cmd; 191 u8 buf_len; 192 union { 193 u8 cmd_resv; 194 u8 ret_status; 195 } cmd_or_resp; 196 u8 checksum; 197 }; 198 199 struct wx_hic_hdr2_req { 200 u8 cmd; 201 u8 buf_lenh; 202 u8 buf_lenl; 203 u8 checksum; 204 }; 205 206 struct wx_hic_hdr2_rsp { 207 u8 cmd; 208 u8 buf_lenl; 209 u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */ 210 u8 checksum; 211 }; 212 213 union wx_hic_hdr2 { 214 struct wx_hic_hdr2_req req; 215 struct wx_hic_hdr2_rsp rsp; 216 }; 217 218 /* These need to be dword aligned */ 219 struct wx_hic_read_shadow_ram { 220 union wx_hic_hdr2 hdr; 221 u32 address; 222 u16 length; 223 u16 pad2; 224 u16 data; 225 u16 pad3; 226 }; 227 228 struct wx_hic_reset { 229 struct wx_hic_hdr hdr; 230 u16 lan_id; 231 u16 reset_type; 232 }; 233 234 /* Bus parameters */ 235 struct wx_bus_info { 236 u8 func; 237 u16 device; 238 }; 239 240 struct wx_thermal_sensor_data { 241 s16 temp; 242 s16 alarm_thresh; 243 s16 dalarm_thresh; 244 }; 245 246 enum wx_mac_type { 247 wx_mac_unknown = 0, 248 wx_mac_sp, 249 wx_mac_em 250 }; 251 252 struct wx_mac_info { 253 enum wx_mac_type type; 254 bool set_lben; 255 u8 addr[ETH_ALEN]; 256 u8 perm_addr[ETH_ALEN]; 257 s32 mc_filter_type; 258 u32 mcft_size; 259 u32 num_rar_entries; 260 u32 max_tx_queues; 261 u32 max_rx_queues; 262 263 u16 max_msix_vectors; 264 struct wx_thermal_sensor_data sensor; 265 }; 266 267 enum wx_eeprom_type { 268 wx_eeprom_uninitialized = 0, 269 wx_eeprom_spi, 270 wx_flash, 271 wx_eeprom_none /* No NVM support */ 272 }; 273 274 struct wx_eeprom_info { 275 enum wx_eeprom_type type; 276 u32 semaphore_delay; 277 u16 word_size; 278 u16 sw_region_offset; 279 }; 280 281 struct wx_addr_filter_info { 282 u32 num_mc_addrs; 283 u32 mta_in_use; 284 bool user_set_promisc; 285 }; 286 287 enum wx_reset_type { 288 WX_LAN_RESET = 0, 289 WX_SW_RESET, 290 WX_GLOBAL_RESET 291 }; 292 293 struct wx_hw { 294 u8 __iomem *hw_addr; 295 struct pci_dev *pdev; 296 struct wx_bus_info bus; 297 struct wx_mac_info mac; 298 struct wx_eeprom_info eeprom; 299 struct wx_addr_filter_info addr_ctrl; 300 u16 device_id; 301 u16 vendor_id; 302 u16 subsystem_device_id; 303 u16 subsystem_vendor_id; 304 u8 revision_id; 305 u16 oem_ssid; 306 u16 oem_svid; 307 bool adapter_stopped; 308 enum wx_reset_type reset_type; 309 }; 310 311 #define WX_INTR_ALL (~0ULL) 312 313 /* register operations */ 314 #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg))) 315 #define rd32(a, reg) readl((a)->hw_addr + (reg)) 316 #define rd32a(a, reg, offset) ( \ 317 rd32((a), (reg) + ((offset) << 2))) 318 #define wr32a(a, reg, off, val) \ 319 wr32((a), (reg) + ((off) << 2), (val)) 320 321 static inline u32 322 rd32m(struct wx_hw *wxhw, u32 reg, u32 mask) 323 { 324 u32 val; 325 326 val = rd32(wxhw, reg); 327 return val & mask; 328 } 329 330 static inline void 331 wr32m(struct wx_hw *wxhw, u32 reg, u32 mask, u32 field) 332 { 333 u32 val; 334 335 val = rd32(wxhw, reg); 336 val = ((val & ~mask) | (field & mask)); 337 338 wr32(wxhw, reg, val); 339 } 340 341 /* On some domestic CPU platforms, sometimes IO is not synchronized with 342 * flushing memory, here use readl() to flush PCI read and write. 343 */ 344 #define WX_WRITE_FLUSH(H) rd32(H, WX_MIS_PWR) 345 346 #define wx_err(wxhw, fmt, arg...) \ 347 dev_err(&(wxhw)->pdev->dev, fmt, ##arg) 348 349 #define wx_dbg(wxhw, fmt, arg...) \ 350 dev_dbg(&(wxhw)->pdev->dev, fmt, ##arg) 351 352 #endif /* _WX_TYPE_H_ */ 353