1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #ifndef _WX_TYPE_H_ 5 #define _WX_TYPE_H_ 6 7 #include <linux/bitfield.h> 8 #include <linux/netdevice.h> 9 10 #define WX_NCSI_SUP 0x8000 11 #define WX_NCSI_MASK 0x8000 12 #define WX_WOL_SUP 0x4000 13 #define WX_WOL_MASK 0x4000 14 15 /* MSI-X capability fields masks */ 16 #define WX_PCIE_MSIX_TBL_SZ_MASK 0x7FF 17 #define WX_PCI_LINK_STATUS 0xB2 18 19 /**************** Global Registers ****************************/ 20 /* chip control Registers */ 21 #define WX_MIS_PWR 0x10000 22 #define WX_MIS_RST 0x1000C 23 #define WX_MIS_RST_LAN_RST(_i) BIT((_i) + 1) 24 #define WX_MIS_RST_SW_RST BIT(0) 25 #define WX_MIS_ST 0x10028 26 #define WX_MIS_ST_MNG_INIT_DN BIT(0) 27 #define WX_MIS_SWSM 0x1002C 28 #define WX_MIS_SWSM_SMBI BIT(0) 29 #define WX_MIS_RST_ST 0x10030 30 #define WX_MIS_RST_ST_RST_INI_SHIFT 8 31 #define WX_MIS_RST_ST_RST_INIT (0xFF << WX_MIS_RST_ST_RST_INI_SHIFT) 32 33 /* FMGR Registers */ 34 #define WX_SPI_CMD 0x10104 35 #define WX_SPI_CMD_READ_DWORD 0x1 36 #define WX_SPI_CLK_DIV 0x3 37 #define WX_SPI_CMD_CMD(_v) FIELD_PREP(GENMASK(30, 28), _v) 38 #define WX_SPI_CMD_CLK(_v) FIELD_PREP(GENMASK(27, 25), _v) 39 #define WX_SPI_CMD_ADDR(_v) FIELD_PREP(GENMASK(23, 0), _v) 40 #define WX_SPI_DATA 0x10108 41 #define WX_SPI_DATA_BYPASS BIT(31) 42 #define WX_SPI_DATA_OP_DONE BIT(0) 43 #define WX_SPI_STATUS 0x1010C 44 #define WX_SPI_STATUS_OPDONE BIT(0) 45 #define WX_SPI_STATUS_FLASH_BYPASS BIT(31) 46 #define WX_SPI_ILDR_STATUS 0x10120 47 48 /* Sensors for PVT(Process Voltage Temperature) */ 49 #define WX_TS_EN 0x10304 50 #define WX_TS_EN_ENA BIT(0) 51 #define WX_TS_ALARM_THRE 0x1030C 52 #define WX_TS_DALARM_THRE 0x10310 53 #define WX_TS_INT_EN 0x10314 54 #define WX_TS_INT_EN_DALARM_INT_EN BIT(1) 55 #define WX_TS_INT_EN_ALARM_INT_EN BIT(0) 56 #define WX_TS_ALARM_ST 0x10318 57 #define WX_TS_ALARM_ST_DALARM BIT(1) 58 #define WX_TS_ALARM_ST_ALARM BIT(0) 59 60 /************************* Port Registers ************************************/ 61 /* port cfg Registers */ 62 #define WX_CFG_PORT_CTL 0x14400 63 #define WX_CFG_PORT_CTL_DRV_LOAD BIT(3) 64 #define WX_CFG_PORT_CTL_QINQ BIT(2) 65 #define WX_CFG_PORT_CTL_D_VLAN BIT(0) /* double vlan*/ 66 #define WX_CFG_TAG_TPID(_i) (0x14430 + ((_i) * 4)) 67 68 /* GPIO Registers */ 69 #define WX_GPIO_DR 0x14800 70 #define WX_GPIO_DR_0 BIT(0) /* SDP0 Data Value */ 71 #define WX_GPIO_DR_1 BIT(1) /* SDP1 Data Value */ 72 #define WX_GPIO_DDR 0x14804 73 #define WX_GPIO_DDR_0 BIT(0) /* SDP0 IO direction */ 74 #define WX_GPIO_DDR_1 BIT(1) /* SDP1 IO direction */ 75 #define WX_GPIO_CTL 0x14808 76 #define WX_GPIO_INTEN 0x14830 77 #define WX_GPIO_INTEN_0 BIT(0) 78 #define WX_GPIO_INTEN_1 BIT(1) 79 #define WX_GPIO_INTMASK 0x14834 80 #define WX_GPIO_INTTYPE_LEVEL 0x14838 81 #define WX_GPIO_POLARITY 0x1483C 82 #define WX_GPIO_EOI 0x1484C 83 84 /*********************** Transmit DMA registers **************************/ 85 /* transmit global control */ 86 #define WX_TDM_CTL 0x18000 87 /* TDM CTL BIT */ 88 #define WX_TDM_CTL_TE BIT(0) /* Transmit Enable */ 89 #define WX_TDM_PB_THRE(_i) (0x18020 + ((_i) * 4)) 90 91 /***************************** RDB registers *********************************/ 92 /* receive packet buffer */ 93 #define WX_RDB_PB_CTL 0x19000 94 #define WX_RDB_PB_CTL_RXEN BIT(31) /* Enable Receiver */ 95 #define WX_RDB_PB_CTL_DISABLED BIT(0) 96 #define WX_RDB_PB_SZ(_i) (0x19020 + ((_i) * 4)) 97 #define WX_RDB_PB_SZ_SHIFT 10 98 /* statistic */ 99 #define WX_RDB_PFCMACDAL 0x19210 100 #define WX_RDB_PFCMACDAH 0x19214 101 /* ring assignment */ 102 #define WX_RDB_PL_CFG(_i) (0x19300 + ((_i) * 4)) 103 #define WX_RDB_PL_CFG_L4HDR BIT(1) 104 #define WX_RDB_PL_CFG_L3HDR BIT(2) 105 #define WX_RDB_PL_CFG_L2HDR BIT(3) 106 #define WX_RDB_PL_CFG_TUN_TUNHDR BIT(4) 107 #define WX_RDB_PL_CFG_TUN_OUTL2HDR BIT(5) 108 109 /******************************* PSR Registers *******************************/ 110 /* psr control */ 111 #define WX_PSR_CTL 0x15000 112 /* Header split receive */ 113 #define WX_PSR_CTL_SW_EN BIT(18) 114 #define WX_PSR_CTL_RSC_ACK BIT(17) 115 #define WX_PSR_CTL_RSC_DIS BIT(16) 116 #define WX_PSR_CTL_PCSD BIT(13) 117 #define WX_PSR_CTL_IPPCSE BIT(12) 118 #define WX_PSR_CTL_BAM BIT(10) 119 #define WX_PSR_CTL_UPE BIT(9) 120 #define WX_PSR_CTL_MPE BIT(8) 121 #define WX_PSR_CTL_MFE BIT(7) 122 #define WX_PSR_CTL_MO_SHIFT 5 123 #define WX_PSR_CTL_MO (0x3 << WX_PSR_CTL_MO_SHIFT) 124 #define WX_PSR_CTL_TPE BIT(4) 125 #define WX_PSR_MAX_SZ 0x15020 126 #define WX_PSR_VLAN_CTL 0x15088 127 #define WX_PSR_VLAN_CTL_CFIEN BIT(29) /* bit 29 */ 128 #define WX_PSR_VLAN_CTL_VFE BIT(30) /* bit 30 */ 129 /* mcasst/ucast overflow tbl */ 130 #define WX_PSR_MC_TBL(_i) (0x15200 + ((_i) * 4)) 131 #define WX_PSR_UC_TBL(_i) (0x15400 + ((_i) * 4)) 132 133 /* VM L2 contorl */ 134 #define WX_PSR_VM_L2CTL(_i) (0x15600 + ((_i) * 4)) 135 #define WX_PSR_VM_L2CTL_UPE BIT(4) /* unicast promiscuous */ 136 #define WX_PSR_VM_L2CTL_VACC BIT(6) /* accept nomatched vlan */ 137 #define WX_PSR_VM_L2CTL_AUPE BIT(8) /* accept untagged packets */ 138 #define WX_PSR_VM_L2CTL_ROMPE BIT(9) /* accept packets in MTA tbl */ 139 #define WX_PSR_VM_L2CTL_ROPE BIT(10) /* accept packets in UC tbl */ 140 #define WX_PSR_VM_L2CTL_BAM BIT(11) /* accept broadcast packets */ 141 #define WX_PSR_VM_L2CTL_MPE BIT(12) /* multicast promiscuous */ 142 143 /* Management */ 144 #define WX_PSR_MNG_FLEX_SEL 0x1582C 145 #define WX_PSR_MNG_FLEX_DW_L(_i) (0x15A00 + ((_i) * 16)) 146 #define WX_PSR_MNG_FLEX_DW_H(_i) (0x15A04 + ((_i) * 16)) 147 #define WX_PSR_MNG_FLEX_MSK(_i) (0x15A08 + ((_i) * 16)) 148 #define WX_PSR_LAN_FLEX_SEL 0x15B8C 149 #define WX_PSR_LAN_FLEX_DW_L(_i) (0x15C00 + ((_i) * 16)) 150 #define WX_PSR_LAN_FLEX_DW_H(_i) (0x15C04 + ((_i) * 16)) 151 #define WX_PSR_LAN_FLEX_MSK(_i) (0x15C08 + ((_i) * 16)) 152 153 /* mac switcher */ 154 #define WX_PSR_MAC_SWC_AD_L 0x16200 155 #define WX_PSR_MAC_SWC_AD_H 0x16204 156 #define WX_PSR_MAC_SWC_AD_H_AD(v) FIELD_PREP(U16_MAX, v) 157 #define WX_PSR_MAC_SWC_AD_H_ADTYPE(v) FIELD_PREP(BIT(30), v) 158 #define WX_PSR_MAC_SWC_AD_H_AV BIT(31) 159 #define WX_PSR_MAC_SWC_VM_L 0x16208 160 #define WX_PSR_MAC_SWC_VM_H 0x1620C 161 #define WX_PSR_MAC_SWC_IDX 0x16210 162 #define WX_CLEAR_VMDQ_ALL 0xFFFFFFFFU 163 164 /********************************* RSEC **************************************/ 165 /* general rsec */ 166 #define WX_RSC_CTL 0x17000 167 #define WX_RSC_CTL_SAVE_MAC_ERR BIT(6) 168 #define WX_RSC_CTL_CRC_STRIP BIT(2) 169 #define WX_RSC_CTL_RX_DIS BIT(1) 170 #define WX_RSC_ST 0x17004 171 #define WX_RSC_ST_RSEC_RDY BIT(0) 172 173 /****************************** TDB ******************************************/ 174 #define WX_TDB_PB_SZ(_i) (0x1CC00 + ((_i) * 4)) 175 #define WX_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */ 176 177 /****************************** TSEC *****************************************/ 178 /* Security Control Registers */ 179 #define WX_TSC_CTL 0x1D000 180 #define WX_TSC_CTL_TX_DIS BIT(1) 181 #define WX_TSC_CTL_TSEC_DIS BIT(0) 182 #define WX_TSC_BUF_AE 0x1D00C 183 #define WX_TSC_BUF_AE_THR GENMASK(9, 0) 184 185 /************************************** MNG ********************************/ 186 #define WX_MNG_SWFW_SYNC 0x1E008 187 #define WX_MNG_SWFW_SYNC_SW_MB BIT(2) 188 #define WX_MNG_SWFW_SYNC_SW_FLASH BIT(3) 189 #define WX_MNG_MBOX 0x1E100 190 #define WX_MNG_MBOX_CTL 0x1E044 191 #define WX_MNG_MBOX_CTL_SWRDY BIT(0) 192 #define WX_MNG_MBOX_CTL_FWRDY BIT(2) 193 194 /************************************* ETH MAC *****************************/ 195 #define WX_MAC_TX_CFG 0x11000 196 #define WX_MAC_TX_CFG_TE BIT(0) 197 #define WX_MAC_TX_CFG_SPEED_MASK GENMASK(30, 29) 198 #define WX_MAC_TX_CFG_SPEED_10G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 0) 199 #define WX_MAC_TX_CFG_SPEED_1G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 3) 200 #define WX_MAC_RX_CFG 0x11004 201 #define WX_MAC_RX_CFG_RE BIT(0) 202 #define WX_MAC_RX_CFG_JE BIT(8) 203 #define WX_MAC_PKT_FLT 0x11008 204 #define WX_MAC_PKT_FLT_PR BIT(0) /* promiscuous mode */ 205 #define WX_MAC_WDG_TIMEOUT 0x1100C 206 #define WX_MAC_RX_FLOW_CTRL 0x11090 207 #define WX_MAC_RX_FLOW_CTRL_RFE BIT(0) /* receive fc enable */ 208 #define WX_MMC_CONTROL 0x11800 209 #define WX_MMC_CONTROL_RSTONRD BIT(2) /* reset on read */ 210 211 /********************************* BAR registers ***************************/ 212 /* Interrupt Registers */ 213 #define WX_BME_CTL 0x12020 214 #define WX_PX_MISC_IC 0x100 215 #define WX_PX_MISC_ICS 0x104 216 #define WX_PX_MISC_IEN 0x108 217 #define WX_PX_INTA 0x110 218 #define WX_PX_GPIE 0x118 219 #define WX_PX_GPIE_MODEL BIT(0) 220 #define WX_PX_IC(_i) (0x120 + (_i) * 4) 221 #define WX_PX_IMS(_i) (0x140 + (_i) * 4) 222 #define WX_PX_IMC(_i) (0x150 + (_i) * 4) 223 #define WX_PX_ISB_ADDR_L 0x160 224 #define WX_PX_ISB_ADDR_H 0x164 225 #define WX_PX_TRANSACTION_PENDING 0x168 226 #define WX_PX_ITRSEL 0x180 227 #define WX_PX_ITR(_i) (0x200 + (_i) * 4) 228 #define WX_PX_ITR_CNT_WDIS BIT(31) 229 #define WX_PX_MISC_IVAR 0x4FC 230 #define WX_PX_IVAR(_i) (0x500 + (_i) * 4) 231 232 #define WX_PX_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 233 #define WX_7K_ITR 595 234 #define WX_12K_ITR 336 235 #define WX_SP_MAX_EITR 0x00000FF8U 236 #define WX_EM_MAX_EITR 0x00007FFCU 237 238 /* transmit DMA Registers */ 239 #define WX_PX_TR_BAL(_i) (0x03000 + ((_i) * 0x40)) 240 #define WX_PX_TR_BAH(_i) (0x03004 + ((_i) * 0x40)) 241 #define WX_PX_TR_WP(_i) (0x03008 + ((_i) * 0x40)) 242 #define WX_PX_TR_RP(_i) (0x0300C + ((_i) * 0x40)) 243 #define WX_PX_TR_CFG(_i) (0x03010 + ((_i) * 0x40)) 244 /* Transmit Config masks */ 245 #define WX_PX_TR_CFG_ENABLE BIT(0) /* Ena specific Tx Queue */ 246 #define WX_PX_TR_CFG_TR_SIZE_SHIFT 1 /* tx desc number per ring */ 247 #define WX_PX_TR_CFG_SWFLSH BIT(26) /* Tx Desc. wr-bk flushing */ 248 #define WX_PX_TR_CFG_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ 249 #define WX_PX_TR_CFG_THRE_SHIFT 8 250 251 /* Receive DMA Registers */ 252 #define WX_PX_RR_BAL(_i) (0x01000 + ((_i) * 0x40)) 253 #define WX_PX_RR_BAH(_i) (0x01004 + ((_i) * 0x40)) 254 #define WX_PX_RR_WP(_i) (0x01008 + ((_i) * 0x40)) 255 #define WX_PX_RR_RP(_i) (0x0100C + ((_i) * 0x40)) 256 #define WX_PX_RR_CFG(_i) (0x01010 + ((_i) * 0x40)) 257 /* PX_RR_CFG bit definitions */ 258 #define WX_PX_RR_CFG_SPLIT_MODE BIT(26) 259 #define WX_PX_RR_CFG_RR_THER_SHIFT 16 260 #define WX_PX_RR_CFG_RR_HDR_SZ GENMASK(15, 12) 261 #define WX_PX_RR_CFG_RR_BUF_SZ GENMASK(11, 8) 262 #define WX_PX_RR_CFG_BHDRSIZE_SHIFT 6 /* 64byte resolution (>> 6) 263 * + at bit 8 offset (<< 12) 264 * = (<< 6) 265 */ 266 #define WX_PX_RR_CFG_BSIZEPKT_SHIFT 2 /* so many KBs */ 267 #define WX_PX_RR_CFG_RR_SIZE_SHIFT 1 268 #define WX_PX_RR_CFG_RR_EN BIT(0) 269 270 /* Number of 80 microseconds we wait for PCI Express master disable */ 271 #define WX_PCI_MASTER_DISABLE_TIMEOUT 80000 272 273 /****************** Manageablility Host Interface defines ********************/ 274 #define WX_HI_MAX_BLOCK_BYTE_LENGTH 256 /* Num of bytes in range */ 275 #define WX_HI_COMMAND_TIMEOUT 1000 /* Process HI command limit */ 276 277 #define FW_READ_SHADOW_RAM_CMD 0x31 278 #define FW_READ_SHADOW_RAM_LEN 0x6 279 #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ 280 #define FW_NVM_DATA_OFFSET 3 281 #define FW_MAX_READ_BUFFER_SIZE 244 282 #define FW_RESET_CMD 0xDF 283 #define FW_RESET_LEN 0x2 284 #define FW_CEM_HDR_LEN 0x4 285 #define FW_CEM_CMD_RESERVED 0X0 286 #define FW_CEM_MAX_RETRIES 3 287 #define FW_CEM_RESP_STATUS_SUCCESS 0x1 288 289 #define WX_SW_REGION_PTR 0x1C 290 291 #define WX_MAC_STATE_DEFAULT 0x1 292 #define WX_MAC_STATE_MODIFIED 0x2 293 #define WX_MAC_STATE_IN_USE 0x4 294 295 #define WX_MAX_RXD 8192 296 #define WX_MAX_TXD 8192 297 298 #define WX_MAX_JUMBO_FRAME_SIZE 9432 /* max payload 9414 */ 299 300 /* Supported Rx Buffer Sizes */ 301 #define WX_RXBUFFER_256 256 /* Used for skb receive header */ 302 #define WX_RXBUFFER_2K 2048 303 #define WX_MAX_RXBUFFER 16384 /* largest size for single descriptor */ 304 305 #if MAX_SKB_FRAGS < 8 306 #define WX_RX_BUFSZ ALIGN(WX_MAX_RXBUFFER / MAX_SKB_FRAGS, 1024) 307 #else 308 #define WX_RX_BUFSZ WX_RXBUFFER_2K 309 #endif 310 311 #define WX_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 312 313 #define WX_MAX_DATA_PER_TXD BIT(14) 314 /* Tx Descriptors needed, worst case */ 315 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), WX_MAX_DATA_PER_TXD) 316 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 317 318 /* Ether Types */ 319 #define WX_ETH_P_CNM 0x22E7 320 321 #define WX_CFG_PORT_ST 0x14404 322 323 /******************* Receive Descriptor bit definitions **********************/ 324 #define WX_RXD_STAT_DD BIT(0) /* Done */ 325 #define WX_RXD_STAT_EOP BIT(1) /* End of Packet */ 326 327 #define WX_RXD_ERR_RXE BIT(29) /* Any MAC Error */ 328 329 /*********************** Transmit Descriptor Config Masks ****************/ 330 #define WX_TXD_STAT_DD BIT(0) /* Descriptor Done */ 331 #define WX_TXD_DTYP_DATA 0 /* Adv Data Descriptor */ 332 #define WX_TXD_PAYLEN_SHIFT 13 /* Desc PAYLEN shift */ 333 #define WX_TXD_EOP BIT(24) /* End of Packet */ 334 #define WX_TXD_IFCS BIT(25) /* Insert FCS */ 335 #define WX_TXD_RS BIT(27) /* Report Status */ 336 337 /* Host Interface Command Structures */ 338 struct wx_hic_hdr { 339 u8 cmd; 340 u8 buf_len; 341 union { 342 u8 cmd_resv; 343 u8 ret_status; 344 } cmd_or_resp; 345 u8 checksum; 346 }; 347 348 struct wx_hic_hdr2_req { 349 u8 cmd; 350 u8 buf_lenh; 351 u8 buf_lenl; 352 u8 checksum; 353 }; 354 355 struct wx_hic_hdr2_rsp { 356 u8 cmd; 357 u8 buf_lenl; 358 u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */ 359 u8 checksum; 360 }; 361 362 union wx_hic_hdr2 { 363 struct wx_hic_hdr2_req req; 364 struct wx_hic_hdr2_rsp rsp; 365 }; 366 367 /* These need to be dword aligned */ 368 struct wx_hic_read_shadow_ram { 369 union wx_hic_hdr2 hdr; 370 u32 address; 371 u16 length; 372 u16 pad2; 373 u16 data; 374 u16 pad3; 375 }; 376 377 struct wx_hic_reset { 378 struct wx_hic_hdr hdr; 379 u16 lan_id; 380 u16 reset_type; 381 }; 382 383 /* Bus parameters */ 384 struct wx_bus_info { 385 u8 func; 386 u16 device; 387 }; 388 389 struct wx_thermal_sensor_data { 390 s16 temp; 391 s16 alarm_thresh; 392 s16 dalarm_thresh; 393 }; 394 395 enum wx_mac_type { 396 wx_mac_unknown = 0, 397 wx_mac_sp, 398 wx_mac_em 399 }; 400 401 enum em_mac_type { 402 em_mac_type_unknown = 0, 403 em_mac_type_mdi, 404 em_mac_type_rgmii 405 }; 406 407 struct wx_mac_info { 408 enum wx_mac_type type; 409 bool set_lben; 410 u8 addr[ETH_ALEN]; 411 u8 perm_addr[ETH_ALEN]; 412 u32 mta_shadow[128]; 413 s32 mc_filter_type; 414 u32 mcft_size; 415 u32 num_rar_entries; 416 u32 rx_pb_size; 417 u32 tx_pb_size; 418 u32 max_tx_queues; 419 u32 max_rx_queues; 420 421 u16 max_msix_vectors; 422 struct wx_thermal_sensor_data sensor; 423 }; 424 425 enum wx_eeprom_type { 426 wx_eeprom_uninitialized = 0, 427 wx_eeprom_spi, 428 wx_flash, 429 wx_eeprom_none /* No NVM support */ 430 }; 431 432 struct wx_eeprom_info { 433 enum wx_eeprom_type type; 434 u32 semaphore_delay; 435 u16 word_size; 436 u16 sw_region_offset; 437 }; 438 439 struct wx_addr_filter_info { 440 u32 num_mc_addrs; 441 u32 mta_in_use; 442 bool user_set_promisc; 443 }; 444 445 struct wx_mac_addr { 446 u8 addr[ETH_ALEN]; 447 u16 state; /* bitmask */ 448 u64 pools; 449 }; 450 451 enum wx_reset_type { 452 WX_LAN_RESET = 0, 453 WX_SW_RESET, 454 WX_GLOBAL_RESET 455 }; 456 457 struct wx_cb { 458 dma_addr_t dma; 459 u16 append_cnt; /* number of skb's appended */ 460 bool page_released; 461 bool dma_released; 462 }; 463 464 #define WX_CB(skb) ((struct wx_cb *)(skb)->cb) 465 466 /* Transmit Descriptor */ 467 union wx_tx_desc { 468 struct { 469 __le64 buffer_addr; /* Address of descriptor's data buf */ 470 __le32 cmd_type_len; 471 __le32 olinfo_status; 472 } read; 473 struct { 474 __le64 rsvd; /* Reserved */ 475 __le32 nxtseq_seed; 476 __le32 status; 477 } wb; 478 }; 479 480 /* Receive Descriptor */ 481 union wx_rx_desc { 482 struct { 483 __le64 pkt_addr; /* Packet buffer address */ 484 __le64 hdr_addr; /* Header buffer address */ 485 } read; 486 struct { 487 struct { 488 union { 489 __le32 data; 490 struct { 491 __le16 pkt_info; /* RSS, Pkt type */ 492 __le16 hdr_info; /* Splithdr, hdrlen */ 493 } hs_rss; 494 } lo_dword; 495 union { 496 __le32 rss; /* RSS Hash */ 497 struct { 498 __le16 ip_id; /* IP id */ 499 __le16 csum; /* Packet Checksum */ 500 } csum_ip; 501 } hi_dword; 502 } lower; 503 struct { 504 __le32 status_error; /* ext status/error */ 505 __le16 length; /* Packet length */ 506 __le16 vlan; /* VLAN tag */ 507 } upper; 508 } wb; /* writeback */ 509 }; 510 511 #define WX_RX_DESC(R, i) \ 512 (&(((union wx_rx_desc *)((R)->desc))[i])) 513 #define WX_TX_DESC(R, i) \ 514 (&(((union wx_tx_desc *)((R)->desc))[i])) 515 516 /* wrapper around a pointer to a socket buffer, 517 * so a DMA handle can be stored along with the buffer 518 */ 519 struct wx_tx_buffer { 520 union wx_tx_desc *next_to_watch; 521 struct sk_buff *skb; 522 unsigned int bytecount; 523 unsigned short gso_segs; 524 DEFINE_DMA_UNMAP_ADDR(dma); 525 DEFINE_DMA_UNMAP_LEN(len); 526 }; 527 528 struct wx_rx_buffer { 529 struct sk_buff *skb; 530 dma_addr_t dma; 531 dma_addr_t page_dma; 532 struct page *page; 533 unsigned int page_offset; 534 u16 pagecnt_bias; 535 }; 536 537 struct wx_queue_stats { 538 u64 packets; 539 u64 bytes; 540 }; 541 542 /* iterator for handling rings in ring container */ 543 #define wx_for_each_ring(posm, headm) \ 544 for (posm = (headm).ring; posm; posm = posm->next) 545 546 struct wx_ring_container { 547 struct wx_ring *ring; /* pointer to linked list of rings */ 548 unsigned int total_bytes; /* total bytes processed this int */ 549 unsigned int total_packets; /* total packets processed this int */ 550 u8 count; /* total number of rings in vector */ 551 u8 itr; /* current ITR setting for ring */ 552 }; 553 554 struct wx_ring { 555 struct wx_ring *next; /* pointer to next ring in q_vector */ 556 struct wx_q_vector *q_vector; /* backpointer to host q_vector */ 557 struct net_device *netdev; /* netdev ring belongs to */ 558 struct device *dev; /* device for DMA mapping */ 559 struct page_pool *page_pool; 560 void *desc; /* descriptor ring memory */ 561 union { 562 struct wx_tx_buffer *tx_buffer_info; 563 struct wx_rx_buffer *rx_buffer_info; 564 }; 565 u8 __iomem *tail; 566 dma_addr_t dma; /* phys. address of descriptor ring */ 567 unsigned int size; /* length in bytes */ 568 569 u16 count; /* amount of descriptors */ 570 571 u8 queue_index; /* needed for multiqueue queue management */ 572 u8 reg_idx; /* holds the special value that gets 573 * the hardware register offset 574 * associated with this ring, which is 575 * different for DCB and RSS modes 576 */ 577 u16 next_to_use; 578 u16 next_to_clean; 579 u16 next_to_alloc; 580 581 struct wx_queue_stats stats; 582 struct u64_stats_sync syncp; 583 } ____cacheline_internodealigned_in_smp; 584 585 struct wx_q_vector { 586 struct wx *wx; 587 int cpu; /* CPU for DCA */ 588 int numa_node; 589 u16 v_idx; /* index of q_vector within array, also used for 590 * finding the bit in EICR and friends that 591 * represents the vector for this ring 592 */ 593 u16 itr; /* Interrupt throttle rate written to EITR */ 594 struct wx_ring_container rx, tx; 595 struct napi_struct napi; 596 struct rcu_head rcu; /* to avoid race with update stats on free */ 597 598 char name[IFNAMSIZ + 17]; 599 600 /* for dynamic allocation of rings associated with this q_vector */ 601 struct wx_ring ring[0] ____cacheline_internodealigned_in_smp; 602 }; 603 604 enum wx_isb_idx { 605 WX_ISB_HEADER, 606 WX_ISB_MISC, 607 WX_ISB_VEC0, 608 WX_ISB_VEC1, 609 WX_ISB_MAX 610 }; 611 612 struct wx { 613 u8 __iomem *hw_addr; 614 struct pci_dev *pdev; 615 struct net_device *netdev; 616 struct wx_bus_info bus; 617 struct wx_mac_info mac; 618 enum em_mac_type mac_type; 619 struct wx_eeprom_info eeprom; 620 struct wx_addr_filter_info addr_ctrl; 621 struct wx_mac_addr *mac_table; 622 u16 device_id; 623 u16 vendor_id; 624 u16 subsystem_device_id; 625 u16 subsystem_vendor_id; 626 u8 revision_id; 627 u16 oem_ssid; 628 u16 oem_svid; 629 u16 msg_enable; 630 bool adapter_stopped; 631 u16 tpid[8]; 632 char eeprom_id[32]; 633 char *driver_name; 634 enum wx_reset_type reset_type; 635 636 /* PHY stuff */ 637 unsigned int link; 638 int speed; 639 int duplex; 640 struct phy_device *phydev; 641 642 bool wol_enabled; 643 bool ncsi_enabled; 644 bool gpio_ctrl; 645 646 /* Tx fast path data */ 647 int num_tx_queues; 648 u16 tx_itr_setting; 649 u16 tx_work_limit; 650 651 /* Rx fast path data */ 652 int num_rx_queues; 653 u16 rx_itr_setting; 654 u16 rx_work_limit; 655 656 int num_q_vectors; /* current number of q_vectors for device */ 657 int max_q_vectors; /* upper limit of q_vectors for device */ 658 659 u32 tx_ring_count; 660 u32 rx_ring_count; 661 662 struct wx_ring *tx_ring[64] ____cacheline_aligned_in_smp; 663 struct wx_ring *rx_ring[64]; 664 struct wx_q_vector *q_vector[64]; 665 666 unsigned int queues_per_pool; 667 struct msix_entry *msix_entries; 668 669 /* misc interrupt status block */ 670 dma_addr_t isb_dma; 671 u32 *isb_mem; 672 u32 isb_tag[WX_ISB_MAX]; 673 674 #define WX_MAX_RETA_ENTRIES 128 675 u8 rss_indir_tbl[WX_MAX_RETA_ENTRIES]; 676 677 #define WX_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */ 678 u32 *rss_key; 679 u32 wol; 680 681 u16 bd_number; 682 }; 683 684 #define WX_INTR_ALL (~0ULL) 685 #define WX_INTR_Q(i) BIT(i) 686 687 /* register operations */ 688 #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg))) 689 #define rd32(a, reg) readl((a)->hw_addr + (reg)) 690 #define rd32a(a, reg, offset) ( \ 691 rd32((a), (reg) + ((offset) << 2))) 692 #define wr32a(a, reg, off, val) \ 693 wr32((a), (reg) + ((off) << 2), (val)) 694 695 static inline u32 696 rd32m(struct wx *wx, u32 reg, u32 mask) 697 { 698 u32 val; 699 700 val = rd32(wx, reg); 701 return val & mask; 702 } 703 704 static inline void 705 wr32m(struct wx *wx, u32 reg, u32 mask, u32 field) 706 { 707 u32 val; 708 709 val = rd32(wx, reg); 710 val = ((val & ~mask) | (field & mask)); 711 712 wr32(wx, reg, val); 713 } 714 715 /* On some domestic CPU platforms, sometimes IO is not synchronized with 716 * flushing memory, here use readl() to flush PCI read and write. 717 */ 718 #define WX_WRITE_FLUSH(H) rd32(H, WX_MIS_PWR) 719 720 #define wx_err(wx, fmt, arg...) \ 721 dev_err(&(wx)->pdev->dev, fmt, ##arg) 722 723 #define wx_dbg(wx, fmt, arg...) \ 724 dev_dbg(&(wx)->pdev->dev, fmt, ##arg) 725 726 #endif /* _WX_TYPE_H_ */ 727