1a34b3e6eSJiawen Wu /* SPDX-License-Identifier: GPL-2.0 */
2a34b3e6eSJiawen Wu /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */
3a34b3e6eSJiawen Wu
4a34b3e6eSJiawen Wu #ifndef _WX_TYPE_H_
5a34b3e6eSJiawen Wu #define _WX_TYPE_H_
6a34b3e6eSJiawen Wu
7860edff5SMengyuan Lou #include <linux/bitfield.h>
83f703186SMengyuan Lou #include <linux/netdevice.h>
9f3b03c65SMengyuan Lou #include <linux/if_vlan.h>
103403960cSMengyuan Lou #include <net/ip.h>
11860edff5SMengyuan Lou
12b0801256SJiawen Wu #define WX_NCSI_SUP 0x8000
13b0801256SJiawen Wu #define WX_NCSI_MASK 0x8000
14b0801256SJiawen Wu #define WX_WOL_SUP 0x4000
15b0801256SJiawen Wu #define WX_WOL_MASK 0x4000
16b0801256SJiawen Wu
1702338c48SMengyuan Lou /* MSI-X capability fields masks */
1802338c48SMengyuan Lou #define WX_PCIE_MSIX_TBL_SZ_MASK 0x7FF
1902338c48SMengyuan Lou #define WX_PCI_LINK_STATUS 0xB2
2002338c48SMengyuan Lou
21b0801256SJiawen Wu /**************** Global Registers ****************************/
22b0801256SJiawen Wu /* chip control Registers */
23b0801256SJiawen Wu #define WX_MIS_PWR 0x10000
24b0801256SJiawen Wu #define WX_MIS_RST 0x1000C
25b0801256SJiawen Wu #define WX_MIS_RST_LAN_RST(_i) BIT((_i) + 1)
261efa9bfeSJiawen Wu #define WX_MIS_RST_SW_RST BIT(0)
271efa9bfeSJiawen Wu #define WX_MIS_ST 0x10028
281efa9bfeSJiawen Wu #define WX_MIS_ST_MNG_INIT_DN BIT(0)
291efa9bfeSJiawen Wu #define WX_MIS_SWSM 0x1002C
301efa9bfeSJiawen Wu #define WX_MIS_SWSM_SMBI BIT(0)
31b0801256SJiawen Wu #define WX_MIS_RST_ST 0x10030
32b0801256SJiawen Wu #define WX_MIS_RST_ST_RST_INI_SHIFT 8
33b0801256SJiawen Wu #define WX_MIS_RST_ST_RST_INIT (0xFF << WX_MIS_RST_ST_RST_INI_SHIFT)
34b0801256SJiawen Wu
35a34b3e6eSJiawen Wu /* FMGR Registers */
36a34b3e6eSJiawen Wu #define WX_SPI_CMD 0x10104
37a34b3e6eSJiawen Wu #define WX_SPI_CMD_READ_DWORD 0x1
38a34b3e6eSJiawen Wu #define WX_SPI_CLK_DIV 0x3
39860edff5SMengyuan Lou #define WX_SPI_CMD_CMD(_v) FIELD_PREP(GENMASK(30, 28), _v)
40860edff5SMengyuan Lou #define WX_SPI_CMD_CLK(_v) FIELD_PREP(GENMASK(27, 25), _v)
41860edff5SMengyuan Lou #define WX_SPI_CMD_ADDR(_v) FIELD_PREP(GENMASK(23, 0), _v)
42a34b3e6eSJiawen Wu #define WX_SPI_DATA 0x10108
43a34b3e6eSJiawen Wu #define WX_SPI_DATA_BYPASS BIT(31)
44a34b3e6eSJiawen Wu #define WX_SPI_DATA_OP_DONE BIT(0)
45a34b3e6eSJiawen Wu #define WX_SPI_STATUS 0x1010C
46a34b3e6eSJiawen Wu #define WX_SPI_STATUS_OPDONE BIT(0)
47a34b3e6eSJiawen Wu #define WX_SPI_STATUS_FLASH_BYPASS BIT(31)
48a34b3e6eSJiawen Wu #define WX_SPI_ILDR_STATUS 0x10120
49a34b3e6eSJiawen Wu
50b0801256SJiawen Wu /* Sensors for PVT(Process Voltage Temperature) */
51b0801256SJiawen Wu #define WX_TS_EN 0x10304
52b0801256SJiawen Wu #define WX_TS_EN_ENA BIT(0)
53b0801256SJiawen Wu #define WX_TS_ALARM_THRE 0x1030C
54b0801256SJiawen Wu #define WX_TS_DALARM_THRE 0x10310
55b0801256SJiawen Wu #define WX_TS_INT_EN 0x10314
56b0801256SJiawen Wu #define WX_TS_INT_EN_DALARM_INT_EN BIT(1)
57b0801256SJiawen Wu #define WX_TS_INT_EN_ALARM_INT_EN BIT(0)
58b0801256SJiawen Wu #define WX_TS_ALARM_ST 0x10318
59b0801256SJiawen Wu #define WX_TS_ALARM_ST_DALARM BIT(1)
60b0801256SJiawen Wu #define WX_TS_ALARM_ST_ALARM BIT(0)
61b0801256SJiawen Wu
621efa9bfeSJiawen Wu /************************* Port Registers ************************************/
631efa9bfeSJiawen Wu /* port cfg Registers */
641efa9bfeSJiawen Wu #define WX_CFG_PORT_CTL 0x14400
651efa9bfeSJiawen Wu #define WX_CFG_PORT_CTL_DRV_LOAD BIT(3)
6618b5b8a9SJiawen Wu #define WX_CFG_PORT_CTL_QINQ BIT(2)
6718b5b8a9SJiawen Wu #define WX_CFG_PORT_CTL_D_VLAN BIT(0) /* double vlan*/
6818b5b8a9SJiawen Wu #define WX_CFG_TAG_TPID(_i) (0x14430 + ((_i) * 4))
69f3b03c65SMengyuan Lou #define WX_CFG_PORT_CTL_NUM_VT_MASK GENMASK(13, 12) /* number of TVs */
70f3b03c65SMengyuan Lou
711efa9bfeSJiawen Wu
723f703186SMengyuan Lou /* GPIO Registers */
733f703186SMengyuan Lou #define WX_GPIO_DR 0x14800
743f703186SMengyuan Lou #define WX_GPIO_DR_0 BIT(0) /* SDP0 Data Value */
753f703186SMengyuan Lou #define WX_GPIO_DR_1 BIT(1) /* SDP1 Data Value */
763f703186SMengyuan Lou #define WX_GPIO_DDR 0x14804
773f703186SMengyuan Lou #define WX_GPIO_DDR_0 BIT(0) /* SDP0 IO direction */
783f703186SMengyuan Lou #define WX_GPIO_DDR_1 BIT(1) /* SDP1 IO direction */
793f703186SMengyuan Lou #define WX_GPIO_CTL 0x14808
803f703186SMengyuan Lou #define WX_GPIO_INTEN 0x14830
813f703186SMengyuan Lou #define WX_GPIO_INTEN_0 BIT(0)
823f703186SMengyuan Lou #define WX_GPIO_INTEN_1 BIT(1)
833f703186SMengyuan Lou #define WX_GPIO_INTMASK 0x14834
843f703186SMengyuan Lou #define WX_GPIO_INTTYPE_LEVEL 0x14838
853f703186SMengyuan Lou #define WX_GPIO_POLARITY 0x1483C
86b83c3731SJiawen Wu #define WX_GPIO_INTSTATUS 0x14844
873f703186SMengyuan Lou #define WX_GPIO_EOI 0x1484C
88b83c3731SJiawen Wu #define WX_GPIO_EXT 0x14850
893f703186SMengyuan Lou
90d21d2c7fSJiawen Wu /*********************** Transmit DMA registers **************************/
91d21d2c7fSJiawen Wu /* transmit global control */
92d21d2c7fSJiawen Wu #define WX_TDM_CTL 0x18000
93d21d2c7fSJiawen Wu /* TDM CTL BIT */
94d21d2c7fSJiawen Wu #define WX_TDM_CTL_TE BIT(0) /* Transmit Enable */
9518b5b8a9SJiawen Wu #define WX_TDM_PB_THRE(_i) (0x18020 + ((_i) * 4))
96f3b03c65SMengyuan Lou #define WX_TDM_RP_IDX 0x1820C
97f3b03c65SMengyuan Lou #define WX_TDM_RP_RATE 0x18404
98d21d2c7fSJiawen Wu
99b0801256SJiawen Wu /***************************** RDB registers *********************************/
100b0801256SJiawen Wu /* receive packet buffer */
101b0801256SJiawen Wu #define WX_RDB_PB_CTL 0x19000
102b0801256SJiawen Wu #define WX_RDB_PB_CTL_RXEN BIT(31) /* Enable Receiver */
103b0801256SJiawen Wu #define WX_RDB_PB_CTL_DISABLED BIT(0)
10418b5b8a9SJiawen Wu #define WX_RDB_PB_SZ(_i) (0x19020 + ((_i) * 4))
10518b5b8a9SJiawen Wu #define WX_RDB_PB_SZ_SHIFT 10
106b0801256SJiawen Wu /* statistic */
107b0801256SJiawen Wu #define WX_RDB_PFCMACDAL 0x19210
108b0801256SJiawen Wu #define WX_RDB_PFCMACDAH 0x19214
10918b5b8a9SJiawen Wu /* ring assignment */
11018b5b8a9SJiawen Wu #define WX_RDB_PL_CFG(_i) (0x19300 + ((_i) * 4))
11118b5b8a9SJiawen Wu #define WX_RDB_PL_CFG_L4HDR BIT(1)
11218b5b8a9SJiawen Wu #define WX_RDB_PL_CFG_L3HDR BIT(2)
11318b5b8a9SJiawen Wu #define WX_RDB_PL_CFG_L2HDR BIT(3)
11418b5b8a9SJiawen Wu #define WX_RDB_PL_CFG_TUN_TUNHDR BIT(4)
11518b5b8a9SJiawen Wu #define WX_RDB_PL_CFG_TUN_OUTL2HDR BIT(5)
1166dbedcffSMengyuan Lou #define WX_RDB_RA_CTL 0x194F4
1176dbedcffSMengyuan Lou #define WX_RDB_RA_CTL_RSS_EN BIT(2) /* RSS Enable */
118b0801256SJiawen Wu
119b0801256SJiawen Wu /******************************* PSR Registers *******************************/
120b0801256SJiawen Wu /* psr control */
121b0801256SJiawen Wu #define WX_PSR_CTL 0x15000
122b0801256SJiawen Wu /* Header split receive */
123b0801256SJiawen Wu #define WX_PSR_CTL_SW_EN BIT(18)
124b0801256SJiawen Wu #define WX_PSR_CTL_RSC_ACK BIT(17)
125b0801256SJiawen Wu #define WX_PSR_CTL_RSC_DIS BIT(16)
126b0801256SJiawen Wu #define WX_PSR_CTL_PCSD BIT(13)
127b0801256SJiawen Wu #define WX_PSR_CTL_IPPCSE BIT(12)
128b0801256SJiawen Wu #define WX_PSR_CTL_BAM BIT(10)
129b0801256SJiawen Wu #define WX_PSR_CTL_UPE BIT(9)
130b0801256SJiawen Wu #define WX_PSR_CTL_MPE BIT(8)
131b0801256SJiawen Wu #define WX_PSR_CTL_MFE BIT(7)
132b0801256SJiawen Wu #define WX_PSR_CTL_MO_SHIFT 5
133b0801256SJiawen Wu #define WX_PSR_CTL_MO (0x3 << WX_PSR_CTL_MO_SHIFT)
134b0801256SJiawen Wu #define WX_PSR_CTL_TPE BIT(4)
13518b5b8a9SJiawen Wu #define WX_PSR_MAX_SZ 0x15020
13618b5b8a9SJiawen Wu #define WX_PSR_VLAN_CTL 0x15088
13718b5b8a9SJiawen Wu #define WX_PSR_VLAN_CTL_CFIEN BIT(29) /* bit 29 */
13818b5b8a9SJiawen Wu #define WX_PSR_VLAN_CTL_VFE BIT(30) /* bit 30 */
139d21d2c7fSJiawen Wu /* mcasst/ucast overflow tbl */
140d21d2c7fSJiawen Wu #define WX_PSR_MC_TBL(_i) (0x15200 + ((_i) * 4))
141d21d2c7fSJiawen Wu #define WX_PSR_UC_TBL(_i) (0x15400 + ((_i) * 4))
142b0801256SJiawen Wu
14318b5b8a9SJiawen Wu /* VM L2 contorl */
14418b5b8a9SJiawen Wu #define WX_PSR_VM_L2CTL(_i) (0x15600 + ((_i) * 4))
14518b5b8a9SJiawen Wu #define WX_PSR_VM_L2CTL_UPE BIT(4) /* unicast promiscuous */
14618b5b8a9SJiawen Wu #define WX_PSR_VM_L2CTL_VACC BIT(6) /* accept nomatched vlan */
14718b5b8a9SJiawen Wu #define WX_PSR_VM_L2CTL_AUPE BIT(8) /* accept untagged packets */
14818b5b8a9SJiawen Wu #define WX_PSR_VM_L2CTL_ROMPE BIT(9) /* accept packets in MTA tbl */
14918b5b8a9SJiawen Wu #define WX_PSR_VM_L2CTL_ROPE BIT(10) /* accept packets in UC tbl */
15018b5b8a9SJiawen Wu #define WX_PSR_VM_L2CTL_BAM BIT(11) /* accept broadcast packets */
15118b5b8a9SJiawen Wu #define WX_PSR_VM_L2CTL_MPE BIT(12) /* multicast promiscuous */
15218b5b8a9SJiawen Wu
153b0801256SJiawen Wu /* Management */
154b0801256SJiawen Wu #define WX_PSR_MNG_FLEX_SEL 0x1582C
155b0801256SJiawen Wu #define WX_PSR_MNG_FLEX_DW_L(_i) (0x15A00 + ((_i) * 16))
156b0801256SJiawen Wu #define WX_PSR_MNG_FLEX_DW_H(_i) (0x15A04 + ((_i) * 16))
157b0801256SJiawen Wu #define WX_PSR_MNG_FLEX_MSK(_i) (0x15A08 + ((_i) * 16))
158b0801256SJiawen Wu #define WX_PSR_LAN_FLEX_SEL 0x15B8C
159b0801256SJiawen Wu #define WX_PSR_LAN_FLEX_DW_L(_i) (0x15C00 + ((_i) * 16))
160b0801256SJiawen Wu #define WX_PSR_LAN_FLEX_DW_H(_i) (0x15C04 + ((_i) * 16))
161b0801256SJiawen Wu #define WX_PSR_LAN_FLEX_MSK(_i) (0x15C08 + ((_i) * 16))
162b0801256SJiawen Wu
1636963e463SMengyuan Lou #define WX_PSR_WKUP_CTL 0x15B80
1646963e463SMengyuan Lou /* Wake Up Filter Control Bit */
1656963e463SMengyuan Lou #define WX_PSR_WKUP_CTL_MAG BIT(1) /* Magic Packet Wakeup Enable */
1666963e463SMengyuan Lou
167f3b03c65SMengyuan Lou /* vlan tbl */
168f3b03c65SMengyuan Lou #define WX_PSR_VLAN_TBL(_i) (0x16000 + ((_i) * 4))
169f3b03c65SMengyuan Lou
170d21d2c7fSJiawen Wu /* mac switcher */
171d21d2c7fSJiawen Wu #define WX_PSR_MAC_SWC_AD_L 0x16200
172d21d2c7fSJiawen Wu #define WX_PSR_MAC_SWC_AD_H 0x16204
173860edff5SMengyuan Lou #define WX_PSR_MAC_SWC_AD_H_AD(v) FIELD_PREP(U16_MAX, v)
174860edff5SMengyuan Lou #define WX_PSR_MAC_SWC_AD_H_ADTYPE(v) FIELD_PREP(BIT(30), v)
175d21d2c7fSJiawen Wu #define WX_PSR_MAC_SWC_AD_H_AV BIT(31)
176d21d2c7fSJiawen Wu #define WX_PSR_MAC_SWC_VM_L 0x16208
177d21d2c7fSJiawen Wu #define WX_PSR_MAC_SWC_VM_H 0x1620C
178d21d2c7fSJiawen Wu #define WX_PSR_MAC_SWC_IDX 0x16210
179d21d2c7fSJiawen Wu #define WX_CLEAR_VMDQ_ALL 0xFFFFFFFFU
180d21d2c7fSJiawen Wu
181f3b03c65SMengyuan Lou /* vlan switch */
182f3b03c65SMengyuan Lou #define WX_PSR_VLAN_SWC 0x16220
183f3b03c65SMengyuan Lou #define WX_PSR_VLAN_SWC_VM_L 0x16224
184f3b03c65SMengyuan Lou #define WX_PSR_VLAN_SWC_VM_H 0x16228
185f3b03c65SMengyuan Lou #define WX_PSR_VLAN_SWC_IDX 0x16230 /* 64 vlan entries */
186f3b03c65SMengyuan Lou /* VLAN pool filtering masks */
187f3b03c65SMengyuan Lou #define WX_PSR_VLAN_SWC_VIEN BIT(31) /* filter is valid */
188f3b03c65SMengyuan Lou #define WX_PSR_VLAN_SWC_ENTRIES 64
189f3b03c65SMengyuan Lou
19018b5b8a9SJiawen Wu /********************************* RSEC **************************************/
19118b5b8a9SJiawen Wu /* general rsec */
19218b5b8a9SJiawen Wu #define WX_RSC_CTL 0x17000
19318b5b8a9SJiawen Wu #define WX_RSC_CTL_SAVE_MAC_ERR BIT(6)
19418b5b8a9SJiawen Wu #define WX_RSC_CTL_CRC_STRIP BIT(2)
19518b5b8a9SJiawen Wu #define WX_RSC_CTL_RX_DIS BIT(1)
19618b5b8a9SJiawen Wu #define WX_RSC_ST 0x17004
19718b5b8a9SJiawen Wu #define WX_RSC_ST_RSEC_RDY BIT(0)
19818b5b8a9SJiawen Wu
19918b5b8a9SJiawen Wu /****************************** TDB ******************************************/
20018b5b8a9SJiawen Wu #define WX_TDB_PB_SZ(_i) (0x1CC00 + ((_i) * 4))
20118b5b8a9SJiawen Wu #define WX_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */
20218b5b8a9SJiawen Wu
20318b5b8a9SJiawen Wu /****************************** TSEC *****************************************/
20418b5b8a9SJiawen Wu /* Security Control Registers */
20518b5b8a9SJiawen Wu #define WX_TSC_CTL 0x1D000
20618b5b8a9SJiawen Wu #define WX_TSC_CTL_TX_DIS BIT(1)
20718b5b8a9SJiawen Wu #define WX_TSC_CTL_TSEC_DIS BIT(0)
208a4414dd1SJiawen Wu #define WX_TSC_ST 0x1D004
209a4414dd1SJiawen Wu #define WX_TSC_ST_SECTX_RDY BIT(0)
21018b5b8a9SJiawen Wu #define WX_TSC_BUF_AE 0x1D00C
21118b5b8a9SJiawen Wu #define WX_TSC_BUF_AE_THR GENMASK(9, 0)
21218b5b8a9SJiawen Wu
2131efa9bfeSJiawen Wu /************************************** MNG ********************************/
2141efa9bfeSJiawen Wu #define WX_MNG_SWFW_SYNC 0x1E008
2151efa9bfeSJiawen Wu #define WX_MNG_SWFW_SYNC_SW_MB BIT(2)
2161efa9bfeSJiawen Wu #define WX_MNG_SWFW_SYNC_SW_FLASH BIT(3)
2171efa9bfeSJiawen Wu #define WX_MNG_MBOX 0x1E100
2181efa9bfeSJiawen Wu #define WX_MNG_MBOX_CTL 0x1E044
2191efa9bfeSJiawen Wu #define WX_MNG_MBOX_CTL_SWRDY BIT(0)
2201efa9bfeSJiawen Wu #define WX_MNG_MBOX_CTL_FWRDY BIT(2)
2211efa9bfeSJiawen Wu
222b0801256SJiawen Wu /************************************* ETH MAC *****************************/
223d21d2c7fSJiawen Wu #define WX_MAC_TX_CFG 0x11000
224d21d2c7fSJiawen Wu #define WX_MAC_TX_CFG_TE BIT(0)
225a1cf597bSMengyuan Lou #define WX_MAC_TX_CFG_SPEED_MASK GENMASK(30, 29)
2260ef7e159SJiawen Wu #define WX_MAC_TX_CFG_SPEED_10G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 0)
227860edff5SMengyuan Lou #define WX_MAC_TX_CFG_SPEED_1G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 3)
228b0801256SJiawen Wu #define WX_MAC_RX_CFG 0x11004
229b0801256SJiawen Wu #define WX_MAC_RX_CFG_RE BIT(0)
230b0801256SJiawen Wu #define WX_MAC_RX_CFG_JE BIT(8)
231b0801256SJiawen Wu #define WX_MAC_PKT_FLT 0x11008
232b0801256SJiawen Wu #define WX_MAC_PKT_FLT_PR BIT(0) /* promiscuous mode */
233a1cf597bSMengyuan Lou #define WX_MAC_WDG_TIMEOUT 0x1100C
234b0801256SJiawen Wu #define WX_MAC_RX_FLOW_CTRL 0x11090
235b0801256SJiawen Wu #define WX_MAC_RX_FLOW_CTRL_RFE BIT(0) /* receive fc enable */
236*02b2a6f9SJiawen Wu /* MDIO Registers */
237*02b2a6f9SJiawen Wu #define WX_MSCA 0x11200
238*02b2a6f9SJiawen Wu #define WX_MSCA_RA(v) FIELD_PREP(U16_MAX, v)
239*02b2a6f9SJiawen Wu #define WX_MSCA_PA(v) FIELD_PREP(GENMASK(20, 16), v)
240*02b2a6f9SJiawen Wu #define WX_MSCA_DA(v) FIELD_PREP(GENMASK(25, 21), v)
241*02b2a6f9SJiawen Wu #define WX_MSCC 0x11204
242*02b2a6f9SJiawen Wu #define WX_MSCC_CMD(v) FIELD_PREP(GENMASK(17, 16), v)
243*02b2a6f9SJiawen Wu
244*02b2a6f9SJiawen Wu enum WX_MSCA_CMD_value {
245*02b2a6f9SJiawen Wu WX_MSCA_CMD_RSV = 0,
246*02b2a6f9SJiawen Wu WX_MSCA_CMD_WRITE,
247*02b2a6f9SJiawen Wu WX_MSCA_CMD_POST_READ,
248*02b2a6f9SJiawen Wu WX_MSCA_CMD_READ,
249*02b2a6f9SJiawen Wu };
250*02b2a6f9SJiawen Wu
251*02b2a6f9SJiawen Wu #define WX_MSCC_SADDR BIT(18)
252*02b2a6f9SJiawen Wu #define WX_MSCC_BUSY BIT(22)
253*02b2a6f9SJiawen Wu #define WX_MDIO_CLK(v) FIELD_PREP(GENMASK(21, 19), v)
254b0801256SJiawen Wu #define WX_MMC_CONTROL 0x11800
255b0801256SJiawen Wu #define WX_MMC_CONTROL_RSTONRD BIT(2) /* reset on read */
256b0801256SJiawen Wu
257b0801256SJiawen Wu /********************************* BAR registers ***************************/
258b0801256SJiawen Wu /* Interrupt Registers */
259b0801256SJiawen Wu #define WX_BME_CTL 0x12020
260b0801256SJiawen Wu #define WX_PX_MISC_IC 0x100
2613f703186SMengyuan Lou #define WX_PX_MISC_ICS 0x104
2623f703186SMengyuan Lou #define WX_PX_MISC_IEN 0x108
2633f703186SMengyuan Lou #define WX_PX_INTA 0x110
2643f703186SMengyuan Lou #define WX_PX_GPIE 0x118
2653f703186SMengyuan Lou #define WX_PX_GPIE_MODEL BIT(0)
26659513714SJiawen Wu #define WX_PX_IC(_i) (0x120 + (_i) * 4)
267b0801256SJiawen Wu #define WX_PX_IMS(_i) (0x140 + (_i) * 4)
2683f703186SMengyuan Lou #define WX_PX_IMC(_i) (0x150 + (_i) * 4)
2693f703186SMengyuan Lou #define WX_PX_ISB_ADDR_L 0x160
2703f703186SMengyuan Lou #define WX_PX_ISB_ADDR_H 0x164
271b0801256SJiawen Wu #define WX_PX_TRANSACTION_PENDING 0x168
2723f703186SMengyuan Lou #define WX_PX_ITRSEL 0x180
2733f703186SMengyuan Lou #define WX_PX_ITR(_i) (0x200 + (_i) * 4)
2743f703186SMengyuan Lou #define WX_PX_ITR_CNT_WDIS BIT(31)
2753f703186SMengyuan Lou #define WX_PX_MISC_IVAR 0x4FC
2763f703186SMengyuan Lou #define WX_PX_IVAR(_i) (0x500 + (_i) * 4)
2773f703186SMengyuan Lou
2783f703186SMengyuan Lou #define WX_PX_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
2793f703186SMengyuan Lou #define WX_7K_ITR 595
2803f703186SMengyuan Lou #define WX_12K_ITR 336
2813f703186SMengyuan Lou #define WX_SP_MAX_EITR 0x00000FF8U
2823f703186SMengyuan Lou #define WX_EM_MAX_EITR 0x00007FFCU
283b0801256SJiawen Wu
284b0801256SJiawen Wu /* transmit DMA Registers */
28518b5b8a9SJiawen Wu #define WX_PX_TR_BAL(_i) (0x03000 + ((_i) * 0x40))
28618b5b8a9SJiawen Wu #define WX_PX_TR_BAH(_i) (0x03004 + ((_i) * 0x40))
28718b5b8a9SJiawen Wu #define WX_PX_TR_WP(_i) (0x03008 + ((_i) * 0x40))
28818b5b8a9SJiawen Wu #define WX_PX_TR_RP(_i) (0x0300C + ((_i) * 0x40))
289b0801256SJiawen Wu #define WX_PX_TR_CFG(_i) (0x03010 + ((_i) * 0x40))
290b0801256SJiawen Wu /* Transmit Config masks */
291b0801256SJiawen Wu #define WX_PX_TR_CFG_ENABLE BIT(0) /* Ena specific Tx Queue */
292b0801256SJiawen Wu #define WX_PX_TR_CFG_TR_SIZE_SHIFT 1 /* tx desc number per ring */
293b0801256SJiawen Wu #define WX_PX_TR_CFG_SWFLSH BIT(26) /* Tx Desc. wr-bk flushing */
294b0801256SJiawen Wu #define WX_PX_TR_CFG_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
295b0801256SJiawen Wu #define WX_PX_TR_CFG_THRE_SHIFT 8
296b0801256SJiawen Wu
297b0801256SJiawen Wu /* Receive DMA Registers */
29818b5b8a9SJiawen Wu #define WX_PX_RR_BAL(_i) (0x01000 + ((_i) * 0x40))
29918b5b8a9SJiawen Wu #define WX_PX_RR_BAH(_i) (0x01004 + ((_i) * 0x40))
30018b5b8a9SJiawen Wu #define WX_PX_RR_WP(_i) (0x01008 + ((_i) * 0x40))
30118b5b8a9SJiawen Wu #define WX_PX_RR_RP(_i) (0x0100C + ((_i) * 0x40))
302b0801256SJiawen Wu #define WX_PX_RR_CFG(_i) (0x01010 + ((_i) * 0x40))
303b0801256SJiawen Wu /* PX_RR_CFG bit definitions */
304f3b03c65SMengyuan Lou #define WX_PX_RR_CFG_VLAN BIT(31)
30518b5b8a9SJiawen Wu #define WX_PX_RR_CFG_SPLIT_MODE BIT(26)
30618b5b8a9SJiawen Wu #define WX_PX_RR_CFG_RR_THER_SHIFT 16
30718b5b8a9SJiawen Wu #define WX_PX_RR_CFG_RR_HDR_SZ GENMASK(15, 12)
30818b5b8a9SJiawen Wu #define WX_PX_RR_CFG_RR_BUF_SZ GENMASK(11, 8)
30918b5b8a9SJiawen Wu #define WX_PX_RR_CFG_BHDRSIZE_SHIFT 6 /* 64byte resolution (>> 6)
31018b5b8a9SJiawen Wu * + at bit 8 offset (<< 12)
31118b5b8a9SJiawen Wu * = (<< 6)
31218b5b8a9SJiawen Wu */
31318b5b8a9SJiawen Wu #define WX_PX_RR_CFG_BSIZEPKT_SHIFT 2 /* so many KBs */
31418b5b8a9SJiawen Wu #define WX_PX_RR_CFG_RR_SIZE_SHIFT 1
315b0801256SJiawen Wu #define WX_PX_RR_CFG_RR_EN BIT(0)
316b0801256SJiawen Wu
317b0801256SJiawen Wu /* Number of 80 microseconds we wait for PCI Express master disable */
318b0801256SJiawen Wu #define WX_PCI_MASTER_DISABLE_TIMEOUT 80000
319b0801256SJiawen Wu
3201efa9bfeSJiawen Wu /****************** Manageablility Host Interface defines ********************/
3211efa9bfeSJiawen Wu #define WX_HI_MAX_BLOCK_BYTE_LENGTH 256 /* Num of bytes in range */
3221efa9bfeSJiawen Wu #define WX_HI_COMMAND_TIMEOUT 1000 /* Process HI command limit */
3231efa9bfeSJiawen Wu
3241efa9bfeSJiawen Wu #define FW_READ_SHADOW_RAM_CMD 0x31
3251efa9bfeSJiawen Wu #define FW_READ_SHADOW_RAM_LEN 0x6
3261efa9bfeSJiawen Wu #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */
3271efa9bfeSJiawen Wu #define FW_NVM_DATA_OFFSET 3
3281efa9bfeSJiawen Wu #define FW_MAX_READ_BUFFER_SIZE 244
3291efa9bfeSJiawen Wu #define FW_RESET_CMD 0xDF
3301efa9bfeSJiawen Wu #define FW_RESET_LEN 0x2
3311efa9bfeSJiawen Wu #define FW_CEM_HDR_LEN 0x4
3321efa9bfeSJiawen Wu #define FW_CEM_CMD_RESERVED 0X0
3331efa9bfeSJiawen Wu #define FW_CEM_MAX_RETRIES 3
3341efa9bfeSJiawen Wu #define FW_CEM_RESP_STATUS_SUCCESS 0x1
3351efa9bfeSJiawen Wu
3361efa9bfeSJiawen Wu #define WX_SW_REGION_PTR 0x1C
3371efa9bfeSJiawen Wu
33879625f45SJiawen Wu #define WX_MAC_STATE_DEFAULT 0x1
33979625f45SJiawen Wu #define WX_MAC_STATE_MODIFIED 0x2
34079625f45SJiawen Wu #define WX_MAC_STATE_IN_USE 0x4
34179625f45SJiawen Wu
34218b5b8a9SJiawen Wu #define WX_MAX_RXD 8192
34318b5b8a9SJiawen Wu #define WX_MAX_TXD 8192
34418b5b8a9SJiawen Wu
34581dc0741SMengyuan Lou #define WX_MAX_JUMBO_FRAME_SIZE 9432 /* max payload 9414 */
346f3b03c65SMengyuan Lou #define VMDQ_P(p) p
34781dc0741SMengyuan Lou
34818b5b8a9SJiawen Wu /* Supported Rx Buffer Sizes */
34918b5b8a9SJiawen Wu #define WX_RXBUFFER_256 256 /* Used for skb receive header */
35018b5b8a9SJiawen Wu #define WX_RXBUFFER_2K 2048
35118b5b8a9SJiawen Wu #define WX_MAX_RXBUFFER 16384 /* largest size for single descriptor */
35218b5b8a9SJiawen Wu
35318b5b8a9SJiawen Wu #if MAX_SKB_FRAGS < 8
35418b5b8a9SJiawen Wu #define WX_RX_BUFSZ ALIGN(WX_MAX_RXBUFFER / MAX_SKB_FRAGS, 1024)
35518b5b8a9SJiawen Wu #else
35618b5b8a9SJiawen Wu #define WX_RX_BUFSZ WX_RXBUFFER_2K
35718b5b8a9SJiawen Wu #endif
35818b5b8a9SJiawen Wu
3593c47e8aeSJiawen Wu #define WX_RX_BUFFER_WRITE 16 /* Must be power of 2 */
36009a50880SMengyuan Lou
36109a50880SMengyuan Lou #define WX_MAX_DATA_PER_TXD BIT(14)
36209a50880SMengyuan Lou /* Tx Descriptors needed, worst case */
36309a50880SMengyuan Lou #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), WX_MAX_DATA_PER_TXD)
36409a50880SMengyuan Lou #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
36509a50880SMengyuan Lou
366803df55dSMengyuan Lou #define WX_CFG_PORT_ST 0x14404
367803df55dSMengyuan Lou
3683c47e8aeSJiawen Wu /******************* Receive Descriptor bit definitions **********************/
3693c47e8aeSJiawen Wu #define WX_RXD_STAT_DD BIT(0) /* Done */
3703c47e8aeSJiawen Wu #define WX_RXD_STAT_EOP BIT(1) /* End of Packet */
371f3b03c65SMengyuan Lou #define WX_RXD_STAT_VP BIT(5) /* IEEE VLAN Pkt */
372ef4f3c19SMengyuan Lou #define WX_RXD_STAT_L4CS BIT(7) /* L4 xsum calculated */
373ef4f3c19SMengyuan Lou #define WX_RXD_STAT_IPCS BIT(8) /* IP xsum calculated */
374ef4f3c19SMengyuan Lou #define WX_RXD_STAT_OUTERIPCS BIT(10) /* Cloud IP xsum calculated*/
3753c47e8aeSJiawen Wu
376ef4f3c19SMengyuan Lou #define WX_RXD_ERR_OUTERIPER BIT(26) /* CRC IP Header error */
3773c47e8aeSJiawen Wu #define WX_RXD_ERR_RXE BIT(29) /* Any MAC Error */
378ef4f3c19SMengyuan Lou #define WX_RXD_ERR_TCPE BIT(30) /* TCP/UDP Checksum Error */
379ef4f3c19SMengyuan Lou #define WX_RXD_ERR_IPE BIT(31) /* IP Checksum Error */
3803c47e8aeSJiawen Wu
381ef4f3c19SMengyuan Lou /* RSS Hash results */
382ef4f3c19SMengyuan Lou #define WX_RXD_RSSTYPE_MASK GENMASK(3, 0)
383ef4f3c19SMengyuan Lou #define WX_RXD_RSSTYPE_IPV4_TCP 0x00000001U
384ef4f3c19SMengyuan Lou #define WX_RXD_RSSTYPE_IPV6_TCP 0x00000003U
385ef4f3c19SMengyuan Lou #define WX_RXD_RSSTYPE_IPV4_SCTP 0x00000004U
386ef4f3c19SMengyuan Lou #define WX_RXD_RSSTYPE_IPV6_SCTP 0x00000006U
387ef4f3c19SMengyuan Lou #define WX_RXD_RSSTYPE_IPV4_UDP 0x00000007U
388ef4f3c19SMengyuan Lou #define WX_RXD_RSSTYPE_IPV6_UDP 0x00000008U
389ef4f3c19SMengyuan Lou
390ef4f3c19SMengyuan Lou #define WX_RSS_L4_TYPES_MASK \
391ef4f3c19SMengyuan Lou ((1ul << WX_RXD_RSSTYPE_IPV4_TCP) | \
392ef4f3c19SMengyuan Lou (1ul << WX_RXD_RSSTYPE_IPV4_UDP) | \
393ef4f3c19SMengyuan Lou (1ul << WX_RXD_RSSTYPE_IPV4_SCTP) | \
394ef4f3c19SMengyuan Lou (1ul << WX_RXD_RSSTYPE_IPV6_TCP) | \
395ef4f3c19SMengyuan Lou (1ul << WX_RXD_RSSTYPE_IPV6_UDP) | \
396ef4f3c19SMengyuan Lou (1ul << WX_RXD_RSSTYPE_IPV6_SCTP))
3973403960cSMengyuan Lou /* TUN */
3983403960cSMengyuan Lou #define WX_PTYPE_TUN_IPV4 0x80
3993403960cSMengyuan Lou #define WX_PTYPE_TUN_IPV6 0xC0
4003403960cSMengyuan Lou
4013403960cSMengyuan Lou /* PKT for TUN */
4023403960cSMengyuan Lou #define WX_PTYPE_PKT_IPIP 0x00 /* IP+IP */
4033403960cSMengyuan Lou #define WX_PTYPE_PKT_IG 0x10 /* IP+GRE */
4043403960cSMengyuan Lou #define WX_PTYPE_PKT_IGM 0x20 /* IP+GRE+MAC */
4053403960cSMengyuan Lou #define WX_PTYPE_PKT_IGMV 0x30 /* IP+GRE+MAC+VLAN */
4063403960cSMengyuan Lou /* PKT for !TUN */
4073403960cSMengyuan Lou #define WX_PTYPE_PKT_MAC 0x10
4083403960cSMengyuan Lou #define WX_PTYPE_PKT_IP 0x20
4093403960cSMengyuan Lou
4103403960cSMengyuan Lou /* TYP for PKT=mac */
4113403960cSMengyuan Lou #define WX_PTYPE_TYP_MAC 0x01
4123403960cSMengyuan Lou /* TYP for PKT=ip */
4133403960cSMengyuan Lou #define WX_PTYPE_PKT_IPV6 0x08
4143403960cSMengyuan Lou #define WX_PTYPE_TYP_IPFRAG 0x01
4153403960cSMengyuan Lou #define WX_PTYPE_TYP_IP 0x02
4163403960cSMengyuan Lou #define WX_PTYPE_TYP_UDP 0x03
4173403960cSMengyuan Lou #define WX_PTYPE_TYP_TCP 0x04
4183403960cSMengyuan Lou #define WX_PTYPE_TYP_SCTP 0x05
4193403960cSMengyuan Lou
420ef4f3c19SMengyuan Lou #define WX_RXD_PKTTYPE(_rxd) \
421ef4f3c19SMengyuan Lou ((le32_to_cpu((_rxd)->wb.lower.lo_dword.data) >> 9) & 0xFF)
422ef4f3c19SMengyuan Lou #define WX_RXD_IPV6EX(_rxd) \
423ef4f3c19SMengyuan Lou ((le32_to_cpu((_rxd)->wb.lower.lo_dword.data) >> 6) & 0x1)
42409a50880SMengyuan Lou /*********************** Transmit Descriptor Config Masks ****************/
42509a50880SMengyuan Lou #define WX_TXD_STAT_DD BIT(0) /* Descriptor Done */
42609a50880SMengyuan Lou #define WX_TXD_DTYP_DATA 0 /* Adv Data Descriptor */
42709a50880SMengyuan Lou #define WX_TXD_PAYLEN_SHIFT 13 /* Desc PAYLEN shift */
42809a50880SMengyuan Lou #define WX_TXD_EOP BIT(24) /* End of Packet */
42909a50880SMengyuan Lou #define WX_TXD_IFCS BIT(25) /* Insert FCS */
43009a50880SMengyuan Lou #define WX_TXD_RS BIT(27) /* Report Status */
43109a50880SMengyuan Lou
4323403960cSMengyuan Lou /*********************** Adv Transmit Descriptor Config Masks ****************/
4333403960cSMengyuan Lou #define WX_TXD_MAC_TSTAMP BIT(19) /* IEEE1588 time stamp */
4343403960cSMengyuan Lou #define WX_TXD_DTYP_CTXT BIT(20) /* Adv Context Desc */
4353403960cSMengyuan Lou #define WX_TXD_LINKSEC BIT(26) /* enable linksec */
4363403960cSMengyuan Lou #define WX_TXD_VLE BIT(30) /* VLAN pkt enable */
4373403960cSMengyuan Lou #define WX_TXD_TSE BIT(31) /* TCP Seg enable */
4383403960cSMengyuan Lou #define WX_TXD_CC BIT(7) /* Check Context */
4393403960cSMengyuan Lou #define WX_TXD_IPSEC BIT(8) /* enable ipsec esp */
4403403960cSMengyuan Lou #define WX_TXD_L4CS BIT(9)
4413403960cSMengyuan Lou #define WX_TXD_IIPCS BIT(10)
4423403960cSMengyuan Lou #define WX_TXD_EIPCS BIT(11)
4433403960cSMengyuan Lou #define WX_TXD_PAYLEN_SHIFT 13 /* Adv desc PAYLEN shift */
4443403960cSMengyuan Lou #define WX_TXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
4453403960cSMengyuan Lou #define WX_TXD_TAG_TPID_SEL_SHIFT 11
4463403960cSMengyuan Lou
4473403960cSMengyuan Lou #define WX_TXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
4483403960cSMengyuan Lou #define WX_TXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
4493403960cSMengyuan Lou
4503403960cSMengyuan Lou #define WX_TXD_OUTER_IPLEN_SHIFT 12 /* Adv ctxt OUTERIPLEN shift */
4513403960cSMengyuan Lou #define WX_TXD_TUNNEL_LEN_SHIFT 21 /* Adv ctxt TUNNELLEN shift */
4523403960cSMengyuan Lou #define WX_TXD_TUNNEL_TYPE_SHIFT 11 /* Adv Tx Desc Tunnel Type shift */
4533403960cSMengyuan Lou #define WX_TXD_TUNNEL_UDP FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 0)
4543403960cSMengyuan Lou #define WX_TXD_TUNNEL_GRE FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 1)
4553403960cSMengyuan Lou
4563403960cSMengyuan Lou enum wx_tx_flags {
4573403960cSMengyuan Lou /* cmd_type flags */
4583403960cSMengyuan Lou WX_TX_FLAGS_HW_VLAN = 0x01,
4593403960cSMengyuan Lou WX_TX_FLAGS_TSO = 0x02,
4603403960cSMengyuan Lou WX_TX_FLAGS_TSTAMP = 0x04,
4613403960cSMengyuan Lou
4623403960cSMengyuan Lou /* olinfo flags */
4633403960cSMengyuan Lou WX_TX_FLAGS_CC = 0x08,
4643403960cSMengyuan Lou WX_TX_FLAGS_IPV4 = 0x10,
4653403960cSMengyuan Lou WX_TX_FLAGS_CSUM = 0x20,
4663403960cSMengyuan Lou WX_TX_FLAGS_OUTER_IPV4 = 0x100,
4673403960cSMengyuan Lou WX_TX_FLAGS_LINKSEC = 0x200,
4683403960cSMengyuan Lou WX_TX_FLAGS_IPSEC = 0x400,
4693403960cSMengyuan Lou };
4703403960cSMengyuan Lou
4713403960cSMengyuan Lou /* VLAN info */
4723403960cSMengyuan Lou #define WX_TX_FLAGS_VLAN_MASK GENMASK(31, 16)
4733403960cSMengyuan Lou #define WX_TX_FLAGS_VLAN_SHIFT 16
4743403960cSMengyuan Lou
475ef4f3c19SMengyuan Lou /* wx_dec_ptype.mac: outer mac */
476ef4f3c19SMengyuan Lou enum wx_dec_ptype_mac {
477ef4f3c19SMengyuan Lou WX_DEC_PTYPE_MAC_IP = 0,
478ef4f3c19SMengyuan Lou WX_DEC_PTYPE_MAC_L2 = 2,
479ef4f3c19SMengyuan Lou WX_DEC_PTYPE_MAC_FCOE = 3,
480ef4f3c19SMengyuan Lou };
481ef4f3c19SMengyuan Lou
482ef4f3c19SMengyuan Lou /* wx_dec_ptype.[e]ip: outer&encaped ip */
483ef4f3c19SMengyuan Lou #define WX_DEC_PTYPE_IP_FRAG 0x4
484ef4f3c19SMengyuan Lou enum wx_dec_ptype_ip {
485ef4f3c19SMengyuan Lou WX_DEC_PTYPE_IP_NONE = 0,
486ef4f3c19SMengyuan Lou WX_DEC_PTYPE_IP_IPV4 = 1,
487ef4f3c19SMengyuan Lou WX_DEC_PTYPE_IP_IPV6 = 2,
488ef4f3c19SMengyuan Lou WX_DEC_PTYPE_IP_FGV4 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV4,
489ef4f3c19SMengyuan Lou WX_DEC_PTYPE_IP_FGV6 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV6,
490ef4f3c19SMengyuan Lou };
491ef4f3c19SMengyuan Lou
492ef4f3c19SMengyuan Lou /* wx_dec_ptype.etype: encaped type */
493ef4f3c19SMengyuan Lou enum wx_dec_ptype_etype {
494ef4f3c19SMengyuan Lou WX_DEC_PTYPE_ETYPE_NONE = 0,
495ef4f3c19SMengyuan Lou WX_DEC_PTYPE_ETYPE_IPIP = 1, /* IP+IP */
496ef4f3c19SMengyuan Lou WX_DEC_PTYPE_ETYPE_IG = 2, /* IP+GRE */
497ef4f3c19SMengyuan Lou WX_DEC_PTYPE_ETYPE_IGM = 3, /* IP+GRE+MAC */
498ef4f3c19SMengyuan Lou WX_DEC_PTYPE_ETYPE_IGMV = 4, /* IP+GRE+MAC+VLAN */
499ef4f3c19SMengyuan Lou };
500ef4f3c19SMengyuan Lou
501ef4f3c19SMengyuan Lou /* wx_dec_ptype.proto: payload proto */
502ef4f3c19SMengyuan Lou enum wx_dec_ptype_prot {
503ef4f3c19SMengyuan Lou WX_DEC_PTYPE_PROT_NONE = 0,
504ef4f3c19SMengyuan Lou WX_DEC_PTYPE_PROT_UDP = 1,
505ef4f3c19SMengyuan Lou WX_DEC_PTYPE_PROT_TCP = 2,
506ef4f3c19SMengyuan Lou WX_DEC_PTYPE_PROT_SCTP = 3,
507ef4f3c19SMengyuan Lou WX_DEC_PTYPE_PROT_ICMP = 4,
508ef4f3c19SMengyuan Lou WX_DEC_PTYPE_PROT_TS = 5, /* time sync */
509ef4f3c19SMengyuan Lou };
510ef4f3c19SMengyuan Lou
511ef4f3c19SMengyuan Lou /* wx_dec_ptype.layer: payload layer */
512ef4f3c19SMengyuan Lou enum wx_dec_ptype_layer {
513ef4f3c19SMengyuan Lou WX_DEC_PTYPE_LAYER_NONE = 0,
514ef4f3c19SMengyuan Lou WX_DEC_PTYPE_LAYER_PAY2 = 1,
515ef4f3c19SMengyuan Lou WX_DEC_PTYPE_LAYER_PAY3 = 2,
516ef4f3c19SMengyuan Lou WX_DEC_PTYPE_LAYER_PAY4 = 3,
517ef4f3c19SMengyuan Lou };
518ef4f3c19SMengyuan Lou
519ef4f3c19SMengyuan Lou struct wx_dec_ptype {
520ef4f3c19SMengyuan Lou u32 known:1;
521ef4f3c19SMengyuan Lou u32 mac:2; /* outer mac */
522ef4f3c19SMengyuan Lou u32 ip:3; /* outer ip*/
523ef4f3c19SMengyuan Lou u32 etype:3; /* encaped type */
524ef4f3c19SMengyuan Lou u32 eip:3; /* encaped ip */
525ef4f3c19SMengyuan Lou u32 prot:4; /* payload proto */
526ef4f3c19SMengyuan Lou u32 layer:3; /* payload layer */
527ef4f3c19SMengyuan Lou };
528ef4f3c19SMengyuan Lou
529ef4f3c19SMengyuan Lou /* macro to make the table lines short */
530ef4f3c19SMengyuan Lou #define WX_PTT(mac, ip, etype, eip, proto, layer)\
531ef4f3c19SMengyuan Lou {1, \
532ef4f3c19SMengyuan Lou WX_DEC_PTYPE_MAC_##mac, /* mac */\
533ef4f3c19SMengyuan Lou WX_DEC_PTYPE_IP_##ip, /* ip */ \
534ef4f3c19SMengyuan Lou WX_DEC_PTYPE_ETYPE_##etype, /* etype */\
535ef4f3c19SMengyuan Lou WX_DEC_PTYPE_IP_##eip, /* eip */\
536ef4f3c19SMengyuan Lou WX_DEC_PTYPE_PROT_##proto, /* proto */\
537ef4f3c19SMengyuan Lou WX_DEC_PTYPE_LAYER_##layer /* layer */}
538ef4f3c19SMengyuan Lou
5391efa9bfeSJiawen Wu /* Host Interface Command Structures */
5401efa9bfeSJiawen Wu struct wx_hic_hdr {
5411efa9bfeSJiawen Wu u8 cmd;
5421efa9bfeSJiawen Wu u8 buf_len;
5431efa9bfeSJiawen Wu union {
5441efa9bfeSJiawen Wu u8 cmd_resv;
5451efa9bfeSJiawen Wu u8 ret_status;
5461efa9bfeSJiawen Wu } cmd_or_resp;
5471efa9bfeSJiawen Wu u8 checksum;
5481efa9bfeSJiawen Wu };
5491efa9bfeSJiawen Wu
5501efa9bfeSJiawen Wu struct wx_hic_hdr2_req {
5511efa9bfeSJiawen Wu u8 cmd;
5521efa9bfeSJiawen Wu u8 buf_lenh;
5531efa9bfeSJiawen Wu u8 buf_lenl;
5541efa9bfeSJiawen Wu u8 checksum;
5551efa9bfeSJiawen Wu };
5561efa9bfeSJiawen Wu
5571efa9bfeSJiawen Wu struct wx_hic_hdr2_rsp {
5581efa9bfeSJiawen Wu u8 cmd;
5591efa9bfeSJiawen Wu u8 buf_lenl;
5601efa9bfeSJiawen Wu u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */
5611efa9bfeSJiawen Wu u8 checksum;
5621efa9bfeSJiawen Wu };
5631efa9bfeSJiawen Wu
5641efa9bfeSJiawen Wu union wx_hic_hdr2 {
5651efa9bfeSJiawen Wu struct wx_hic_hdr2_req req;
5661efa9bfeSJiawen Wu struct wx_hic_hdr2_rsp rsp;
5671efa9bfeSJiawen Wu };
5681efa9bfeSJiawen Wu
5691efa9bfeSJiawen Wu /* These need to be dword aligned */
5701efa9bfeSJiawen Wu struct wx_hic_read_shadow_ram {
5711efa9bfeSJiawen Wu union wx_hic_hdr2 hdr;
5721efa9bfeSJiawen Wu u32 address;
5731efa9bfeSJiawen Wu u16 length;
5741efa9bfeSJiawen Wu u16 pad2;
5751efa9bfeSJiawen Wu u16 data;
5761efa9bfeSJiawen Wu u16 pad3;
5771efa9bfeSJiawen Wu };
5781efa9bfeSJiawen Wu
5791efa9bfeSJiawen Wu struct wx_hic_reset {
5801efa9bfeSJiawen Wu struct wx_hic_hdr hdr;
5811efa9bfeSJiawen Wu u16 lan_id;
5821efa9bfeSJiawen Wu u16 reset_type;
5831efa9bfeSJiawen Wu };
5841efa9bfeSJiawen Wu
585a34b3e6eSJiawen Wu /* Bus parameters */
586a34b3e6eSJiawen Wu struct wx_bus_info {
587a34b3e6eSJiawen Wu u8 func;
588a34b3e6eSJiawen Wu u16 device;
589a34b3e6eSJiawen Wu };
590a34b3e6eSJiawen Wu
591b0801256SJiawen Wu struct wx_thermal_sensor_data {
592b0801256SJiawen Wu s16 temp;
593b0801256SJiawen Wu s16 alarm_thresh;
594b0801256SJiawen Wu s16 dalarm_thresh;
595b0801256SJiawen Wu };
596b0801256SJiawen Wu
597b0801256SJiawen Wu enum wx_mac_type {
598b0801256SJiawen Wu wx_mac_unknown = 0,
599b0801256SJiawen Wu wx_mac_sp,
600b0801256SJiawen Wu wx_mac_em
601b0801256SJiawen Wu };
602b0801256SJiawen Wu
603*02b2a6f9SJiawen Wu enum sp_media_type {
604*02b2a6f9SJiawen Wu sp_media_unknown = 0,
605*02b2a6f9SJiawen Wu sp_media_fiber,
606*02b2a6f9SJiawen Wu sp_media_copper,
607*02b2a6f9SJiawen Wu sp_media_backplane
608*02b2a6f9SJiawen Wu };
609*02b2a6f9SJiawen Wu
610803df55dSMengyuan Lou enum em_mac_type {
611803df55dSMengyuan Lou em_mac_type_unknown = 0,
612803df55dSMengyuan Lou em_mac_type_mdi,
613803df55dSMengyuan Lou em_mac_type_rgmii
614803df55dSMengyuan Lou };
615803df55dSMengyuan Lou
616b0801256SJiawen Wu struct wx_mac_info {
617b0801256SJiawen Wu enum wx_mac_type type;
618b0801256SJiawen Wu bool set_lben;
619d21d2c7fSJiawen Wu u8 addr[ETH_ALEN];
620d21d2c7fSJiawen Wu u8 perm_addr[ETH_ALEN];
62118b5b8a9SJiawen Wu u32 mta_shadow[128];
622d21d2c7fSJiawen Wu s32 mc_filter_type;
623d21d2c7fSJiawen Wu u32 mcft_size;
624f3b03c65SMengyuan Lou u32 vft_shadow[128];
625f3b03c65SMengyuan Lou u32 vft_size;
626d21d2c7fSJiawen Wu u32 num_rar_entries;
62718b5b8a9SJiawen Wu u32 rx_pb_size;
62818b5b8a9SJiawen Wu u32 tx_pb_size;
629b0801256SJiawen Wu u32 max_tx_queues;
630b0801256SJiawen Wu u32 max_rx_queues;
63102338c48SMengyuan Lou
63202338c48SMengyuan Lou u16 max_msix_vectors;
633b0801256SJiawen Wu struct wx_thermal_sensor_data sensor;
634b0801256SJiawen Wu };
635b0801256SJiawen Wu
6361efa9bfeSJiawen Wu enum wx_eeprom_type {
6371efa9bfeSJiawen Wu wx_eeprom_uninitialized = 0,
6381efa9bfeSJiawen Wu wx_eeprom_spi,
6391efa9bfeSJiawen Wu wx_flash,
6401efa9bfeSJiawen Wu wx_eeprom_none /* No NVM support */
6411efa9bfeSJiawen Wu };
6421efa9bfeSJiawen Wu
6431efa9bfeSJiawen Wu struct wx_eeprom_info {
6441efa9bfeSJiawen Wu enum wx_eeprom_type type;
6451efa9bfeSJiawen Wu u32 semaphore_delay;
6461efa9bfeSJiawen Wu u16 word_size;
6471efa9bfeSJiawen Wu u16 sw_region_offset;
6481efa9bfeSJiawen Wu };
6491efa9bfeSJiawen Wu
650d21d2c7fSJiawen Wu struct wx_addr_filter_info {
651d21d2c7fSJiawen Wu u32 num_mc_addrs;
652d21d2c7fSJiawen Wu u32 mta_in_use;
653d21d2c7fSJiawen Wu bool user_set_promisc;
654d21d2c7fSJiawen Wu };
655d21d2c7fSJiawen Wu
65679625f45SJiawen Wu struct wx_mac_addr {
65779625f45SJiawen Wu u8 addr[ETH_ALEN];
65879625f45SJiawen Wu u16 state; /* bitmask */
65979625f45SJiawen Wu u64 pools;
66079625f45SJiawen Wu };
66179625f45SJiawen Wu
6621efa9bfeSJiawen Wu enum wx_reset_type {
6631efa9bfeSJiawen Wu WX_LAN_RESET = 0,
6641efa9bfeSJiawen Wu WX_SW_RESET,
6651efa9bfeSJiawen Wu WX_GLOBAL_RESET
6661efa9bfeSJiawen Wu };
6671efa9bfeSJiawen Wu
6683c47e8aeSJiawen Wu struct wx_cb {
6693c47e8aeSJiawen Wu dma_addr_t dma;
6703c47e8aeSJiawen Wu u16 append_cnt; /* number of skb's appended */
6713c47e8aeSJiawen Wu bool page_released;
6723c47e8aeSJiawen Wu bool dma_released;
6733c47e8aeSJiawen Wu };
6743c47e8aeSJiawen Wu
6753c47e8aeSJiawen Wu #define WX_CB(skb) ((struct wx_cb *)(skb)->cb)
6763c47e8aeSJiawen Wu
677850b9711SJiawen Wu /* Transmit Descriptor */
678850b9711SJiawen Wu union wx_tx_desc {
679850b9711SJiawen Wu struct {
680850b9711SJiawen Wu __le64 buffer_addr; /* Address of descriptor's data buf */
681850b9711SJiawen Wu __le32 cmd_type_len;
682850b9711SJiawen Wu __le32 olinfo_status;
683850b9711SJiawen Wu } read;
684850b9711SJiawen Wu struct {
685850b9711SJiawen Wu __le64 rsvd; /* Reserved */
686850b9711SJiawen Wu __le32 nxtseq_seed;
687850b9711SJiawen Wu __le32 status;
688850b9711SJiawen Wu } wb;
689850b9711SJiawen Wu };
690850b9711SJiawen Wu
691850b9711SJiawen Wu /* Receive Descriptor */
692850b9711SJiawen Wu union wx_rx_desc {
693850b9711SJiawen Wu struct {
694850b9711SJiawen Wu __le64 pkt_addr; /* Packet buffer address */
695850b9711SJiawen Wu __le64 hdr_addr; /* Header buffer address */
696850b9711SJiawen Wu } read;
697850b9711SJiawen Wu struct {
698850b9711SJiawen Wu struct {
699850b9711SJiawen Wu union {
700850b9711SJiawen Wu __le32 data;
701850b9711SJiawen Wu struct {
702850b9711SJiawen Wu __le16 pkt_info; /* RSS, Pkt type */
703850b9711SJiawen Wu __le16 hdr_info; /* Splithdr, hdrlen */
704850b9711SJiawen Wu } hs_rss;
705850b9711SJiawen Wu } lo_dword;
706850b9711SJiawen Wu union {
707850b9711SJiawen Wu __le32 rss; /* RSS Hash */
708850b9711SJiawen Wu struct {
709850b9711SJiawen Wu __le16 ip_id; /* IP id */
710850b9711SJiawen Wu __le16 csum; /* Packet Checksum */
711850b9711SJiawen Wu } csum_ip;
712850b9711SJiawen Wu } hi_dword;
713850b9711SJiawen Wu } lower;
714850b9711SJiawen Wu struct {
715850b9711SJiawen Wu __le32 status_error; /* ext status/error */
716850b9711SJiawen Wu __le16 length; /* Packet length */
717850b9711SJiawen Wu __le16 vlan; /* VLAN tag */
718850b9711SJiawen Wu } upper;
719850b9711SJiawen Wu } wb; /* writeback */
720850b9711SJiawen Wu };
721850b9711SJiawen Wu
7223403960cSMengyuan Lou struct wx_tx_context_desc {
7233403960cSMengyuan Lou __le32 vlan_macip_lens;
7243403960cSMengyuan Lou __le32 seqnum_seed;
7253403960cSMengyuan Lou __le32 type_tucmd_mlhl;
7263403960cSMengyuan Lou __le32 mss_l4len_idx;
7273403960cSMengyuan Lou };
7283403960cSMengyuan Lou
7293403960cSMengyuan Lou /* if _flag is in _input, return _result */
7303403960cSMengyuan Lou #define WX_SET_FLAG(_input, _flag, _result) \
7313403960cSMengyuan Lou (((_flag) <= (_result)) ? \
7323403960cSMengyuan Lou ((u32)((_input) & (_flag)) * ((_result) / (_flag))) : \
7333403960cSMengyuan Lou ((u32)((_input) & (_flag)) / ((_flag) / (_result))))
7343403960cSMengyuan Lou
7353c47e8aeSJiawen Wu #define WX_RX_DESC(R, i) \
7363c47e8aeSJiawen Wu (&(((union wx_rx_desc *)((R)->desc))[i]))
73709a50880SMengyuan Lou #define WX_TX_DESC(R, i) \
73809a50880SMengyuan Lou (&(((union wx_tx_desc *)((R)->desc))[i]))
7393403960cSMengyuan Lou #define WX_TX_CTXTDESC(R, i) \
7403403960cSMengyuan Lou (&(((struct wx_tx_context_desc *)((R)->desc))[i]))
7413c47e8aeSJiawen Wu
742850b9711SJiawen Wu /* wrapper around a pointer to a socket buffer,
743850b9711SJiawen Wu * so a DMA handle can be stored along with the buffer
744850b9711SJiawen Wu */
745850b9711SJiawen Wu struct wx_tx_buffer {
746850b9711SJiawen Wu union wx_tx_desc *next_to_watch;
747850b9711SJiawen Wu struct sk_buff *skb;
748850b9711SJiawen Wu unsigned int bytecount;
749850b9711SJiawen Wu unsigned short gso_segs;
750850b9711SJiawen Wu DEFINE_DMA_UNMAP_ADDR(dma);
751850b9711SJiawen Wu DEFINE_DMA_UNMAP_LEN(len);
7523403960cSMengyuan Lou __be16 protocol;
7533403960cSMengyuan Lou u32 tx_flags;
754850b9711SJiawen Wu };
755850b9711SJiawen Wu
756850b9711SJiawen Wu struct wx_rx_buffer {
757850b9711SJiawen Wu struct sk_buff *skb;
758850b9711SJiawen Wu dma_addr_t dma;
759850b9711SJiawen Wu dma_addr_t page_dma;
760850b9711SJiawen Wu struct page *page;
761850b9711SJiawen Wu unsigned int page_offset;
7623c47e8aeSJiawen Wu };
7633c47e8aeSJiawen Wu
7643c47e8aeSJiawen Wu struct wx_queue_stats {
7653c47e8aeSJiawen Wu u64 packets;
7663c47e8aeSJiawen Wu u64 bytes;
767850b9711SJiawen Wu };
768850b9711SJiawen Wu
769ef4f3c19SMengyuan Lou struct wx_rx_queue_stats {
770ef4f3c19SMengyuan Lou u64 csum_good_cnt;
771ef4f3c19SMengyuan Lou u64 csum_err;
772ef4f3c19SMengyuan Lou };
773ef4f3c19SMengyuan Lou
7743f703186SMengyuan Lou /* iterator for handling rings in ring container */
7753f703186SMengyuan Lou #define wx_for_each_ring(posm, headm) \
7763f703186SMengyuan Lou for (posm = (headm).ring; posm; posm = posm->next)
7773f703186SMengyuan Lou
7783f703186SMengyuan Lou struct wx_ring_container {
7793f703186SMengyuan Lou struct wx_ring *ring; /* pointer to linked list of rings */
7803c47e8aeSJiawen Wu unsigned int total_bytes; /* total bytes processed this int */
7813c47e8aeSJiawen Wu unsigned int total_packets; /* total packets processed this int */
7823f703186SMengyuan Lou u8 count; /* total number of rings in vector */
7833f703186SMengyuan Lou u8 itr; /* current ITR setting for ring */
7843f703186SMengyuan Lou };
7853f703186SMengyuan Lou struct wx_ring {
7863f703186SMengyuan Lou struct wx_ring *next; /* pointer to next ring in q_vector */
7873f703186SMengyuan Lou struct wx_q_vector *q_vector; /* backpointer to host q_vector */
7883f703186SMengyuan Lou struct net_device *netdev; /* netdev ring belongs to */
7893f703186SMengyuan Lou struct device *dev; /* device for DMA mapping */
790850b9711SJiawen Wu struct page_pool *page_pool;
791850b9711SJiawen Wu void *desc; /* descriptor ring memory */
792850b9711SJiawen Wu union {
793850b9711SJiawen Wu struct wx_tx_buffer *tx_buffer_info;
794850b9711SJiawen Wu struct wx_rx_buffer *rx_buffer_info;
795850b9711SJiawen Wu };
79618b5b8a9SJiawen Wu u8 __iomem *tail;
797850b9711SJiawen Wu dma_addr_t dma; /* phys. address of descriptor ring */
798850b9711SJiawen Wu unsigned int size; /* length in bytes */
7993f703186SMengyuan Lou
8003f703186SMengyuan Lou u16 count; /* amount of descriptors */
8013f703186SMengyuan Lou
8023f703186SMengyuan Lou u8 queue_index; /* needed for multiqueue queue management */
8033f703186SMengyuan Lou u8 reg_idx; /* holds the special value that gets
8043f703186SMengyuan Lou * the hardware register offset
8053f703186SMengyuan Lou * associated with this ring, which is
8063f703186SMengyuan Lou * different for DCB and RSS modes
8073f703186SMengyuan Lou */
8083c47e8aeSJiawen Wu u16 next_to_use;
8093c47e8aeSJiawen Wu u16 next_to_clean;
8103c47e8aeSJiawen Wu u16 next_to_alloc;
8113c47e8aeSJiawen Wu
8123c47e8aeSJiawen Wu struct wx_queue_stats stats;
8133c47e8aeSJiawen Wu struct u64_stats_sync syncp;
814ef4f3c19SMengyuan Lou union {
815ef4f3c19SMengyuan Lou struct wx_rx_queue_stats rx_stats;
816ef4f3c19SMengyuan Lou };
8173f703186SMengyuan Lou } ____cacheline_internodealigned_in_smp;
8183f703186SMengyuan Lou
8193f703186SMengyuan Lou struct wx_q_vector {
8203f703186SMengyuan Lou struct wx *wx;
8213f703186SMengyuan Lou int cpu; /* CPU for DCA */
822850b9711SJiawen Wu int numa_node;
8233f703186SMengyuan Lou u16 v_idx; /* index of q_vector within array, also used for
8243f703186SMengyuan Lou * finding the bit in EICR and friends that
8253f703186SMengyuan Lou * represents the vector for this ring
8263f703186SMengyuan Lou */
8273f703186SMengyuan Lou u16 itr; /* Interrupt throttle rate written to EITR */
8283f703186SMengyuan Lou struct wx_ring_container rx, tx;
8293f703186SMengyuan Lou struct napi_struct napi;
8303f703186SMengyuan Lou struct rcu_head rcu; /* to avoid race with update stats on free */
8313f703186SMengyuan Lou
8323f703186SMengyuan Lou char name[IFNAMSIZ + 17];
8333f703186SMengyuan Lou
8343f703186SMengyuan Lou /* for dynamic allocation of rings associated with this q_vector */
835fe6559faSGustavo A. R. Silva struct wx_ring ring[] ____cacheline_internodealigned_in_smp;
8363f703186SMengyuan Lou };
8373f703186SMengyuan Lou
8383f703186SMengyuan Lou enum wx_isb_idx {
8393f703186SMengyuan Lou WX_ISB_HEADER,
8403f703186SMengyuan Lou WX_ISB_MISC,
8413f703186SMengyuan Lou WX_ISB_VEC0,
8423f703186SMengyuan Lou WX_ISB_VEC1,
8433f703186SMengyuan Lou WX_ISB_MAX
8443f703186SMengyuan Lou };
8453f703186SMengyuan Lou
8469607a3e6SJiawen Wu struct wx {
847f3b03c65SMengyuan Lou unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
848f3b03c65SMengyuan Lou
849c3e382adSJiawen Wu void *priv;
850a34b3e6eSJiawen Wu u8 __iomem *hw_addr;
851a34b3e6eSJiawen Wu struct pci_dev *pdev;
85279625f45SJiawen Wu struct net_device *netdev;
853a34b3e6eSJiawen Wu struct wx_bus_info bus;
854b0801256SJiawen Wu struct wx_mac_info mac;
855803df55dSMengyuan Lou enum em_mac_type mac_type;
856*02b2a6f9SJiawen Wu enum sp_media_type media_type;
8571efa9bfeSJiawen Wu struct wx_eeprom_info eeprom;
858d21d2c7fSJiawen Wu struct wx_addr_filter_info addr_ctrl;
85979625f45SJiawen Wu struct wx_mac_addr *mac_table;
860a34b3e6eSJiawen Wu u16 device_id;
861a34b3e6eSJiawen Wu u16 vendor_id;
862a34b3e6eSJiawen Wu u16 subsystem_device_id;
863a34b3e6eSJiawen Wu u16 subsystem_vendor_id;
864a34b3e6eSJiawen Wu u8 revision_id;
865a34b3e6eSJiawen Wu u16 oem_ssid;
866a34b3e6eSJiawen Wu u16 oem_svid;
867270a71e6SJiawen Wu u16 msg_enable;
868b0801256SJiawen Wu bool adapter_stopped;
86918b5b8a9SJiawen Wu u16 tpid[8];
870270a71e6SJiawen Wu char eeprom_id[32];
8711b8d1c50SMengyuan Lou char *driver_name;
8721efa9bfeSJiawen Wu enum wx_reset_type reset_type;
873803df55dSMengyuan Lou
874a1cf597bSMengyuan Lou /* PHY stuff */
875a1cf597bSMengyuan Lou unsigned int link;
876a1cf597bSMengyuan Lou int speed;
877a1cf597bSMengyuan Lou int duplex;
878a1cf597bSMengyuan Lou struct phy_device *phydev;
879a1cf597bSMengyuan Lou
8806963e463SMengyuan Lou bool wol_hw_supported;
881803df55dSMengyuan Lou bool ncsi_enabled;
882803df55dSMengyuan Lou bool gpio_ctrl;
883b83c3731SJiawen Wu raw_spinlock_t gpio_lock;
884803df55dSMengyuan Lou
885803df55dSMengyuan Lou /* Tx fast path data */
886803df55dSMengyuan Lou int num_tx_queues;
887803df55dSMengyuan Lou u16 tx_itr_setting;
888803df55dSMengyuan Lou u16 tx_work_limit;
889803df55dSMengyuan Lou
890803df55dSMengyuan Lou /* Rx fast path data */
891803df55dSMengyuan Lou int num_rx_queues;
892803df55dSMengyuan Lou u16 rx_itr_setting;
893803df55dSMengyuan Lou u16 rx_work_limit;
894803df55dSMengyuan Lou
895803df55dSMengyuan Lou int num_q_vectors; /* current number of q_vectors for device */
896803df55dSMengyuan Lou int max_q_vectors; /* upper limit of q_vectors for device */
897803df55dSMengyuan Lou
898803df55dSMengyuan Lou u32 tx_ring_count;
899803df55dSMengyuan Lou u32 rx_ring_count;
900803df55dSMengyuan Lou
9013f703186SMengyuan Lou struct wx_ring *tx_ring[64] ____cacheline_aligned_in_smp;
9023f703186SMengyuan Lou struct wx_ring *rx_ring[64];
9033f703186SMengyuan Lou struct wx_q_vector *q_vector[64];
9043f703186SMengyuan Lou
9053f703186SMengyuan Lou unsigned int queues_per_pool;
9063f703186SMengyuan Lou struct msix_entry *msix_entries;
9073f703186SMengyuan Lou
9083f703186SMengyuan Lou /* misc interrupt status block */
9093f703186SMengyuan Lou dma_addr_t isb_dma;
9103f703186SMengyuan Lou u32 *isb_mem;
9113f703186SMengyuan Lou u32 isb_tag[WX_ISB_MAX];
9123f703186SMengyuan Lou
913803df55dSMengyuan Lou #define WX_MAX_RETA_ENTRIES 128
914803df55dSMengyuan Lou u8 rss_indir_tbl[WX_MAX_RETA_ENTRIES];
915803df55dSMengyuan Lou
916803df55dSMengyuan Lou #define WX_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */
917803df55dSMengyuan Lou u32 *rss_key;
918803df55dSMengyuan Lou u32 wol;
919803df55dSMengyuan Lou
920803df55dSMengyuan Lou u16 bd_number;
921a34b3e6eSJiawen Wu };
922a34b3e6eSJiawen Wu
923b0801256SJiawen Wu #define WX_INTR_ALL (~0ULL)
9243c47e8aeSJiawen Wu #define WX_INTR_Q(i) BIT(i)
925b0801256SJiawen Wu
926a34b3e6eSJiawen Wu /* register operations */
927a34b3e6eSJiawen Wu #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
928a34b3e6eSJiawen Wu #define rd32(a, reg) readl((a)->hw_addr + (reg))
9291efa9bfeSJiawen Wu #define rd32a(a, reg, offset) ( \
9301efa9bfeSJiawen Wu rd32((a), (reg) + ((offset) << 2)))
9311efa9bfeSJiawen Wu #define wr32a(a, reg, off, val) \
9321efa9bfeSJiawen Wu wr32((a), (reg) + ((off) << 2), (val))
933a34b3e6eSJiawen Wu
934b0801256SJiawen Wu static inline u32
rd32m(struct wx * wx,u32 reg,u32 mask)9359607a3e6SJiawen Wu rd32m(struct wx *wx, u32 reg, u32 mask)
936b0801256SJiawen Wu {
937b0801256SJiawen Wu u32 val;
938b0801256SJiawen Wu
9399607a3e6SJiawen Wu val = rd32(wx, reg);
940b0801256SJiawen Wu return val & mask;
941b0801256SJiawen Wu }
942b0801256SJiawen Wu
943b0801256SJiawen Wu static inline void
wr32m(struct wx * wx,u32 reg,u32 mask,u32 field)9449607a3e6SJiawen Wu wr32m(struct wx *wx, u32 reg, u32 mask, u32 field)
945b0801256SJiawen Wu {
946b0801256SJiawen Wu u32 val;
947b0801256SJiawen Wu
9489607a3e6SJiawen Wu val = rd32(wx, reg);
949b0801256SJiawen Wu val = ((val & ~mask) | (field & mask));
950b0801256SJiawen Wu
9519607a3e6SJiawen Wu wr32(wx, reg, val);
952b0801256SJiawen Wu }
953b0801256SJiawen Wu
954b0801256SJiawen Wu /* On some domestic CPU platforms, sometimes IO is not synchronized with
955b0801256SJiawen Wu * flushing memory, here use readl() to flush PCI read and write.
956b0801256SJiawen Wu */
957b0801256SJiawen Wu #define WX_WRITE_FLUSH(H) rd32(H, WX_MIS_PWR)
958b0801256SJiawen Wu
9599607a3e6SJiawen Wu #define wx_err(wx, fmt, arg...) \
9609607a3e6SJiawen Wu dev_err(&(wx)->pdev->dev, fmt, ##arg)
961a34b3e6eSJiawen Wu
9629607a3e6SJiawen Wu #define wx_dbg(wx, fmt, arg...) \
9639607a3e6SJiawen Wu dev_dbg(&(wx)->pdev->dev, fmt, ##arg)
964d21d2c7fSJiawen Wu
965a34b3e6eSJiawen Wu #endif /* _WX_TYPE_H_ */
966