1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */
3 
4 #include <linux/etherdevice.h>
5 #include <net/ip6_checksum.h>
6 #include <net/page_pool.h>
7 #include <net/inet_ecn.h>
8 #include <linux/iopoll.h>
9 #include <linux/sctp.h>
10 #include <linux/pci.h>
11 #include <net/tcp.h>
12 #include <net/ip.h>
13 
14 #include "wx_type.h"
15 #include "wx_lib.h"
16 #include "wx_hw.h"
17 
18 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
19 static struct wx_dec_ptype wx_ptype_lookup[256] = {
20 	/* L2: mac */
21 	[0x11] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
22 	[0x12] = WX_PTT(L2, NONE, NONE, NONE, TS,   PAY2),
23 	[0x13] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
24 	[0x14] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
25 	[0x15] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE),
26 	[0x16] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
27 	[0x17] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE),
28 
29 	/* L2: ethertype filter */
30 	[0x18 ... 0x1F] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE),
31 
32 	/* L3: ip non-tunnel */
33 	[0x21] = WX_PTT(IP, FGV4, NONE, NONE, NONE, PAY3),
34 	[0x22] = WX_PTT(IP, IPV4, NONE, NONE, NONE, PAY3),
35 	[0x23] = WX_PTT(IP, IPV4, NONE, NONE, UDP,  PAY4),
36 	[0x24] = WX_PTT(IP, IPV4, NONE, NONE, TCP,  PAY4),
37 	[0x25] = WX_PTT(IP, IPV4, NONE, NONE, SCTP, PAY4),
38 	[0x29] = WX_PTT(IP, FGV6, NONE, NONE, NONE, PAY3),
39 	[0x2A] = WX_PTT(IP, IPV6, NONE, NONE, NONE, PAY3),
40 	[0x2B] = WX_PTT(IP, IPV6, NONE, NONE, UDP,  PAY3),
41 	[0x2C] = WX_PTT(IP, IPV6, NONE, NONE, TCP,  PAY4),
42 	[0x2D] = WX_PTT(IP, IPV6, NONE, NONE, SCTP, PAY4),
43 
44 	/* L2: fcoe */
45 	[0x30 ... 0x34] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3),
46 	[0x38 ... 0x3C] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3),
47 
48 	/* IPv4 --> IPv4/IPv6 */
49 	[0x81] = WX_PTT(IP, IPV4, IPIP, FGV4, NONE, PAY3),
50 	[0x82] = WX_PTT(IP, IPV4, IPIP, IPV4, NONE, PAY3),
51 	[0x83] = WX_PTT(IP, IPV4, IPIP, IPV4, UDP,  PAY4),
52 	[0x84] = WX_PTT(IP, IPV4, IPIP, IPV4, TCP,  PAY4),
53 	[0x85] = WX_PTT(IP, IPV4, IPIP, IPV4, SCTP, PAY4),
54 	[0x89] = WX_PTT(IP, IPV4, IPIP, FGV6, NONE, PAY3),
55 	[0x8A] = WX_PTT(IP, IPV4, IPIP, IPV6, NONE, PAY3),
56 	[0x8B] = WX_PTT(IP, IPV4, IPIP, IPV6, UDP,  PAY4),
57 	[0x8C] = WX_PTT(IP, IPV4, IPIP, IPV6, TCP,  PAY4),
58 	[0x8D] = WX_PTT(IP, IPV4, IPIP, IPV6, SCTP, PAY4),
59 
60 	/* IPv4 --> GRE/NAT --> NONE/IPv4/IPv6 */
61 	[0x90] = WX_PTT(IP, IPV4, IG, NONE, NONE, PAY3),
62 	[0x91] = WX_PTT(IP, IPV4, IG, FGV4, NONE, PAY3),
63 	[0x92] = WX_PTT(IP, IPV4, IG, IPV4, NONE, PAY3),
64 	[0x93] = WX_PTT(IP, IPV4, IG, IPV4, UDP,  PAY4),
65 	[0x94] = WX_PTT(IP, IPV4, IG, IPV4, TCP,  PAY4),
66 	[0x95] = WX_PTT(IP, IPV4, IG, IPV4, SCTP, PAY4),
67 	[0x99] = WX_PTT(IP, IPV4, IG, FGV6, NONE, PAY3),
68 	[0x9A] = WX_PTT(IP, IPV4, IG, IPV6, NONE, PAY3),
69 	[0x9B] = WX_PTT(IP, IPV4, IG, IPV6, UDP,  PAY4),
70 	[0x9C] = WX_PTT(IP, IPV4, IG, IPV6, TCP,  PAY4),
71 	[0x9D] = WX_PTT(IP, IPV4, IG, IPV6, SCTP, PAY4),
72 
73 	/* IPv4 --> GRE/NAT --> MAC --> NONE/IPv4/IPv6 */
74 	[0xA0] = WX_PTT(IP, IPV4, IGM, NONE, NONE, PAY3),
75 	[0xA1] = WX_PTT(IP, IPV4, IGM, FGV4, NONE, PAY3),
76 	[0xA2] = WX_PTT(IP, IPV4, IGM, IPV4, NONE, PAY3),
77 	[0xA3] = WX_PTT(IP, IPV4, IGM, IPV4, UDP,  PAY4),
78 	[0xA4] = WX_PTT(IP, IPV4, IGM, IPV4, TCP,  PAY4),
79 	[0xA5] = WX_PTT(IP, IPV4, IGM, IPV4, SCTP, PAY4),
80 	[0xA9] = WX_PTT(IP, IPV4, IGM, FGV6, NONE, PAY3),
81 	[0xAA] = WX_PTT(IP, IPV4, IGM, IPV6, NONE, PAY3),
82 	[0xAB] = WX_PTT(IP, IPV4, IGM, IPV6, UDP,  PAY4),
83 	[0xAC] = WX_PTT(IP, IPV4, IGM, IPV6, TCP,  PAY4),
84 	[0xAD] = WX_PTT(IP, IPV4, IGM, IPV6, SCTP, PAY4),
85 
86 	/* IPv4 --> GRE/NAT --> MAC+VLAN --> NONE/IPv4/IPv6 */
87 	[0xB0] = WX_PTT(IP, IPV4, IGMV, NONE, NONE, PAY3),
88 	[0xB1] = WX_PTT(IP, IPV4, IGMV, FGV4, NONE, PAY3),
89 	[0xB2] = WX_PTT(IP, IPV4, IGMV, IPV4, NONE, PAY3),
90 	[0xB3] = WX_PTT(IP, IPV4, IGMV, IPV4, UDP,  PAY4),
91 	[0xB4] = WX_PTT(IP, IPV4, IGMV, IPV4, TCP,  PAY4),
92 	[0xB5] = WX_PTT(IP, IPV4, IGMV, IPV4, SCTP, PAY4),
93 	[0xB9] = WX_PTT(IP, IPV4, IGMV, FGV6, NONE, PAY3),
94 	[0xBA] = WX_PTT(IP, IPV4, IGMV, IPV6, NONE, PAY3),
95 	[0xBB] = WX_PTT(IP, IPV4, IGMV, IPV6, UDP,  PAY4),
96 	[0xBC] = WX_PTT(IP, IPV4, IGMV, IPV6, TCP,  PAY4),
97 	[0xBD] = WX_PTT(IP, IPV4, IGMV, IPV6, SCTP, PAY4),
98 
99 	/* IPv6 --> IPv4/IPv6 */
100 	[0xC1] = WX_PTT(IP, IPV6, IPIP, FGV4, NONE, PAY3),
101 	[0xC2] = WX_PTT(IP, IPV6, IPIP, IPV4, NONE, PAY3),
102 	[0xC3] = WX_PTT(IP, IPV6, IPIP, IPV4, UDP,  PAY4),
103 	[0xC4] = WX_PTT(IP, IPV6, IPIP, IPV4, TCP,  PAY4),
104 	[0xC5] = WX_PTT(IP, IPV6, IPIP, IPV4, SCTP, PAY4),
105 	[0xC9] = WX_PTT(IP, IPV6, IPIP, FGV6, NONE, PAY3),
106 	[0xCA] = WX_PTT(IP, IPV6, IPIP, IPV6, NONE, PAY3),
107 	[0xCB] = WX_PTT(IP, IPV6, IPIP, IPV6, UDP,  PAY4),
108 	[0xCC] = WX_PTT(IP, IPV6, IPIP, IPV6, TCP,  PAY4),
109 	[0xCD] = WX_PTT(IP, IPV6, IPIP, IPV6, SCTP, PAY4),
110 
111 	/* IPv6 --> GRE/NAT -> NONE/IPv4/IPv6 */
112 	[0xD0] = WX_PTT(IP, IPV6, IG, NONE, NONE, PAY3),
113 	[0xD1] = WX_PTT(IP, IPV6, IG, FGV4, NONE, PAY3),
114 	[0xD2] = WX_PTT(IP, IPV6, IG, IPV4, NONE, PAY3),
115 	[0xD3] = WX_PTT(IP, IPV6, IG, IPV4, UDP,  PAY4),
116 	[0xD4] = WX_PTT(IP, IPV6, IG, IPV4, TCP,  PAY4),
117 	[0xD5] = WX_PTT(IP, IPV6, IG, IPV4, SCTP, PAY4),
118 	[0xD9] = WX_PTT(IP, IPV6, IG, FGV6, NONE, PAY3),
119 	[0xDA] = WX_PTT(IP, IPV6, IG, IPV6, NONE, PAY3),
120 	[0xDB] = WX_PTT(IP, IPV6, IG, IPV6, UDP,  PAY4),
121 	[0xDC] = WX_PTT(IP, IPV6, IG, IPV6, TCP,  PAY4),
122 	[0xDD] = WX_PTT(IP, IPV6, IG, IPV6, SCTP, PAY4),
123 
124 	/* IPv6 --> GRE/NAT -> MAC -> NONE/IPv4/IPv6 */
125 	[0xE0] = WX_PTT(IP, IPV6, IGM, NONE, NONE, PAY3),
126 	[0xE1] = WX_PTT(IP, IPV6, IGM, FGV4, NONE, PAY3),
127 	[0xE2] = WX_PTT(IP, IPV6, IGM, IPV4, NONE, PAY3),
128 	[0xE3] = WX_PTT(IP, IPV6, IGM, IPV4, UDP,  PAY4),
129 	[0xE4] = WX_PTT(IP, IPV6, IGM, IPV4, TCP,  PAY4),
130 	[0xE5] = WX_PTT(IP, IPV6, IGM, IPV4, SCTP, PAY4),
131 	[0xE9] = WX_PTT(IP, IPV6, IGM, FGV6, NONE, PAY3),
132 	[0xEA] = WX_PTT(IP, IPV6, IGM, IPV6, NONE, PAY3),
133 	[0xEB] = WX_PTT(IP, IPV6, IGM, IPV6, UDP,  PAY4),
134 	[0xEC] = WX_PTT(IP, IPV6, IGM, IPV6, TCP,  PAY4),
135 	[0xED] = WX_PTT(IP, IPV6, IGM, IPV6, SCTP, PAY4),
136 
137 	/* IPv6 --> GRE/NAT -> MAC--> NONE/IPv */
138 	[0xF0] = WX_PTT(IP, IPV6, IGMV, NONE, NONE, PAY3),
139 	[0xF1] = WX_PTT(IP, IPV6, IGMV, FGV4, NONE, PAY3),
140 	[0xF2] = WX_PTT(IP, IPV6, IGMV, IPV4, NONE, PAY3),
141 	[0xF3] = WX_PTT(IP, IPV6, IGMV, IPV4, UDP,  PAY4),
142 	[0xF4] = WX_PTT(IP, IPV6, IGMV, IPV4, TCP,  PAY4),
143 	[0xF5] = WX_PTT(IP, IPV6, IGMV, IPV4, SCTP, PAY4),
144 	[0xF9] = WX_PTT(IP, IPV6, IGMV, FGV6, NONE, PAY3),
145 	[0xFA] = WX_PTT(IP, IPV6, IGMV, IPV6, NONE, PAY3),
146 	[0xFB] = WX_PTT(IP, IPV6, IGMV, IPV6, UDP,  PAY4),
147 	[0xFC] = WX_PTT(IP, IPV6, IGMV, IPV6, TCP,  PAY4),
148 	[0xFD] = WX_PTT(IP, IPV6, IGMV, IPV6, SCTP, PAY4),
149 };
150 
151 static struct wx_dec_ptype wx_decode_ptype(const u8 ptype)
152 {
153 	return wx_ptype_lookup[ptype];
154 }
155 
156 /* wx_test_staterr - tests bits in Rx descriptor status and error fields */
157 static __le32 wx_test_staterr(union wx_rx_desc *rx_desc,
158 			      const u32 stat_err_bits)
159 {
160 	return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
161 }
162 
163 static bool wx_can_reuse_rx_page(struct wx_rx_buffer *rx_buffer,
164 				 int rx_buffer_pgcnt)
165 {
166 	unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
167 	struct page *page = rx_buffer->page;
168 
169 	/* avoid re-using remote and pfmemalloc pages */
170 	if (!dev_page_is_reusable(page))
171 		return false;
172 
173 #if (PAGE_SIZE < 8192)
174 	/* if we are only owner of page we can reuse it */
175 	if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1))
176 		return false;
177 #endif
178 
179 	/* If we have drained the page fragment pool we need to update
180 	 * the pagecnt_bias and page count so that we fully restock the
181 	 * number of references the driver holds.
182 	 */
183 	if (unlikely(pagecnt_bias == 1)) {
184 		page_ref_add(page, USHRT_MAX - 1);
185 		rx_buffer->pagecnt_bias = USHRT_MAX;
186 	}
187 
188 	return true;
189 }
190 
191 /**
192  * wx_reuse_rx_page - page flip buffer and store it back on the ring
193  * @rx_ring: rx descriptor ring to store buffers on
194  * @old_buff: donor buffer to have page reused
195  *
196  * Synchronizes page for reuse by the adapter
197  **/
198 static void wx_reuse_rx_page(struct wx_ring *rx_ring,
199 			     struct wx_rx_buffer *old_buff)
200 {
201 	u16 nta = rx_ring->next_to_alloc;
202 	struct wx_rx_buffer *new_buff;
203 
204 	new_buff = &rx_ring->rx_buffer_info[nta];
205 
206 	/* update, and store next to alloc */
207 	nta++;
208 	rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
209 
210 	/* transfer page from old buffer to new buffer */
211 	new_buff->page = old_buff->page;
212 	new_buff->page_dma = old_buff->page_dma;
213 	new_buff->page_offset = old_buff->page_offset;
214 	new_buff->pagecnt_bias	= old_buff->pagecnt_bias;
215 }
216 
217 static void wx_dma_sync_frag(struct wx_ring *rx_ring,
218 			     struct wx_rx_buffer *rx_buffer)
219 {
220 	struct sk_buff *skb = rx_buffer->skb;
221 	skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
222 
223 	dma_sync_single_range_for_cpu(rx_ring->dev,
224 				      WX_CB(skb)->dma,
225 				      skb_frag_off(frag),
226 				      skb_frag_size(frag),
227 				      DMA_FROM_DEVICE);
228 
229 	/* If the page was released, just unmap it. */
230 	if (unlikely(WX_CB(skb)->page_released))
231 		page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false);
232 }
233 
234 static struct wx_rx_buffer *wx_get_rx_buffer(struct wx_ring *rx_ring,
235 					     union wx_rx_desc *rx_desc,
236 					     struct sk_buff **skb,
237 					     int *rx_buffer_pgcnt)
238 {
239 	struct wx_rx_buffer *rx_buffer;
240 	unsigned int size;
241 
242 	rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
243 	size = le16_to_cpu(rx_desc->wb.upper.length);
244 
245 #if (PAGE_SIZE < 8192)
246 	*rx_buffer_pgcnt = page_count(rx_buffer->page);
247 #else
248 	*rx_buffer_pgcnt = 0;
249 #endif
250 
251 	prefetchw(rx_buffer->page);
252 	*skb = rx_buffer->skb;
253 
254 	/* Delay unmapping of the first packet. It carries the header
255 	 * information, HW may still access the header after the writeback.
256 	 * Only unmap it when EOP is reached
257 	 */
258 	if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)) {
259 		if (!*skb)
260 			goto skip_sync;
261 	} else {
262 		if (*skb)
263 			wx_dma_sync_frag(rx_ring, rx_buffer);
264 	}
265 
266 	/* we are reusing so sync this buffer for CPU use */
267 	dma_sync_single_range_for_cpu(rx_ring->dev,
268 				      rx_buffer->dma,
269 				      rx_buffer->page_offset,
270 				      size,
271 				      DMA_FROM_DEVICE);
272 skip_sync:
273 	rx_buffer->pagecnt_bias--;
274 
275 	return rx_buffer;
276 }
277 
278 static void wx_put_rx_buffer(struct wx_ring *rx_ring,
279 			     struct wx_rx_buffer *rx_buffer,
280 			     struct sk_buff *skb,
281 			     int rx_buffer_pgcnt)
282 {
283 	if (wx_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) {
284 		/* hand second half of page back to the ring */
285 		wx_reuse_rx_page(rx_ring, rx_buffer);
286 	} else {
287 		if (!IS_ERR(skb) && WX_CB(skb)->dma == rx_buffer->dma)
288 			/* the page has been released from the ring */
289 			WX_CB(skb)->page_released = true;
290 		else
291 			page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false);
292 
293 		__page_frag_cache_drain(rx_buffer->page,
294 					rx_buffer->pagecnt_bias);
295 	}
296 
297 	/* clear contents of rx_buffer */
298 	rx_buffer->page = NULL;
299 	rx_buffer->skb = NULL;
300 }
301 
302 static struct sk_buff *wx_build_skb(struct wx_ring *rx_ring,
303 				    struct wx_rx_buffer *rx_buffer,
304 				    union wx_rx_desc *rx_desc)
305 {
306 	unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
307 #if (PAGE_SIZE < 8192)
308 	unsigned int truesize = WX_RX_BUFSZ;
309 #else
310 	unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
311 #endif
312 	struct sk_buff *skb = rx_buffer->skb;
313 
314 	if (!skb) {
315 		void *page_addr = page_address(rx_buffer->page) +
316 				  rx_buffer->page_offset;
317 
318 		/* prefetch first cache line of first page */
319 		prefetch(page_addr);
320 #if L1_CACHE_BYTES < 128
321 		prefetch(page_addr + L1_CACHE_BYTES);
322 #endif
323 
324 		/* allocate a skb to store the frags */
325 		skb = napi_alloc_skb(&rx_ring->q_vector->napi, WX_RXBUFFER_256);
326 		if (unlikely(!skb))
327 			return NULL;
328 
329 		/* we will be copying header into skb->data in
330 		 * pskb_may_pull so it is in our interest to prefetch
331 		 * it now to avoid a possible cache miss
332 		 */
333 		prefetchw(skb->data);
334 
335 		if (size <= WX_RXBUFFER_256) {
336 			memcpy(__skb_put(skb, size), page_addr,
337 			       ALIGN(size, sizeof(long)));
338 			rx_buffer->pagecnt_bias++;
339 
340 			return skb;
341 		}
342 
343 		if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP))
344 			WX_CB(skb)->dma = rx_buffer->dma;
345 
346 		skb_add_rx_frag(skb, 0, rx_buffer->page,
347 				rx_buffer->page_offset,
348 				size, truesize);
349 		goto out;
350 
351 	} else {
352 		skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
353 				rx_buffer->page_offset, size, truesize);
354 	}
355 
356 out:
357 #if (PAGE_SIZE < 8192)
358 	/* flip page offset to other buffer */
359 	rx_buffer->page_offset ^= truesize;
360 #else
361 	/* move offset up to the next cache line */
362 	rx_buffer->page_offset += truesize;
363 #endif
364 
365 	return skb;
366 }
367 
368 static bool wx_alloc_mapped_page(struct wx_ring *rx_ring,
369 				 struct wx_rx_buffer *bi)
370 {
371 	struct page *page = bi->page;
372 	dma_addr_t dma;
373 
374 	/* since we are recycling buffers we should seldom need to alloc */
375 	if (likely(page))
376 		return true;
377 
378 	page = page_pool_dev_alloc_pages(rx_ring->page_pool);
379 	WARN_ON(!page);
380 	dma = page_pool_get_dma_addr(page);
381 
382 	bi->page_dma = dma;
383 	bi->page = page;
384 	bi->page_offset = 0;
385 	page_ref_add(page, USHRT_MAX - 1);
386 	bi->pagecnt_bias = USHRT_MAX;
387 
388 	return true;
389 }
390 
391 /**
392  * wx_alloc_rx_buffers - Replace used receive buffers
393  * @rx_ring: ring to place buffers on
394  * @cleaned_count: number of buffers to replace
395  **/
396 void wx_alloc_rx_buffers(struct wx_ring *rx_ring, u16 cleaned_count)
397 {
398 	u16 i = rx_ring->next_to_use;
399 	union wx_rx_desc *rx_desc;
400 	struct wx_rx_buffer *bi;
401 
402 	/* nothing to do */
403 	if (!cleaned_count)
404 		return;
405 
406 	rx_desc = WX_RX_DESC(rx_ring, i);
407 	bi = &rx_ring->rx_buffer_info[i];
408 	i -= rx_ring->count;
409 
410 	do {
411 		if (!wx_alloc_mapped_page(rx_ring, bi))
412 			break;
413 
414 		/* sync the buffer for use by the device */
415 		dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
416 						 bi->page_offset,
417 						 WX_RX_BUFSZ,
418 						 DMA_FROM_DEVICE);
419 
420 		rx_desc->read.pkt_addr =
421 			cpu_to_le64(bi->page_dma + bi->page_offset);
422 
423 		rx_desc++;
424 		bi++;
425 		i++;
426 		if (unlikely(!i)) {
427 			rx_desc = WX_RX_DESC(rx_ring, 0);
428 			bi = rx_ring->rx_buffer_info;
429 			i -= rx_ring->count;
430 		}
431 
432 		/* clear the status bits for the next_to_use descriptor */
433 		rx_desc->wb.upper.status_error = 0;
434 
435 		cleaned_count--;
436 	} while (cleaned_count);
437 
438 	i += rx_ring->count;
439 
440 	if (rx_ring->next_to_use != i) {
441 		rx_ring->next_to_use = i;
442 		/* update next to alloc since we have filled the ring */
443 		rx_ring->next_to_alloc = i;
444 
445 		/* Force memory writes to complete before letting h/w
446 		 * know there are new descriptors to fetch.  (Only
447 		 * applicable for weak-ordered memory model archs,
448 		 * such as IA-64).
449 		 */
450 		wmb();
451 		writel(i, rx_ring->tail);
452 	}
453 }
454 
455 u16 wx_desc_unused(struct wx_ring *ring)
456 {
457 	u16 ntc = ring->next_to_clean;
458 	u16 ntu = ring->next_to_use;
459 
460 	return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
461 }
462 
463 /**
464  * wx_is_non_eop - process handling of non-EOP buffers
465  * @rx_ring: Rx ring being processed
466  * @rx_desc: Rx descriptor for current buffer
467  * @skb: Current socket buffer containing buffer in progress
468  *
469  * This function updates next to clean. If the buffer is an EOP buffer
470  * this function exits returning false, otherwise it will place the
471  * sk_buff in the next buffer to be chained and return true indicating
472  * that this is in fact a non-EOP buffer.
473  **/
474 static bool wx_is_non_eop(struct wx_ring *rx_ring,
475 			  union wx_rx_desc *rx_desc,
476 			  struct sk_buff *skb)
477 {
478 	u32 ntc = rx_ring->next_to_clean + 1;
479 
480 	/* fetch, update, and store next to clean */
481 	ntc = (ntc < rx_ring->count) ? ntc : 0;
482 	rx_ring->next_to_clean = ntc;
483 
484 	prefetch(WX_RX_DESC(rx_ring, ntc));
485 
486 	/* if we are the last buffer then there is nothing else to do */
487 	if (likely(wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)))
488 		return false;
489 
490 	rx_ring->rx_buffer_info[ntc].skb = skb;
491 
492 	return true;
493 }
494 
495 static void wx_pull_tail(struct sk_buff *skb)
496 {
497 	skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
498 	unsigned int pull_len;
499 	unsigned char *va;
500 
501 	/* it is valid to use page_address instead of kmap since we are
502 	 * working with pages allocated out of the lomem pool per
503 	 * alloc_page(GFP_ATOMIC)
504 	 */
505 	va = skb_frag_address(frag);
506 
507 	/* we need the header to contain the greater of either ETH_HLEN or
508 	 * 60 bytes if the skb->len is less than 60 for skb_pad.
509 	 */
510 	pull_len = eth_get_headlen(skb->dev, va, WX_RXBUFFER_256);
511 
512 	/* align pull length to size of long to optimize memcpy performance */
513 	skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
514 
515 	/* update all of the pointers */
516 	skb_frag_size_sub(frag, pull_len);
517 	skb_frag_off_add(frag, pull_len);
518 	skb->data_len -= pull_len;
519 	skb->tail += pull_len;
520 }
521 
522 /**
523  * wx_cleanup_headers - Correct corrupted or empty headers
524  * @rx_ring: rx descriptor ring packet is being transacted on
525  * @rx_desc: pointer to the EOP Rx descriptor
526  * @skb: pointer to current skb being fixed
527  *
528  * Check for corrupted packet headers caused by senders on the local L2
529  * embedded NIC switch not setting up their Tx Descriptors right.  These
530  * should be very rare.
531  *
532  * Also address the case where we are pulling data in on pages only
533  * and as such no data is present in the skb header.
534  *
535  * In addition if skb is not at least 60 bytes we need to pad it so that
536  * it is large enough to qualify as a valid Ethernet frame.
537  *
538  * Returns true if an error was encountered and skb was freed.
539  **/
540 static bool wx_cleanup_headers(struct wx_ring *rx_ring,
541 			       union wx_rx_desc *rx_desc,
542 			       struct sk_buff *skb)
543 {
544 	struct net_device *netdev = rx_ring->netdev;
545 
546 	/* verify that the packet does not have any known errors */
547 	if (!netdev ||
548 	    unlikely(wx_test_staterr(rx_desc, WX_RXD_ERR_RXE) &&
549 		     !(netdev->features & NETIF_F_RXALL))) {
550 		dev_kfree_skb_any(skb);
551 		return true;
552 	}
553 
554 	/* place header in linear portion of buffer */
555 	if (!skb_headlen(skb))
556 		wx_pull_tail(skb);
557 
558 	/* if eth_skb_pad returns an error the skb was freed */
559 	if (eth_skb_pad(skb))
560 		return true;
561 
562 	return false;
563 }
564 
565 static void wx_rx_hash(struct wx_ring *ring,
566 		       union wx_rx_desc *rx_desc,
567 		       struct sk_buff *skb)
568 {
569 	u16 rss_type;
570 
571 	if (!(ring->netdev->features & NETIF_F_RXHASH))
572 		return;
573 
574 	rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
575 			       WX_RXD_RSSTYPE_MASK;
576 
577 	if (!rss_type)
578 		return;
579 
580 	skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
581 		     (WX_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
582 		     PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
583 }
584 
585 /**
586  * wx_rx_checksum - indicate in skb if hw indicated a good cksum
587  * @ring: structure containing ring specific data
588  * @rx_desc: current Rx descriptor being processed
589  * @skb: skb currently being received and modified
590  **/
591 static void wx_rx_checksum(struct wx_ring *ring,
592 			   union wx_rx_desc *rx_desc,
593 			   struct sk_buff *skb)
594 {
595 	struct wx_dec_ptype dptype = wx_decode_ptype(WX_RXD_PKTTYPE(rx_desc));
596 
597 	skb_checksum_none_assert(skb);
598 	/* Rx csum disabled */
599 	if (!(ring->netdev->features & NETIF_F_RXCSUM))
600 		return;
601 
602 	/* if IPv4 header checksum error */
603 	if ((wx_test_staterr(rx_desc, WX_RXD_STAT_IPCS) &&
604 	     wx_test_staterr(rx_desc, WX_RXD_ERR_IPE)) ||
605 	    (wx_test_staterr(rx_desc, WX_RXD_STAT_OUTERIPCS) &&
606 	     wx_test_staterr(rx_desc, WX_RXD_ERR_OUTERIPER))) {
607 		ring->rx_stats.csum_err++;
608 		return;
609 	}
610 
611 	/* L4 checksum offload flag must set for the below code to work */
612 	if (!wx_test_staterr(rx_desc, WX_RXD_STAT_L4CS))
613 		return;
614 
615 	/* Hardware can't guarantee csum if IPv6 Dest Header found */
616 	if (dptype.prot != WX_DEC_PTYPE_PROT_SCTP && WX_RXD_IPV6EX(rx_desc))
617 		return;
618 
619 	/* if L4 checksum error */
620 	if (wx_test_staterr(rx_desc, WX_RXD_ERR_TCPE)) {
621 		ring->rx_stats.csum_err++;
622 		return;
623 	}
624 
625 	/* It must be a TCP or UDP or SCTP packet with a valid checksum */
626 	skb->ip_summed = CHECKSUM_UNNECESSARY;
627 
628 	/* If there is an outer header present that might contain a checksum
629 	 * we need to bump the checksum level by 1 to reflect the fact that
630 	 * we are indicating we validated the inner checksum.
631 	 */
632 	if (dptype.etype >= WX_DEC_PTYPE_ETYPE_IG)
633 		__skb_incr_checksum_unnecessary(skb);
634 	ring->rx_stats.csum_good_cnt++;
635 }
636 
637 static void wx_rx_vlan(struct wx_ring *ring, union wx_rx_desc *rx_desc,
638 		       struct sk_buff *skb)
639 {
640 	u16 ethertype;
641 	u8 idx = 0;
642 
643 	if ((ring->netdev->features &
644 	     (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) &&
645 	    wx_test_staterr(rx_desc, WX_RXD_STAT_VP)) {
646 		idx = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
647 		       0x1c0) >> 6;
648 		ethertype = ring->q_vector->wx->tpid[idx];
649 		__vlan_hwaccel_put_tag(skb, htons(ethertype),
650 				       le16_to_cpu(rx_desc->wb.upper.vlan));
651 	}
652 }
653 
654 /**
655  * wx_process_skb_fields - Populate skb header fields from Rx descriptor
656  * @rx_ring: rx descriptor ring packet is being transacted on
657  * @rx_desc: pointer to the EOP Rx descriptor
658  * @skb: pointer to current skb being populated
659  *
660  * This function checks the ring, descriptor, and packet information in
661  * order to populate the hash, checksum, protocol, and
662  * other fields within the skb.
663  **/
664 static void wx_process_skb_fields(struct wx_ring *rx_ring,
665 				  union wx_rx_desc *rx_desc,
666 				  struct sk_buff *skb)
667 {
668 	wx_rx_hash(rx_ring, rx_desc, skb);
669 	wx_rx_checksum(rx_ring, rx_desc, skb);
670 	wx_rx_vlan(rx_ring, rx_desc, skb);
671 	skb_record_rx_queue(skb, rx_ring->queue_index);
672 	skb->protocol = eth_type_trans(skb, rx_ring->netdev);
673 }
674 
675 /**
676  * wx_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
677  * @q_vector: structure containing interrupt and ring information
678  * @rx_ring: rx descriptor ring to transact packets on
679  * @budget: Total limit on number of packets to process
680  *
681  * This function provides a "bounce buffer" approach to Rx interrupt
682  * processing.  The advantage to this is that on systems that have
683  * expensive overhead for IOMMU access this provides a means of avoiding
684  * it by maintaining the mapping of the page to the system.
685  *
686  * Returns amount of work completed.
687  **/
688 static int wx_clean_rx_irq(struct wx_q_vector *q_vector,
689 			   struct wx_ring *rx_ring,
690 			   int budget)
691 {
692 	unsigned int total_rx_bytes = 0, total_rx_packets = 0;
693 	u16 cleaned_count = wx_desc_unused(rx_ring);
694 
695 	do {
696 		struct wx_rx_buffer *rx_buffer;
697 		union wx_rx_desc *rx_desc;
698 		struct sk_buff *skb;
699 		int rx_buffer_pgcnt;
700 
701 		/* return some buffers to hardware, one at a time is too slow */
702 		if (cleaned_count >= WX_RX_BUFFER_WRITE) {
703 			wx_alloc_rx_buffers(rx_ring, cleaned_count);
704 			cleaned_count = 0;
705 		}
706 
707 		rx_desc = WX_RX_DESC(rx_ring, rx_ring->next_to_clean);
708 		if (!wx_test_staterr(rx_desc, WX_RXD_STAT_DD))
709 			break;
710 
711 		/* This memory barrier is needed to keep us from reading
712 		 * any other fields out of the rx_desc until we know the
713 		 * descriptor has been written back
714 		 */
715 		dma_rmb();
716 
717 		rx_buffer = wx_get_rx_buffer(rx_ring, rx_desc, &skb, &rx_buffer_pgcnt);
718 
719 		/* retrieve a buffer from the ring */
720 		skb = wx_build_skb(rx_ring, rx_buffer, rx_desc);
721 
722 		/* exit if we failed to retrieve a buffer */
723 		if (!skb) {
724 			rx_buffer->pagecnt_bias++;
725 			break;
726 		}
727 
728 		wx_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt);
729 		cleaned_count++;
730 
731 		/* place incomplete frames back on ring for completion */
732 		if (wx_is_non_eop(rx_ring, rx_desc, skb))
733 			continue;
734 
735 		/* verify the packet layout is correct */
736 		if (wx_cleanup_headers(rx_ring, rx_desc, skb))
737 			continue;
738 
739 		/* probably a little skewed due to removing CRC */
740 		total_rx_bytes += skb->len;
741 
742 		/* populate checksum, timestamp, VLAN, and protocol */
743 		wx_process_skb_fields(rx_ring, rx_desc, skb);
744 		napi_gro_receive(&q_vector->napi, skb);
745 
746 		/* update budget accounting */
747 		total_rx_packets++;
748 	} while (likely(total_rx_packets < budget));
749 
750 	u64_stats_update_begin(&rx_ring->syncp);
751 	rx_ring->stats.packets += total_rx_packets;
752 	rx_ring->stats.bytes += total_rx_bytes;
753 	u64_stats_update_end(&rx_ring->syncp);
754 	q_vector->rx.total_packets += total_rx_packets;
755 	q_vector->rx.total_bytes += total_rx_bytes;
756 
757 	return total_rx_packets;
758 }
759 
760 static struct netdev_queue *wx_txring_txq(const struct wx_ring *ring)
761 {
762 	return netdev_get_tx_queue(ring->netdev, ring->queue_index);
763 }
764 
765 /**
766  * wx_clean_tx_irq - Reclaim resources after transmit completes
767  * @q_vector: structure containing interrupt and ring information
768  * @tx_ring: tx ring to clean
769  * @napi_budget: Used to determine if we are in netpoll
770  **/
771 static bool wx_clean_tx_irq(struct wx_q_vector *q_vector,
772 			    struct wx_ring *tx_ring, int napi_budget)
773 {
774 	unsigned int budget = q_vector->wx->tx_work_limit;
775 	unsigned int total_bytes = 0, total_packets = 0;
776 	unsigned int i = tx_ring->next_to_clean;
777 	struct wx_tx_buffer *tx_buffer;
778 	union wx_tx_desc *tx_desc;
779 
780 	if (!netif_carrier_ok(tx_ring->netdev))
781 		return true;
782 
783 	tx_buffer = &tx_ring->tx_buffer_info[i];
784 	tx_desc = WX_TX_DESC(tx_ring, i);
785 	i -= tx_ring->count;
786 
787 	do {
788 		union wx_tx_desc *eop_desc = tx_buffer->next_to_watch;
789 
790 		/* if next_to_watch is not set then there is no work pending */
791 		if (!eop_desc)
792 			break;
793 
794 		/* prevent any other reads prior to eop_desc */
795 		smp_rmb();
796 
797 		/* if DD is not set pending work has not been completed */
798 		if (!(eop_desc->wb.status & cpu_to_le32(WX_TXD_STAT_DD)))
799 			break;
800 
801 		/* clear next_to_watch to prevent false hangs */
802 		tx_buffer->next_to_watch = NULL;
803 
804 		/* update the statistics for this packet */
805 		total_bytes += tx_buffer->bytecount;
806 		total_packets += tx_buffer->gso_segs;
807 
808 		/* free the skb */
809 		napi_consume_skb(tx_buffer->skb, napi_budget);
810 
811 		/* unmap skb header data */
812 		dma_unmap_single(tx_ring->dev,
813 				 dma_unmap_addr(tx_buffer, dma),
814 				 dma_unmap_len(tx_buffer, len),
815 				 DMA_TO_DEVICE);
816 
817 		/* clear tx_buffer data */
818 		dma_unmap_len_set(tx_buffer, len, 0);
819 
820 		/* unmap remaining buffers */
821 		while (tx_desc != eop_desc) {
822 			tx_buffer++;
823 			tx_desc++;
824 			i++;
825 			if (unlikely(!i)) {
826 				i -= tx_ring->count;
827 				tx_buffer = tx_ring->tx_buffer_info;
828 				tx_desc = WX_TX_DESC(tx_ring, 0);
829 			}
830 
831 			/* unmap any remaining paged data */
832 			if (dma_unmap_len(tx_buffer, len)) {
833 				dma_unmap_page(tx_ring->dev,
834 					       dma_unmap_addr(tx_buffer, dma),
835 					       dma_unmap_len(tx_buffer, len),
836 					       DMA_TO_DEVICE);
837 				dma_unmap_len_set(tx_buffer, len, 0);
838 			}
839 		}
840 
841 		/* move us one more past the eop_desc for start of next pkt */
842 		tx_buffer++;
843 		tx_desc++;
844 		i++;
845 		if (unlikely(!i)) {
846 			i -= tx_ring->count;
847 			tx_buffer = tx_ring->tx_buffer_info;
848 			tx_desc = WX_TX_DESC(tx_ring, 0);
849 		}
850 
851 		/* issue prefetch for next Tx descriptor */
852 		prefetch(tx_desc);
853 
854 		/* update budget accounting */
855 		budget--;
856 	} while (likely(budget));
857 
858 	i += tx_ring->count;
859 	tx_ring->next_to_clean = i;
860 	u64_stats_update_begin(&tx_ring->syncp);
861 	tx_ring->stats.bytes += total_bytes;
862 	tx_ring->stats.packets += total_packets;
863 	u64_stats_update_end(&tx_ring->syncp);
864 	q_vector->tx.total_bytes += total_bytes;
865 	q_vector->tx.total_packets += total_packets;
866 
867 	netdev_tx_completed_queue(wx_txring_txq(tx_ring),
868 				  total_packets, total_bytes);
869 
870 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
871 	if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
872 		     (wx_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
873 		/* Make sure that anybody stopping the queue after this
874 		 * sees the new next_to_clean.
875 		 */
876 		smp_mb();
877 
878 		if (__netif_subqueue_stopped(tx_ring->netdev,
879 					     tx_ring->queue_index) &&
880 		    netif_running(tx_ring->netdev))
881 			netif_wake_subqueue(tx_ring->netdev,
882 					    tx_ring->queue_index);
883 	}
884 
885 	return !!budget;
886 }
887 
888 /**
889  * wx_poll - NAPI polling RX/TX cleanup routine
890  * @napi: napi struct with our devices info in it
891  * @budget: amount of work driver is allowed to do this pass, in packets
892  *
893  * This function will clean all queues associated with a q_vector.
894  **/
895 static int wx_poll(struct napi_struct *napi, int budget)
896 {
897 	struct wx_q_vector *q_vector = container_of(napi, struct wx_q_vector, napi);
898 	int per_ring_budget, work_done = 0;
899 	struct wx *wx = q_vector->wx;
900 	bool clean_complete = true;
901 	struct wx_ring *ring;
902 
903 	wx_for_each_ring(ring, q_vector->tx) {
904 		if (!wx_clean_tx_irq(q_vector, ring, budget))
905 			clean_complete = false;
906 	}
907 
908 	/* Exit if we are called by netpoll */
909 	if (budget <= 0)
910 		return budget;
911 
912 	/* attempt to distribute budget to each queue fairly, but don't allow
913 	 * the budget to go below 1 because we'll exit polling
914 	 */
915 	if (q_vector->rx.count > 1)
916 		per_ring_budget = max(budget / q_vector->rx.count, 1);
917 	else
918 		per_ring_budget = budget;
919 
920 	wx_for_each_ring(ring, q_vector->rx) {
921 		int cleaned = wx_clean_rx_irq(q_vector, ring, per_ring_budget);
922 
923 		work_done += cleaned;
924 		if (cleaned >= per_ring_budget)
925 			clean_complete = false;
926 	}
927 
928 	/* If all work not completed, return budget and keep polling */
929 	if (!clean_complete)
930 		return budget;
931 
932 	/* all work done, exit the polling mode */
933 	if (likely(napi_complete_done(napi, work_done))) {
934 		if (netif_running(wx->netdev))
935 			wx_intr_enable(wx, WX_INTR_Q(q_vector->v_idx));
936 	}
937 
938 	return min(work_done, budget - 1);
939 }
940 
941 static int wx_maybe_stop_tx(struct wx_ring *tx_ring, u16 size)
942 {
943 	if (likely(wx_desc_unused(tx_ring) >= size))
944 		return 0;
945 
946 	netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
947 
948 	/* For the next check */
949 	smp_mb();
950 
951 	/* We need to check again in a case another CPU has just
952 	 * made room available.
953 	 */
954 	if (likely(wx_desc_unused(tx_ring) < size))
955 		return -EBUSY;
956 
957 	/* A reprieve! - use start_queue because it doesn't call schedule */
958 	netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
959 
960 	return 0;
961 }
962 
963 static u32 wx_tx_cmd_type(u32 tx_flags)
964 {
965 	/* set type for advanced descriptor with frame checksum insertion */
966 	u32 cmd_type = WX_TXD_DTYP_DATA | WX_TXD_IFCS;
967 
968 	/* set HW vlan bit if vlan is present */
969 	cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_HW_VLAN, WX_TXD_VLE);
970 	/* set segmentation enable bits for TSO/FSO */
971 	cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSO, WX_TXD_TSE);
972 	/* set timestamp bit if present */
973 	cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSTAMP, WX_TXD_MAC_TSTAMP);
974 	cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_LINKSEC, WX_TXD_LINKSEC);
975 
976 	return cmd_type;
977 }
978 
979 static void wx_tx_olinfo_status(union wx_tx_desc *tx_desc,
980 				u32 tx_flags, unsigned int paylen)
981 {
982 	u32 olinfo_status = paylen << WX_TXD_PAYLEN_SHIFT;
983 
984 	/* enable L4 checksum for TSO and TX checksum offload */
985 	olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CSUM, WX_TXD_L4CS);
986 	/* enable IPv4 checksum for TSO */
987 	olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPV4, WX_TXD_IIPCS);
988 	/* enable outer IPv4 checksum for TSO */
989 	olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_OUTER_IPV4,
990 				     WX_TXD_EIPCS);
991 	/* Check Context must be set if Tx switch is enabled, which it
992 	 * always is for case where virtual functions are running
993 	 */
994 	olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CC, WX_TXD_CC);
995 	olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPSEC,
996 				     WX_TXD_IPSEC);
997 	tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
998 }
999 
1000 static void wx_tx_map(struct wx_ring *tx_ring,
1001 		      struct wx_tx_buffer *first,
1002 		      const u8 hdr_len)
1003 {
1004 	struct sk_buff *skb = first->skb;
1005 	struct wx_tx_buffer *tx_buffer;
1006 	u32 tx_flags = first->tx_flags;
1007 	u16 i = tx_ring->next_to_use;
1008 	unsigned int data_len, size;
1009 	union wx_tx_desc *tx_desc;
1010 	skb_frag_t *frag;
1011 	dma_addr_t dma;
1012 	u32 cmd_type;
1013 
1014 	cmd_type = wx_tx_cmd_type(tx_flags);
1015 	tx_desc = WX_TX_DESC(tx_ring, i);
1016 	wx_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
1017 
1018 	size = skb_headlen(skb);
1019 	data_len = skb->data_len;
1020 	dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1021 
1022 	tx_buffer = first;
1023 
1024 	for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1025 		if (dma_mapping_error(tx_ring->dev, dma))
1026 			goto dma_error;
1027 
1028 		/* record length, and DMA address */
1029 		dma_unmap_len_set(tx_buffer, len, size);
1030 		dma_unmap_addr_set(tx_buffer, dma, dma);
1031 
1032 		tx_desc->read.buffer_addr = cpu_to_le64(dma);
1033 
1034 		while (unlikely(size > WX_MAX_DATA_PER_TXD)) {
1035 			tx_desc->read.cmd_type_len =
1036 				cpu_to_le32(cmd_type ^ WX_MAX_DATA_PER_TXD);
1037 
1038 			i++;
1039 			tx_desc++;
1040 			if (i == tx_ring->count) {
1041 				tx_desc = WX_TX_DESC(tx_ring, 0);
1042 				i = 0;
1043 			}
1044 			tx_desc->read.olinfo_status = 0;
1045 
1046 			dma += WX_MAX_DATA_PER_TXD;
1047 			size -= WX_MAX_DATA_PER_TXD;
1048 
1049 			tx_desc->read.buffer_addr = cpu_to_le64(dma);
1050 		}
1051 
1052 		if (likely(!data_len))
1053 			break;
1054 
1055 		tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
1056 
1057 		i++;
1058 		tx_desc++;
1059 		if (i == tx_ring->count) {
1060 			tx_desc = WX_TX_DESC(tx_ring, 0);
1061 			i = 0;
1062 		}
1063 		tx_desc->read.olinfo_status = 0;
1064 
1065 		size = skb_frag_size(frag);
1066 
1067 		data_len -= size;
1068 
1069 		dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1070 				       DMA_TO_DEVICE);
1071 
1072 		tx_buffer = &tx_ring->tx_buffer_info[i];
1073 	}
1074 
1075 	/* write last descriptor with RS and EOP bits */
1076 	cmd_type |= size | WX_TXD_EOP | WX_TXD_RS;
1077 	tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
1078 
1079 	netdev_tx_sent_queue(wx_txring_txq(tx_ring), first->bytecount);
1080 
1081 	skb_tx_timestamp(skb);
1082 
1083 	/* Force memory writes to complete before letting h/w know there
1084 	 * are new descriptors to fetch.  (Only applicable for weak-ordered
1085 	 * memory model archs, such as IA-64).
1086 	 *
1087 	 * We also need this memory barrier to make certain all of the
1088 	 * status bits have been updated before next_to_watch is written.
1089 	 */
1090 	wmb();
1091 
1092 	/* set next_to_watch value indicating a packet is present */
1093 	first->next_to_watch = tx_desc;
1094 
1095 	i++;
1096 	if (i == tx_ring->count)
1097 		i = 0;
1098 
1099 	tx_ring->next_to_use = i;
1100 
1101 	wx_maybe_stop_tx(tx_ring, DESC_NEEDED);
1102 
1103 	if (netif_xmit_stopped(wx_txring_txq(tx_ring)) || !netdev_xmit_more())
1104 		writel(i, tx_ring->tail);
1105 
1106 	return;
1107 dma_error:
1108 	dev_err(tx_ring->dev, "TX DMA map failed\n");
1109 
1110 	/* clear dma mappings for failed tx_buffer_info map */
1111 	for (;;) {
1112 		tx_buffer = &tx_ring->tx_buffer_info[i];
1113 		if (dma_unmap_len(tx_buffer, len))
1114 			dma_unmap_page(tx_ring->dev,
1115 				       dma_unmap_addr(tx_buffer, dma),
1116 				       dma_unmap_len(tx_buffer, len),
1117 				       DMA_TO_DEVICE);
1118 		dma_unmap_len_set(tx_buffer, len, 0);
1119 		if (tx_buffer == first)
1120 			break;
1121 		if (i == 0)
1122 			i += tx_ring->count;
1123 		i--;
1124 	}
1125 
1126 	dev_kfree_skb_any(first->skb);
1127 	first->skb = NULL;
1128 
1129 	tx_ring->next_to_use = i;
1130 }
1131 
1132 static void wx_tx_ctxtdesc(struct wx_ring *tx_ring, u32 vlan_macip_lens,
1133 			   u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
1134 {
1135 	struct wx_tx_context_desc *context_desc;
1136 	u16 i = tx_ring->next_to_use;
1137 
1138 	context_desc = WX_TX_CTXTDESC(tx_ring, i);
1139 	i++;
1140 	tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1141 
1142 	/* set bits to identify this as an advanced context descriptor */
1143 	type_tucmd |= WX_TXD_DTYP_CTXT;
1144 	context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
1145 	context_desc->seqnum_seed       = cpu_to_le32(fcoe_sof_eof);
1146 	context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
1147 	context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
1148 }
1149 
1150 static void wx_get_ipv6_proto(struct sk_buff *skb, int offset, u8 *nexthdr)
1151 {
1152 	struct ipv6hdr *hdr = (struct ipv6hdr *)(skb->data + offset);
1153 
1154 	*nexthdr = hdr->nexthdr;
1155 	offset += sizeof(struct ipv6hdr);
1156 	while (ipv6_ext_hdr(*nexthdr)) {
1157 		struct ipv6_opt_hdr _hdr, *hp;
1158 
1159 		if (*nexthdr == NEXTHDR_NONE)
1160 			return;
1161 		hp = skb_header_pointer(skb, offset, sizeof(_hdr), &_hdr);
1162 		if (!hp)
1163 			return;
1164 		if (*nexthdr == NEXTHDR_FRAGMENT)
1165 			break;
1166 		*nexthdr = hp->nexthdr;
1167 	}
1168 }
1169 
1170 union network_header {
1171 	struct iphdr *ipv4;
1172 	struct ipv6hdr *ipv6;
1173 	void *raw;
1174 };
1175 
1176 static u8 wx_encode_tx_desc_ptype(const struct wx_tx_buffer *first)
1177 {
1178 	u8 tun_prot = 0, l4_prot = 0, ptype = 0;
1179 	struct sk_buff *skb = first->skb;
1180 
1181 	if (skb->encapsulation) {
1182 		union network_header hdr;
1183 
1184 		switch (first->protocol) {
1185 		case htons(ETH_P_IP):
1186 			tun_prot = ip_hdr(skb)->protocol;
1187 			ptype = WX_PTYPE_TUN_IPV4;
1188 			break;
1189 		case htons(ETH_P_IPV6):
1190 			wx_get_ipv6_proto(skb, skb_network_offset(skb), &tun_prot);
1191 			ptype = WX_PTYPE_TUN_IPV6;
1192 			break;
1193 		default:
1194 			return ptype;
1195 		}
1196 
1197 		if (tun_prot == IPPROTO_IPIP) {
1198 			hdr.raw = (void *)inner_ip_hdr(skb);
1199 			ptype |= WX_PTYPE_PKT_IPIP;
1200 		} else if (tun_prot == IPPROTO_UDP) {
1201 			hdr.raw = (void *)inner_ip_hdr(skb);
1202 			if (skb->inner_protocol_type != ENCAP_TYPE_ETHER ||
1203 			    skb->inner_protocol != htons(ETH_P_TEB)) {
1204 				ptype |= WX_PTYPE_PKT_IG;
1205 			} else {
1206 				if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto
1207 				     == htons(ETH_P_8021Q))
1208 					ptype |= WX_PTYPE_PKT_IGMV;
1209 				else
1210 					ptype |= WX_PTYPE_PKT_IGM;
1211 			}
1212 
1213 		} else if (tun_prot == IPPROTO_GRE) {
1214 			hdr.raw = (void *)inner_ip_hdr(skb);
1215 			if (skb->inner_protocol ==  htons(ETH_P_IP) ||
1216 			    skb->inner_protocol ==  htons(ETH_P_IPV6)) {
1217 				ptype |= WX_PTYPE_PKT_IG;
1218 			} else {
1219 				if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto
1220 				    == htons(ETH_P_8021Q))
1221 					ptype |= WX_PTYPE_PKT_IGMV;
1222 				else
1223 					ptype |= WX_PTYPE_PKT_IGM;
1224 			}
1225 		} else {
1226 			return ptype;
1227 		}
1228 
1229 		switch (hdr.ipv4->version) {
1230 		case IPVERSION:
1231 			l4_prot = hdr.ipv4->protocol;
1232 			break;
1233 		case 6:
1234 			wx_get_ipv6_proto(skb, skb_inner_network_offset(skb), &l4_prot);
1235 			ptype |= WX_PTYPE_PKT_IPV6;
1236 			break;
1237 		default:
1238 			return ptype;
1239 		}
1240 	} else {
1241 		switch (first->protocol) {
1242 		case htons(ETH_P_IP):
1243 			l4_prot = ip_hdr(skb)->protocol;
1244 			ptype = WX_PTYPE_PKT_IP;
1245 			break;
1246 		case htons(ETH_P_IPV6):
1247 			wx_get_ipv6_proto(skb, skb_network_offset(skb), &l4_prot);
1248 			ptype = WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6;
1249 			break;
1250 		default:
1251 			return WX_PTYPE_PKT_MAC | WX_PTYPE_TYP_MAC;
1252 		}
1253 	}
1254 	switch (l4_prot) {
1255 	case IPPROTO_TCP:
1256 		ptype |= WX_PTYPE_TYP_TCP;
1257 		break;
1258 	case IPPROTO_UDP:
1259 		ptype |= WX_PTYPE_TYP_UDP;
1260 		break;
1261 	case IPPROTO_SCTP:
1262 		ptype |= WX_PTYPE_TYP_SCTP;
1263 		break;
1264 	default:
1265 		ptype |= WX_PTYPE_TYP_IP;
1266 		break;
1267 	}
1268 
1269 	return ptype;
1270 }
1271 
1272 static int wx_tso(struct wx_ring *tx_ring, struct wx_tx_buffer *first,
1273 		  u8 *hdr_len, u8 ptype)
1274 {
1275 	u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
1276 	struct net_device *netdev = tx_ring->netdev;
1277 	u32 l4len, tunhdr_eiplen_tunlen = 0;
1278 	struct sk_buff *skb = first->skb;
1279 	bool enc = skb->encapsulation;
1280 	struct ipv6hdr *ipv6h;
1281 	struct tcphdr *tcph;
1282 	struct iphdr *iph;
1283 	u8 tun_prot = 0;
1284 	int err;
1285 
1286 	if (skb->ip_summed != CHECKSUM_PARTIAL)
1287 		return 0;
1288 
1289 	if (!skb_is_gso(skb))
1290 		return 0;
1291 
1292 	err = skb_cow_head(skb, 0);
1293 	if (err < 0)
1294 		return err;
1295 
1296 	/* indicates the inner headers in the skbuff are valid. */
1297 	iph = enc ? inner_ip_hdr(skb) : ip_hdr(skb);
1298 	if (iph->version == 4) {
1299 		tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1300 		iph->tot_len = 0;
1301 		iph->check = 0;
1302 		tcph->check = ~csum_tcpudp_magic(iph->saddr,
1303 						 iph->daddr, 0,
1304 						 IPPROTO_TCP, 0);
1305 		first->tx_flags |= WX_TX_FLAGS_TSO |
1306 				   WX_TX_FLAGS_CSUM |
1307 				   WX_TX_FLAGS_IPV4 |
1308 				   WX_TX_FLAGS_CC;
1309 	} else if (iph->version == 6 && skb_is_gso_v6(skb)) {
1310 		ipv6h = enc ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1311 		tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1312 		ipv6h->payload_len = 0;
1313 		tcph->check = ~csum_ipv6_magic(&ipv6h->saddr,
1314 					       &ipv6h->daddr, 0,
1315 					       IPPROTO_TCP, 0);
1316 		first->tx_flags |= WX_TX_FLAGS_TSO |
1317 				   WX_TX_FLAGS_CSUM |
1318 				   WX_TX_FLAGS_CC;
1319 	}
1320 
1321 	/* compute header lengths */
1322 	l4len = enc ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1323 	*hdr_len = enc ? (skb_inner_transport_header(skb) - skb->data) :
1324 			 skb_transport_offset(skb);
1325 	*hdr_len += l4len;
1326 
1327 	/* update gso size and bytecount with header size */
1328 	first->gso_segs = skb_shinfo(skb)->gso_segs;
1329 	first->bytecount += (first->gso_segs - 1) * *hdr_len;
1330 
1331 	/* mss_l4len_id: use 0 as index for TSO */
1332 	mss_l4len_idx = l4len << WX_TXD_L4LEN_SHIFT;
1333 	mss_l4len_idx |= skb_shinfo(skb)->gso_size << WX_TXD_MSS_SHIFT;
1334 
1335 	/* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
1336 	if (enc) {
1337 		switch (first->protocol) {
1338 		case htons(ETH_P_IP):
1339 			tun_prot = ip_hdr(skb)->protocol;
1340 			first->tx_flags |= WX_TX_FLAGS_OUTER_IPV4;
1341 			break;
1342 		case htons(ETH_P_IPV6):
1343 			tun_prot = ipv6_hdr(skb)->nexthdr;
1344 			break;
1345 		default:
1346 			break;
1347 		}
1348 		switch (tun_prot) {
1349 		case IPPROTO_UDP:
1350 			tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP;
1351 			tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) <<
1352 						 WX_TXD_OUTER_IPLEN_SHIFT) |
1353 						(((skb_inner_mac_header(skb) -
1354 						skb_transport_header(skb)) >> 1) <<
1355 						WX_TXD_TUNNEL_LEN_SHIFT);
1356 			break;
1357 		case IPPROTO_GRE:
1358 			tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE;
1359 			tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) <<
1360 						 WX_TXD_OUTER_IPLEN_SHIFT) |
1361 						(((skb_inner_mac_header(skb) -
1362 						skb_transport_header(skb)) >> 1) <<
1363 						WX_TXD_TUNNEL_LEN_SHIFT);
1364 			break;
1365 		case IPPROTO_IPIP:
1366 			tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) -
1367 						(char *)ip_hdr(skb)) >> 2) <<
1368 						WX_TXD_OUTER_IPLEN_SHIFT;
1369 			break;
1370 		default:
1371 			break;
1372 		}
1373 		vlan_macip_lens = skb_inner_network_header_len(skb) >> 1;
1374 	} else {
1375 		vlan_macip_lens = skb_network_header_len(skb) >> 1;
1376 	}
1377 
1378 	vlan_macip_lens |= skb_network_offset(skb) << WX_TXD_MACLEN_SHIFT;
1379 	vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK;
1380 
1381 	type_tucmd = ptype << 24;
1382 	if (skb->vlan_proto == htons(ETH_P_8021AD) &&
1383 	    netdev->features & NETIF_F_HW_VLAN_STAG_TX)
1384 		type_tucmd |= WX_SET_FLAG(first->tx_flags,
1385 					  WX_TX_FLAGS_HW_VLAN,
1386 					  0x1 << WX_TXD_TAG_TPID_SEL_SHIFT);
1387 	wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen,
1388 		       type_tucmd, mss_l4len_idx);
1389 
1390 	return 1;
1391 }
1392 
1393 static void wx_tx_csum(struct wx_ring *tx_ring, struct wx_tx_buffer *first,
1394 		       u8 ptype)
1395 {
1396 	u32 tunhdr_eiplen_tunlen = 0, vlan_macip_lens = 0;
1397 	struct net_device *netdev = tx_ring->netdev;
1398 	u32 mss_l4len_idx = 0, type_tucmd;
1399 	struct sk_buff *skb = first->skb;
1400 	u8 tun_prot = 0;
1401 
1402 	if (skb->ip_summed != CHECKSUM_PARTIAL) {
1403 		if (!(first->tx_flags & WX_TX_FLAGS_HW_VLAN) &&
1404 		    !(first->tx_flags & WX_TX_FLAGS_CC))
1405 			return;
1406 		vlan_macip_lens = skb_network_offset(skb) <<
1407 				  WX_TXD_MACLEN_SHIFT;
1408 	} else {
1409 		u8 l4_prot = 0;
1410 		union {
1411 			struct iphdr *ipv4;
1412 			struct ipv6hdr *ipv6;
1413 			u8 *raw;
1414 		} network_hdr;
1415 		union {
1416 			struct tcphdr *tcphdr;
1417 			u8 *raw;
1418 		} transport_hdr;
1419 
1420 		if (skb->encapsulation) {
1421 			network_hdr.raw = skb_inner_network_header(skb);
1422 			transport_hdr.raw = skb_inner_transport_header(skb);
1423 			vlan_macip_lens = skb_network_offset(skb) <<
1424 					  WX_TXD_MACLEN_SHIFT;
1425 			switch (first->protocol) {
1426 			case htons(ETH_P_IP):
1427 				tun_prot = ip_hdr(skb)->protocol;
1428 				break;
1429 			case htons(ETH_P_IPV6):
1430 				tun_prot = ipv6_hdr(skb)->nexthdr;
1431 				break;
1432 			default:
1433 				return;
1434 			}
1435 			switch (tun_prot) {
1436 			case IPPROTO_UDP:
1437 				tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP;
1438 				tunhdr_eiplen_tunlen |=
1439 					((skb_network_header_len(skb) >> 2) <<
1440 					WX_TXD_OUTER_IPLEN_SHIFT) |
1441 					(((skb_inner_mac_header(skb) -
1442 					skb_transport_header(skb)) >> 1) <<
1443 					WX_TXD_TUNNEL_LEN_SHIFT);
1444 				break;
1445 			case IPPROTO_GRE:
1446 				tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE;
1447 				tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) <<
1448 							 WX_TXD_OUTER_IPLEN_SHIFT) |
1449 							 (((skb_inner_mac_header(skb) -
1450 							    skb_transport_header(skb)) >> 1) <<
1451 							  WX_TXD_TUNNEL_LEN_SHIFT);
1452 				break;
1453 			case IPPROTO_IPIP:
1454 				tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) -
1455 							(char *)ip_hdr(skb)) >> 2) <<
1456 							WX_TXD_OUTER_IPLEN_SHIFT;
1457 				break;
1458 			default:
1459 				break;
1460 			}
1461 
1462 		} else {
1463 			network_hdr.raw = skb_network_header(skb);
1464 			transport_hdr.raw = skb_transport_header(skb);
1465 			vlan_macip_lens = skb_network_offset(skb) <<
1466 					  WX_TXD_MACLEN_SHIFT;
1467 		}
1468 
1469 		switch (network_hdr.ipv4->version) {
1470 		case IPVERSION:
1471 			vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1;
1472 			l4_prot = network_hdr.ipv4->protocol;
1473 			break;
1474 		case 6:
1475 			vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1;
1476 			l4_prot = network_hdr.ipv6->nexthdr;
1477 			break;
1478 		default:
1479 			break;
1480 		}
1481 
1482 		switch (l4_prot) {
1483 		case IPPROTO_TCP:
1484 		mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) <<
1485 				WX_TXD_L4LEN_SHIFT;
1486 			break;
1487 		case IPPROTO_SCTP:
1488 			mss_l4len_idx = sizeof(struct sctphdr) <<
1489 					WX_TXD_L4LEN_SHIFT;
1490 			break;
1491 		case IPPROTO_UDP:
1492 			mss_l4len_idx = sizeof(struct udphdr) <<
1493 					WX_TXD_L4LEN_SHIFT;
1494 			break;
1495 		default:
1496 			break;
1497 		}
1498 
1499 		/* update TX checksum flag */
1500 		first->tx_flags |= WX_TX_FLAGS_CSUM;
1501 	}
1502 	first->tx_flags |= WX_TX_FLAGS_CC;
1503 	/* vlan_macip_lens: MACLEN, VLAN tag */
1504 	vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK;
1505 
1506 	type_tucmd = ptype << 24;
1507 	if (skb->vlan_proto == htons(ETH_P_8021AD) &&
1508 	    netdev->features & NETIF_F_HW_VLAN_STAG_TX)
1509 		type_tucmd |= WX_SET_FLAG(first->tx_flags,
1510 					  WX_TX_FLAGS_HW_VLAN,
1511 					  0x1 << WX_TXD_TAG_TPID_SEL_SHIFT);
1512 	wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen,
1513 		       type_tucmd, mss_l4len_idx);
1514 }
1515 
1516 static netdev_tx_t wx_xmit_frame_ring(struct sk_buff *skb,
1517 				      struct wx_ring *tx_ring)
1518 {
1519 	u16 count = TXD_USE_COUNT(skb_headlen(skb));
1520 	struct wx_tx_buffer *first;
1521 	u8 hdr_len = 0, ptype;
1522 	unsigned short f;
1523 	u32 tx_flags = 0;
1524 	int tso;
1525 
1526 	/* need: 1 descriptor per page * PAGE_SIZE/WX_MAX_DATA_PER_TXD,
1527 	 *       + 1 desc for skb_headlen/WX_MAX_DATA_PER_TXD,
1528 	 *       + 2 desc gap to keep tail from touching head,
1529 	 *       + 1 desc for context descriptor,
1530 	 * otherwise try next time
1531 	 */
1532 	for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1533 		count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)->
1534 						     frags[f]));
1535 
1536 	if (wx_maybe_stop_tx(tx_ring, count + 3))
1537 		return NETDEV_TX_BUSY;
1538 
1539 	/* record the location of the first descriptor for this packet */
1540 	first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
1541 	first->skb = skb;
1542 	first->bytecount = skb->len;
1543 	first->gso_segs = 1;
1544 
1545 	/* if we have a HW VLAN tag being added default to the HW one */
1546 	if (skb_vlan_tag_present(skb)) {
1547 		tx_flags |= skb_vlan_tag_get(skb) << WX_TX_FLAGS_VLAN_SHIFT;
1548 		tx_flags |= WX_TX_FLAGS_HW_VLAN;
1549 	}
1550 
1551 	/* record initial flags and protocol */
1552 	first->tx_flags = tx_flags;
1553 	first->protocol = vlan_get_protocol(skb);
1554 
1555 	ptype = wx_encode_tx_desc_ptype(first);
1556 
1557 	tso = wx_tso(tx_ring, first, &hdr_len, ptype);
1558 	if (tso < 0)
1559 		goto out_drop;
1560 	else if (!tso)
1561 		wx_tx_csum(tx_ring, first, ptype);
1562 	wx_tx_map(tx_ring, first, hdr_len);
1563 
1564 	return NETDEV_TX_OK;
1565 out_drop:
1566 	dev_kfree_skb_any(first->skb);
1567 	first->skb = NULL;
1568 
1569 	return NETDEV_TX_OK;
1570 }
1571 
1572 netdev_tx_t wx_xmit_frame(struct sk_buff *skb,
1573 			  struct net_device *netdev)
1574 {
1575 	unsigned int r_idx = skb->queue_mapping;
1576 	struct wx *wx = netdev_priv(netdev);
1577 	struct wx_ring *tx_ring;
1578 
1579 	if (!netif_carrier_ok(netdev)) {
1580 		dev_kfree_skb_any(skb);
1581 		return NETDEV_TX_OK;
1582 	}
1583 
1584 	/* The minimum packet size for olinfo paylen is 17 so pad the skb
1585 	 * in order to meet this minimum size requirement.
1586 	 */
1587 	if (skb_put_padto(skb, 17))
1588 		return NETDEV_TX_OK;
1589 
1590 	if (r_idx >= wx->num_tx_queues)
1591 		r_idx = r_idx % wx->num_tx_queues;
1592 	tx_ring = wx->tx_ring[r_idx];
1593 
1594 	return wx_xmit_frame_ring(skb, tx_ring);
1595 }
1596 EXPORT_SYMBOL(wx_xmit_frame);
1597 
1598 void wx_napi_enable_all(struct wx *wx)
1599 {
1600 	struct wx_q_vector *q_vector;
1601 	int q_idx;
1602 
1603 	for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) {
1604 		q_vector = wx->q_vector[q_idx];
1605 		napi_enable(&q_vector->napi);
1606 	}
1607 }
1608 EXPORT_SYMBOL(wx_napi_enable_all);
1609 
1610 void wx_napi_disable_all(struct wx *wx)
1611 {
1612 	struct wx_q_vector *q_vector;
1613 	int q_idx;
1614 
1615 	for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) {
1616 		q_vector = wx->q_vector[q_idx];
1617 		napi_disable(&q_vector->napi);
1618 	}
1619 }
1620 EXPORT_SYMBOL(wx_napi_disable_all);
1621 
1622 /**
1623  * wx_set_rss_queues: Allocate queues for RSS
1624  * @wx: board private structure to initialize
1625  *
1626  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
1627  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
1628  *
1629  **/
1630 static void wx_set_rss_queues(struct wx *wx)
1631 {
1632 	wx->num_rx_queues = wx->mac.max_rx_queues;
1633 	wx->num_tx_queues = wx->mac.max_tx_queues;
1634 }
1635 
1636 static void wx_set_num_queues(struct wx *wx)
1637 {
1638 	/* Start with base case */
1639 	wx->num_rx_queues = 1;
1640 	wx->num_tx_queues = 1;
1641 	wx->queues_per_pool = 1;
1642 
1643 	wx_set_rss_queues(wx);
1644 }
1645 
1646 /**
1647  * wx_acquire_msix_vectors - acquire MSI-X vectors
1648  * @wx: board private structure
1649  *
1650  * Attempts to acquire a suitable range of MSI-X vector interrupts. Will
1651  * return a negative error code if unable to acquire MSI-X vectors for any
1652  * reason.
1653  */
1654 static int wx_acquire_msix_vectors(struct wx *wx)
1655 {
1656 	struct irq_affinity affd = {0, };
1657 	int nvecs, i;
1658 
1659 	nvecs = min_t(int, num_online_cpus(), wx->mac.max_msix_vectors);
1660 
1661 	wx->msix_entries = kcalloc(nvecs,
1662 				   sizeof(struct msix_entry),
1663 				   GFP_KERNEL);
1664 	if (!wx->msix_entries)
1665 		return -ENOMEM;
1666 
1667 	nvecs = pci_alloc_irq_vectors_affinity(wx->pdev, nvecs,
1668 					       nvecs,
1669 					       PCI_IRQ_MSIX | PCI_IRQ_AFFINITY,
1670 					       &affd);
1671 	if (nvecs < 0) {
1672 		wx_err(wx, "Failed to allocate MSI-X interrupts. Err: %d\n", nvecs);
1673 		kfree(wx->msix_entries);
1674 		wx->msix_entries = NULL;
1675 		return nvecs;
1676 	}
1677 
1678 	for (i = 0; i < nvecs; i++) {
1679 		wx->msix_entries[i].entry = i;
1680 		wx->msix_entries[i].vector = pci_irq_vector(wx->pdev, i);
1681 	}
1682 
1683 	/* one for msix_other */
1684 	nvecs -= 1;
1685 	wx->num_q_vectors = nvecs;
1686 	wx->num_rx_queues = nvecs;
1687 	wx->num_tx_queues = nvecs;
1688 
1689 	return 0;
1690 }
1691 
1692 /**
1693  * wx_set_interrupt_capability - set MSI-X or MSI if supported
1694  * @wx: board private structure to initialize
1695  *
1696  * Attempt to configure the interrupts using the best available
1697  * capabilities of the hardware and the kernel.
1698  **/
1699 static int wx_set_interrupt_capability(struct wx *wx)
1700 {
1701 	struct pci_dev *pdev = wx->pdev;
1702 	int nvecs, ret;
1703 
1704 	/* We will try to get MSI-X interrupts first */
1705 	ret = wx_acquire_msix_vectors(wx);
1706 	if (ret == 0 || (ret == -ENOMEM))
1707 		return ret;
1708 
1709 	wx->num_rx_queues = 1;
1710 	wx->num_tx_queues = 1;
1711 	wx->num_q_vectors = 1;
1712 
1713 	/* minmum one for queue, one for misc*/
1714 	nvecs = 1;
1715 	nvecs = pci_alloc_irq_vectors(pdev, nvecs,
1716 				      nvecs, PCI_IRQ_MSI | PCI_IRQ_LEGACY);
1717 	if (nvecs == 1) {
1718 		if (pdev->msi_enabled)
1719 			wx_err(wx, "Fallback to MSI.\n");
1720 		else
1721 			wx_err(wx, "Fallback to LEGACY.\n");
1722 	} else {
1723 		wx_err(wx, "Failed to allocate MSI/LEGACY interrupts. Error: %d\n", nvecs);
1724 		return nvecs;
1725 	}
1726 
1727 	pdev->irq = pci_irq_vector(pdev, 0);
1728 
1729 	return 0;
1730 }
1731 
1732 /**
1733  * wx_cache_ring_rss - Descriptor ring to register mapping for RSS
1734  * @wx: board private structure to initialize
1735  *
1736  * Cache the descriptor ring offsets for RSS, ATR, FCoE, and SR-IOV.
1737  *
1738  **/
1739 static void wx_cache_ring_rss(struct wx *wx)
1740 {
1741 	u16 i;
1742 
1743 	for (i = 0; i < wx->num_rx_queues; i++)
1744 		wx->rx_ring[i]->reg_idx = i;
1745 
1746 	for (i = 0; i < wx->num_tx_queues; i++)
1747 		wx->tx_ring[i]->reg_idx = i;
1748 }
1749 
1750 static void wx_add_ring(struct wx_ring *ring, struct wx_ring_container *head)
1751 {
1752 	ring->next = head->ring;
1753 	head->ring = ring;
1754 	head->count++;
1755 }
1756 
1757 /**
1758  * wx_alloc_q_vector - Allocate memory for a single interrupt vector
1759  * @wx: board private structure to initialize
1760  * @v_count: q_vectors allocated on wx, used for ring interleaving
1761  * @v_idx: index of vector in wx struct
1762  * @txr_count: total number of Tx rings to allocate
1763  * @txr_idx: index of first Tx ring to allocate
1764  * @rxr_count: total number of Rx rings to allocate
1765  * @rxr_idx: index of first Rx ring to allocate
1766  *
1767  * We allocate one q_vector.  If allocation fails we return -ENOMEM.
1768  **/
1769 static int wx_alloc_q_vector(struct wx *wx,
1770 			     unsigned int v_count, unsigned int v_idx,
1771 			     unsigned int txr_count, unsigned int txr_idx,
1772 			     unsigned int rxr_count, unsigned int rxr_idx)
1773 {
1774 	struct wx_q_vector *q_vector;
1775 	int ring_count, default_itr;
1776 	struct wx_ring *ring;
1777 
1778 	/* note this will allocate space for the ring structure as well! */
1779 	ring_count = txr_count + rxr_count;
1780 
1781 	q_vector = kzalloc(struct_size(q_vector, ring, ring_count),
1782 			   GFP_KERNEL);
1783 	if (!q_vector)
1784 		return -ENOMEM;
1785 
1786 	/* initialize NAPI */
1787 	netif_napi_add(wx->netdev, &q_vector->napi,
1788 		       wx_poll);
1789 
1790 	/* tie q_vector and wx together */
1791 	wx->q_vector[v_idx] = q_vector;
1792 	q_vector->wx = wx;
1793 	q_vector->v_idx = v_idx;
1794 	if (cpu_online(v_idx))
1795 		q_vector->numa_node = cpu_to_node(v_idx);
1796 
1797 	/* initialize pointer to rings */
1798 	ring = q_vector->ring;
1799 
1800 	if (wx->mac.type == wx_mac_sp)
1801 		default_itr = WX_12K_ITR;
1802 	else
1803 		default_itr = WX_7K_ITR;
1804 	/* initialize ITR */
1805 	if (txr_count && !rxr_count)
1806 		/* tx only vector */
1807 		q_vector->itr = wx->tx_itr_setting ?
1808 				default_itr : wx->tx_itr_setting;
1809 	else
1810 		/* rx or rx/tx vector */
1811 		q_vector->itr = wx->rx_itr_setting ?
1812 				default_itr : wx->rx_itr_setting;
1813 
1814 	while (txr_count) {
1815 		/* assign generic ring traits */
1816 		ring->dev = &wx->pdev->dev;
1817 		ring->netdev = wx->netdev;
1818 
1819 		/* configure backlink on ring */
1820 		ring->q_vector = q_vector;
1821 
1822 		/* update q_vector Tx values */
1823 		wx_add_ring(ring, &q_vector->tx);
1824 
1825 		/* apply Tx specific ring traits */
1826 		ring->count = wx->tx_ring_count;
1827 
1828 		ring->queue_index = txr_idx;
1829 
1830 		/* assign ring to wx */
1831 		wx->tx_ring[txr_idx] = ring;
1832 
1833 		/* update count and index */
1834 		txr_count--;
1835 		txr_idx += v_count;
1836 
1837 		/* push pointer to next ring */
1838 		ring++;
1839 	}
1840 
1841 	while (rxr_count) {
1842 		/* assign generic ring traits */
1843 		ring->dev = &wx->pdev->dev;
1844 		ring->netdev = wx->netdev;
1845 
1846 		/* configure backlink on ring */
1847 		ring->q_vector = q_vector;
1848 
1849 		/* update q_vector Rx values */
1850 		wx_add_ring(ring, &q_vector->rx);
1851 
1852 		/* apply Rx specific ring traits */
1853 		ring->count = wx->rx_ring_count;
1854 		ring->queue_index = rxr_idx;
1855 
1856 		/* assign ring to wx */
1857 		wx->rx_ring[rxr_idx] = ring;
1858 
1859 		/* update count and index */
1860 		rxr_count--;
1861 		rxr_idx += v_count;
1862 
1863 		/* push pointer to next ring */
1864 		ring++;
1865 	}
1866 
1867 	return 0;
1868 }
1869 
1870 /**
1871  * wx_free_q_vector - Free memory allocated for specific interrupt vector
1872  * @wx: board private structure to initialize
1873  * @v_idx: Index of vector to be freed
1874  *
1875  * This function frees the memory allocated to the q_vector.  In addition if
1876  * NAPI is enabled it will delete any references to the NAPI struct prior
1877  * to freeing the q_vector.
1878  **/
1879 static void wx_free_q_vector(struct wx *wx, int v_idx)
1880 {
1881 	struct wx_q_vector *q_vector = wx->q_vector[v_idx];
1882 	struct wx_ring *ring;
1883 
1884 	wx_for_each_ring(ring, q_vector->tx)
1885 		wx->tx_ring[ring->queue_index] = NULL;
1886 
1887 	wx_for_each_ring(ring, q_vector->rx)
1888 		wx->rx_ring[ring->queue_index] = NULL;
1889 
1890 	wx->q_vector[v_idx] = NULL;
1891 	netif_napi_del(&q_vector->napi);
1892 	kfree_rcu(q_vector, rcu);
1893 }
1894 
1895 /**
1896  * wx_alloc_q_vectors - Allocate memory for interrupt vectors
1897  * @wx: board private structure to initialize
1898  *
1899  * We allocate one q_vector per queue interrupt.  If allocation fails we
1900  * return -ENOMEM.
1901  **/
1902 static int wx_alloc_q_vectors(struct wx *wx)
1903 {
1904 	unsigned int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1905 	unsigned int rxr_remaining = wx->num_rx_queues;
1906 	unsigned int txr_remaining = wx->num_tx_queues;
1907 	unsigned int q_vectors = wx->num_q_vectors;
1908 	int rqpv, tqpv;
1909 	int err;
1910 
1911 	for (; v_idx < q_vectors; v_idx++) {
1912 		rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1913 		tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1914 		err = wx_alloc_q_vector(wx, q_vectors, v_idx,
1915 					tqpv, txr_idx,
1916 					rqpv, rxr_idx);
1917 
1918 		if (err)
1919 			goto err_out;
1920 
1921 		/* update counts and index */
1922 		rxr_remaining -= rqpv;
1923 		txr_remaining -= tqpv;
1924 		rxr_idx++;
1925 		txr_idx++;
1926 	}
1927 
1928 	return 0;
1929 
1930 err_out:
1931 	wx->num_tx_queues = 0;
1932 	wx->num_rx_queues = 0;
1933 	wx->num_q_vectors = 0;
1934 
1935 	while (v_idx--)
1936 		wx_free_q_vector(wx, v_idx);
1937 
1938 	return -ENOMEM;
1939 }
1940 
1941 /**
1942  * wx_free_q_vectors - Free memory allocated for interrupt vectors
1943  * @wx: board private structure to initialize
1944  *
1945  * This function frees the memory allocated to the q_vectors.  In addition if
1946  * NAPI is enabled it will delete any references to the NAPI struct prior
1947  * to freeing the q_vector.
1948  **/
1949 static void wx_free_q_vectors(struct wx *wx)
1950 {
1951 	int v_idx = wx->num_q_vectors;
1952 
1953 	wx->num_tx_queues = 0;
1954 	wx->num_rx_queues = 0;
1955 	wx->num_q_vectors = 0;
1956 
1957 	while (v_idx--)
1958 		wx_free_q_vector(wx, v_idx);
1959 }
1960 
1961 void wx_reset_interrupt_capability(struct wx *wx)
1962 {
1963 	struct pci_dev *pdev = wx->pdev;
1964 
1965 	if (!pdev->msi_enabled && !pdev->msix_enabled)
1966 		return;
1967 
1968 	pci_free_irq_vectors(wx->pdev);
1969 	if (pdev->msix_enabled) {
1970 		kfree(wx->msix_entries);
1971 		wx->msix_entries = NULL;
1972 	}
1973 }
1974 EXPORT_SYMBOL(wx_reset_interrupt_capability);
1975 
1976 /**
1977  * wx_clear_interrupt_scheme - Clear the current interrupt scheme settings
1978  * @wx: board private structure to clear interrupt scheme on
1979  *
1980  * We go through and clear interrupt specific resources and reset the structure
1981  * to pre-load conditions
1982  **/
1983 void wx_clear_interrupt_scheme(struct wx *wx)
1984 {
1985 	wx_free_q_vectors(wx);
1986 	wx_reset_interrupt_capability(wx);
1987 }
1988 EXPORT_SYMBOL(wx_clear_interrupt_scheme);
1989 
1990 int wx_init_interrupt_scheme(struct wx *wx)
1991 {
1992 	int ret;
1993 
1994 	/* Number of supported queues */
1995 	wx_set_num_queues(wx);
1996 
1997 	/* Set interrupt mode */
1998 	ret = wx_set_interrupt_capability(wx);
1999 	if (ret) {
2000 		wx_err(wx, "Allocate irq vectors for failed.\n");
2001 		return ret;
2002 	}
2003 
2004 	/* Allocate memory for queues */
2005 	ret = wx_alloc_q_vectors(wx);
2006 	if (ret) {
2007 		wx_err(wx, "Unable to allocate memory for queue vectors.\n");
2008 		wx_reset_interrupt_capability(wx);
2009 		return ret;
2010 	}
2011 
2012 	wx_cache_ring_rss(wx);
2013 
2014 	return 0;
2015 }
2016 EXPORT_SYMBOL(wx_init_interrupt_scheme);
2017 
2018 irqreturn_t wx_msix_clean_rings(int __always_unused irq, void *data)
2019 {
2020 	struct wx_q_vector *q_vector = data;
2021 
2022 	/* EIAM disabled interrupts (on this vector) for us */
2023 	if (q_vector->rx.ring || q_vector->tx.ring)
2024 		napi_schedule_irqoff(&q_vector->napi);
2025 
2026 	return IRQ_HANDLED;
2027 }
2028 EXPORT_SYMBOL(wx_msix_clean_rings);
2029 
2030 void wx_free_irq(struct wx *wx)
2031 {
2032 	struct pci_dev *pdev = wx->pdev;
2033 	int vector;
2034 
2035 	if (!(pdev->msix_enabled)) {
2036 		free_irq(pdev->irq, wx);
2037 		return;
2038 	}
2039 
2040 	for (vector = 0; vector < wx->num_q_vectors; vector++) {
2041 		struct wx_q_vector *q_vector = wx->q_vector[vector];
2042 		struct msix_entry *entry = &wx->msix_entries[vector];
2043 
2044 		/* free only the irqs that were actually requested */
2045 		if (!q_vector->rx.ring && !q_vector->tx.ring)
2046 			continue;
2047 
2048 		free_irq(entry->vector, q_vector);
2049 	}
2050 
2051 	if (wx->mac.type == wx_mac_em)
2052 		free_irq(wx->msix_entries[vector].vector, wx);
2053 }
2054 EXPORT_SYMBOL(wx_free_irq);
2055 
2056 /**
2057  * wx_setup_isb_resources - allocate interrupt status resources
2058  * @wx: board private structure
2059  *
2060  * Return 0 on success, negative on failure
2061  **/
2062 int wx_setup_isb_resources(struct wx *wx)
2063 {
2064 	struct pci_dev *pdev = wx->pdev;
2065 
2066 	wx->isb_mem = dma_alloc_coherent(&pdev->dev,
2067 					 sizeof(u32) * 4,
2068 					 &wx->isb_dma,
2069 					 GFP_KERNEL);
2070 	if (!wx->isb_mem) {
2071 		wx_err(wx, "Alloc isb_mem failed\n");
2072 		return -ENOMEM;
2073 	}
2074 
2075 	return 0;
2076 }
2077 EXPORT_SYMBOL(wx_setup_isb_resources);
2078 
2079 /**
2080  * wx_free_isb_resources - allocate all queues Rx resources
2081  * @wx: board private structure
2082  *
2083  * Return 0 on success, negative on failure
2084  **/
2085 void wx_free_isb_resources(struct wx *wx)
2086 {
2087 	struct pci_dev *pdev = wx->pdev;
2088 
2089 	dma_free_coherent(&pdev->dev, sizeof(u32) * 4,
2090 			  wx->isb_mem, wx->isb_dma);
2091 	wx->isb_mem = NULL;
2092 }
2093 EXPORT_SYMBOL(wx_free_isb_resources);
2094 
2095 u32 wx_misc_isb(struct wx *wx, enum wx_isb_idx idx)
2096 {
2097 	u32 cur_tag = 0;
2098 
2099 	cur_tag = wx->isb_mem[WX_ISB_HEADER];
2100 	wx->isb_tag[idx] = cur_tag;
2101 
2102 	return (__force u32)cpu_to_le32(wx->isb_mem[idx]);
2103 }
2104 EXPORT_SYMBOL(wx_misc_isb);
2105 
2106 /**
2107  * wx_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
2108  * @wx: pointer to wx struct
2109  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
2110  * @queue: queue to map the corresponding interrupt to
2111  * @msix_vector: the vector to map to the corresponding queue
2112  *
2113  **/
2114 static void wx_set_ivar(struct wx *wx, s8 direction,
2115 			u16 queue, u16 msix_vector)
2116 {
2117 	u32 ivar, index;
2118 
2119 	if (direction == -1) {
2120 		/* other causes */
2121 		msix_vector |= WX_PX_IVAR_ALLOC_VAL;
2122 		index = 0;
2123 		ivar = rd32(wx, WX_PX_MISC_IVAR);
2124 		ivar &= ~(0xFF << index);
2125 		ivar |= (msix_vector << index);
2126 		wr32(wx, WX_PX_MISC_IVAR, ivar);
2127 	} else {
2128 		/* tx or rx causes */
2129 		msix_vector |= WX_PX_IVAR_ALLOC_VAL;
2130 		index = ((16 * (queue & 1)) + (8 * direction));
2131 		ivar = rd32(wx, WX_PX_IVAR(queue >> 1));
2132 		ivar &= ~(0xFF << index);
2133 		ivar |= (msix_vector << index);
2134 		wr32(wx, WX_PX_IVAR(queue >> 1), ivar);
2135 	}
2136 }
2137 
2138 /**
2139  * wx_write_eitr - write EITR register in hardware specific way
2140  * @q_vector: structure containing interrupt and ring information
2141  *
2142  * This function is made to be called by ethtool and by the driver
2143  * when it needs to update EITR registers at runtime.  Hardware
2144  * specific quirks/differences are taken care of here.
2145  */
2146 static void wx_write_eitr(struct wx_q_vector *q_vector)
2147 {
2148 	struct wx *wx = q_vector->wx;
2149 	int v_idx = q_vector->v_idx;
2150 	u32 itr_reg;
2151 
2152 	if (wx->mac.type == wx_mac_sp)
2153 		itr_reg = q_vector->itr & WX_SP_MAX_EITR;
2154 	else
2155 		itr_reg = q_vector->itr & WX_EM_MAX_EITR;
2156 
2157 	itr_reg |= WX_PX_ITR_CNT_WDIS;
2158 
2159 	wr32(wx, WX_PX_ITR(v_idx), itr_reg);
2160 }
2161 
2162 /**
2163  * wx_configure_vectors - Configure vectors for hardware
2164  * @wx: board private structure
2165  *
2166  * wx_configure_vectors sets up the hardware to properly generate MSI-X/MSI/LEGACY
2167  * interrupts.
2168  **/
2169 void wx_configure_vectors(struct wx *wx)
2170 {
2171 	struct pci_dev *pdev = wx->pdev;
2172 	u32 eitrsel = 0;
2173 	u16 v_idx;
2174 
2175 	if (pdev->msix_enabled) {
2176 		/* Populate MSIX to EITR Select */
2177 		wr32(wx, WX_PX_ITRSEL, eitrsel);
2178 		/* use EIAM to auto-mask when MSI-X interrupt is asserted
2179 		 * this saves a register write for every interrupt
2180 		 */
2181 		wr32(wx, WX_PX_GPIE, WX_PX_GPIE_MODEL);
2182 	} else {
2183 		/* legacy interrupts, use EIAM to auto-mask when reading EICR,
2184 		 * specifically only auto mask tx and rx interrupts.
2185 		 */
2186 		wr32(wx, WX_PX_GPIE, 0);
2187 	}
2188 
2189 	/* Populate the IVAR table and set the ITR values to the
2190 	 * corresponding register.
2191 	 */
2192 	for (v_idx = 0; v_idx < wx->num_q_vectors; v_idx++) {
2193 		struct wx_q_vector *q_vector = wx->q_vector[v_idx];
2194 		struct wx_ring *ring;
2195 
2196 		wx_for_each_ring(ring, q_vector->rx)
2197 			wx_set_ivar(wx, 0, ring->reg_idx, v_idx);
2198 
2199 		wx_for_each_ring(ring, q_vector->tx)
2200 			wx_set_ivar(wx, 1, ring->reg_idx, v_idx);
2201 
2202 		wx_write_eitr(q_vector);
2203 	}
2204 
2205 	wx_set_ivar(wx, -1, 0, v_idx);
2206 	if (pdev->msix_enabled)
2207 		wr32(wx, WX_PX_ITR(v_idx), 1950);
2208 }
2209 EXPORT_SYMBOL(wx_configure_vectors);
2210 
2211 /**
2212  * wx_clean_rx_ring - Free Rx Buffers per Queue
2213  * @rx_ring: ring to free buffers from
2214  **/
2215 static void wx_clean_rx_ring(struct wx_ring *rx_ring)
2216 {
2217 	struct wx_rx_buffer *rx_buffer;
2218 	u16 i = rx_ring->next_to_clean;
2219 
2220 	rx_buffer = &rx_ring->rx_buffer_info[i];
2221 
2222 	/* Free all the Rx ring sk_buffs */
2223 	while (i != rx_ring->next_to_alloc) {
2224 		if (rx_buffer->skb) {
2225 			struct sk_buff *skb = rx_buffer->skb;
2226 
2227 			if (WX_CB(skb)->page_released)
2228 				page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false);
2229 
2230 			dev_kfree_skb(skb);
2231 		}
2232 
2233 		/* Invalidate cache lines that may have been written to by
2234 		 * device so that we avoid corrupting memory.
2235 		 */
2236 		dma_sync_single_range_for_cpu(rx_ring->dev,
2237 					      rx_buffer->dma,
2238 					      rx_buffer->page_offset,
2239 					      WX_RX_BUFSZ,
2240 					      DMA_FROM_DEVICE);
2241 
2242 		/* free resources associated with mapping */
2243 		page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false);
2244 		__page_frag_cache_drain(rx_buffer->page,
2245 					rx_buffer->pagecnt_bias);
2246 
2247 		i++;
2248 		rx_buffer++;
2249 		if (i == rx_ring->count) {
2250 			i = 0;
2251 			rx_buffer = rx_ring->rx_buffer_info;
2252 		}
2253 	}
2254 
2255 	rx_ring->next_to_alloc = 0;
2256 	rx_ring->next_to_clean = 0;
2257 	rx_ring->next_to_use = 0;
2258 }
2259 
2260 /**
2261  * wx_clean_all_rx_rings - Free Rx Buffers for all queues
2262  * @wx: board private structure
2263  **/
2264 void wx_clean_all_rx_rings(struct wx *wx)
2265 {
2266 	int i;
2267 
2268 	for (i = 0; i < wx->num_rx_queues; i++)
2269 		wx_clean_rx_ring(wx->rx_ring[i]);
2270 }
2271 EXPORT_SYMBOL(wx_clean_all_rx_rings);
2272 
2273 /**
2274  * wx_free_rx_resources - Free Rx Resources
2275  * @rx_ring: ring to clean the resources from
2276  *
2277  * Free all receive software resources
2278  **/
2279 static void wx_free_rx_resources(struct wx_ring *rx_ring)
2280 {
2281 	wx_clean_rx_ring(rx_ring);
2282 	kvfree(rx_ring->rx_buffer_info);
2283 	rx_ring->rx_buffer_info = NULL;
2284 
2285 	/* if not set, then don't free */
2286 	if (!rx_ring->desc)
2287 		return;
2288 
2289 	dma_free_coherent(rx_ring->dev, rx_ring->size,
2290 			  rx_ring->desc, rx_ring->dma);
2291 
2292 	rx_ring->desc = NULL;
2293 
2294 	if (rx_ring->page_pool) {
2295 		page_pool_destroy(rx_ring->page_pool);
2296 		rx_ring->page_pool = NULL;
2297 	}
2298 }
2299 
2300 /**
2301  * wx_free_all_rx_resources - Free Rx Resources for All Queues
2302  * @wx: pointer to hardware structure
2303  *
2304  * Free all receive software resources
2305  **/
2306 static void wx_free_all_rx_resources(struct wx *wx)
2307 {
2308 	int i;
2309 
2310 	for (i = 0; i < wx->num_rx_queues; i++)
2311 		wx_free_rx_resources(wx->rx_ring[i]);
2312 }
2313 
2314 /**
2315  * wx_clean_tx_ring - Free Tx Buffers
2316  * @tx_ring: ring to be cleaned
2317  **/
2318 static void wx_clean_tx_ring(struct wx_ring *tx_ring)
2319 {
2320 	struct wx_tx_buffer *tx_buffer;
2321 	u16 i = tx_ring->next_to_clean;
2322 
2323 	tx_buffer = &tx_ring->tx_buffer_info[i];
2324 
2325 	while (i != tx_ring->next_to_use) {
2326 		union wx_tx_desc *eop_desc, *tx_desc;
2327 
2328 		/* Free all the Tx ring sk_buffs */
2329 		dev_kfree_skb_any(tx_buffer->skb);
2330 
2331 		/* unmap skb header data */
2332 		dma_unmap_single(tx_ring->dev,
2333 				 dma_unmap_addr(tx_buffer, dma),
2334 				 dma_unmap_len(tx_buffer, len),
2335 				 DMA_TO_DEVICE);
2336 
2337 		/* check for eop_desc to determine the end of the packet */
2338 		eop_desc = tx_buffer->next_to_watch;
2339 		tx_desc = WX_TX_DESC(tx_ring, i);
2340 
2341 		/* unmap remaining buffers */
2342 		while (tx_desc != eop_desc) {
2343 			tx_buffer++;
2344 			tx_desc++;
2345 			i++;
2346 			if (unlikely(i == tx_ring->count)) {
2347 				i = 0;
2348 				tx_buffer = tx_ring->tx_buffer_info;
2349 				tx_desc = WX_TX_DESC(tx_ring, 0);
2350 			}
2351 
2352 			/* unmap any remaining paged data */
2353 			if (dma_unmap_len(tx_buffer, len))
2354 				dma_unmap_page(tx_ring->dev,
2355 					       dma_unmap_addr(tx_buffer, dma),
2356 					       dma_unmap_len(tx_buffer, len),
2357 					       DMA_TO_DEVICE);
2358 		}
2359 
2360 		/* move us one more past the eop_desc for start of next pkt */
2361 		tx_buffer++;
2362 		i++;
2363 		if (unlikely(i == tx_ring->count)) {
2364 			i = 0;
2365 			tx_buffer = tx_ring->tx_buffer_info;
2366 		}
2367 	}
2368 
2369 	netdev_tx_reset_queue(wx_txring_txq(tx_ring));
2370 
2371 	/* reset next_to_use and next_to_clean */
2372 	tx_ring->next_to_use = 0;
2373 	tx_ring->next_to_clean = 0;
2374 }
2375 
2376 /**
2377  * wx_clean_all_tx_rings - Free Tx Buffers for all queues
2378  * @wx: board private structure
2379  **/
2380 void wx_clean_all_tx_rings(struct wx *wx)
2381 {
2382 	int i;
2383 
2384 	for (i = 0; i < wx->num_tx_queues; i++)
2385 		wx_clean_tx_ring(wx->tx_ring[i]);
2386 }
2387 EXPORT_SYMBOL(wx_clean_all_tx_rings);
2388 
2389 /**
2390  * wx_free_tx_resources - Free Tx Resources per Queue
2391  * @tx_ring: Tx descriptor ring for a specific queue
2392  *
2393  * Free all transmit software resources
2394  **/
2395 static void wx_free_tx_resources(struct wx_ring *tx_ring)
2396 {
2397 	wx_clean_tx_ring(tx_ring);
2398 	kvfree(tx_ring->tx_buffer_info);
2399 	tx_ring->tx_buffer_info = NULL;
2400 
2401 	/* if not set, then don't free */
2402 	if (!tx_ring->desc)
2403 		return;
2404 
2405 	dma_free_coherent(tx_ring->dev, tx_ring->size,
2406 			  tx_ring->desc, tx_ring->dma);
2407 	tx_ring->desc = NULL;
2408 }
2409 
2410 /**
2411  * wx_free_all_tx_resources - Free Tx Resources for All Queues
2412  * @wx: pointer to hardware structure
2413  *
2414  * Free all transmit software resources
2415  **/
2416 static void wx_free_all_tx_resources(struct wx *wx)
2417 {
2418 	int i;
2419 
2420 	for (i = 0; i < wx->num_tx_queues; i++)
2421 		wx_free_tx_resources(wx->tx_ring[i]);
2422 }
2423 
2424 void wx_free_resources(struct wx *wx)
2425 {
2426 	wx_free_isb_resources(wx);
2427 	wx_free_all_rx_resources(wx);
2428 	wx_free_all_tx_resources(wx);
2429 }
2430 EXPORT_SYMBOL(wx_free_resources);
2431 
2432 static int wx_alloc_page_pool(struct wx_ring *rx_ring)
2433 {
2434 	int ret = 0;
2435 
2436 	struct page_pool_params pp_params = {
2437 		.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
2438 		.order = 0,
2439 		.pool_size = rx_ring->size,
2440 		.nid = dev_to_node(rx_ring->dev),
2441 		.dev = rx_ring->dev,
2442 		.dma_dir = DMA_FROM_DEVICE,
2443 		.offset = 0,
2444 		.max_len = PAGE_SIZE,
2445 	};
2446 
2447 	rx_ring->page_pool = page_pool_create(&pp_params);
2448 	if (IS_ERR(rx_ring->page_pool)) {
2449 		ret = PTR_ERR(rx_ring->page_pool);
2450 		rx_ring->page_pool = NULL;
2451 	}
2452 
2453 	return ret;
2454 }
2455 
2456 /**
2457  * wx_setup_rx_resources - allocate Rx resources (Descriptors)
2458  * @rx_ring: rx descriptor ring (for a specific queue) to setup
2459  *
2460  * Returns 0 on success, negative on failure
2461  **/
2462 static int wx_setup_rx_resources(struct wx_ring *rx_ring)
2463 {
2464 	struct device *dev = rx_ring->dev;
2465 	int orig_node = dev_to_node(dev);
2466 	int numa_node = NUMA_NO_NODE;
2467 	int size, ret;
2468 
2469 	size = sizeof(struct wx_rx_buffer) * rx_ring->count;
2470 
2471 	if (rx_ring->q_vector)
2472 		numa_node = rx_ring->q_vector->numa_node;
2473 
2474 	rx_ring->rx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node);
2475 	if (!rx_ring->rx_buffer_info)
2476 		rx_ring->rx_buffer_info = kvmalloc(size, GFP_KERNEL);
2477 	if (!rx_ring->rx_buffer_info)
2478 		goto err;
2479 
2480 	/* Round up to nearest 4K */
2481 	rx_ring->size = rx_ring->count * sizeof(union wx_rx_desc);
2482 	rx_ring->size = ALIGN(rx_ring->size, 4096);
2483 
2484 	set_dev_node(dev, numa_node);
2485 	rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
2486 					   &rx_ring->dma, GFP_KERNEL);
2487 	if (!rx_ring->desc) {
2488 		set_dev_node(dev, orig_node);
2489 		rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
2490 						   &rx_ring->dma, GFP_KERNEL);
2491 	}
2492 
2493 	if (!rx_ring->desc)
2494 		goto err;
2495 
2496 	rx_ring->next_to_clean = 0;
2497 	rx_ring->next_to_use = 0;
2498 
2499 	ret = wx_alloc_page_pool(rx_ring);
2500 	if (ret < 0) {
2501 		dev_err(rx_ring->dev, "Page pool creation failed: %d\n", ret);
2502 		goto err_desc;
2503 	}
2504 
2505 	return 0;
2506 
2507 err_desc:
2508 	dma_free_coherent(dev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2509 err:
2510 	kvfree(rx_ring->rx_buffer_info);
2511 	rx_ring->rx_buffer_info = NULL;
2512 	dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
2513 	return -ENOMEM;
2514 }
2515 
2516 /**
2517  * wx_setup_all_rx_resources - allocate all queues Rx resources
2518  * @wx: pointer to hardware structure
2519  *
2520  * If this function returns with an error, then it's possible one or
2521  * more of the rings is populated (while the rest are not).  It is the
2522  * callers duty to clean those orphaned rings.
2523  *
2524  * Return 0 on success, negative on failure
2525  **/
2526 static int wx_setup_all_rx_resources(struct wx *wx)
2527 {
2528 	int i, err = 0;
2529 
2530 	for (i = 0; i < wx->num_rx_queues; i++) {
2531 		err = wx_setup_rx_resources(wx->rx_ring[i]);
2532 		if (!err)
2533 			continue;
2534 
2535 		wx_err(wx, "Allocation for Rx Queue %u failed\n", i);
2536 		goto err_setup_rx;
2537 	}
2538 
2539 	return 0;
2540 err_setup_rx:
2541 	/* rewind the index freeing the rings as we go */
2542 	while (i--)
2543 		wx_free_rx_resources(wx->rx_ring[i]);
2544 	return err;
2545 }
2546 
2547 /**
2548  * wx_setup_tx_resources - allocate Tx resources (Descriptors)
2549  * @tx_ring: tx descriptor ring (for a specific queue) to setup
2550  *
2551  * Return 0 on success, negative on failure
2552  **/
2553 static int wx_setup_tx_resources(struct wx_ring *tx_ring)
2554 {
2555 	struct device *dev = tx_ring->dev;
2556 	int orig_node = dev_to_node(dev);
2557 	int numa_node = NUMA_NO_NODE;
2558 	int size;
2559 
2560 	size = sizeof(struct wx_tx_buffer) * tx_ring->count;
2561 
2562 	if (tx_ring->q_vector)
2563 		numa_node = tx_ring->q_vector->numa_node;
2564 
2565 	tx_ring->tx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node);
2566 	if (!tx_ring->tx_buffer_info)
2567 		tx_ring->tx_buffer_info = kvmalloc(size, GFP_KERNEL);
2568 	if (!tx_ring->tx_buffer_info)
2569 		goto err;
2570 
2571 	/* round up to nearest 4K */
2572 	tx_ring->size = tx_ring->count * sizeof(union wx_tx_desc);
2573 	tx_ring->size = ALIGN(tx_ring->size, 4096);
2574 
2575 	set_dev_node(dev, numa_node);
2576 	tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2577 					   &tx_ring->dma, GFP_KERNEL);
2578 	if (!tx_ring->desc) {
2579 		set_dev_node(dev, orig_node);
2580 		tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2581 						   &tx_ring->dma, GFP_KERNEL);
2582 	}
2583 
2584 	if (!tx_ring->desc)
2585 		goto err;
2586 
2587 	tx_ring->next_to_use = 0;
2588 	tx_ring->next_to_clean = 0;
2589 
2590 	return 0;
2591 
2592 err:
2593 	kvfree(tx_ring->tx_buffer_info);
2594 	tx_ring->tx_buffer_info = NULL;
2595 	dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
2596 	return -ENOMEM;
2597 }
2598 
2599 /**
2600  * wx_setup_all_tx_resources - allocate all queues Tx resources
2601  * @wx: pointer to private structure
2602  *
2603  * If this function returns with an error, then it's possible one or
2604  * more of the rings is populated (while the rest are not).  It is the
2605  * callers duty to clean those orphaned rings.
2606  *
2607  * Return 0 on success, negative on failure
2608  **/
2609 static int wx_setup_all_tx_resources(struct wx *wx)
2610 {
2611 	int i, err = 0;
2612 
2613 	for (i = 0; i < wx->num_tx_queues; i++) {
2614 		err = wx_setup_tx_resources(wx->tx_ring[i]);
2615 		if (!err)
2616 			continue;
2617 
2618 		wx_err(wx, "Allocation for Tx Queue %u failed\n", i);
2619 		goto err_setup_tx;
2620 	}
2621 
2622 	return 0;
2623 err_setup_tx:
2624 	/* rewind the index freeing the rings as we go */
2625 	while (i--)
2626 		wx_free_tx_resources(wx->tx_ring[i]);
2627 	return err;
2628 }
2629 
2630 int wx_setup_resources(struct wx *wx)
2631 {
2632 	int err;
2633 
2634 	/* allocate transmit descriptors */
2635 	err = wx_setup_all_tx_resources(wx);
2636 	if (err)
2637 		return err;
2638 
2639 	/* allocate receive descriptors */
2640 	err = wx_setup_all_rx_resources(wx);
2641 	if (err)
2642 		goto err_free_tx;
2643 
2644 	err = wx_setup_isb_resources(wx);
2645 	if (err)
2646 		goto err_free_rx;
2647 
2648 	return 0;
2649 
2650 err_free_rx:
2651 	wx_free_all_rx_resources(wx);
2652 err_free_tx:
2653 	wx_free_all_tx_resources(wx);
2654 
2655 	return err;
2656 }
2657 EXPORT_SYMBOL(wx_setup_resources);
2658 
2659 /**
2660  * wx_get_stats64 - Get System Network Statistics
2661  * @netdev: network interface device structure
2662  * @stats: storage space for 64bit statistics
2663  */
2664 void wx_get_stats64(struct net_device *netdev,
2665 		    struct rtnl_link_stats64 *stats)
2666 {
2667 	struct wx *wx = netdev_priv(netdev);
2668 	int i;
2669 
2670 	rcu_read_lock();
2671 	for (i = 0; i < wx->num_rx_queues; i++) {
2672 		struct wx_ring *ring = READ_ONCE(wx->rx_ring[i]);
2673 		u64 bytes, packets;
2674 		unsigned int start;
2675 
2676 		if (ring) {
2677 			do {
2678 				start = u64_stats_fetch_begin(&ring->syncp);
2679 				packets = ring->stats.packets;
2680 				bytes   = ring->stats.bytes;
2681 			} while (u64_stats_fetch_retry(&ring->syncp, start));
2682 			stats->rx_packets += packets;
2683 			stats->rx_bytes   += bytes;
2684 		}
2685 	}
2686 
2687 	for (i = 0; i < wx->num_tx_queues; i++) {
2688 		struct wx_ring *ring = READ_ONCE(wx->tx_ring[i]);
2689 		u64 bytes, packets;
2690 		unsigned int start;
2691 
2692 		if (ring) {
2693 			do {
2694 				start = u64_stats_fetch_begin(&ring->syncp);
2695 				packets = ring->stats.packets;
2696 				bytes   = ring->stats.bytes;
2697 			} while (u64_stats_fetch_retry(&ring->syncp,
2698 							   start));
2699 			stats->tx_packets += packets;
2700 			stats->tx_bytes   += bytes;
2701 		}
2702 	}
2703 
2704 	rcu_read_unlock();
2705 }
2706 EXPORT_SYMBOL(wx_get_stats64);
2707 
2708 int wx_set_features(struct net_device *netdev, netdev_features_t features)
2709 {
2710 	netdev_features_t changed = netdev->features ^ features;
2711 	struct wx *wx = netdev_priv(netdev);
2712 
2713 	if (changed & NETIF_F_RXHASH)
2714 		wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN,
2715 		      WX_RDB_RA_CTL_RSS_EN);
2716 	else
2717 		wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN, 0);
2718 
2719 	if (changed &
2720 	    (NETIF_F_HW_VLAN_CTAG_RX |
2721 	     NETIF_F_HW_VLAN_STAG_RX))
2722 		wx_set_rx_mode(netdev);
2723 
2724 	return 1;
2725 }
2726 EXPORT_SYMBOL(wx_set_features);
2727 
2728 MODULE_LICENSE("GPL");
2729