1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/etherdevice.h> 5 #include <net/ip6_checksum.h> 6 #include <net/page_pool/helpers.h> 7 #include <net/inet_ecn.h> 8 #include <linux/iopoll.h> 9 #include <linux/sctp.h> 10 #include <linux/pci.h> 11 #include <net/tcp.h> 12 #include <net/ip.h> 13 14 #include "wx_type.h" 15 #include "wx_lib.h" 16 #include "wx_hw.h" 17 18 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 19 static struct wx_dec_ptype wx_ptype_lookup[256] = { 20 /* L2: mac */ 21 [0x11] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 22 [0x12] = WX_PTT(L2, NONE, NONE, NONE, TS, PAY2), 23 [0x13] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 24 [0x14] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 25 [0x15] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE), 26 [0x16] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 27 [0x17] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE), 28 29 /* L2: ethertype filter */ 30 [0x18 ... 0x1F] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE), 31 32 /* L3: ip non-tunnel */ 33 [0x21] = WX_PTT(IP, FGV4, NONE, NONE, NONE, PAY3), 34 [0x22] = WX_PTT(IP, IPV4, NONE, NONE, NONE, PAY3), 35 [0x23] = WX_PTT(IP, IPV4, NONE, NONE, UDP, PAY4), 36 [0x24] = WX_PTT(IP, IPV4, NONE, NONE, TCP, PAY4), 37 [0x25] = WX_PTT(IP, IPV4, NONE, NONE, SCTP, PAY4), 38 [0x29] = WX_PTT(IP, FGV6, NONE, NONE, NONE, PAY3), 39 [0x2A] = WX_PTT(IP, IPV6, NONE, NONE, NONE, PAY3), 40 [0x2B] = WX_PTT(IP, IPV6, NONE, NONE, UDP, PAY3), 41 [0x2C] = WX_PTT(IP, IPV6, NONE, NONE, TCP, PAY4), 42 [0x2D] = WX_PTT(IP, IPV6, NONE, NONE, SCTP, PAY4), 43 44 /* L2: fcoe */ 45 [0x30 ... 0x34] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3), 46 [0x38 ... 0x3C] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3), 47 48 /* IPv4 --> IPv4/IPv6 */ 49 [0x81] = WX_PTT(IP, IPV4, IPIP, FGV4, NONE, PAY3), 50 [0x82] = WX_PTT(IP, IPV4, IPIP, IPV4, NONE, PAY3), 51 [0x83] = WX_PTT(IP, IPV4, IPIP, IPV4, UDP, PAY4), 52 [0x84] = WX_PTT(IP, IPV4, IPIP, IPV4, TCP, PAY4), 53 [0x85] = WX_PTT(IP, IPV4, IPIP, IPV4, SCTP, PAY4), 54 [0x89] = WX_PTT(IP, IPV4, IPIP, FGV6, NONE, PAY3), 55 [0x8A] = WX_PTT(IP, IPV4, IPIP, IPV6, NONE, PAY3), 56 [0x8B] = WX_PTT(IP, IPV4, IPIP, IPV6, UDP, PAY4), 57 [0x8C] = WX_PTT(IP, IPV4, IPIP, IPV6, TCP, PAY4), 58 [0x8D] = WX_PTT(IP, IPV4, IPIP, IPV6, SCTP, PAY4), 59 60 /* IPv4 --> GRE/NAT --> NONE/IPv4/IPv6 */ 61 [0x90] = WX_PTT(IP, IPV4, IG, NONE, NONE, PAY3), 62 [0x91] = WX_PTT(IP, IPV4, IG, FGV4, NONE, PAY3), 63 [0x92] = WX_PTT(IP, IPV4, IG, IPV4, NONE, PAY3), 64 [0x93] = WX_PTT(IP, IPV4, IG, IPV4, UDP, PAY4), 65 [0x94] = WX_PTT(IP, IPV4, IG, IPV4, TCP, PAY4), 66 [0x95] = WX_PTT(IP, IPV4, IG, IPV4, SCTP, PAY4), 67 [0x99] = WX_PTT(IP, IPV4, IG, FGV6, NONE, PAY3), 68 [0x9A] = WX_PTT(IP, IPV4, IG, IPV6, NONE, PAY3), 69 [0x9B] = WX_PTT(IP, IPV4, IG, IPV6, UDP, PAY4), 70 [0x9C] = WX_PTT(IP, IPV4, IG, IPV6, TCP, PAY4), 71 [0x9D] = WX_PTT(IP, IPV4, IG, IPV6, SCTP, PAY4), 72 73 /* IPv4 --> GRE/NAT --> MAC --> NONE/IPv4/IPv6 */ 74 [0xA0] = WX_PTT(IP, IPV4, IGM, NONE, NONE, PAY3), 75 [0xA1] = WX_PTT(IP, IPV4, IGM, FGV4, NONE, PAY3), 76 [0xA2] = WX_PTT(IP, IPV4, IGM, IPV4, NONE, PAY3), 77 [0xA3] = WX_PTT(IP, IPV4, IGM, IPV4, UDP, PAY4), 78 [0xA4] = WX_PTT(IP, IPV4, IGM, IPV4, TCP, PAY4), 79 [0xA5] = WX_PTT(IP, IPV4, IGM, IPV4, SCTP, PAY4), 80 [0xA9] = WX_PTT(IP, IPV4, IGM, FGV6, NONE, PAY3), 81 [0xAA] = WX_PTT(IP, IPV4, IGM, IPV6, NONE, PAY3), 82 [0xAB] = WX_PTT(IP, IPV4, IGM, IPV6, UDP, PAY4), 83 [0xAC] = WX_PTT(IP, IPV4, IGM, IPV6, TCP, PAY4), 84 [0xAD] = WX_PTT(IP, IPV4, IGM, IPV6, SCTP, PAY4), 85 86 /* IPv4 --> GRE/NAT --> MAC+VLAN --> NONE/IPv4/IPv6 */ 87 [0xB0] = WX_PTT(IP, IPV4, IGMV, NONE, NONE, PAY3), 88 [0xB1] = WX_PTT(IP, IPV4, IGMV, FGV4, NONE, PAY3), 89 [0xB2] = WX_PTT(IP, IPV4, IGMV, IPV4, NONE, PAY3), 90 [0xB3] = WX_PTT(IP, IPV4, IGMV, IPV4, UDP, PAY4), 91 [0xB4] = WX_PTT(IP, IPV4, IGMV, IPV4, TCP, PAY4), 92 [0xB5] = WX_PTT(IP, IPV4, IGMV, IPV4, SCTP, PAY4), 93 [0xB9] = WX_PTT(IP, IPV4, IGMV, FGV6, NONE, PAY3), 94 [0xBA] = WX_PTT(IP, IPV4, IGMV, IPV6, NONE, PAY3), 95 [0xBB] = WX_PTT(IP, IPV4, IGMV, IPV6, UDP, PAY4), 96 [0xBC] = WX_PTT(IP, IPV4, IGMV, IPV6, TCP, PAY4), 97 [0xBD] = WX_PTT(IP, IPV4, IGMV, IPV6, SCTP, PAY4), 98 99 /* IPv6 --> IPv4/IPv6 */ 100 [0xC1] = WX_PTT(IP, IPV6, IPIP, FGV4, NONE, PAY3), 101 [0xC2] = WX_PTT(IP, IPV6, IPIP, IPV4, NONE, PAY3), 102 [0xC3] = WX_PTT(IP, IPV6, IPIP, IPV4, UDP, PAY4), 103 [0xC4] = WX_PTT(IP, IPV6, IPIP, IPV4, TCP, PAY4), 104 [0xC5] = WX_PTT(IP, IPV6, IPIP, IPV4, SCTP, PAY4), 105 [0xC9] = WX_PTT(IP, IPV6, IPIP, FGV6, NONE, PAY3), 106 [0xCA] = WX_PTT(IP, IPV6, IPIP, IPV6, NONE, PAY3), 107 [0xCB] = WX_PTT(IP, IPV6, IPIP, IPV6, UDP, PAY4), 108 [0xCC] = WX_PTT(IP, IPV6, IPIP, IPV6, TCP, PAY4), 109 [0xCD] = WX_PTT(IP, IPV6, IPIP, IPV6, SCTP, PAY4), 110 111 /* IPv6 --> GRE/NAT -> NONE/IPv4/IPv6 */ 112 [0xD0] = WX_PTT(IP, IPV6, IG, NONE, NONE, PAY3), 113 [0xD1] = WX_PTT(IP, IPV6, IG, FGV4, NONE, PAY3), 114 [0xD2] = WX_PTT(IP, IPV6, IG, IPV4, NONE, PAY3), 115 [0xD3] = WX_PTT(IP, IPV6, IG, IPV4, UDP, PAY4), 116 [0xD4] = WX_PTT(IP, IPV6, IG, IPV4, TCP, PAY4), 117 [0xD5] = WX_PTT(IP, IPV6, IG, IPV4, SCTP, PAY4), 118 [0xD9] = WX_PTT(IP, IPV6, IG, FGV6, NONE, PAY3), 119 [0xDA] = WX_PTT(IP, IPV6, IG, IPV6, NONE, PAY3), 120 [0xDB] = WX_PTT(IP, IPV6, IG, IPV6, UDP, PAY4), 121 [0xDC] = WX_PTT(IP, IPV6, IG, IPV6, TCP, PAY4), 122 [0xDD] = WX_PTT(IP, IPV6, IG, IPV6, SCTP, PAY4), 123 124 /* IPv6 --> GRE/NAT -> MAC -> NONE/IPv4/IPv6 */ 125 [0xE0] = WX_PTT(IP, IPV6, IGM, NONE, NONE, PAY3), 126 [0xE1] = WX_PTT(IP, IPV6, IGM, FGV4, NONE, PAY3), 127 [0xE2] = WX_PTT(IP, IPV6, IGM, IPV4, NONE, PAY3), 128 [0xE3] = WX_PTT(IP, IPV6, IGM, IPV4, UDP, PAY4), 129 [0xE4] = WX_PTT(IP, IPV6, IGM, IPV4, TCP, PAY4), 130 [0xE5] = WX_PTT(IP, IPV6, IGM, IPV4, SCTP, PAY4), 131 [0xE9] = WX_PTT(IP, IPV6, IGM, FGV6, NONE, PAY3), 132 [0xEA] = WX_PTT(IP, IPV6, IGM, IPV6, NONE, PAY3), 133 [0xEB] = WX_PTT(IP, IPV6, IGM, IPV6, UDP, PAY4), 134 [0xEC] = WX_PTT(IP, IPV6, IGM, IPV6, TCP, PAY4), 135 [0xED] = WX_PTT(IP, IPV6, IGM, IPV6, SCTP, PAY4), 136 137 /* IPv6 --> GRE/NAT -> MAC--> NONE/IPv */ 138 [0xF0] = WX_PTT(IP, IPV6, IGMV, NONE, NONE, PAY3), 139 [0xF1] = WX_PTT(IP, IPV6, IGMV, FGV4, NONE, PAY3), 140 [0xF2] = WX_PTT(IP, IPV6, IGMV, IPV4, NONE, PAY3), 141 [0xF3] = WX_PTT(IP, IPV6, IGMV, IPV4, UDP, PAY4), 142 [0xF4] = WX_PTT(IP, IPV6, IGMV, IPV4, TCP, PAY4), 143 [0xF5] = WX_PTT(IP, IPV6, IGMV, IPV4, SCTP, PAY4), 144 [0xF9] = WX_PTT(IP, IPV6, IGMV, FGV6, NONE, PAY3), 145 [0xFA] = WX_PTT(IP, IPV6, IGMV, IPV6, NONE, PAY3), 146 [0xFB] = WX_PTT(IP, IPV6, IGMV, IPV6, UDP, PAY4), 147 [0xFC] = WX_PTT(IP, IPV6, IGMV, IPV6, TCP, PAY4), 148 [0xFD] = WX_PTT(IP, IPV6, IGMV, IPV6, SCTP, PAY4), 149 }; 150 151 static struct wx_dec_ptype wx_decode_ptype(const u8 ptype) 152 { 153 return wx_ptype_lookup[ptype]; 154 } 155 156 /* wx_test_staterr - tests bits in Rx descriptor status and error fields */ 157 static __le32 wx_test_staterr(union wx_rx_desc *rx_desc, 158 const u32 stat_err_bits) 159 { 160 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 161 } 162 163 static void wx_dma_sync_frag(struct wx_ring *rx_ring, 164 struct wx_rx_buffer *rx_buffer) 165 { 166 struct sk_buff *skb = rx_buffer->skb; 167 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 168 169 dma_sync_single_range_for_cpu(rx_ring->dev, 170 WX_CB(skb)->dma, 171 skb_frag_off(frag), 172 skb_frag_size(frag), 173 DMA_FROM_DEVICE); 174 175 /* If the page was released, just unmap it. */ 176 if (unlikely(WX_CB(skb)->page_released)) 177 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false); 178 } 179 180 static struct wx_rx_buffer *wx_get_rx_buffer(struct wx_ring *rx_ring, 181 union wx_rx_desc *rx_desc, 182 struct sk_buff **skb, 183 int *rx_buffer_pgcnt) 184 { 185 struct wx_rx_buffer *rx_buffer; 186 unsigned int size; 187 188 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 189 size = le16_to_cpu(rx_desc->wb.upper.length); 190 191 #if (PAGE_SIZE < 8192) 192 *rx_buffer_pgcnt = page_count(rx_buffer->page); 193 #else 194 *rx_buffer_pgcnt = 0; 195 #endif 196 197 prefetchw(rx_buffer->page); 198 *skb = rx_buffer->skb; 199 200 /* Delay unmapping of the first packet. It carries the header 201 * information, HW may still access the header after the writeback. 202 * Only unmap it when EOP is reached 203 */ 204 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)) { 205 if (!*skb) 206 goto skip_sync; 207 } else { 208 if (*skb) 209 wx_dma_sync_frag(rx_ring, rx_buffer); 210 } 211 212 /* we are reusing so sync this buffer for CPU use */ 213 dma_sync_single_range_for_cpu(rx_ring->dev, 214 rx_buffer->dma, 215 rx_buffer->page_offset, 216 size, 217 DMA_FROM_DEVICE); 218 skip_sync: 219 return rx_buffer; 220 } 221 222 static void wx_put_rx_buffer(struct wx_ring *rx_ring, 223 struct wx_rx_buffer *rx_buffer, 224 struct sk_buff *skb, 225 int rx_buffer_pgcnt) 226 { 227 if (!IS_ERR(skb) && WX_CB(skb)->dma == rx_buffer->dma) 228 /* the page has been released from the ring */ 229 WX_CB(skb)->page_released = true; 230 231 /* clear contents of rx_buffer */ 232 rx_buffer->page = NULL; 233 rx_buffer->skb = NULL; 234 } 235 236 static struct sk_buff *wx_build_skb(struct wx_ring *rx_ring, 237 struct wx_rx_buffer *rx_buffer, 238 union wx_rx_desc *rx_desc) 239 { 240 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 241 #if (PAGE_SIZE < 8192) 242 unsigned int truesize = WX_RX_BUFSZ; 243 #else 244 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 245 #endif 246 struct sk_buff *skb = rx_buffer->skb; 247 248 if (!skb) { 249 void *page_addr = page_address(rx_buffer->page) + 250 rx_buffer->page_offset; 251 252 /* prefetch first cache line of first page */ 253 prefetch(page_addr); 254 #if L1_CACHE_BYTES < 128 255 prefetch(page_addr + L1_CACHE_BYTES); 256 #endif 257 258 /* allocate a skb to store the frags */ 259 skb = napi_alloc_skb(&rx_ring->q_vector->napi, WX_RXBUFFER_256); 260 if (unlikely(!skb)) 261 return NULL; 262 263 /* we will be copying header into skb->data in 264 * pskb_may_pull so it is in our interest to prefetch 265 * it now to avoid a possible cache miss 266 */ 267 prefetchw(skb->data); 268 269 if (size <= WX_RXBUFFER_256) { 270 memcpy(__skb_put(skb, size), page_addr, 271 ALIGN(size, sizeof(long))); 272 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, true); 273 return skb; 274 } 275 276 skb_mark_for_recycle(skb); 277 278 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)) 279 WX_CB(skb)->dma = rx_buffer->dma; 280 281 skb_add_rx_frag(skb, 0, rx_buffer->page, 282 rx_buffer->page_offset, 283 size, truesize); 284 goto out; 285 286 } else { 287 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 288 rx_buffer->page_offset, size, truesize); 289 } 290 291 out: 292 #if (PAGE_SIZE < 8192) 293 /* flip page offset to other buffer */ 294 rx_buffer->page_offset ^= truesize; 295 #else 296 /* move offset up to the next cache line */ 297 rx_buffer->page_offset += truesize; 298 #endif 299 300 return skb; 301 } 302 303 static bool wx_alloc_mapped_page(struct wx_ring *rx_ring, 304 struct wx_rx_buffer *bi) 305 { 306 struct page *page = bi->page; 307 dma_addr_t dma; 308 309 /* since we are recycling buffers we should seldom need to alloc */ 310 if (likely(page)) 311 return true; 312 313 page = page_pool_dev_alloc_pages(rx_ring->page_pool); 314 WARN_ON(!page); 315 dma = page_pool_get_dma_addr(page); 316 317 bi->page_dma = dma; 318 bi->page = page; 319 bi->page_offset = 0; 320 321 return true; 322 } 323 324 /** 325 * wx_alloc_rx_buffers - Replace used receive buffers 326 * @rx_ring: ring to place buffers on 327 * @cleaned_count: number of buffers to replace 328 **/ 329 void wx_alloc_rx_buffers(struct wx_ring *rx_ring, u16 cleaned_count) 330 { 331 u16 i = rx_ring->next_to_use; 332 union wx_rx_desc *rx_desc; 333 struct wx_rx_buffer *bi; 334 335 /* nothing to do */ 336 if (!cleaned_count) 337 return; 338 339 rx_desc = WX_RX_DESC(rx_ring, i); 340 bi = &rx_ring->rx_buffer_info[i]; 341 i -= rx_ring->count; 342 343 do { 344 if (!wx_alloc_mapped_page(rx_ring, bi)) 345 break; 346 347 /* sync the buffer for use by the device */ 348 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 349 bi->page_offset, 350 WX_RX_BUFSZ, 351 DMA_FROM_DEVICE); 352 353 rx_desc->read.pkt_addr = 354 cpu_to_le64(bi->page_dma + bi->page_offset); 355 356 rx_desc++; 357 bi++; 358 i++; 359 if (unlikely(!i)) { 360 rx_desc = WX_RX_DESC(rx_ring, 0); 361 bi = rx_ring->rx_buffer_info; 362 i -= rx_ring->count; 363 } 364 365 /* clear the status bits for the next_to_use descriptor */ 366 rx_desc->wb.upper.status_error = 0; 367 368 cleaned_count--; 369 } while (cleaned_count); 370 371 i += rx_ring->count; 372 373 if (rx_ring->next_to_use != i) { 374 rx_ring->next_to_use = i; 375 /* update next to alloc since we have filled the ring */ 376 rx_ring->next_to_alloc = i; 377 378 /* Force memory writes to complete before letting h/w 379 * know there are new descriptors to fetch. (Only 380 * applicable for weak-ordered memory model archs, 381 * such as IA-64). 382 */ 383 wmb(); 384 writel(i, rx_ring->tail); 385 } 386 } 387 388 u16 wx_desc_unused(struct wx_ring *ring) 389 { 390 u16 ntc = ring->next_to_clean; 391 u16 ntu = ring->next_to_use; 392 393 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 394 } 395 396 /** 397 * wx_is_non_eop - process handling of non-EOP buffers 398 * @rx_ring: Rx ring being processed 399 * @rx_desc: Rx descriptor for current buffer 400 * @skb: Current socket buffer containing buffer in progress 401 * 402 * This function updates next to clean. If the buffer is an EOP buffer 403 * this function exits returning false, otherwise it will place the 404 * sk_buff in the next buffer to be chained and return true indicating 405 * that this is in fact a non-EOP buffer. 406 **/ 407 static bool wx_is_non_eop(struct wx_ring *rx_ring, 408 union wx_rx_desc *rx_desc, 409 struct sk_buff *skb) 410 { 411 u32 ntc = rx_ring->next_to_clean + 1; 412 413 /* fetch, update, and store next to clean */ 414 ntc = (ntc < rx_ring->count) ? ntc : 0; 415 rx_ring->next_to_clean = ntc; 416 417 prefetch(WX_RX_DESC(rx_ring, ntc)); 418 419 /* if we are the last buffer then there is nothing else to do */ 420 if (likely(wx_test_staterr(rx_desc, WX_RXD_STAT_EOP))) 421 return false; 422 423 rx_ring->rx_buffer_info[ntc].skb = skb; 424 425 return true; 426 } 427 428 static void wx_pull_tail(struct sk_buff *skb) 429 { 430 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 431 unsigned int pull_len; 432 unsigned char *va; 433 434 /* it is valid to use page_address instead of kmap since we are 435 * working with pages allocated out of the lomem pool per 436 * alloc_page(GFP_ATOMIC) 437 */ 438 va = skb_frag_address(frag); 439 440 /* we need the header to contain the greater of either ETH_HLEN or 441 * 60 bytes if the skb->len is less than 60 for skb_pad. 442 */ 443 pull_len = eth_get_headlen(skb->dev, va, WX_RXBUFFER_256); 444 445 /* align pull length to size of long to optimize memcpy performance */ 446 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 447 448 /* update all of the pointers */ 449 skb_frag_size_sub(frag, pull_len); 450 skb_frag_off_add(frag, pull_len); 451 skb->data_len -= pull_len; 452 skb->tail += pull_len; 453 } 454 455 /** 456 * wx_cleanup_headers - Correct corrupted or empty headers 457 * @rx_ring: rx descriptor ring packet is being transacted on 458 * @rx_desc: pointer to the EOP Rx descriptor 459 * @skb: pointer to current skb being fixed 460 * 461 * Check for corrupted packet headers caused by senders on the local L2 462 * embedded NIC switch not setting up their Tx Descriptors right. These 463 * should be very rare. 464 * 465 * Also address the case where we are pulling data in on pages only 466 * and as such no data is present in the skb header. 467 * 468 * In addition if skb is not at least 60 bytes we need to pad it so that 469 * it is large enough to qualify as a valid Ethernet frame. 470 * 471 * Returns true if an error was encountered and skb was freed. 472 **/ 473 static bool wx_cleanup_headers(struct wx_ring *rx_ring, 474 union wx_rx_desc *rx_desc, 475 struct sk_buff *skb) 476 { 477 struct net_device *netdev = rx_ring->netdev; 478 479 /* verify that the packet does not have any known errors */ 480 if (!netdev || 481 unlikely(wx_test_staterr(rx_desc, WX_RXD_ERR_RXE) && 482 !(netdev->features & NETIF_F_RXALL))) { 483 dev_kfree_skb_any(skb); 484 return true; 485 } 486 487 /* place header in linear portion of buffer */ 488 if (!skb_headlen(skb)) 489 wx_pull_tail(skb); 490 491 /* if eth_skb_pad returns an error the skb was freed */ 492 if (eth_skb_pad(skb)) 493 return true; 494 495 return false; 496 } 497 498 static void wx_rx_hash(struct wx_ring *ring, 499 union wx_rx_desc *rx_desc, 500 struct sk_buff *skb) 501 { 502 u16 rss_type; 503 504 if (!(ring->netdev->features & NETIF_F_RXHASH)) 505 return; 506 507 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 508 WX_RXD_RSSTYPE_MASK; 509 510 if (!rss_type) 511 return; 512 513 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 514 (WX_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 515 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 516 } 517 518 /** 519 * wx_rx_checksum - indicate in skb if hw indicated a good cksum 520 * @ring: structure containing ring specific data 521 * @rx_desc: current Rx descriptor being processed 522 * @skb: skb currently being received and modified 523 **/ 524 static void wx_rx_checksum(struct wx_ring *ring, 525 union wx_rx_desc *rx_desc, 526 struct sk_buff *skb) 527 { 528 struct wx_dec_ptype dptype = wx_decode_ptype(WX_RXD_PKTTYPE(rx_desc)); 529 530 skb_checksum_none_assert(skb); 531 /* Rx csum disabled */ 532 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 533 return; 534 535 /* if IPv4 header checksum error */ 536 if ((wx_test_staterr(rx_desc, WX_RXD_STAT_IPCS) && 537 wx_test_staterr(rx_desc, WX_RXD_ERR_IPE)) || 538 (wx_test_staterr(rx_desc, WX_RXD_STAT_OUTERIPCS) && 539 wx_test_staterr(rx_desc, WX_RXD_ERR_OUTERIPER))) { 540 ring->rx_stats.csum_err++; 541 return; 542 } 543 544 /* L4 checksum offload flag must set for the below code to work */ 545 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_L4CS)) 546 return; 547 548 /* Hardware can't guarantee csum if IPv6 Dest Header found */ 549 if (dptype.prot != WX_DEC_PTYPE_PROT_SCTP && WX_RXD_IPV6EX(rx_desc)) 550 return; 551 552 /* if L4 checksum error */ 553 if (wx_test_staterr(rx_desc, WX_RXD_ERR_TCPE)) { 554 ring->rx_stats.csum_err++; 555 return; 556 } 557 558 /* It must be a TCP or UDP or SCTP packet with a valid checksum */ 559 skb->ip_summed = CHECKSUM_UNNECESSARY; 560 561 /* If there is an outer header present that might contain a checksum 562 * we need to bump the checksum level by 1 to reflect the fact that 563 * we are indicating we validated the inner checksum. 564 */ 565 if (dptype.etype >= WX_DEC_PTYPE_ETYPE_IG) 566 __skb_incr_checksum_unnecessary(skb); 567 ring->rx_stats.csum_good_cnt++; 568 } 569 570 static void wx_rx_vlan(struct wx_ring *ring, union wx_rx_desc *rx_desc, 571 struct sk_buff *skb) 572 { 573 u16 ethertype; 574 u8 idx = 0; 575 576 if ((ring->netdev->features & 577 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) && 578 wx_test_staterr(rx_desc, WX_RXD_STAT_VP)) { 579 idx = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 580 0x1c0) >> 6; 581 ethertype = ring->q_vector->wx->tpid[idx]; 582 __vlan_hwaccel_put_tag(skb, htons(ethertype), 583 le16_to_cpu(rx_desc->wb.upper.vlan)); 584 } 585 } 586 587 /** 588 * wx_process_skb_fields - Populate skb header fields from Rx descriptor 589 * @rx_ring: rx descriptor ring packet is being transacted on 590 * @rx_desc: pointer to the EOP Rx descriptor 591 * @skb: pointer to current skb being populated 592 * 593 * This function checks the ring, descriptor, and packet information in 594 * order to populate the hash, checksum, protocol, and 595 * other fields within the skb. 596 **/ 597 static void wx_process_skb_fields(struct wx_ring *rx_ring, 598 union wx_rx_desc *rx_desc, 599 struct sk_buff *skb) 600 { 601 wx_rx_hash(rx_ring, rx_desc, skb); 602 wx_rx_checksum(rx_ring, rx_desc, skb); 603 wx_rx_vlan(rx_ring, rx_desc, skb); 604 skb_record_rx_queue(skb, rx_ring->queue_index); 605 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 606 } 607 608 /** 609 * wx_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 610 * @q_vector: structure containing interrupt and ring information 611 * @rx_ring: rx descriptor ring to transact packets on 612 * @budget: Total limit on number of packets to process 613 * 614 * This function provides a "bounce buffer" approach to Rx interrupt 615 * processing. The advantage to this is that on systems that have 616 * expensive overhead for IOMMU access this provides a means of avoiding 617 * it by maintaining the mapping of the page to the system. 618 * 619 * Returns amount of work completed. 620 **/ 621 static int wx_clean_rx_irq(struct wx_q_vector *q_vector, 622 struct wx_ring *rx_ring, 623 int budget) 624 { 625 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 626 u16 cleaned_count = wx_desc_unused(rx_ring); 627 628 do { 629 struct wx_rx_buffer *rx_buffer; 630 union wx_rx_desc *rx_desc; 631 struct sk_buff *skb; 632 int rx_buffer_pgcnt; 633 634 /* return some buffers to hardware, one at a time is too slow */ 635 if (cleaned_count >= WX_RX_BUFFER_WRITE) { 636 wx_alloc_rx_buffers(rx_ring, cleaned_count); 637 cleaned_count = 0; 638 } 639 640 rx_desc = WX_RX_DESC(rx_ring, rx_ring->next_to_clean); 641 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_DD)) 642 break; 643 644 /* This memory barrier is needed to keep us from reading 645 * any other fields out of the rx_desc until we know the 646 * descriptor has been written back 647 */ 648 dma_rmb(); 649 650 rx_buffer = wx_get_rx_buffer(rx_ring, rx_desc, &skb, &rx_buffer_pgcnt); 651 652 /* retrieve a buffer from the ring */ 653 skb = wx_build_skb(rx_ring, rx_buffer, rx_desc); 654 655 /* exit if we failed to retrieve a buffer */ 656 if (!skb) { 657 break; 658 } 659 660 wx_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt); 661 cleaned_count++; 662 663 /* place incomplete frames back on ring for completion */ 664 if (wx_is_non_eop(rx_ring, rx_desc, skb)) 665 continue; 666 667 /* verify the packet layout is correct */ 668 if (wx_cleanup_headers(rx_ring, rx_desc, skb)) 669 continue; 670 671 /* probably a little skewed due to removing CRC */ 672 total_rx_bytes += skb->len; 673 674 /* populate checksum, timestamp, VLAN, and protocol */ 675 wx_process_skb_fields(rx_ring, rx_desc, skb); 676 napi_gro_receive(&q_vector->napi, skb); 677 678 /* update budget accounting */ 679 total_rx_packets++; 680 } while (likely(total_rx_packets < budget)); 681 682 u64_stats_update_begin(&rx_ring->syncp); 683 rx_ring->stats.packets += total_rx_packets; 684 rx_ring->stats.bytes += total_rx_bytes; 685 u64_stats_update_end(&rx_ring->syncp); 686 q_vector->rx.total_packets += total_rx_packets; 687 q_vector->rx.total_bytes += total_rx_bytes; 688 689 return total_rx_packets; 690 } 691 692 static struct netdev_queue *wx_txring_txq(const struct wx_ring *ring) 693 { 694 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 695 } 696 697 /** 698 * wx_clean_tx_irq - Reclaim resources after transmit completes 699 * @q_vector: structure containing interrupt and ring information 700 * @tx_ring: tx ring to clean 701 * @napi_budget: Used to determine if we are in netpoll 702 **/ 703 static bool wx_clean_tx_irq(struct wx_q_vector *q_vector, 704 struct wx_ring *tx_ring, int napi_budget) 705 { 706 unsigned int budget = q_vector->wx->tx_work_limit; 707 unsigned int total_bytes = 0, total_packets = 0; 708 unsigned int i = tx_ring->next_to_clean; 709 struct wx_tx_buffer *tx_buffer; 710 union wx_tx_desc *tx_desc; 711 712 if (!netif_carrier_ok(tx_ring->netdev)) 713 return true; 714 715 tx_buffer = &tx_ring->tx_buffer_info[i]; 716 tx_desc = WX_TX_DESC(tx_ring, i); 717 i -= tx_ring->count; 718 719 do { 720 union wx_tx_desc *eop_desc = tx_buffer->next_to_watch; 721 722 /* if next_to_watch is not set then there is no work pending */ 723 if (!eop_desc) 724 break; 725 726 /* prevent any other reads prior to eop_desc */ 727 smp_rmb(); 728 729 /* if DD is not set pending work has not been completed */ 730 if (!(eop_desc->wb.status & cpu_to_le32(WX_TXD_STAT_DD))) 731 break; 732 733 /* clear next_to_watch to prevent false hangs */ 734 tx_buffer->next_to_watch = NULL; 735 736 /* update the statistics for this packet */ 737 total_bytes += tx_buffer->bytecount; 738 total_packets += tx_buffer->gso_segs; 739 740 /* free the skb */ 741 napi_consume_skb(tx_buffer->skb, napi_budget); 742 743 /* unmap skb header data */ 744 dma_unmap_single(tx_ring->dev, 745 dma_unmap_addr(tx_buffer, dma), 746 dma_unmap_len(tx_buffer, len), 747 DMA_TO_DEVICE); 748 749 /* clear tx_buffer data */ 750 dma_unmap_len_set(tx_buffer, len, 0); 751 752 /* unmap remaining buffers */ 753 while (tx_desc != eop_desc) { 754 tx_buffer++; 755 tx_desc++; 756 i++; 757 if (unlikely(!i)) { 758 i -= tx_ring->count; 759 tx_buffer = tx_ring->tx_buffer_info; 760 tx_desc = WX_TX_DESC(tx_ring, 0); 761 } 762 763 /* unmap any remaining paged data */ 764 if (dma_unmap_len(tx_buffer, len)) { 765 dma_unmap_page(tx_ring->dev, 766 dma_unmap_addr(tx_buffer, dma), 767 dma_unmap_len(tx_buffer, len), 768 DMA_TO_DEVICE); 769 dma_unmap_len_set(tx_buffer, len, 0); 770 } 771 } 772 773 /* move us one more past the eop_desc for start of next pkt */ 774 tx_buffer++; 775 tx_desc++; 776 i++; 777 if (unlikely(!i)) { 778 i -= tx_ring->count; 779 tx_buffer = tx_ring->tx_buffer_info; 780 tx_desc = WX_TX_DESC(tx_ring, 0); 781 } 782 783 /* issue prefetch for next Tx descriptor */ 784 prefetch(tx_desc); 785 786 /* update budget accounting */ 787 budget--; 788 } while (likely(budget)); 789 790 i += tx_ring->count; 791 tx_ring->next_to_clean = i; 792 u64_stats_update_begin(&tx_ring->syncp); 793 tx_ring->stats.bytes += total_bytes; 794 tx_ring->stats.packets += total_packets; 795 u64_stats_update_end(&tx_ring->syncp); 796 q_vector->tx.total_bytes += total_bytes; 797 q_vector->tx.total_packets += total_packets; 798 799 netdev_tx_completed_queue(wx_txring_txq(tx_ring), 800 total_packets, total_bytes); 801 802 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 803 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 804 (wx_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 805 /* Make sure that anybody stopping the queue after this 806 * sees the new next_to_clean. 807 */ 808 smp_mb(); 809 810 if (__netif_subqueue_stopped(tx_ring->netdev, 811 tx_ring->queue_index) && 812 netif_running(tx_ring->netdev)) 813 netif_wake_subqueue(tx_ring->netdev, 814 tx_ring->queue_index); 815 } 816 817 return !!budget; 818 } 819 820 /** 821 * wx_poll - NAPI polling RX/TX cleanup routine 822 * @napi: napi struct with our devices info in it 823 * @budget: amount of work driver is allowed to do this pass, in packets 824 * 825 * This function will clean all queues associated with a q_vector. 826 **/ 827 static int wx_poll(struct napi_struct *napi, int budget) 828 { 829 struct wx_q_vector *q_vector = container_of(napi, struct wx_q_vector, napi); 830 int per_ring_budget, work_done = 0; 831 struct wx *wx = q_vector->wx; 832 bool clean_complete = true; 833 struct wx_ring *ring; 834 835 wx_for_each_ring(ring, q_vector->tx) { 836 if (!wx_clean_tx_irq(q_vector, ring, budget)) 837 clean_complete = false; 838 } 839 840 /* Exit if we are called by netpoll */ 841 if (budget <= 0) 842 return budget; 843 844 /* attempt to distribute budget to each queue fairly, but don't allow 845 * the budget to go below 1 because we'll exit polling 846 */ 847 if (q_vector->rx.count > 1) 848 per_ring_budget = max(budget / q_vector->rx.count, 1); 849 else 850 per_ring_budget = budget; 851 852 wx_for_each_ring(ring, q_vector->rx) { 853 int cleaned = wx_clean_rx_irq(q_vector, ring, per_ring_budget); 854 855 work_done += cleaned; 856 if (cleaned >= per_ring_budget) 857 clean_complete = false; 858 } 859 860 /* If all work not completed, return budget and keep polling */ 861 if (!clean_complete) 862 return budget; 863 864 /* all work done, exit the polling mode */ 865 if (likely(napi_complete_done(napi, work_done))) { 866 if (netif_running(wx->netdev)) 867 wx_intr_enable(wx, WX_INTR_Q(q_vector->v_idx)); 868 } 869 870 return min(work_done, budget - 1); 871 } 872 873 static int wx_maybe_stop_tx(struct wx_ring *tx_ring, u16 size) 874 { 875 if (likely(wx_desc_unused(tx_ring) >= size)) 876 return 0; 877 878 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 879 880 /* For the next check */ 881 smp_mb(); 882 883 /* We need to check again in a case another CPU has just 884 * made room available. 885 */ 886 if (likely(wx_desc_unused(tx_ring) < size)) 887 return -EBUSY; 888 889 /* A reprieve! - use start_queue because it doesn't call schedule */ 890 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 891 892 return 0; 893 } 894 895 static u32 wx_tx_cmd_type(u32 tx_flags) 896 { 897 /* set type for advanced descriptor with frame checksum insertion */ 898 u32 cmd_type = WX_TXD_DTYP_DATA | WX_TXD_IFCS; 899 900 /* set HW vlan bit if vlan is present */ 901 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_HW_VLAN, WX_TXD_VLE); 902 /* set segmentation enable bits for TSO/FSO */ 903 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSO, WX_TXD_TSE); 904 /* set timestamp bit if present */ 905 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSTAMP, WX_TXD_MAC_TSTAMP); 906 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_LINKSEC, WX_TXD_LINKSEC); 907 908 return cmd_type; 909 } 910 911 static void wx_tx_olinfo_status(union wx_tx_desc *tx_desc, 912 u32 tx_flags, unsigned int paylen) 913 { 914 u32 olinfo_status = paylen << WX_TXD_PAYLEN_SHIFT; 915 916 /* enable L4 checksum for TSO and TX checksum offload */ 917 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CSUM, WX_TXD_L4CS); 918 /* enable IPv4 checksum for TSO */ 919 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPV4, WX_TXD_IIPCS); 920 /* enable outer IPv4 checksum for TSO */ 921 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_OUTER_IPV4, 922 WX_TXD_EIPCS); 923 /* Check Context must be set if Tx switch is enabled, which it 924 * always is for case where virtual functions are running 925 */ 926 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CC, WX_TXD_CC); 927 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPSEC, 928 WX_TXD_IPSEC); 929 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 930 } 931 932 static void wx_tx_map(struct wx_ring *tx_ring, 933 struct wx_tx_buffer *first, 934 const u8 hdr_len) 935 { 936 struct sk_buff *skb = first->skb; 937 struct wx_tx_buffer *tx_buffer; 938 u32 tx_flags = first->tx_flags; 939 u16 i = tx_ring->next_to_use; 940 unsigned int data_len, size; 941 union wx_tx_desc *tx_desc; 942 skb_frag_t *frag; 943 dma_addr_t dma; 944 u32 cmd_type; 945 946 cmd_type = wx_tx_cmd_type(tx_flags); 947 tx_desc = WX_TX_DESC(tx_ring, i); 948 wx_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 949 950 size = skb_headlen(skb); 951 data_len = skb->data_len; 952 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 953 954 tx_buffer = first; 955 956 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 957 if (dma_mapping_error(tx_ring->dev, dma)) 958 goto dma_error; 959 960 /* record length, and DMA address */ 961 dma_unmap_len_set(tx_buffer, len, size); 962 dma_unmap_addr_set(tx_buffer, dma, dma); 963 964 tx_desc->read.buffer_addr = cpu_to_le64(dma); 965 966 while (unlikely(size > WX_MAX_DATA_PER_TXD)) { 967 tx_desc->read.cmd_type_len = 968 cpu_to_le32(cmd_type ^ WX_MAX_DATA_PER_TXD); 969 970 i++; 971 tx_desc++; 972 if (i == tx_ring->count) { 973 tx_desc = WX_TX_DESC(tx_ring, 0); 974 i = 0; 975 } 976 tx_desc->read.olinfo_status = 0; 977 978 dma += WX_MAX_DATA_PER_TXD; 979 size -= WX_MAX_DATA_PER_TXD; 980 981 tx_desc->read.buffer_addr = cpu_to_le64(dma); 982 } 983 984 if (likely(!data_len)) 985 break; 986 987 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 988 989 i++; 990 tx_desc++; 991 if (i == tx_ring->count) { 992 tx_desc = WX_TX_DESC(tx_ring, 0); 993 i = 0; 994 } 995 tx_desc->read.olinfo_status = 0; 996 997 size = skb_frag_size(frag); 998 999 data_len -= size; 1000 1001 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 1002 DMA_TO_DEVICE); 1003 1004 tx_buffer = &tx_ring->tx_buffer_info[i]; 1005 } 1006 1007 /* write last descriptor with RS and EOP bits */ 1008 cmd_type |= size | WX_TXD_EOP | WX_TXD_RS; 1009 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 1010 1011 netdev_tx_sent_queue(wx_txring_txq(tx_ring), first->bytecount); 1012 1013 skb_tx_timestamp(skb); 1014 1015 /* Force memory writes to complete before letting h/w know there 1016 * are new descriptors to fetch. (Only applicable for weak-ordered 1017 * memory model archs, such as IA-64). 1018 * 1019 * We also need this memory barrier to make certain all of the 1020 * status bits have been updated before next_to_watch is written. 1021 */ 1022 wmb(); 1023 1024 /* set next_to_watch value indicating a packet is present */ 1025 first->next_to_watch = tx_desc; 1026 1027 i++; 1028 if (i == tx_ring->count) 1029 i = 0; 1030 1031 tx_ring->next_to_use = i; 1032 1033 wx_maybe_stop_tx(tx_ring, DESC_NEEDED); 1034 1035 if (netif_xmit_stopped(wx_txring_txq(tx_ring)) || !netdev_xmit_more()) 1036 writel(i, tx_ring->tail); 1037 1038 return; 1039 dma_error: 1040 dev_err(tx_ring->dev, "TX DMA map failed\n"); 1041 1042 /* clear dma mappings for failed tx_buffer_info map */ 1043 for (;;) { 1044 tx_buffer = &tx_ring->tx_buffer_info[i]; 1045 if (dma_unmap_len(tx_buffer, len)) 1046 dma_unmap_page(tx_ring->dev, 1047 dma_unmap_addr(tx_buffer, dma), 1048 dma_unmap_len(tx_buffer, len), 1049 DMA_TO_DEVICE); 1050 dma_unmap_len_set(tx_buffer, len, 0); 1051 if (tx_buffer == first) 1052 break; 1053 if (i == 0) 1054 i += tx_ring->count; 1055 i--; 1056 } 1057 1058 dev_kfree_skb_any(first->skb); 1059 first->skb = NULL; 1060 1061 tx_ring->next_to_use = i; 1062 } 1063 1064 static void wx_tx_ctxtdesc(struct wx_ring *tx_ring, u32 vlan_macip_lens, 1065 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx) 1066 { 1067 struct wx_tx_context_desc *context_desc; 1068 u16 i = tx_ring->next_to_use; 1069 1070 context_desc = WX_TX_CTXTDESC(tx_ring, i); 1071 i++; 1072 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 1073 1074 /* set bits to identify this as an advanced context descriptor */ 1075 type_tucmd |= WX_TXD_DTYP_CTXT; 1076 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 1077 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof); 1078 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 1079 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 1080 } 1081 1082 static void wx_get_ipv6_proto(struct sk_buff *skb, int offset, u8 *nexthdr) 1083 { 1084 struct ipv6hdr *hdr = (struct ipv6hdr *)(skb->data + offset); 1085 1086 *nexthdr = hdr->nexthdr; 1087 offset += sizeof(struct ipv6hdr); 1088 while (ipv6_ext_hdr(*nexthdr)) { 1089 struct ipv6_opt_hdr _hdr, *hp; 1090 1091 if (*nexthdr == NEXTHDR_NONE) 1092 return; 1093 hp = skb_header_pointer(skb, offset, sizeof(_hdr), &_hdr); 1094 if (!hp) 1095 return; 1096 if (*nexthdr == NEXTHDR_FRAGMENT) 1097 break; 1098 *nexthdr = hp->nexthdr; 1099 } 1100 } 1101 1102 union network_header { 1103 struct iphdr *ipv4; 1104 struct ipv6hdr *ipv6; 1105 void *raw; 1106 }; 1107 1108 static u8 wx_encode_tx_desc_ptype(const struct wx_tx_buffer *first) 1109 { 1110 u8 tun_prot = 0, l4_prot = 0, ptype = 0; 1111 struct sk_buff *skb = first->skb; 1112 1113 if (skb->encapsulation) { 1114 union network_header hdr; 1115 1116 switch (first->protocol) { 1117 case htons(ETH_P_IP): 1118 tun_prot = ip_hdr(skb)->protocol; 1119 ptype = WX_PTYPE_TUN_IPV4; 1120 break; 1121 case htons(ETH_P_IPV6): 1122 wx_get_ipv6_proto(skb, skb_network_offset(skb), &tun_prot); 1123 ptype = WX_PTYPE_TUN_IPV6; 1124 break; 1125 default: 1126 return ptype; 1127 } 1128 1129 if (tun_prot == IPPROTO_IPIP) { 1130 hdr.raw = (void *)inner_ip_hdr(skb); 1131 ptype |= WX_PTYPE_PKT_IPIP; 1132 } else if (tun_prot == IPPROTO_UDP) { 1133 hdr.raw = (void *)inner_ip_hdr(skb); 1134 if (skb->inner_protocol_type != ENCAP_TYPE_ETHER || 1135 skb->inner_protocol != htons(ETH_P_TEB)) { 1136 ptype |= WX_PTYPE_PKT_IG; 1137 } else { 1138 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto 1139 == htons(ETH_P_8021Q)) 1140 ptype |= WX_PTYPE_PKT_IGMV; 1141 else 1142 ptype |= WX_PTYPE_PKT_IGM; 1143 } 1144 1145 } else if (tun_prot == IPPROTO_GRE) { 1146 hdr.raw = (void *)inner_ip_hdr(skb); 1147 if (skb->inner_protocol == htons(ETH_P_IP) || 1148 skb->inner_protocol == htons(ETH_P_IPV6)) { 1149 ptype |= WX_PTYPE_PKT_IG; 1150 } else { 1151 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto 1152 == htons(ETH_P_8021Q)) 1153 ptype |= WX_PTYPE_PKT_IGMV; 1154 else 1155 ptype |= WX_PTYPE_PKT_IGM; 1156 } 1157 } else { 1158 return ptype; 1159 } 1160 1161 switch (hdr.ipv4->version) { 1162 case IPVERSION: 1163 l4_prot = hdr.ipv4->protocol; 1164 break; 1165 case 6: 1166 wx_get_ipv6_proto(skb, skb_inner_network_offset(skb), &l4_prot); 1167 ptype |= WX_PTYPE_PKT_IPV6; 1168 break; 1169 default: 1170 return ptype; 1171 } 1172 } else { 1173 switch (first->protocol) { 1174 case htons(ETH_P_IP): 1175 l4_prot = ip_hdr(skb)->protocol; 1176 ptype = WX_PTYPE_PKT_IP; 1177 break; 1178 case htons(ETH_P_IPV6): 1179 wx_get_ipv6_proto(skb, skb_network_offset(skb), &l4_prot); 1180 ptype = WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6; 1181 break; 1182 default: 1183 return WX_PTYPE_PKT_MAC | WX_PTYPE_TYP_MAC; 1184 } 1185 } 1186 switch (l4_prot) { 1187 case IPPROTO_TCP: 1188 ptype |= WX_PTYPE_TYP_TCP; 1189 break; 1190 case IPPROTO_UDP: 1191 ptype |= WX_PTYPE_TYP_UDP; 1192 break; 1193 case IPPROTO_SCTP: 1194 ptype |= WX_PTYPE_TYP_SCTP; 1195 break; 1196 default: 1197 ptype |= WX_PTYPE_TYP_IP; 1198 break; 1199 } 1200 1201 return ptype; 1202 } 1203 1204 static int wx_tso(struct wx_ring *tx_ring, struct wx_tx_buffer *first, 1205 u8 *hdr_len, u8 ptype) 1206 { 1207 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 1208 struct net_device *netdev = tx_ring->netdev; 1209 u32 l4len, tunhdr_eiplen_tunlen = 0; 1210 struct sk_buff *skb = first->skb; 1211 bool enc = skb->encapsulation; 1212 struct ipv6hdr *ipv6h; 1213 struct tcphdr *tcph; 1214 struct iphdr *iph; 1215 u8 tun_prot = 0; 1216 int err; 1217 1218 if (skb->ip_summed != CHECKSUM_PARTIAL) 1219 return 0; 1220 1221 if (!skb_is_gso(skb)) 1222 return 0; 1223 1224 err = skb_cow_head(skb, 0); 1225 if (err < 0) 1226 return err; 1227 1228 /* indicates the inner headers in the skbuff are valid. */ 1229 iph = enc ? inner_ip_hdr(skb) : ip_hdr(skb); 1230 if (iph->version == 4) { 1231 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb); 1232 iph->tot_len = 0; 1233 iph->check = 0; 1234 tcph->check = ~csum_tcpudp_magic(iph->saddr, 1235 iph->daddr, 0, 1236 IPPROTO_TCP, 0); 1237 first->tx_flags |= WX_TX_FLAGS_TSO | 1238 WX_TX_FLAGS_CSUM | 1239 WX_TX_FLAGS_IPV4 | 1240 WX_TX_FLAGS_CC; 1241 } else if (iph->version == 6 && skb_is_gso_v6(skb)) { 1242 ipv6h = enc ? inner_ipv6_hdr(skb) : ipv6_hdr(skb); 1243 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb); 1244 ipv6h->payload_len = 0; 1245 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, 1246 &ipv6h->daddr, 0, 1247 IPPROTO_TCP, 0); 1248 first->tx_flags |= WX_TX_FLAGS_TSO | 1249 WX_TX_FLAGS_CSUM | 1250 WX_TX_FLAGS_CC; 1251 } 1252 1253 /* compute header lengths */ 1254 l4len = enc ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb); 1255 *hdr_len = enc ? (skb_inner_transport_header(skb) - skb->data) : 1256 skb_transport_offset(skb); 1257 *hdr_len += l4len; 1258 1259 /* update gso size and bytecount with header size */ 1260 first->gso_segs = skb_shinfo(skb)->gso_segs; 1261 first->bytecount += (first->gso_segs - 1) * *hdr_len; 1262 1263 /* mss_l4len_id: use 0 as index for TSO */ 1264 mss_l4len_idx = l4len << WX_TXD_L4LEN_SHIFT; 1265 mss_l4len_idx |= skb_shinfo(skb)->gso_size << WX_TXD_MSS_SHIFT; 1266 1267 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 1268 if (enc) { 1269 switch (first->protocol) { 1270 case htons(ETH_P_IP): 1271 tun_prot = ip_hdr(skb)->protocol; 1272 first->tx_flags |= WX_TX_FLAGS_OUTER_IPV4; 1273 break; 1274 case htons(ETH_P_IPV6): 1275 tun_prot = ipv6_hdr(skb)->nexthdr; 1276 break; 1277 default: 1278 break; 1279 } 1280 switch (tun_prot) { 1281 case IPPROTO_UDP: 1282 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP; 1283 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) << 1284 WX_TXD_OUTER_IPLEN_SHIFT) | 1285 (((skb_inner_mac_header(skb) - 1286 skb_transport_header(skb)) >> 1) << 1287 WX_TXD_TUNNEL_LEN_SHIFT); 1288 break; 1289 case IPPROTO_GRE: 1290 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE; 1291 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) << 1292 WX_TXD_OUTER_IPLEN_SHIFT) | 1293 (((skb_inner_mac_header(skb) - 1294 skb_transport_header(skb)) >> 1) << 1295 WX_TXD_TUNNEL_LEN_SHIFT); 1296 break; 1297 case IPPROTO_IPIP: 1298 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) - 1299 (char *)ip_hdr(skb)) >> 2) << 1300 WX_TXD_OUTER_IPLEN_SHIFT; 1301 break; 1302 default: 1303 break; 1304 } 1305 vlan_macip_lens = skb_inner_network_header_len(skb) >> 1; 1306 } else { 1307 vlan_macip_lens = skb_network_header_len(skb) >> 1; 1308 } 1309 1310 vlan_macip_lens |= skb_network_offset(skb) << WX_TXD_MACLEN_SHIFT; 1311 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK; 1312 1313 type_tucmd = ptype << 24; 1314 if (skb->vlan_proto == htons(ETH_P_8021AD) && 1315 netdev->features & NETIF_F_HW_VLAN_STAG_TX) 1316 type_tucmd |= WX_SET_FLAG(first->tx_flags, 1317 WX_TX_FLAGS_HW_VLAN, 1318 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT); 1319 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen, 1320 type_tucmd, mss_l4len_idx); 1321 1322 return 1; 1323 } 1324 1325 static void wx_tx_csum(struct wx_ring *tx_ring, struct wx_tx_buffer *first, 1326 u8 ptype) 1327 { 1328 u32 tunhdr_eiplen_tunlen = 0, vlan_macip_lens = 0; 1329 struct net_device *netdev = tx_ring->netdev; 1330 u32 mss_l4len_idx = 0, type_tucmd; 1331 struct sk_buff *skb = first->skb; 1332 u8 tun_prot = 0; 1333 1334 if (skb->ip_summed != CHECKSUM_PARTIAL) { 1335 if (!(first->tx_flags & WX_TX_FLAGS_HW_VLAN) && 1336 !(first->tx_flags & WX_TX_FLAGS_CC)) 1337 return; 1338 vlan_macip_lens = skb_network_offset(skb) << 1339 WX_TXD_MACLEN_SHIFT; 1340 } else { 1341 u8 l4_prot = 0; 1342 union { 1343 struct iphdr *ipv4; 1344 struct ipv6hdr *ipv6; 1345 u8 *raw; 1346 } network_hdr; 1347 union { 1348 struct tcphdr *tcphdr; 1349 u8 *raw; 1350 } transport_hdr; 1351 1352 if (skb->encapsulation) { 1353 network_hdr.raw = skb_inner_network_header(skb); 1354 transport_hdr.raw = skb_inner_transport_header(skb); 1355 vlan_macip_lens = skb_network_offset(skb) << 1356 WX_TXD_MACLEN_SHIFT; 1357 switch (first->protocol) { 1358 case htons(ETH_P_IP): 1359 tun_prot = ip_hdr(skb)->protocol; 1360 break; 1361 case htons(ETH_P_IPV6): 1362 tun_prot = ipv6_hdr(skb)->nexthdr; 1363 break; 1364 default: 1365 return; 1366 } 1367 switch (tun_prot) { 1368 case IPPROTO_UDP: 1369 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP; 1370 tunhdr_eiplen_tunlen |= 1371 ((skb_network_header_len(skb) >> 2) << 1372 WX_TXD_OUTER_IPLEN_SHIFT) | 1373 (((skb_inner_mac_header(skb) - 1374 skb_transport_header(skb)) >> 1) << 1375 WX_TXD_TUNNEL_LEN_SHIFT); 1376 break; 1377 case IPPROTO_GRE: 1378 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE; 1379 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) << 1380 WX_TXD_OUTER_IPLEN_SHIFT) | 1381 (((skb_inner_mac_header(skb) - 1382 skb_transport_header(skb)) >> 1) << 1383 WX_TXD_TUNNEL_LEN_SHIFT); 1384 break; 1385 case IPPROTO_IPIP: 1386 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) - 1387 (char *)ip_hdr(skb)) >> 2) << 1388 WX_TXD_OUTER_IPLEN_SHIFT; 1389 break; 1390 default: 1391 break; 1392 } 1393 1394 } else { 1395 network_hdr.raw = skb_network_header(skb); 1396 transport_hdr.raw = skb_transport_header(skb); 1397 vlan_macip_lens = skb_network_offset(skb) << 1398 WX_TXD_MACLEN_SHIFT; 1399 } 1400 1401 switch (network_hdr.ipv4->version) { 1402 case IPVERSION: 1403 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1; 1404 l4_prot = network_hdr.ipv4->protocol; 1405 break; 1406 case 6: 1407 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1; 1408 l4_prot = network_hdr.ipv6->nexthdr; 1409 break; 1410 default: 1411 break; 1412 } 1413 1414 switch (l4_prot) { 1415 case IPPROTO_TCP: 1416 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) << 1417 WX_TXD_L4LEN_SHIFT; 1418 break; 1419 case IPPROTO_SCTP: 1420 mss_l4len_idx = sizeof(struct sctphdr) << 1421 WX_TXD_L4LEN_SHIFT; 1422 break; 1423 case IPPROTO_UDP: 1424 mss_l4len_idx = sizeof(struct udphdr) << 1425 WX_TXD_L4LEN_SHIFT; 1426 break; 1427 default: 1428 break; 1429 } 1430 1431 /* update TX checksum flag */ 1432 first->tx_flags |= WX_TX_FLAGS_CSUM; 1433 } 1434 first->tx_flags |= WX_TX_FLAGS_CC; 1435 /* vlan_macip_lens: MACLEN, VLAN tag */ 1436 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK; 1437 1438 type_tucmd = ptype << 24; 1439 if (skb->vlan_proto == htons(ETH_P_8021AD) && 1440 netdev->features & NETIF_F_HW_VLAN_STAG_TX) 1441 type_tucmd |= WX_SET_FLAG(first->tx_flags, 1442 WX_TX_FLAGS_HW_VLAN, 1443 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT); 1444 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen, 1445 type_tucmd, mss_l4len_idx); 1446 } 1447 1448 static netdev_tx_t wx_xmit_frame_ring(struct sk_buff *skb, 1449 struct wx_ring *tx_ring) 1450 { 1451 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 1452 struct wx_tx_buffer *first; 1453 u8 hdr_len = 0, ptype; 1454 unsigned short f; 1455 u32 tx_flags = 0; 1456 int tso; 1457 1458 /* need: 1 descriptor per page * PAGE_SIZE/WX_MAX_DATA_PER_TXD, 1459 * + 1 desc for skb_headlen/WX_MAX_DATA_PER_TXD, 1460 * + 2 desc gap to keep tail from touching head, 1461 * + 1 desc for context descriptor, 1462 * otherwise try next time 1463 */ 1464 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 1465 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)-> 1466 frags[f])); 1467 1468 if (wx_maybe_stop_tx(tx_ring, count + 3)) 1469 return NETDEV_TX_BUSY; 1470 1471 /* record the location of the first descriptor for this packet */ 1472 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 1473 first->skb = skb; 1474 first->bytecount = skb->len; 1475 first->gso_segs = 1; 1476 1477 /* if we have a HW VLAN tag being added default to the HW one */ 1478 if (skb_vlan_tag_present(skb)) { 1479 tx_flags |= skb_vlan_tag_get(skb) << WX_TX_FLAGS_VLAN_SHIFT; 1480 tx_flags |= WX_TX_FLAGS_HW_VLAN; 1481 } 1482 1483 /* record initial flags and protocol */ 1484 first->tx_flags = tx_flags; 1485 first->protocol = vlan_get_protocol(skb); 1486 1487 ptype = wx_encode_tx_desc_ptype(first); 1488 1489 tso = wx_tso(tx_ring, first, &hdr_len, ptype); 1490 if (tso < 0) 1491 goto out_drop; 1492 else if (!tso) 1493 wx_tx_csum(tx_ring, first, ptype); 1494 wx_tx_map(tx_ring, first, hdr_len); 1495 1496 return NETDEV_TX_OK; 1497 out_drop: 1498 dev_kfree_skb_any(first->skb); 1499 first->skb = NULL; 1500 1501 return NETDEV_TX_OK; 1502 } 1503 1504 netdev_tx_t wx_xmit_frame(struct sk_buff *skb, 1505 struct net_device *netdev) 1506 { 1507 unsigned int r_idx = skb->queue_mapping; 1508 struct wx *wx = netdev_priv(netdev); 1509 struct wx_ring *tx_ring; 1510 1511 if (!netif_carrier_ok(netdev)) { 1512 dev_kfree_skb_any(skb); 1513 return NETDEV_TX_OK; 1514 } 1515 1516 /* The minimum packet size for olinfo paylen is 17 so pad the skb 1517 * in order to meet this minimum size requirement. 1518 */ 1519 if (skb_put_padto(skb, 17)) 1520 return NETDEV_TX_OK; 1521 1522 if (r_idx >= wx->num_tx_queues) 1523 r_idx = r_idx % wx->num_tx_queues; 1524 tx_ring = wx->tx_ring[r_idx]; 1525 1526 return wx_xmit_frame_ring(skb, tx_ring); 1527 } 1528 EXPORT_SYMBOL(wx_xmit_frame); 1529 1530 void wx_napi_enable_all(struct wx *wx) 1531 { 1532 struct wx_q_vector *q_vector; 1533 int q_idx; 1534 1535 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) { 1536 q_vector = wx->q_vector[q_idx]; 1537 napi_enable(&q_vector->napi); 1538 } 1539 } 1540 EXPORT_SYMBOL(wx_napi_enable_all); 1541 1542 void wx_napi_disable_all(struct wx *wx) 1543 { 1544 struct wx_q_vector *q_vector; 1545 int q_idx; 1546 1547 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) { 1548 q_vector = wx->q_vector[q_idx]; 1549 napi_disable(&q_vector->napi); 1550 } 1551 } 1552 EXPORT_SYMBOL(wx_napi_disable_all); 1553 1554 /** 1555 * wx_set_rss_queues: Allocate queues for RSS 1556 * @wx: board private structure to initialize 1557 * 1558 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try 1559 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. 1560 * 1561 **/ 1562 static void wx_set_rss_queues(struct wx *wx) 1563 { 1564 wx->num_rx_queues = wx->mac.max_rx_queues; 1565 wx->num_tx_queues = wx->mac.max_tx_queues; 1566 } 1567 1568 static void wx_set_num_queues(struct wx *wx) 1569 { 1570 /* Start with base case */ 1571 wx->num_rx_queues = 1; 1572 wx->num_tx_queues = 1; 1573 wx->queues_per_pool = 1; 1574 1575 wx_set_rss_queues(wx); 1576 } 1577 1578 /** 1579 * wx_acquire_msix_vectors - acquire MSI-X vectors 1580 * @wx: board private structure 1581 * 1582 * Attempts to acquire a suitable range of MSI-X vector interrupts. Will 1583 * return a negative error code if unable to acquire MSI-X vectors for any 1584 * reason. 1585 */ 1586 static int wx_acquire_msix_vectors(struct wx *wx) 1587 { 1588 struct irq_affinity affd = {0, }; 1589 int nvecs, i; 1590 1591 nvecs = min_t(int, num_online_cpus(), wx->mac.max_msix_vectors); 1592 1593 wx->msix_entries = kcalloc(nvecs, 1594 sizeof(struct msix_entry), 1595 GFP_KERNEL); 1596 if (!wx->msix_entries) 1597 return -ENOMEM; 1598 1599 nvecs = pci_alloc_irq_vectors_affinity(wx->pdev, nvecs, 1600 nvecs, 1601 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, 1602 &affd); 1603 if (nvecs < 0) { 1604 wx_err(wx, "Failed to allocate MSI-X interrupts. Err: %d\n", nvecs); 1605 kfree(wx->msix_entries); 1606 wx->msix_entries = NULL; 1607 return nvecs; 1608 } 1609 1610 for (i = 0; i < nvecs; i++) { 1611 wx->msix_entries[i].entry = i; 1612 wx->msix_entries[i].vector = pci_irq_vector(wx->pdev, i); 1613 } 1614 1615 /* one for msix_other */ 1616 nvecs -= 1; 1617 wx->num_q_vectors = nvecs; 1618 wx->num_rx_queues = nvecs; 1619 wx->num_tx_queues = nvecs; 1620 1621 return 0; 1622 } 1623 1624 /** 1625 * wx_set_interrupt_capability - set MSI-X or MSI if supported 1626 * @wx: board private structure to initialize 1627 * 1628 * Attempt to configure the interrupts using the best available 1629 * capabilities of the hardware and the kernel. 1630 **/ 1631 static int wx_set_interrupt_capability(struct wx *wx) 1632 { 1633 struct pci_dev *pdev = wx->pdev; 1634 int nvecs, ret; 1635 1636 /* We will try to get MSI-X interrupts first */ 1637 ret = wx_acquire_msix_vectors(wx); 1638 if (ret == 0 || (ret == -ENOMEM)) 1639 return ret; 1640 1641 wx->num_rx_queues = 1; 1642 wx->num_tx_queues = 1; 1643 wx->num_q_vectors = 1; 1644 1645 /* minmum one for queue, one for misc*/ 1646 nvecs = 1; 1647 nvecs = pci_alloc_irq_vectors(pdev, nvecs, 1648 nvecs, PCI_IRQ_MSI | PCI_IRQ_LEGACY); 1649 if (nvecs == 1) { 1650 if (pdev->msi_enabled) 1651 wx_err(wx, "Fallback to MSI.\n"); 1652 else 1653 wx_err(wx, "Fallback to LEGACY.\n"); 1654 } else { 1655 wx_err(wx, "Failed to allocate MSI/LEGACY interrupts. Error: %d\n", nvecs); 1656 return nvecs; 1657 } 1658 1659 pdev->irq = pci_irq_vector(pdev, 0); 1660 wx->num_q_vectors = 1; 1661 1662 return 0; 1663 } 1664 1665 /** 1666 * wx_cache_ring_rss - Descriptor ring to register mapping for RSS 1667 * @wx: board private structure to initialize 1668 * 1669 * Cache the descriptor ring offsets for RSS, ATR, FCoE, and SR-IOV. 1670 * 1671 **/ 1672 static void wx_cache_ring_rss(struct wx *wx) 1673 { 1674 u16 i; 1675 1676 for (i = 0; i < wx->num_rx_queues; i++) 1677 wx->rx_ring[i]->reg_idx = i; 1678 1679 for (i = 0; i < wx->num_tx_queues; i++) 1680 wx->tx_ring[i]->reg_idx = i; 1681 } 1682 1683 static void wx_add_ring(struct wx_ring *ring, struct wx_ring_container *head) 1684 { 1685 ring->next = head->ring; 1686 head->ring = ring; 1687 head->count++; 1688 } 1689 1690 /** 1691 * wx_alloc_q_vector - Allocate memory for a single interrupt vector 1692 * @wx: board private structure to initialize 1693 * @v_count: q_vectors allocated on wx, used for ring interleaving 1694 * @v_idx: index of vector in wx struct 1695 * @txr_count: total number of Tx rings to allocate 1696 * @txr_idx: index of first Tx ring to allocate 1697 * @rxr_count: total number of Rx rings to allocate 1698 * @rxr_idx: index of first Rx ring to allocate 1699 * 1700 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1701 **/ 1702 static int wx_alloc_q_vector(struct wx *wx, 1703 unsigned int v_count, unsigned int v_idx, 1704 unsigned int txr_count, unsigned int txr_idx, 1705 unsigned int rxr_count, unsigned int rxr_idx) 1706 { 1707 struct wx_q_vector *q_vector; 1708 int ring_count, default_itr; 1709 struct wx_ring *ring; 1710 1711 /* note this will allocate space for the ring structure as well! */ 1712 ring_count = txr_count + rxr_count; 1713 1714 q_vector = kzalloc(struct_size(q_vector, ring, ring_count), 1715 GFP_KERNEL); 1716 if (!q_vector) 1717 return -ENOMEM; 1718 1719 /* initialize NAPI */ 1720 netif_napi_add(wx->netdev, &q_vector->napi, 1721 wx_poll); 1722 1723 /* tie q_vector and wx together */ 1724 wx->q_vector[v_idx] = q_vector; 1725 q_vector->wx = wx; 1726 q_vector->v_idx = v_idx; 1727 if (cpu_online(v_idx)) 1728 q_vector->numa_node = cpu_to_node(v_idx); 1729 1730 /* initialize pointer to rings */ 1731 ring = q_vector->ring; 1732 1733 if (wx->mac.type == wx_mac_sp) 1734 default_itr = WX_12K_ITR; 1735 else 1736 default_itr = WX_7K_ITR; 1737 /* initialize ITR */ 1738 if (txr_count && !rxr_count) 1739 /* tx only vector */ 1740 q_vector->itr = wx->tx_itr_setting ? 1741 default_itr : wx->tx_itr_setting; 1742 else 1743 /* rx or rx/tx vector */ 1744 q_vector->itr = wx->rx_itr_setting ? 1745 default_itr : wx->rx_itr_setting; 1746 1747 while (txr_count) { 1748 /* assign generic ring traits */ 1749 ring->dev = &wx->pdev->dev; 1750 ring->netdev = wx->netdev; 1751 1752 /* configure backlink on ring */ 1753 ring->q_vector = q_vector; 1754 1755 /* update q_vector Tx values */ 1756 wx_add_ring(ring, &q_vector->tx); 1757 1758 /* apply Tx specific ring traits */ 1759 ring->count = wx->tx_ring_count; 1760 1761 ring->queue_index = txr_idx; 1762 1763 /* assign ring to wx */ 1764 wx->tx_ring[txr_idx] = ring; 1765 1766 /* update count and index */ 1767 txr_count--; 1768 txr_idx += v_count; 1769 1770 /* push pointer to next ring */ 1771 ring++; 1772 } 1773 1774 while (rxr_count) { 1775 /* assign generic ring traits */ 1776 ring->dev = &wx->pdev->dev; 1777 ring->netdev = wx->netdev; 1778 1779 /* configure backlink on ring */ 1780 ring->q_vector = q_vector; 1781 1782 /* update q_vector Rx values */ 1783 wx_add_ring(ring, &q_vector->rx); 1784 1785 /* apply Rx specific ring traits */ 1786 ring->count = wx->rx_ring_count; 1787 ring->queue_index = rxr_idx; 1788 1789 /* assign ring to wx */ 1790 wx->rx_ring[rxr_idx] = ring; 1791 1792 /* update count and index */ 1793 rxr_count--; 1794 rxr_idx += v_count; 1795 1796 /* push pointer to next ring */ 1797 ring++; 1798 } 1799 1800 return 0; 1801 } 1802 1803 /** 1804 * wx_free_q_vector - Free memory allocated for specific interrupt vector 1805 * @wx: board private structure to initialize 1806 * @v_idx: Index of vector to be freed 1807 * 1808 * This function frees the memory allocated to the q_vector. In addition if 1809 * NAPI is enabled it will delete any references to the NAPI struct prior 1810 * to freeing the q_vector. 1811 **/ 1812 static void wx_free_q_vector(struct wx *wx, int v_idx) 1813 { 1814 struct wx_q_vector *q_vector = wx->q_vector[v_idx]; 1815 struct wx_ring *ring; 1816 1817 wx_for_each_ring(ring, q_vector->tx) 1818 wx->tx_ring[ring->queue_index] = NULL; 1819 1820 wx_for_each_ring(ring, q_vector->rx) 1821 wx->rx_ring[ring->queue_index] = NULL; 1822 1823 wx->q_vector[v_idx] = NULL; 1824 netif_napi_del(&q_vector->napi); 1825 kfree_rcu(q_vector, rcu); 1826 } 1827 1828 /** 1829 * wx_alloc_q_vectors - Allocate memory for interrupt vectors 1830 * @wx: board private structure to initialize 1831 * 1832 * We allocate one q_vector per queue interrupt. If allocation fails we 1833 * return -ENOMEM. 1834 **/ 1835 static int wx_alloc_q_vectors(struct wx *wx) 1836 { 1837 unsigned int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1838 unsigned int rxr_remaining = wx->num_rx_queues; 1839 unsigned int txr_remaining = wx->num_tx_queues; 1840 unsigned int q_vectors = wx->num_q_vectors; 1841 int rqpv, tqpv; 1842 int err; 1843 1844 for (; v_idx < q_vectors; v_idx++) { 1845 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1846 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1847 err = wx_alloc_q_vector(wx, q_vectors, v_idx, 1848 tqpv, txr_idx, 1849 rqpv, rxr_idx); 1850 1851 if (err) 1852 goto err_out; 1853 1854 /* update counts and index */ 1855 rxr_remaining -= rqpv; 1856 txr_remaining -= tqpv; 1857 rxr_idx++; 1858 txr_idx++; 1859 } 1860 1861 return 0; 1862 1863 err_out: 1864 wx->num_tx_queues = 0; 1865 wx->num_rx_queues = 0; 1866 wx->num_q_vectors = 0; 1867 1868 while (v_idx--) 1869 wx_free_q_vector(wx, v_idx); 1870 1871 return -ENOMEM; 1872 } 1873 1874 /** 1875 * wx_free_q_vectors - Free memory allocated for interrupt vectors 1876 * @wx: board private structure to initialize 1877 * 1878 * This function frees the memory allocated to the q_vectors. In addition if 1879 * NAPI is enabled it will delete any references to the NAPI struct prior 1880 * to freeing the q_vector. 1881 **/ 1882 static void wx_free_q_vectors(struct wx *wx) 1883 { 1884 int v_idx = wx->num_q_vectors; 1885 1886 wx->num_tx_queues = 0; 1887 wx->num_rx_queues = 0; 1888 wx->num_q_vectors = 0; 1889 1890 while (v_idx--) 1891 wx_free_q_vector(wx, v_idx); 1892 } 1893 1894 void wx_reset_interrupt_capability(struct wx *wx) 1895 { 1896 struct pci_dev *pdev = wx->pdev; 1897 1898 if (!pdev->msi_enabled && !pdev->msix_enabled) 1899 return; 1900 1901 if (pdev->msix_enabled) { 1902 kfree(wx->msix_entries); 1903 wx->msix_entries = NULL; 1904 } 1905 pci_free_irq_vectors(wx->pdev); 1906 } 1907 EXPORT_SYMBOL(wx_reset_interrupt_capability); 1908 1909 /** 1910 * wx_clear_interrupt_scheme - Clear the current interrupt scheme settings 1911 * @wx: board private structure to clear interrupt scheme on 1912 * 1913 * We go through and clear interrupt specific resources and reset the structure 1914 * to pre-load conditions 1915 **/ 1916 void wx_clear_interrupt_scheme(struct wx *wx) 1917 { 1918 wx_free_q_vectors(wx); 1919 wx_reset_interrupt_capability(wx); 1920 } 1921 EXPORT_SYMBOL(wx_clear_interrupt_scheme); 1922 1923 int wx_init_interrupt_scheme(struct wx *wx) 1924 { 1925 int ret; 1926 1927 /* Number of supported queues */ 1928 wx_set_num_queues(wx); 1929 1930 /* Set interrupt mode */ 1931 ret = wx_set_interrupt_capability(wx); 1932 if (ret) { 1933 wx_err(wx, "Allocate irq vectors for failed.\n"); 1934 return ret; 1935 } 1936 1937 /* Allocate memory for queues */ 1938 ret = wx_alloc_q_vectors(wx); 1939 if (ret) { 1940 wx_err(wx, "Unable to allocate memory for queue vectors.\n"); 1941 wx_reset_interrupt_capability(wx); 1942 return ret; 1943 } 1944 1945 wx_cache_ring_rss(wx); 1946 1947 return 0; 1948 } 1949 EXPORT_SYMBOL(wx_init_interrupt_scheme); 1950 1951 irqreturn_t wx_msix_clean_rings(int __always_unused irq, void *data) 1952 { 1953 struct wx_q_vector *q_vector = data; 1954 1955 /* EIAM disabled interrupts (on this vector) for us */ 1956 if (q_vector->rx.ring || q_vector->tx.ring) 1957 napi_schedule_irqoff(&q_vector->napi); 1958 1959 return IRQ_HANDLED; 1960 } 1961 EXPORT_SYMBOL(wx_msix_clean_rings); 1962 1963 void wx_free_irq(struct wx *wx) 1964 { 1965 struct pci_dev *pdev = wx->pdev; 1966 int vector; 1967 1968 if (!(pdev->msix_enabled)) { 1969 free_irq(pdev->irq, wx); 1970 return; 1971 } 1972 1973 for (vector = 0; vector < wx->num_q_vectors; vector++) { 1974 struct wx_q_vector *q_vector = wx->q_vector[vector]; 1975 struct msix_entry *entry = &wx->msix_entries[vector]; 1976 1977 /* free only the irqs that were actually requested */ 1978 if (!q_vector->rx.ring && !q_vector->tx.ring) 1979 continue; 1980 1981 free_irq(entry->vector, q_vector); 1982 } 1983 1984 if (wx->mac.type == wx_mac_em) 1985 free_irq(wx->msix_entries[vector].vector, wx); 1986 } 1987 EXPORT_SYMBOL(wx_free_irq); 1988 1989 /** 1990 * wx_setup_isb_resources - allocate interrupt status resources 1991 * @wx: board private structure 1992 * 1993 * Return 0 on success, negative on failure 1994 **/ 1995 int wx_setup_isb_resources(struct wx *wx) 1996 { 1997 struct pci_dev *pdev = wx->pdev; 1998 1999 wx->isb_mem = dma_alloc_coherent(&pdev->dev, 2000 sizeof(u32) * 4, 2001 &wx->isb_dma, 2002 GFP_KERNEL); 2003 if (!wx->isb_mem) { 2004 wx_err(wx, "Alloc isb_mem failed\n"); 2005 return -ENOMEM; 2006 } 2007 2008 return 0; 2009 } 2010 EXPORT_SYMBOL(wx_setup_isb_resources); 2011 2012 /** 2013 * wx_free_isb_resources - allocate all queues Rx resources 2014 * @wx: board private structure 2015 * 2016 * Return 0 on success, negative on failure 2017 **/ 2018 void wx_free_isb_resources(struct wx *wx) 2019 { 2020 struct pci_dev *pdev = wx->pdev; 2021 2022 dma_free_coherent(&pdev->dev, sizeof(u32) * 4, 2023 wx->isb_mem, wx->isb_dma); 2024 wx->isb_mem = NULL; 2025 } 2026 EXPORT_SYMBOL(wx_free_isb_resources); 2027 2028 u32 wx_misc_isb(struct wx *wx, enum wx_isb_idx idx) 2029 { 2030 u32 cur_tag = 0; 2031 2032 cur_tag = wx->isb_mem[WX_ISB_HEADER]; 2033 wx->isb_tag[idx] = cur_tag; 2034 2035 return (__force u32)cpu_to_le32(wx->isb_mem[idx]); 2036 } 2037 EXPORT_SYMBOL(wx_misc_isb); 2038 2039 /** 2040 * wx_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 2041 * @wx: pointer to wx struct 2042 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 2043 * @queue: queue to map the corresponding interrupt to 2044 * @msix_vector: the vector to map to the corresponding queue 2045 * 2046 **/ 2047 static void wx_set_ivar(struct wx *wx, s8 direction, 2048 u16 queue, u16 msix_vector) 2049 { 2050 u32 ivar, index; 2051 2052 if (direction == -1) { 2053 /* other causes */ 2054 msix_vector |= WX_PX_IVAR_ALLOC_VAL; 2055 index = 0; 2056 ivar = rd32(wx, WX_PX_MISC_IVAR); 2057 ivar &= ~(0xFF << index); 2058 ivar |= (msix_vector << index); 2059 wr32(wx, WX_PX_MISC_IVAR, ivar); 2060 } else { 2061 /* tx or rx causes */ 2062 msix_vector |= WX_PX_IVAR_ALLOC_VAL; 2063 index = ((16 * (queue & 1)) + (8 * direction)); 2064 ivar = rd32(wx, WX_PX_IVAR(queue >> 1)); 2065 ivar &= ~(0xFF << index); 2066 ivar |= (msix_vector << index); 2067 wr32(wx, WX_PX_IVAR(queue >> 1), ivar); 2068 } 2069 } 2070 2071 /** 2072 * wx_write_eitr - write EITR register in hardware specific way 2073 * @q_vector: structure containing interrupt and ring information 2074 * 2075 * This function is made to be called by ethtool and by the driver 2076 * when it needs to update EITR registers at runtime. Hardware 2077 * specific quirks/differences are taken care of here. 2078 */ 2079 static void wx_write_eitr(struct wx_q_vector *q_vector) 2080 { 2081 struct wx *wx = q_vector->wx; 2082 int v_idx = q_vector->v_idx; 2083 u32 itr_reg; 2084 2085 if (wx->mac.type == wx_mac_sp) 2086 itr_reg = q_vector->itr & WX_SP_MAX_EITR; 2087 else 2088 itr_reg = q_vector->itr & WX_EM_MAX_EITR; 2089 2090 itr_reg |= WX_PX_ITR_CNT_WDIS; 2091 2092 wr32(wx, WX_PX_ITR(v_idx), itr_reg); 2093 } 2094 2095 /** 2096 * wx_configure_vectors - Configure vectors for hardware 2097 * @wx: board private structure 2098 * 2099 * wx_configure_vectors sets up the hardware to properly generate MSI-X/MSI/LEGACY 2100 * interrupts. 2101 **/ 2102 void wx_configure_vectors(struct wx *wx) 2103 { 2104 struct pci_dev *pdev = wx->pdev; 2105 u32 eitrsel = 0; 2106 u16 v_idx; 2107 2108 if (pdev->msix_enabled) { 2109 /* Populate MSIX to EITR Select */ 2110 wr32(wx, WX_PX_ITRSEL, eitrsel); 2111 /* use EIAM to auto-mask when MSI-X interrupt is asserted 2112 * this saves a register write for every interrupt 2113 */ 2114 wr32(wx, WX_PX_GPIE, WX_PX_GPIE_MODEL); 2115 } else { 2116 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 2117 * specifically only auto mask tx and rx interrupts. 2118 */ 2119 wr32(wx, WX_PX_GPIE, 0); 2120 } 2121 2122 /* Populate the IVAR table and set the ITR values to the 2123 * corresponding register. 2124 */ 2125 for (v_idx = 0; v_idx < wx->num_q_vectors; v_idx++) { 2126 struct wx_q_vector *q_vector = wx->q_vector[v_idx]; 2127 struct wx_ring *ring; 2128 2129 wx_for_each_ring(ring, q_vector->rx) 2130 wx_set_ivar(wx, 0, ring->reg_idx, v_idx); 2131 2132 wx_for_each_ring(ring, q_vector->tx) 2133 wx_set_ivar(wx, 1, ring->reg_idx, v_idx); 2134 2135 wx_write_eitr(q_vector); 2136 } 2137 2138 wx_set_ivar(wx, -1, 0, v_idx); 2139 if (pdev->msix_enabled) 2140 wr32(wx, WX_PX_ITR(v_idx), 1950); 2141 } 2142 EXPORT_SYMBOL(wx_configure_vectors); 2143 2144 /** 2145 * wx_clean_rx_ring - Free Rx Buffers per Queue 2146 * @rx_ring: ring to free buffers from 2147 **/ 2148 static void wx_clean_rx_ring(struct wx_ring *rx_ring) 2149 { 2150 struct wx_rx_buffer *rx_buffer; 2151 u16 i = rx_ring->next_to_clean; 2152 2153 rx_buffer = &rx_ring->rx_buffer_info[i]; 2154 2155 /* Free all the Rx ring sk_buffs */ 2156 while (i != rx_ring->next_to_alloc) { 2157 if (rx_buffer->skb) { 2158 struct sk_buff *skb = rx_buffer->skb; 2159 2160 if (WX_CB(skb)->page_released) 2161 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false); 2162 2163 dev_kfree_skb(skb); 2164 } 2165 2166 /* Invalidate cache lines that may have been written to by 2167 * device so that we avoid corrupting memory. 2168 */ 2169 dma_sync_single_range_for_cpu(rx_ring->dev, 2170 rx_buffer->dma, 2171 rx_buffer->page_offset, 2172 WX_RX_BUFSZ, 2173 DMA_FROM_DEVICE); 2174 2175 /* free resources associated with mapping */ 2176 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false); 2177 2178 i++; 2179 rx_buffer++; 2180 if (i == rx_ring->count) { 2181 i = 0; 2182 rx_buffer = rx_ring->rx_buffer_info; 2183 } 2184 } 2185 2186 rx_ring->next_to_alloc = 0; 2187 rx_ring->next_to_clean = 0; 2188 rx_ring->next_to_use = 0; 2189 } 2190 2191 /** 2192 * wx_clean_all_rx_rings - Free Rx Buffers for all queues 2193 * @wx: board private structure 2194 **/ 2195 void wx_clean_all_rx_rings(struct wx *wx) 2196 { 2197 int i; 2198 2199 for (i = 0; i < wx->num_rx_queues; i++) 2200 wx_clean_rx_ring(wx->rx_ring[i]); 2201 } 2202 EXPORT_SYMBOL(wx_clean_all_rx_rings); 2203 2204 /** 2205 * wx_free_rx_resources - Free Rx Resources 2206 * @rx_ring: ring to clean the resources from 2207 * 2208 * Free all receive software resources 2209 **/ 2210 static void wx_free_rx_resources(struct wx_ring *rx_ring) 2211 { 2212 wx_clean_rx_ring(rx_ring); 2213 kvfree(rx_ring->rx_buffer_info); 2214 rx_ring->rx_buffer_info = NULL; 2215 2216 /* if not set, then don't free */ 2217 if (!rx_ring->desc) 2218 return; 2219 2220 dma_free_coherent(rx_ring->dev, rx_ring->size, 2221 rx_ring->desc, rx_ring->dma); 2222 2223 rx_ring->desc = NULL; 2224 2225 if (rx_ring->page_pool) { 2226 page_pool_destroy(rx_ring->page_pool); 2227 rx_ring->page_pool = NULL; 2228 } 2229 } 2230 2231 /** 2232 * wx_free_all_rx_resources - Free Rx Resources for All Queues 2233 * @wx: pointer to hardware structure 2234 * 2235 * Free all receive software resources 2236 **/ 2237 static void wx_free_all_rx_resources(struct wx *wx) 2238 { 2239 int i; 2240 2241 for (i = 0; i < wx->num_rx_queues; i++) 2242 wx_free_rx_resources(wx->rx_ring[i]); 2243 } 2244 2245 /** 2246 * wx_clean_tx_ring - Free Tx Buffers 2247 * @tx_ring: ring to be cleaned 2248 **/ 2249 static void wx_clean_tx_ring(struct wx_ring *tx_ring) 2250 { 2251 struct wx_tx_buffer *tx_buffer; 2252 u16 i = tx_ring->next_to_clean; 2253 2254 tx_buffer = &tx_ring->tx_buffer_info[i]; 2255 2256 while (i != tx_ring->next_to_use) { 2257 union wx_tx_desc *eop_desc, *tx_desc; 2258 2259 /* Free all the Tx ring sk_buffs */ 2260 dev_kfree_skb_any(tx_buffer->skb); 2261 2262 /* unmap skb header data */ 2263 dma_unmap_single(tx_ring->dev, 2264 dma_unmap_addr(tx_buffer, dma), 2265 dma_unmap_len(tx_buffer, len), 2266 DMA_TO_DEVICE); 2267 2268 /* check for eop_desc to determine the end of the packet */ 2269 eop_desc = tx_buffer->next_to_watch; 2270 tx_desc = WX_TX_DESC(tx_ring, i); 2271 2272 /* unmap remaining buffers */ 2273 while (tx_desc != eop_desc) { 2274 tx_buffer++; 2275 tx_desc++; 2276 i++; 2277 if (unlikely(i == tx_ring->count)) { 2278 i = 0; 2279 tx_buffer = tx_ring->tx_buffer_info; 2280 tx_desc = WX_TX_DESC(tx_ring, 0); 2281 } 2282 2283 /* unmap any remaining paged data */ 2284 if (dma_unmap_len(tx_buffer, len)) 2285 dma_unmap_page(tx_ring->dev, 2286 dma_unmap_addr(tx_buffer, dma), 2287 dma_unmap_len(tx_buffer, len), 2288 DMA_TO_DEVICE); 2289 } 2290 2291 /* move us one more past the eop_desc for start of next pkt */ 2292 tx_buffer++; 2293 i++; 2294 if (unlikely(i == tx_ring->count)) { 2295 i = 0; 2296 tx_buffer = tx_ring->tx_buffer_info; 2297 } 2298 } 2299 2300 netdev_tx_reset_queue(wx_txring_txq(tx_ring)); 2301 2302 /* reset next_to_use and next_to_clean */ 2303 tx_ring->next_to_use = 0; 2304 tx_ring->next_to_clean = 0; 2305 } 2306 2307 /** 2308 * wx_clean_all_tx_rings - Free Tx Buffers for all queues 2309 * @wx: board private structure 2310 **/ 2311 void wx_clean_all_tx_rings(struct wx *wx) 2312 { 2313 int i; 2314 2315 for (i = 0; i < wx->num_tx_queues; i++) 2316 wx_clean_tx_ring(wx->tx_ring[i]); 2317 } 2318 EXPORT_SYMBOL(wx_clean_all_tx_rings); 2319 2320 /** 2321 * wx_free_tx_resources - Free Tx Resources per Queue 2322 * @tx_ring: Tx descriptor ring for a specific queue 2323 * 2324 * Free all transmit software resources 2325 **/ 2326 static void wx_free_tx_resources(struct wx_ring *tx_ring) 2327 { 2328 wx_clean_tx_ring(tx_ring); 2329 kvfree(tx_ring->tx_buffer_info); 2330 tx_ring->tx_buffer_info = NULL; 2331 2332 /* if not set, then don't free */ 2333 if (!tx_ring->desc) 2334 return; 2335 2336 dma_free_coherent(tx_ring->dev, tx_ring->size, 2337 tx_ring->desc, tx_ring->dma); 2338 tx_ring->desc = NULL; 2339 } 2340 2341 /** 2342 * wx_free_all_tx_resources - Free Tx Resources for All Queues 2343 * @wx: pointer to hardware structure 2344 * 2345 * Free all transmit software resources 2346 **/ 2347 static void wx_free_all_tx_resources(struct wx *wx) 2348 { 2349 int i; 2350 2351 for (i = 0; i < wx->num_tx_queues; i++) 2352 wx_free_tx_resources(wx->tx_ring[i]); 2353 } 2354 2355 void wx_free_resources(struct wx *wx) 2356 { 2357 wx_free_isb_resources(wx); 2358 wx_free_all_rx_resources(wx); 2359 wx_free_all_tx_resources(wx); 2360 } 2361 EXPORT_SYMBOL(wx_free_resources); 2362 2363 static int wx_alloc_page_pool(struct wx_ring *rx_ring) 2364 { 2365 int ret = 0; 2366 2367 struct page_pool_params pp_params = { 2368 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 2369 .order = 0, 2370 .pool_size = rx_ring->size, 2371 .nid = dev_to_node(rx_ring->dev), 2372 .dev = rx_ring->dev, 2373 .dma_dir = DMA_FROM_DEVICE, 2374 .offset = 0, 2375 .max_len = PAGE_SIZE, 2376 }; 2377 2378 rx_ring->page_pool = page_pool_create(&pp_params); 2379 if (IS_ERR(rx_ring->page_pool)) { 2380 ret = PTR_ERR(rx_ring->page_pool); 2381 rx_ring->page_pool = NULL; 2382 } 2383 2384 return ret; 2385 } 2386 2387 /** 2388 * wx_setup_rx_resources - allocate Rx resources (Descriptors) 2389 * @rx_ring: rx descriptor ring (for a specific queue) to setup 2390 * 2391 * Returns 0 on success, negative on failure 2392 **/ 2393 static int wx_setup_rx_resources(struct wx_ring *rx_ring) 2394 { 2395 struct device *dev = rx_ring->dev; 2396 int orig_node = dev_to_node(dev); 2397 int numa_node = NUMA_NO_NODE; 2398 int size, ret; 2399 2400 size = sizeof(struct wx_rx_buffer) * rx_ring->count; 2401 2402 if (rx_ring->q_vector) 2403 numa_node = rx_ring->q_vector->numa_node; 2404 2405 rx_ring->rx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node); 2406 if (!rx_ring->rx_buffer_info) 2407 rx_ring->rx_buffer_info = kvmalloc(size, GFP_KERNEL); 2408 if (!rx_ring->rx_buffer_info) 2409 goto err; 2410 2411 /* Round up to nearest 4K */ 2412 rx_ring->size = rx_ring->count * sizeof(union wx_rx_desc); 2413 rx_ring->size = ALIGN(rx_ring->size, 4096); 2414 2415 set_dev_node(dev, numa_node); 2416 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 2417 &rx_ring->dma, GFP_KERNEL); 2418 if (!rx_ring->desc) { 2419 set_dev_node(dev, orig_node); 2420 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 2421 &rx_ring->dma, GFP_KERNEL); 2422 } 2423 2424 if (!rx_ring->desc) 2425 goto err; 2426 2427 rx_ring->next_to_clean = 0; 2428 rx_ring->next_to_use = 0; 2429 2430 ret = wx_alloc_page_pool(rx_ring); 2431 if (ret < 0) { 2432 dev_err(rx_ring->dev, "Page pool creation failed: %d\n", ret); 2433 goto err_desc; 2434 } 2435 2436 return 0; 2437 2438 err_desc: 2439 dma_free_coherent(dev, rx_ring->size, rx_ring->desc, rx_ring->dma); 2440 err: 2441 kvfree(rx_ring->rx_buffer_info); 2442 rx_ring->rx_buffer_info = NULL; 2443 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 2444 return -ENOMEM; 2445 } 2446 2447 /** 2448 * wx_setup_all_rx_resources - allocate all queues Rx resources 2449 * @wx: pointer to hardware structure 2450 * 2451 * If this function returns with an error, then it's possible one or 2452 * more of the rings is populated (while the rest are not). It is the 2453 * callers duty to clean those orphaned rings. 2454 * 2455 * Return 0 on success, negative on failure 2456 **/ 2457 static int wx_setup_all_rx_resources(struct wx *wx) 2458 { 2459 int i, err = 0; 2460 2461 for (i = 0; i < wx->num_rx_queues; i++) { 2462 err = wx_setup_rx_resources(wx->rx_ring[i]); 2463 if (!err) 2464 continue; 2465 2466 wx_err(wx, "Allocation for Rx Queue %u failed\n", i); 2467 goto err_setup_rx; 2468 } 2469 2470 return 0; 2471 err_setup_rx: 2472 /* rewind the index freeing the rings as we go */ 2473 while (i--) 2474 wx_free_rx_resources(wx->rx_ring[i]); 2475 return err; 2476 } 2477 2478 /** 2479 * wx_setup_tx_resources - allocate Tx resources (Descriptors) 2480 * @tx_ring: tx descriptor ring (for a specific queue) to setup 2481 * 2482 * Return 0 on success, negative on failure 2483 **/ 2484 static int wx_setup_tx_resources(struct wx_ring *tx_ring) 2485 { 2486 struct device *dev = tx_ring->dev; 2487 int orig_node = dev_to_node(dev); 2488 int numa_node = NUMA_NO_NODE; 2489 int size; 2490 2491 size = sizeof(struct wx_tx_buffer) * tx_ring->count; 2492 2493 if (tx_ring->q_vector) 2494 numa_node = tx_ring->q_vector->numa_node; 2495 2496 tx_ring->tx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node); 2497 if (!tx_ring->tx_buffer_info) 2498 tx_ring->tx_buffer_info = kvmalloc(size, GFP_KERNEL); 2499 if (!tx_ring->tx_buffer_info) 2500 goto err; 2501 2502 /* round up to nearest 4K */ 2503 tx_ring->size = tx_ring->count * sizeof(union wx_tx_desc); 2504 tx_ring->size = ALIGN(tx_ring->size, 4096); 2505 2506 set_dev_node(dev, numa_node); 2507 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 2508 &tx_ring->dma, GFP_KERNEL); 2509 if (!tx_ring->desc) { 2510 set_dev_node(dev, orig_node); 2511 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 2512 &tx_ring->dma, GFP_KERNEL); 2513 } 2514 2515 if (!tx_ring->desc) 2516 goto err; 2517 2518 tx_ring->next_to_use = 0; 2519 tx_ring->next_to_clean = 0; 2520 2521 return 0; 2522 2523 err: 2524 kvfree(tx_ring->tx_buffer_info); 2525 tx_ring->tx_buffer_info = NULL; 2526 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 2527 return -ENOMEM; 2528 } 2529 2530 /** 2531 * wx_setup_all_tx_resources - allocate all queues Tx resources 2532 * @wx: pointer to private structure 2533 * 2534 * If this function returns with an error, then it's possible one or 2535 * more of the rings is populated (while the rest are not). It is the 2536 * callers duty to clean those orphaned rings. 2537 * 2538 * Return 0 on success, negative on failure 2539 **/ 2540 static int wx_setup_all_tx_resources(struct wx *wx) 2541 { 2542 int i, err = 0; 2543 2544 for (i = 0; i < wx->num_tx_queues; i++) { 2545 err = wx_setup_tx_resources(wx->tx_ring[i]); 2546 if (!err) 2547 continue; 2548 2549 wx_err(wx, "Allocation for Tx Queue %u failed\n", i); 2550 goto err_setup_tx; 2551 } 2552 2553 return 0; 2554 err_setup_tx: 2555 /* rewind the index freeing the rings as we go */ 2556 while (i--) 2557 wx_free_tx_resources(wx->tx_ring[i]); 2558 return err; 2559 } 2560 2561 int wx_setup_resources(struct wx *wx) 2562 { 2563 int err; 2564 2565 /* allocate transmit descriptors */ 2566 err = wx_setup_all_tx_resources(wx); 2567 if (err) 2568 return err; 2569 2570 /* allocate receive descriptors */ 2571 err = wx_setup_all_rx_resources(wx); 2572 if (err) 2573 goto err_free_tx; 2574 2575 err = wx_setup_isb_resources(wx); 2576 if (err) 2577 goto err_free_rx; 2578 2579 return 0; 2580 2581 err_free_rx: 2582 wx_free_all_rx_resources(wx); 2583 err_free_tx: 2584 wx_free_all_tx_resources(wx); 2585 2586 return err; 2587 } 2588 EXPORT_SYMBOL(wx_setup_resources); 2589 2590 /** 2591 * wx_get_stats64 - Get System Network Statistics 2592 * @netdev: network interface device structure 2593 * @stats: storage space for 64bit statistics 2594 */ 2595 void wx_get_stats64(struct net_device *netdev, 2596 struct rtnl_link_stats64 *stats) 2597 { 2598 struct wx *wx = netdev_priv(netdev); 2599 int i; 2600 2601 rcu_read_lock(); 2602 for (i = 0; i < wx->num_rx_queues; i++) { 2603 struct wx_ring *ring = READ_ONCE(wx->rx_ring[i]); 2604 u64 bytes, packets; 2605 unsigned int start; 2606 2607 if (ring) { 2608 do { 2609 start = u64_stats_fetch_begin(&ring->syncp); 2610 packets = ring->stats.packets; 2611 bytes = ring->stats.bytes; 2612 } while (u64_stats_fetch_retry(&ring->syncp, start)); 2613 stats->rx_packets += packets; 2614 stats->rx_bytes += bytes; 2615 } 2616 } 2617 2618 for (i = 0; i < wx->num_tx_queues; i++) { 2619 struct wx_ring *ring = READ_ONCE(wx->tx_ring[i]); 2620 u64 bytes, packets; 2621 unsigned int start; 2622 2623 if (ring) { 2624 do { 2625 start = u64_stats_fetch_begin(&ring->syncp); 2626 packets = ring->stats.packets; 2627 bytes = ring->stats.bytes; 2628 } while (u64_stats_fetch_retry(&ring->syncp, 2629 start)); 2630 stats->tx_packets += packets; 2631 stats->tx_bytes += bytes; 2632 } 2633 } 2634 2635 rcu_read_unlock(); 2636 } 2637 EXPORT_SYMBOL(wx_get_stats64); 2638 2639 int wx_set_features(struct net_device *netdev, netdev_features_t features) 2640 { 2641 netdev_features_t changed = netdev->features ^ features; 2642 struct wx *wx = netdev_priv(netdev); 2643 2644 if (changed & NETIF_F_RXHASH) 2645 wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN, 2646 WX_RDB_RA_CTL_RSS_EN); 2647 else 2648 wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN, 0); 2649 2650 netdev->features = features; 2651 2652 if (changed & 2653 (NETIF_F_HW_VLAN_CTAG_RX | 2654 NETIF_F_HW_VLAN_STAG_RX)) 2655 wx_set_rx_mode(netdev); 2656 2657 return 0; 2658 } 2659 EXPORT_SYMBOL(wx_set_features); 2660 2661 MODULE_LICENSE("GPL"); 2662