1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/netdevice.h> 6 #include <linux/if_ether.h> 7 #include <linux/iopoll.h> 8 #include <linux/pci.h> 9 10 #include "wx_type.h" 11 #include "wx_lib.h" 12 #include "wx_hw.h" 13 14 static void wx_intr_disable(struct wx *wx, u64 qmask) 15 { 16 u32 mask; 17 18 mask = (qmask & U32_MAX); 19 if (mask) 20 wr32(wx, WX_PX_IMS(0), mask); 21 22 if (wx->mac.type == wx_mac_sp) { 23 mask = (qmask >> 32); 24 if (mask) 25 wr32(wx, WX_PX_IMS(1), mask); 26 } 27 } 28 29 void wx_intr_enable(struct wx *wx, u64 qmask) 30 { 31 u32 mask; 32 33 mask = (qmask & U32_MAX); 34 if (mask) 35 wr32(wx, WX_PX_IMC(0), mask); 36 if (wx->mac.type == wx_mac_sp) { 37 mask = (qmask >> 32); 38 if (mask) 39 wr32(wx, WX_PX_IMC(1), mask); 40 } 41 } 42 EXPORT_SYMBOL(wx_intr_enable); 43 44 /** 45 * wx_irq_disable - Mask off interrupt generation on the NIC 46 * @wx: board private structure 47 **/ 48 void wx_irq_disable(struct wx *wx) 49 { 50 struct pci_dev *pdev = wx->pdev; 51 52 wr32(wx, WX_PX_MISC_IEN, 0); 53 wx_intr_disable(wx, WX_INTR_ALL); 54 55 if (pdev->msix_enabled) { 56 int vector; 57 58 for (vector = 0; vector < wx->num_q_vectors; vector++) 59 synchronize_irq(wx->msix_entries[vector].vector); 60 61 synchronize_irq(wx->msix_entries[vector].vector); 62 } else { 63 synchronize_irq(pdev->irq); 64 } 65 } 66 EXPORT_SYMBOL(wx_irq_disable); 67 68 /* cmd_addr is used for some special command: 69 * 1. to be sector address, when implemented erase sector command 70 * 2. to be flash address when implemented read, write flash address 71 */ 72 static int wx_fmgr_cmd_op(struct wx *wx, u32 cmd, u32 cmd_addr) 73 { 74 u32 cmd_val = 0, val = 0; 75 76 cmd_val = WX_SPI_CMD_CMD(cmd) | 77 WX_SPI_CMD_CLK(WX_SPI_CLK_DIV) | 78 cmd_addr; 79 wr32(wx, WX_SPI_CMD, cmd_val); 80 81 return read_poll_timeout(rd32, val, (val & 0x1), 10, 100000, 82 false, wx, WX_SPI_STATUS); 83 } 84 85 static int wx_flash_read_dword(struct wx *wx, u32 addr, u32 *data) 86 { 87 int ret = 0; 88 89 ret = wx_fmgr_cmd_op(wx, WX_SPI_CMD_READ_DWORD, addr); 90 if (ret < 0) 91 return ret; 92 93 *data = rd32(wx, WX_SPI_DATA); 94 95 return ret; 96 } 97 98 int wx_check_flash_load(struct wx *hw, u32 check_bit) 99 { 100 u32 reg = 0; 101 int err = 0; 102 103 /* if there's flash existing */ 104 if (!(rd32(hw, WX_SPI_STATUS) & 105 WX_SPI_STATUS_FLASH_BYPASS)) { 106 /* wait hw load flash done */ 107 err = read_poll_timeout(rd32, reg, !(reg & check_bit), 20000, 2000000, 108 false, hw, WX_SPI_ILDR_STATUS); 109 if (err < 0) 110 wx_err(hw, "Check flash load timeout.\n"); 111 } 112 113 return err; 114 } 115 EXPORT_SYMBOL(wx_check_flash_load); 116 117 void wx_control_hw(struct wx *wx, bool drv) 118 { 119 /* True : Let firmware know the driver has taken over 120 * False : Let firmware take over control of hw 121 */ 122 wr32m(wx, WX_CFG_PORT_CTL, WX_CFG_PORT_CTL_DRV_LOAD, 123 drv ? WX_CFG_PORT_CTL_DRV_LOAD : 0); 124 } 125 EXPORT_SYMBOL(wx_control_hw); 126 127 /** 128 * wx_mng_present - returns 0 when management capability is present 129 * @wx: pointer to hardware structure 130 */ 131 int wx_mng_present(struct wx *wx) 132 { 133 u32 fwsm; 134 135 fwsm = rd32(wx, WX_MIS_ST); 136 if (fwsm & WX_MIS_ST_MNG_INIT_DN) 137 return 0; 138 else 139 return -EACCES; 140 } 141 EXPORT_SYMBOL(wx_mng_present); 142 143 /* Software lock to be held while software semaphore is being accessed. */ 144 static DEFINE_MUTEX(wx_sw_sync_lock); 145 146 /** 147 * wx_release_sw_sync - Release SW semaphore 148 * @wx: pointer to hardware structure 149 * @mask: Mask to specify which semaphore to release 150 * 151 * Releases the SW semaphore for the specified 152 * function (CSR, PHY0, PHY1, EEPROM, Flash) 153 **/ 154 static void wx_release_sw_sync(struct wx *wx, u32 mask) 155 { 156 mutex_lock(&wx_sw_sync_lock); 157 wr32m(wx, WX_MNG_SWFW_SYNC, mask, 0); 158 mutex_unlock(&wx_sw_sync_lock); 159 } 160 161 /** 162 * wx_acquire_sw_sync - Acquire SW semaphore 163 * @wx: pointer to hardware structure 164 * @mask: Mask to specify which semaphore to acquire 165 * 166 * Acquires the SW semaphore for the specified 167 * function (CSR, PHY0, PHY1, EEPROM, Flash) 168 **/ 169 static int wx_acquire_sw_sync(struct wx *wx, u32 mask) 170 { 171 u32 sem = 0; 172 int ret = 0; 173 174 mutex_lock(&wx_sw_sync_lock); 175 ret = read_poll_timeout(rd32, sem, !(sem & mask), 176 5000, 2000000, false, wx, WX_MNG_SWFW_SYNC); 177 if (!ret) { 178 sem |= mask; 179 wr32(wx, WX_MNG_SWFW_SYNC, sem); 180 } else { 181 wx_err(wx, "SW Semaphore not granted: 0x%x.\n", sem); 182 } 183 mutex_unlock(&wx_sw_sync_lock); 184 185 return ret; 186 } 187 188 /** 189 * wx_host_interface_command - Issue command to manageability block 190 * @wx: pointer to the HW structure 191 * @buffer: contains the command to write and where the return status will 192 * be placed 193 * @length: length of buffer, must be multiple of 4 bytes 194 * @timeout: time in ms to wait for command completion 195 * @return_data: read and return data from the buffer (true) or not (false) 196 * Needed because FW structures are big endian and decoding of 197 * these fields can be 8 bit or 16 bit based on command. Decoding 198 * is not easily understood without making a table of commands. 199 * So we will leave this up to the caller to read back the data 200 * in these cases. 201 **/ 202 int wx_host_interface_command(struct wx *wx, u32 *buffer, 203 u32 length, u32 timeout, bool return_data) 204 { 205 u32 hdr_size = sizeof(struct wx_hic_hdr); 206 u32 hicr, i, bi, buf[64] = {}; 207 int status = 0; 208 u32 dword_len; 209 u16 buf_len; 210 211 if (length == 0 || length > WX_HI_MAX_BLOCK_BYTE_LENGTH) { 212 wx_err(wx, "Buffer length failure buffersize=%d.\n", length); 213 return -EINVAL; 214 } 215 216 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_MB); 217 if (status != 0) 218 return status; 219 220 /* Calculate length in DWORDs. We must be DWORD aligned */ 221 if ((length % (sizeof(u32))) != 0) { 222 wx_err(wx, "Buffer length failure, not aligned to dword"); 223 status = -EINVAL; 224 goto rel_out; 225 } 226 227 dword_len = length >> 2; 228 229 /* The device driver writes the relevant command block 230 * into the ram area. 231 */ 232 for (i = 0; i < dword_len; i++) { 233 wr32a(wx, WX_MNG_MBOX, i, (__force u32)cpu_to_le32(buffer[i])); 234 /* write flush */ 235 buf[i] = rd32a(wx, WX_MNG_MBOX, i); 236 } 237 /* Setting this bit tells the ARC that a new command is pending. */ 238 wr32m(wx, WX_MNG_MBOX_CTL, 239 WX_MNG_MBOX_CTL_SWRDY, WX_MNG_MBOX_CTL_SWRDY); 240 241 status = read_poll_timeout(rd32, hicr, hicr & WX_MNG_MBOX_CTL_FWRDY, 1000, 242 timeout * 1000, false, wx, WX_MNG_MBOX_CTL); 243 244 /* Check command completion */ 245 if (status) { 246 wx_dbg(wx, "Command has failed with no status valid.\n"); 247 248 buf[0] = rd32(wx, WX_MNG_MBOX); 249 if ((buffer[0] & 0xff) != (~buf[0] >> 24)) { 250 status = -EINVAL; 251 goto rel_out; 252 } 253 if ((buf[0] & 0xff0000) >> 16 == 0x80) { 254 wx_dbg(wx, "It's unknown cmd.\n"); 255 status = -EINVAL; 256 goto rel_out; 257 } 258 259 wx_dbg(wx, "write value:\n"); 260 for (i = 0; i < dword_len; i++) 261 wx_dbg(wx, "%x ", buffer[i]); 262 wx_dbg(wx, "read value:\n"); 263 for (i = 0; i < dword_len; i++) 264 wx_dbg(wx, "%x ", buf[i]); 265 } 266 267 if (!return_data) 268 goto rel_out; 269 270 /* Calculate length in DWORDs */ 271 dword_len = hdr_size >> 2; 272 273 /* first pull in the header so we know the buffer length */ 274 for (bi = 0; bi < dword_len; bi++) { 275 buffer[bi] = rd32a(wx, WX_MNG_MBOX, bi); 276 le32_to_cpus(&buffer[bi]); 277 } 278 279 /* If there is any thing in data position pull it in */ 280 buf_len = ((struct wx_hic_hdr *)buffer)->buf_len; 281 if (buf_len == 0) 282 goto rel_out; 283 284 if (length < buf_len + hdr_size) { 285 wx_err(wx, "Buffer not large enough for reply message.\n"); 286 status = -EFAULT; 287 goto rel_out; 288 } 289 290 /* Calculate length in DWORDs, add 3 for odd lengths */ 291 dword_len = (buf_len + 3) >> 2; 292 293 /* Pull in the rest of the buffer (bi is where we left off) */ 294 for (; bi <= dword_len; bi++) { 295 buffer[bi] = rd32a(wx, WX_MNG_MBOX, bi); 296 le32_to_cpus(&buffer[bi]); 297 } 298 299 rel_out: 300 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_MB); 301 return status; 302 } 303 EXPORT_SYMBOL(wx_host_interface_command); 304 305 /** 306 * wx_read_ee_hostif_data - Read EEPROM word using a host interface cmd 307 * assuming that the semaphore is already obtained. 308 * @wx: pointer to hardware structure 309 * @offset: offset of word in the EEPROM to read 310 * @data: word read from the EEPROM 311 * 312 * Reads a 16 bit word from the EEPROM using the hostif. 313 **/ 314 static int wx_read_ee_hostif_data(struct wx *wx, u16 offset, u16 *data) 315 { 316 struct wx_hic_read_shadow_ram buffer; 317 int status; 318 319 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 320 buffer.hdr.req.buf_lenh = 0; 321 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 322 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 323 324 /* convert offset from words to bytes */ 325 buffer.address = (__force u32)cpu_to_be32(offset * 2); 326 /* one word */ 327 buffer.length = (__force u16)cpu_to_be16(sizeof(u16)); 328 329 status = wx_host_interface_command(wx, (u32 *)&buffer, sizeof(buffer), 330 WX_HI_COMMAND_TIMEOUT, false); 331 332 if (status != 0) 333 return status; 334 335 *data = (u16)rd32a(wx, WX_MNG_MBOX, FW_NVM_DATA_OFFSET); 336 337 return status; 338 } 339 340 /** 341 * wx_read_ee_hostif - Read EEPROM word using a host interface cmd 342 * @wx: pointer to hardware structure 343 * @offset: offset of word in the EEPROM to read 344 * @data: word read from the EEPROM 345 * 346 * Reads a 16 bit word from the EEPROM using the hostif. 347 **/ 348 int wx_read_ee_hostif(struct wx *wx, u16 offset, u16 *data) 349 { 350 int status = 0; 351 352 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 353 if (status == 0) { 354 status = wx_read_ee_hostif_data(wx, offset, data); 355 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 356 } 357 358 return status; 359 } 360 EXPORT_SYMBOL(wx_read_ee_hostif); 361 362 /** 363 * wx_read_ee_hostif_buffer- Read EEPROM word(s) using hostif 364 * @wx: pointer to hardware structure 365 * @offset: offset of word in the EEPROM to read 366 * @words: number of words 367 * @data: word(s) read from the EEPROM 368 * 369 * Reads a 16 bit word(s) from the EEPROM using the hostif. 370 **/ 371 int wx_read_ee_hostif_buffer(struct wx *wx, 372 u16 offset, u16 words, u16 *data) 373 { 374 struct wx_hic_read_shadow_ram buffer; 375 u32 current_word = 0; 376 u16 words_to_read; 377 u32 value = 0; 378 int status; 379 u32 i; 380 381 /* Take semaphore for the entire operation. */ 382 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 383 if (status != 0) 384 return status; 385 386 while (words) { 387 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 388 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 389 else 390 words_to_read = words; 391 392 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 393 buffer.hdr.req.buf_lenh = 0; 394 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 395 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 396 397 /* convert offset from words to bytes */ 398 buffer.address = (__force u32)cpu_to_be32((offset + current_word) * 2); 399 buffer.length = (__force u16)cpu_to_be16(words_to_read * 2); 400 401 status = wx_host_interface_command(wx, (u32 *)&buffer, 402 sizeof(buffer), 403 WX_HI_COMMAND_TIMEOUT, 404 false); 405 406 if (status != 0) { 407 wx_err(wx, "Host interface command failed\n"); 408 goto out; 409 } 410 411 for (i = 0; i < words_to_read; i++) { 412 u32 reg = WX_MNG_MBOX + (FW_NVM_DATA_OFFSET << 2) + 2 * i; 413 414 value = rd32(wx, reg); 415 data[current_word] = (u16)(value & 0xffff); 416 current_word++; 417 i++; 418 if (i < words_to_read) { 419 value >>= 16; 420 data[current_word] = (u16)(value & 0xffff); 421 current_word++; 422 } 423 } 424 words -= words_to_read; 425 } 426 427 out: 428 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 429 return status; 430 } 431 EXPORT_SYMBOL(wx_read_ee_hostif_buffer); 432 433 /** 434 * wx_calculate_checksum - Calculate checksum for buffer 435 * @buffer: pointer to EEPROM 436 * @length: size of EEPROM to calculate a checksum for 437 * Calculates the checksum for some buffer on a specified length. The 438 * checksum calculated is returned. 439 **/ 440 static u8 wx_calculate_checksum(u8 *buffer, u32 length) 441 { 442 u8 sum = 0; 443 u32 i; 444 445 if (!buffer) 446 return 0; 447 448 for (i = 0; i < length; i++) 449 sum += buffer[i]; 450 451 return (u8)(0 - sum); 452 } 453 454 /** 455 * wx_reset_hostif - send reset cmd to fw 456 * @wx: pointer to hardware structure 457 * 458 * Sends reset cmd to firmware through the manageability 459 * block. 460 **/ 461 int wx_reset_hostif(struct wx *wx) 462 { 463 struct wx_hic_reset reset_cmd; 464 int ret_val = 0; 465 int i; 466 467 reset_cmd.hdr.cmd = FW_RESET_CMD; 468 reset_cmd.hdr.buf_len = FW_RESET_LEN; 469 reset_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 470 reset_cmd.lan_id = wx->bus.func; 471 reset_cmd.reset_type = (u16)wx->reset_type; 472 reset_cmd.hdr.checksum = 0; 473 reset_cmd.hdr.checksum = wx_calculate_checksum((u8 *)&reset_cmd, 474 (FW_CEM_HDR_LEN + 475 reset_cmd.hdr.buf_len)); 476 477 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 478 ret_val = wx_host_interface_command(wx, (u32 *)&reset_cmd, 479 sizeof(reset_cmd), 480 WX_HI_COMMAND_TIMEOUT, 481 true); 482 if (ret_val != 0) 483 continue; 484 485 if (reset_cmd.hdr.cmd_or_resp.ret_status == 486 FW_CEM_RESP_STATUS_SUCCESS) 487 ret_val = 0; 488 else 489 ret_val = -EFAULT; 490 491 break; 492 } 493 494 return ret_val; 495 } 496 EXPORT_SYMBOL(wx_reset_hostif); 497 498 /** 499 * wx_init_eeprom_params - Initialize EEPROM params 500 * @wx: pointer to hardware structure 501 * 502 * Initializes the EEPROM parameters wx_eeprom_info within the 503 * wx_hw struct in order to set up EEPROM access. 504 **/ 505 void wx_init_eeprom_params(struct wx *wx) 506 { 507 struct wx_eeprom_info *eeprom = &wx->eeprom; 508 u16 eeprom_size; 509 u16 data = 0x80; 510 511 if (eeprom->type == wx_eeprom_uninitialized) { 512 eeprom->semaphore_delay = 10; 513 eeprom->type = wx_eeprom_none; 514 515 if (!(rd32(wx, WX_SPI_STATUS) & 516 WX_SPI_STATUS_FLASH_BYPASS)) { 517 eeprom->type = wx_flash; 518 519 eeprom_size = 4096; 520 eeprom->word_size = eeprom_size >> 1; 521 522 wx_dbg(wx, "Eeprom params: type = %d, size = %d\n", 523 eeprom->type, eeprom->word_size); 524 } 525 } 526 527 if (wx->mac.type == wx_mac_sp) { 528 if (wx_read_ee_hostif(wx, WX_SW_REGION_PTR, &data)) { 529 wx_err(wx, "NVM Read Error\n"); 530 return; 531 } 532 data = data >> 1; 533 } 534 535 eeprom->sw_region_offset = data; 536 } 537 EXPORT_SYMBOL(wx_init_eeprom_params); 538 539 /** 540 * wx_get_mac_addr - Generic get MAC address 541 * @wx: pointer to hardware structure 542 * @mac_addr: Adapter MAC address 543 * 544 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 545 * A reset of the adapter must be performed prior to calling this function 546 * in order for the MAC address to have been loaded from the EEPROM into RAR0 547 **/ 548 void wx_get_mac_addr(struct wx *wx, u8 *mac_addr) 549 { 550 u32 rar_high; 551 u32 rar_low; 552 u16 i; 553 554 wr32(wx, WX_PSR_MAC_SWC_IDX, 0); 555 rar_high = rd32(wx, WX_PSR_MAC_SWC_AD_H); 556 rar_low = rd32(wx, WX_PSR_MAC_SWC_AD_L); 557 558 for (i = 0; i < 2; i++) 559 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8); 560 561 for (i = 0; i < 4; i++) 562 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8); 563 } 564 EXPORT_SYMBOL(wx_get_mac_addr); 565 566 /** 567 * wx_set_rar - Set Rx address register 568 * @wx: pointer to hardware structure 569 * @index: Receive address register to write 570 * @addr: Address to put into receive address register 571 * @pools: VMDq "set" or "pool" index 572 * @enable_addr: set flag that address is active 573 * 574 * Puts an ethernet address into a receive address register. 575 **/ 576 static int wx_set_rar(struct wx *wx, u32 index, u8 *addr, u64 pools, 577 u32 enable_addr) 578 { 579 u32 rar_entries = wx->mac.num_rar_entries; 580 u32 rar_low, rar_high; 581 582 /* Make sure we are using a valid rar index range */ 583 if (index >= rar_entries) { 584 wx_err(wx, "RAR index %d is out of range.\n", index); 585 return -EINVAL; 586 } 587 588 /* select the MAC address */ 589 wr32(wx, WX_PSR_MAC_SWC_IDX, index); 590 591 /* setup VMDq pool mapping */ 592 wr32(wx, WX_PSR_MAC_SWC_VM_L, pools & 0xFFFFFFFF); 593 if (wx->mac.type == wx_mac_sp) 594 wr32(wx, WX_PSR_MAC_SWC_VM_H, pools >> 32); 595 596 /* HW expects these in little endian so we reverse the byte 597 * order from network order (big endian) to little endian 598 * 599 * Some parts put the VMDq setting in the extra RAH bits, 600 * so save everything except the lower 16 bits that hold part 601 * of the address and the address valid bit. 602 */ 603 rar_low = ((u32)addr[5] | 604 ((u32)addr[4] << 8) | 605 ((u32)addr[3] << 16) | 606 ((u32)addr[2] << 24)); 607 rar_high = ((u32)addr[1] | 608 ((u32)addr[0] << 8)); 609 if (enable_addr != 0) 610 rar_high |= WX_PSR_MAC_SWC_AD_H_AV; 611 612 wr32(wx, WX_PSR_MAC_SWC_AD_L, rar_low); 613 wr32m(wx, WX_PSR_MAC_SWC_AD_H, 614 (WX_PSR_MAC_SWC_AD_H_AD(U16_MAX) | 615 WX_PSR_MAC_SWC_AD_H_ADTYPE(1) | 616 WX_PSR_MAC_SWC_AD_H_AV), 617 rar_high); 618 619 return 0; 620 } 621 622 /** 623 * wx_clear_rar - Remove Rx address register 624 * @wx: pointer to hardware structure 625 * @index: Receive address register to write 626 * 627 * Clears an ethernet address from a receive address register. 628 **/ 629 static int wx_clear_rar(struct wx *wx, u32 index) 630 { 631 u32 rar_entries = wx->mac.num_rar_entries; 632 633 /* Make sure we are using a valid rar index range */ 634 if (index >= rar_entries) { 635 wx_err(wx, "RAR index %d is out of range.\n", index); 636 return -EINVAL; 637 } 638 639 /* Some parts put the VMDq setting in the extra RAH bits, 640 * so save everything except the lower 16 bits that hold part 641 * of the address and the address valid bit. 642 */ 643 wr32(wx, WX_PSR_MAC_SWC_IDX, index); 644 645 wr32(wx, WX_PSR_MAC_SWC_VM_L, 0); 646 wr32(wx, WX_PSR_MAC_SWC_VM_H, 0); 647 648 wr32(wx, WX_PSR_MAC_SWC_AD_L, 0); 649 wr32m(wx, WX_PSR_MAC_SWC_AD_H, 650 (WX_PSR_MAC_SWC_AD_H_AD(U16_MAX) | 651 WX_PSR_MAC_SWC_AD_H_ADTYPE(1) | 652 WX_PSR_MAC_SWC_AD_H_AV), 653 0); 654 655 return 0; 656 } 657 658 /** 659 * wx_clear_vmdq - Disassociate a VMDq pool index from a rx address 660 * @wx: pointer to hardware struct 661 * @rar: receive address register index to disassociate 662 * @vmdq: VMDq pool index to remove from the rar 663 **/ 664 static int wx_clear_vmdq(struct wx *wx, u32 rar, u32 __maybe_unused vmdq) 665 { 666 u32 rar_entries = wx->mac.num_rar_entries; 667 u32 mpsar_lo, mpsar_hi; 668 669 /* Make sure we are using a valid rar index range */ 670 if (rar >= rar_entries) { 671 wx_err(wx, "RAR index %d is out of range.\n", rar); 672 return -EINVAL; 673 } 674 675 wr32(wx, WX_PSR_MAC_SWC_IDX, rar); 676 mpsar_lo = rd32(wx, WX_PSR_MAC_SWC_VM_L); 677 mpsar_hi = rd32(wx, WX_PSR_MAC_SWC_VM_H); 678 679 if (!mpsar_lo && !mpsar_hi) 680 return 0; 681 682 /* was that the last pool using this rar? */ 683 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) 684 wx_clear_rar(wx, rar); 685 686 return 0; 687 } 688 689 /** 690 * wx_init_uta_tables - Initialize the Unicast Table Array 691 * @wx: pointer to hardware structure 692 **/ 693 static void wx_init_uta_tables(struct wx *wx) 694 { 695 int i; 696 697 wx_dbg(wx, " Clearing UTA\n"); 698 699 for (i = 0; i < 128; i++) 700 wr32(wx, WX_PSR_UC_TBL(i), 0); 701 } 702 703 /** 704 * wx_init_rx_addrs - Initializes receive address filters. 705 * @wx: pointer to hardware structure 706 * 707 * Places the MAC address in receive address register 0 and clears the rest 708 * of the receive address registers. Clears the multicast table. Assumes 709 * the receiver is in reset when the routine is called. 710 **/ 711 void wx_init_rx_addrs(struct wx *wx) 712 { 713 u32 rar_entries = wx->mac.num_rar_entries; 714 u32 psrctl; 715 int i; 716 717 /* If the current mac address is valid, assume it is a software override 718 * to the permanent address. 719 * Otherwise, use the permanent address from the eeprom. 720 */ 721 if (!is_valid_ether_addr(wx->mac.addr)) { 722 /* Get the MAC address from the RAR0 for later reference */ 723 wx_get_mac_addr(wx, wx->mac.addr); 724 wx_dbg(wx, "Keeping Current RAR0 Addr = %pM\n", wx->mac.addr); 725 } else { 726 /* Setup the receive address. */ 727 wx_dbg(wx, "Overriding MAC Address in RAR[0]\n"); 728 wx_dbg(wx, "New MAC Addr = %pM\n", wx->mac.addr); 729 730 wx_set_rar(wx, 0, wx->mac.addr, 0, WX_PSR_MAC_SWC_AD_H_AV); 731 732 if (wx->mac.type == wx_mac_sp) { 733 /* clear VMDq pool/queue selection for RAR 0 */ 734 wx_clear_vmdq(wx, 0, WX_CLEAR_VMDQ_ALL); 735 } 736 } 737 738 /* Zero out the other receive addresses. */ 739 wx_dbg(wx, "Clearing RAR[1-%d]\n", rar_entries - 1); 740 for (i = 1; i < rar_entries; i++) { 741 wr32(wx, WX_PSR_MAC_SWC_IDX, i); 742 wr32(wx, WX_PSR_MAC_SWC_AD_L, 0); 743 wr32(wx, WX_PSR_MAC_SWC_AD_H, 0); 744 } 745 746 /* Clear the MTA */ 747 wx->addr_ctrl.mta_in_use = 0; 748 psrctl = rd32(wx, WX_PSR_CTL); 749 psrctl &= ~(WX_PSR_CTL_MO | WX_PSR_CTL_MFE); 750 psrctl |= wx->mac.mc_filter_type << WX_PSR_CTL_MO_SHIFT; 751 wr32(wx, WX_PSR_CTL, psrctl); 752 wx_dbg(wx, " Clearing MTA\n"); 753 for (i = 0; i < wx->mac.mcft_size; i++) 754 wr32(wx, WX_PSR_MC_TBL(i), 0); 755 756 wx_init_uta_tables(wx); 757 } 758 EXPORT_SYMBOL(wx_init_rx_addrs); 759 760 static void wx_sync_mac_table(struct wx *wx) 761 { 762 int i; 763 764 for (i = 0; i < wx->mac.num_rar_entries; i++) { 765 if (wx->mac_table[i].state & WX_MAC_STATE_MODIFIED) { 766 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) { 767 wx_set_rar(wx, i, 768 wx->mac_table[i].addr, 769 wx->mac_table[i].pools, 770 WX_PSR_MAC_SWC_AD_H_AV); 771 } else { 772 wx_clear_rar(wx, i); 773 } 774 wx->mac_table[i].state &= ~(WX_MAC_STATE_MODIFIED); 775 } 776 } 777 } 778 779 /* this function destroys the first RAR entry */ 780 void wx_mac_set_default_filter(struct wx *wx, u8 *addr) 781 { 782 memcpy(&wx->mac_table[0].addr, addr, ETH_ALEN); 783 wx->mac_table[0].pools = 1ULL; 784 wx->mac_table[0].state = (WX_MAC_STATE_DEFAULT | WX_MAC_STATE_IN_USE); 785 wx_set_rar(wx, 0, wx->mac_table[0].addr, 786 wx->mac_table[0].pools, 787 WX_PSR_MAC_SWC_AD_H_AV); 788 } 789 EXPORT_SYMBOL(wx_mac_set_default_filter); 790 791 void wx_flush_sw_mac_table(struct wx *wx) 792 { 793 u32 i; 794 795 for (i = 0; i < wx->mac.num_rar_entries; i++) { 796 if (!(wx->mac_table[i].state & WX_MAC_STATE_IN_USE)) 797 continue; 798 799 wx->mac_table[i].state |= WX_MAC_STATE_MODIFIED; 800 wx->mac_table[i].state &= ~WX_MAC_STATE_IN_USE; 801 memset(wx->mac_table[i].addr, 0, ETH_ALEN); 802 wx->mac_table[i].pools = 0; 803 } 804 wx_sync_mac_table(wx); 805 } 806 EXPORT_SYMBOL(wx_flush_sw_mac_table); 807 808 static int wx_add_mac_filter(struct wx *wx, u8 *addr, u16 pool) 809 { 810 u32 i; 811 812 if (is_zero_ether_addr(addr)) 813 return -EINVAL; 814 815 for (i = 0; i < wx->mac.num_rar_entries; i++) { 816 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) { 817 if (ether_addr_equal(addr, wx->mac_table[i].addr)) { 818 if (wx->mac_table[i].pools != (1ULL << pool)) { 819 memcpy(wx->mac_table[i].addr, addr, ETH_ALEN); 820 wx->mac_table[i].pools |= (1ULL << pool); 821 wx_sync_mac_table(wx); 822 return i; 823 } 824 } 825 } 826 827 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) 828 continue; 829 wx->mac_table[i].state |= (WX_MAC_STATE_MODIFIED | 830 WX_MAC_STATE_IN_USE); 831 memcpy(wx->mac_table[i].addr, addr, ETH_ALEN); 832 wx->mac_table[i].pools |= (1ULL << pool); 833 wx_sync_mac_table(wx); 834 return i; 835 } 836 return -ENOMEM; 837 } 838 839 static int wx_del_mac_filter(struct wx *wx, u8 *addr, u16 pool) 840 { 841 u32 i; 842 843 if (is_zero_ether_addr(addr)) 844 return -EINVAL; 845 846 /* search table for addr, if found, set to 0 and sync */ 847 for (i = 0; i < wx->mac.num_rar_entries; i++) { 848 if (!ether_addr_equal(addr, wx->mac_table[i].addr)) 849 continue; 850 851 wx->mac_table[i].state |= WX_MAC_STATE_MODIFIED; 852 wx->mac_table[i].pools &= ~(1ULL << pool); 853 if (!wx->mac_table[i].pools) { 854 wx->mac_table[i].state &= ~WX_MAC_STATE_IN_USE; 855 memset(wx->mac_table[i].addr, 0, ETH_ALEN); 856 } 857 wx_sync_mac_table(wx); 858 return 0; 859 } 860 return -ENOMEM; 861 } 862 863 static int wx_available_rars(struct wx *wx) 864 { 865 u32 i, count = 0; 866 867 for (i = 0; i < wx->mac.num_rar_entries; i++) { 868 if (wx->mac_table[i].state == 0) 869 count++; 870 } 871 872 return count; 873 } 874 875 /** 876 * wx_write_uc_addr_list - write unicast addresses to RAR table 877 * @netdev: network interface device structure 878 * @pool: index for mac table 879 * 880 * Writes unicast address list to the RAR table. 881 * Returns: -ENOMEM on failure/insufficient address space 882 * 0 on no addresses written 883 * X on writing X addresses to the RAR table 884 **/ 885 static int wx_write_uc_addr_list(struct net_device *netdev, int pool) 886 { 887 struct wx *wx = netdev_priv(netdev); 888 int count = 0; 889 890 /* return ENOMEM indicating insufficient memory for addresses */ 891 if (netdev_uc_count(netdev) > wx_available_rars(wx)) 892 return -ENOMEM; 893 894 if (!netdev_uc_empty(netdev)) { 895 struct netdev_hw_addr *ha; 896 897 netdev_for_each_uc_addr(ha, netdev) { 898 wx_del_mac_filter(wx, ha->addr, pool); 899 wx_add_mac_filter(wx, ha->addr, pool); 900 count++; 901 } 902 } 903 return count; 904 } 905 906 /** 907 * wx_mta_vector - Determines bit-vector in multicast table to set 908 * @wx: pointer to private structure 909 * @mc_addr: the multicast address 910 * 911 * Extracts the 12 bits, from a multicast address, to determine which 912 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 913 * incoming rx multicast addresses, to determine the bit-vector to check in 914 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 915 * by the MO field of the MCSTCTRL. The MO field is set during initialization 916 * to mc_filter_type. 917 **/ 918 static u32 wx_mta_vector(struct wx *wx, u8 *mc_addr) 919 { 920 u32 vector = 0; 921 922 switch (wx->mac.mc_filter_type) { 923 case 0: /* use bits [47:36] of the address */ 924 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 925 break; 926 case 1: /* use bits [46:35] of the address */ 927 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 928 break; 929 case 2: /* use bits [45:34] of the address */ 930 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 931 break; 932 case 3: /* use bits [43:32] of the address */ 933 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 934 break; 935 default: /* Invalid mc_filter_type */ 936 wx_err(wx, "MC filter type param set incorrectly\n"); 937 break; 938 } 939 940 /* vector can only be 12-bits or boundary will be exceeded */ 941 vector &= 0xFFF; 942 return vector; 943 } 944 945 /** 946 * wx_set_mta - Set bit-vector in multicast table 947 * @wx: pointer to private structure 948 * @mc_addr: Multicast address 949 * 950 * Sets the bit-vector in the multicast table. 951 **/ 952 static void wx_set_mta(struct wx *wx, u8 *mc_addr) 953 { 954 u32 vector, vector_bit, vector_reg; 955 956 wx->addr_ctrl.mta_in_use++; 957 958 vector = wx_mta_vector(wx, mc_addr); 959 wx_dbg(wx, " bit-vector = 0x%03X\n", vector); 960 961 /* The MTA is a register array of 128 32-bit registers. It is treated 962 * like an array of 4096 bits. We want to set bit 963 * BitArray[vector_value]. So we figure out what register the bit is 964 * in, read it, OR in the new bit, then write back the new value. The 965 * register is determined by the upper 7 bits of the vector value and 966 * the bit within that register are determined by the lower 5 bits of 967 * the value. 968 */ 969 vector_reg = (vector >> 5) & 0x7F; 970 vector_bit = vector & 0x1F; 971 wx->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 972 } 973 974 /** 975 * wx_update_mc_addr_list - Updates MAC list of multicast addresses 976 * @wx: pointer to private structure 977 * @netdev: pointer to net device structure 978 * 979 * The given list replaces any existing list. Clears the MC addrs from receive 980 * address registers and the multicast table. Uses unused receive address 981 * registers for the first multicast addresses, and hashes the rest into the 982 * multicast table. 983 **/ 984 static void wx_update_mc_addr_list(struct wx *wx, struct net_device *netdev) 985 { 986 struct netdev_hw_addr *ha; 987 u32 i, psrctl; 988 989 /* Set the new number of MC addresses that we are being requested to 990 * use. 991 */ 992 wx->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); 993 wx->addr_ctrl.mta_in_use = 0; 994 995 /* Clear mta_shadow */ 996 wx_dbg(wx, " Clearing MTA\n"); 997 memset(&wx->mac.mta_shadow, 0, sizeof(wx->mac.mta_shadow)); 998 999 /* Update mta_shadow */ 1000 netdev_for_each_mc_addr(ha, netdev) { 1001 wx_dbg(wx, " Adding the multicast addresses:\n"); 1002 wx_set_mta(wx, ha->addr); 1003 } 1004 1005 /* Enable mta */ 1006 for (i = 0; i < wx->mac.mcft_size; i++) 1007 wr32a(wx, WX_PSR_MC_TBL(0), i, 1008 wx->mac.mta_shadow[i]); 1009 1010 if (wx->addr_ctrl.mta_in_use > 0) { 1011 psrctl = rd32(wx, WX_PSR_CTL); 1012 psrctl &= ~(WX_PSR_CTL_MO | WX_PSR_CTL_MFE); 1013 psrctl |= WX_PSR_CTL_MFE | 1014 (wx->mac.mc_filter_type << WX_PSR_CTL_MO_SHIFT); 1015 wr32(wx, WX_PSR_CTL, psrctl); 1016 } 1017 1018 wx_dbg(wx, "Update mc addr list Complete\n"); 1019 } 1020 1021 /** 1022 * wx_write_mc_addr_list - write multicast addresses to MTA 1023 * @netdev: network interface device structure 1024 * 1025 * Writes multicast address list to the MTA hash table. 1026 * Returns: 0 on no addresses written 1027 * X on writing X addresses to MTA 1028 **/ 1029 static int wx_write_mc_addr_list(struct net_device *netdev) 1030 { 1031 struct wx *wx = netdev_priv(netdev); 1032 1033 if (!netif_running(netdev)) 1034 return 0; 1035 1036 wx_update_mc_addr_list(wx, netdev); 1037 1038 return netdev_mc_count(netdev); 1039 } 1040 1041 /** 1042 * wx_set_mac - Change the Ethernet Address of the NIC 1043 * @netdev: network interface device structure 1044 * @p: pointer to an address structure 1045 * 1046 * Returns 0 on success, negative on failure 1047 **/ 1048 int wx_set_mac(struct net_device *netdev, void *p) 1049 { 1050 struct wx *wx = netdev_priv(netdev); 1051 struct sockaddr *addr = p; 1052 int retval; 1053 1054 retval = eth_prepare_mac_addr_change(netdev, addr); 1055 if (retval) 1056 return retval; 1057 1058 wx_del_mac_filter(wx, wx->mac.addr, 0); 1059 eth_hw_addr_set(netdev, addr->sa_data); 1060 memcpy(wx->mac.addr, addr->sa_data, netdev->addr_len); 1061 1062 wx_mac_set_default_filter(wx, wx->mac.addr); 1063 1064 return 0; 1065 } 1066 EXPORT_SYMBOL(wx_set_mac); 1067 1068 void wx_disable_rx(struct wx *wx) 1069 { 1070 u32 pfdtxgswc; 1071 u32 rxctrl; 1072 1073 rxctrl = rd32(wx, WX_RDB_PB_CTL); 1074 if (rxctrl & WX_RDB_PB_CTL_RXEN) { 1075 pfdtxgswc = rd32(wx, WX_PSR_CTL); 1076 if (pfdtxgswc & WX_PSR_CTL_SW_EN) { 1077 pfdtxgswc &= ~WX_PSR_CTL_SW_EN; 1078 wr32(wx, WX_PSR_CTL, pfdtxgswc); 1079 wx->mac.set_lben = true; 1080 } else { 1081 wx->mac.set_lben = false; 1082 } 1083 rxctrl &= ~WX_RDB_PB_CTL_RXEN; 1084 wr32(wx, WX_RDB_PB_CTL, rxctrl); 1085 1086 if (!(((wx->subsystem_device_id & WX_NCSI_MASK) == WX_NCSI_SUP) || 1087 ((wx->subsystem_device_id & WX_WOL_MASK) == WX_WOL_SUP))) { 1088 /* disable mac receiver */ 1089 wr32m(wx, WX_MAC_RX_CFG, 1090 WX_MAC_RX_CFG_RE, 0); 1091 } 1092 } 1093 } 1094 EXPORT_SYMBOL(wx_disable_rx); 1095 1096 static void wx_enable_rx(struct wx *wx) 1097 { 1098 u32 psrctl; 1099 1100 /* enable mac receiver */ 1101 wr32m(wx, WX_MAC_RX_CFG, 1102 WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE); 1103 1104 wr32m(wx, WX_RDB_PB_CTL, 1105 WX_RDB_PB_CTL_RXEN, WX_RDB_PB_CTL_RXEN); 1106 1107 if (wx->mac.set_lben) { 1108 psrctl = rd32(wx, WX_PSR_CTL); 1109 psrctl |= WX_PSR_CTL_SW_EN; 1110 wr32(wx, WX_PSR_CTL, psrctl); 1111 wx->mac.set_lben = false; 1112 } 1113 } 1114 1115 /** 1116 * wx_set_rxpba - Initialize Rx packet buffer 1117 * @wx: pointer to private structure 1118 **/ 1119 static void wx_set_rxpba(struct wx *wx) 1120 { 1121 u32 rxpktsize, txpktsize, txpbthresh; 1122 1123 rxpktsize = wx->mac.rx_pb_size << WX_RDB_PB_SZ_SHIFT; 1124 wr32(wx, WX_RDB_PB_SZ(0), rxpktsize); 1125 1126 /* Only support an equally distributed Tx packet buffer strategy. */ 1127 txpktsize = wx->mac.tx_pb_size; 1128 txpbthresh = (txpktsize / 1024) - WX_TXPKT_SIZE_MAX; 1129 wr32(wx, WX_TDB_PB_SZ(0), txpktsize); 1130 wr32(wx, WX_TDM_PB_THRE(0), txpbthresh); 1131 } 1132 1133 static void wx_configure_port(struct wx *wx) 1134 { 1135 u32 value, i; 1136 1137 value = WX_CFG_PORT_CTL_D_VLAN | WX_CFG_PORT_CTL_QINQ; 1138 wr32m(wx, WX_CFG_PORT_CTL, 1139 WX_CFG_PORT_CTL_D_VLAN | 1140 WX_CFG_PORT_CTL_QINQ, 1141 value); 1142 1143 wr32(wx, WX_CFG_TAG_TPID(0), 1144 ETH_P_8021Q | ETH_P_8021AD << 16); 1145 wx->tpid[0] = ETH_P_8021Q; 1146 wx->tpid[1] = ETH_P_8021AD; 1147 for (i = 1; i < 4; i++) 1148 wr32(wx, WX_CFG_TAG_TPID(i), 1149 ETH_P_8021Q | ETH_P_8021Q << 16); 1150 for (i = 2; i < 8; i++) 1151 wx->tpid[i] = ETH_P_8021Q; 1152 } 1153 1154 /** 1155 * wx_disable_sec_rx_path - Stops the receive data path 1156 * @wx: pointer to private structure 1157 * 1158 * Stops the receive data path and waits for the HW to internally empty 1159 * the Rx security block 1160 **/ 1161 static int wx_disable_sec_rx_path(struct wx *wx) 1162 { 1163 u32 secrx; 1164 1165 wr32m(wx, WX_RSC_CTL, 1166 WX_RSC_CTL_RX_DIS, WX_RSC_CTL_RX_DIS); 1167 1168 return read_poll_timeout(rd32, secrx, secrx & WX_RSC_ST_RSEC_RDY, 1169 1000, 40000, false, wx, WX_RSC_ST); 1170 } 1171 1172 /** 1173 * wx_enable_sec_rx_path - Enables the receive data path 1174 * @wx: pointer to private structure 1175 * 1176 * Enables the receive data path. 1177 **/ 1178 static void wx_enable_sec_rx_path(struct wx *wx) 1179 { 1180 wr32m(wx, WX_RSC_CTL, WX_RSC_CTL_RX_DIS, 0); 1181 WX_WRITE_FLUSH(wx); 1182 } 1183 1184 void wx_set_rx_mode(struct net_device *netdev) 1185 { 1186 struct wx *wx = netdev_priv(netdev); 1187 u32 fctrl, vmolr, vlnctrl; 1188 int count; 1189 1190 /* Check for Promiscuous and All Multicast modes */ 1191 fctrl = rd32(wx, WX_PSR_CTL); 1192 fctrl &= ~(WX_PSR_CTL_UPE | WX_PSR_CTL_MPE); 1193 vmolr = rd32(wx, WX_PSR_VM_L2CTL(0)); 1194 vmolr &= ~(WX_PSR_VM_L2CTL_UPE | 1195 WX_PSR_VM_L2CTL_MPE | 1196 WX_PSR_VM_L2CTL_ROPE | 1197 WX_PSR_VM_L2CTL_ROMPE); 1198 vlnctrl = rd32(wx, WX_PSR_VLAN_CTL); 1199 vlnctrl &= ~(WX_PSR_VLAN_CTL_VFE | WX_PSR_VLAN_CTL_CFIEN); 1200 1201 /* set all bits that we expect to always be set */ 1202 fctrl |= WX_PSR_CTL_BAM | WX_PSR_CTL_MFE; 1203 vmolr |= WX_PSR_VM_L2CTL_BAM | 1204 WX_PSR_VM_L2CTL_AUPE | 1205 WX_PSR_VM_L2CTL_VACC; 1206 vlnctrl |= WX_PSR_VLAN_CTL_VFE; 1207 1208 wx->addr_ctrl.user_set_promisc = false; 1209 if (netdev->flags & IFF_PROMISC) { 1210 wx->addr_ctrl.user_set_promisc = true; 1211 fctrl |= WX_PSR_CTL_UPE | WX_PSR_CTL_MPE; 1212 /* pf don't want packets routing to vf, so clear UPE */ 1213 vmolr |= WX_PSR_VM_L2CTL_MPE; 1214 vlnctrl &= ~WX_PSR_VLAN_CTL_VFE; 1215 } 1216 1217 if (netdev->flags & IFF_ALLMULTI) { 1218 fctrl |= WX_PSR_CTL_MPE; 1219 vmolr |= WX_PSR_VM_L2CTL_MPE; 1220 } 1221 1222 if (netdev->features & NETIF_F_RXALL) { 1223 vmolr |= (WX_PSR_VM_L2CTL_UPE | WX_PSR_VM_L2CTL_MPE); 1224 vlnctrl &= ~WX_PSR_VLAN_CTL_VFE; 1225 /* receive bad packets */ 1226 wr32m(wx, WX_RSC_CTL, 1227 WX_RSC_CTL_SAVE_MAC_ERR, 1228 WX_RSC_CTL_SAVE_MAC_ERR); 1229 } else { 1230 vmolr |= WX_PSR_VM_L2CTL_ROPE | WX_PSR_VM_L2CTL_ROMPE; 1231 } 1232 1233 /* Write addresses to available RAR registers, if there is not 1234 * sufficient space to store all the addresses then enable 1235 * unicast promiscuous mode 1236 */ 1237 count = wx_write_uc_addr_list(netdev, 0); 1238 if (count < 0) { 1239 vmolr &= ~WX_PSR_VM_L2CTL_ROPE; 1240 vmolr |= WX_PSR_VM_L2CTL_UPE; 1241 } 1242 1243 /* Write addresses to the MTA, if the attempt fails 1244 * then we should just turn on promiscuous mode so 1245 * that we can at least receive multicast traffic 1246 */ 1247 count = wx_write_mc_addr_list(netdev); 1248 if (count < 0) { 1249 vmolr &= ~WX_PSR_VM_L2CTL_ROMPE; 1250 vmolr |= WX_PSR_VM_L2CTL_MPE; 1251 } 1252 1253 wr32(wx, WX_PSR_VLAN_CTL, vlnctrl); 1254 wr32(wx, WX_PSR_CTL, fctrl); 1255 wr32(wx, WX_PSR_VM_L2CTL(0), vmolr); 1256 } 1257 EXPORT_SYMBOL(wx_set_rx_mode); 1258 1259 static void wx_set_rx_buffer_len(struct wx *wx) 1260 { 1261 struct net_device *netdev = wx->netdev; 1262 u32 mhadd, max_frame; 1263 1264 max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 1265 /* adjust max frame to be at least the size of a standard frame */ 1266 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 1267 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 1268 1269 mhadd = rd32(wx, WX_PSR_MAX_SZ); 1270 if (max_frame != mhadd) 1271 wr32(wx, WX_PSR_MAX_SZ, max_frame); 1272 } 1273 1274 /* Disable the specified rx queue */ 1275 void wx_disable_rx_queue(struct wx *wx, struct wx_ring *ring) 1276 { 1277 u8 reg_idx = ring->reg_idx; 1278 u32 rxdctl; 1279 int ret; 1280 1281 /* write value back with RRCFG.EN bit cleared */ 1282 wr32m(wx, WX_PX_RR_CFG(reg_idx), 1283 WX_PX_RR_CFG_RR_EN, 0); 1284 1285 /* the hardware may take up to 100us to really disable the rx queue */ 1286 ret = read_poll_timeout(rd32, rxdctl, !(rxdctl & WX_PX_RR_CFG_RR_EN), 1287 10, 100, true, wx, WX_PX_RR_CFG(reg_idx)); 1288 1289 if (ret == -ETIMEDOUT) { 1290 /* Just for information */ 1291 wx_err(wx, 1292 "RRCFG.EN on Rx queue %d not cleared within the polling period\n", 1293 reg_idx); 1294 } 1295 } 1296 EXPORT_SYMBOL(wx_disable_rx_queue); 1297 1298 static void wx_enable_rx_queue(struct wx *wx, struct wx_ring *ring) 1299 { 1300 u8 reg_idx = ring->reg_idx; 1301 u32 rxdctl; 1302 int ret; 1303 1304 ret = read_poll_timeout(rd32, rxdctl, rxdctl & WX_PX_RR_CFG_RR_EN, 1305 1000, 10000, true, wx, WX_PX_RR_CFG(reg_idx)); 1306 1307 if (ret == -ETIMEDOUT) { 1308 /* Just for information */ 1309 wx_err(wx, 1310 "RRCFG.EN on Rx queue %d not set within the polling period\n", 1311 reg_idx); 1312 } 1313 } 1314 1315 static void wx_configure_srrctl(struct wx *wx, 1316 struct wx_ring *rx_ring) 1317 { 1318 u16 reg_idx = rx_ring->reg_idx; 1319 u32 srrctl; 1320 1321 srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx)); 1322 srrctl &= ~(WX_PX_RR_CFG_RR_HDR_SZ | 1323 WX_PX_RR_CFG_RR_BUF_SZ | 1324 WX_PX_RR_CFG_SPLIT_MODE); 1325 /* configure header buffer length, needed for RSC */ 1326 srrctl |= WX_RXBUFFER_256 << WX_PX_RR_CFG_BHDRSIZE_SHIFT; 1327 1328 /* configure the packet buffer length */ 1329 srrctl |= WX_RX_BUFSZ >> WX_PX_RR_CFG_BSIZEPKT_SHIFT; 1330 1331 wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl); 1332 } 1333 1334 static void wx_configure_tx_ring(struct wx *wx, 1335 struct wx_ring *ring) 1336 { 1337 u32 txdctl = WX_PX_TR_CFG_ENABLE; 1338 u8 reg_idx = ring->reg_idx; 1339 u64 tdba = ring->dma; 1340 int ret; 1341 1342 /* disable queue to avoid issues while updating state */ 1343 wr32(wx, WX_PX_TR_CFG(reg_idx), WX_PX_TR_CFG_SWFLSH); 1344 WX_WRITE_FLUSH(wx); 1345 1346 wr32(wx, WX_PX_TR_BAL(reg_idx), tdba & DMA_BIT_MASK(32)); 1347 wr32(wx, WX_PX_TR_BAH(reg_idx), upper_32_bits(tdba)); 1348 1349 /* reset head and tail pointers */ 1350 wr32(wx, WX_PX_TR_RP(reg_idx), 0); 1351 wr32(wx, WX_PX_TR_WP(reg_idx), 0); 1352 ring->tail = wx->hw_addr + WX_PX_TR_WP(reg_idx); 1353 1354 if (ring->count < WX_MAX_TXD) 1355 txdctl |= ring->count / 128 << WX_PX_TR_CFG_TR_SIZE_SHIFT; 1356 txdctl |= 0x20 << WX_PX_TR_CFG_WTHRESH_SHIFT; 1357 1358 /* reinitialize tx_buffer_info */ 1359 memset(ring->tx_buffer_info, 0, 1360 sizeof(struct wx_tx_buffer) * ring->count); 1361 1362 /* enable queue */ 1363 wr32(wx, WX_PX_TR_CFG(reg_idx), txdctl); 1364 1365 /* poll to verify queue is enabled */ 1366 ret = read_poll_timeout(rd32, txdctl, txdctl & WX_PX_TR_CFG_ENABLE, 1367 1000, 10000, true, wx, WX_PX_TR_CFG(reg_idx)); 1368 if (ret == -ETIMEDOUT) 1369 wx_err(wx, "Could not enable Tx Queue %d\n", reg_idx); 1370 } 1371 1372 static void wx_configure_rx_ring(struct wx *wx, 1373 struct wx_ring *ring) 1374 { 1375 u16 reg_idx = ring->reg_idx; 1376 union wx_rx_desc *rx_desc; 1377 u64 rdba = ring->dma; 1378 u32 rxdctl; 1379 1380 /* disable queue to avoid issues while updating state */ 1381 rxdctl = rd32(wx, WX_PX_RR_CFG(reg_idx)); 1382 wx_disable_rx_queue(wx, ring); 1383 1384 wr32(wx, WX_PX_RR_BAL(reg_idx), rdba & DMA_BIT_MASK(32)); 1385 wr32(wx, WX_PX_RR_BAH(reg_idx), upper_32_bits(rdba)); 1386 1387 if (ring->count == WX_MAX_RXD) 1388 rxdctl |= 0 << WX_PX_RR_CFG_RR_SIZE_SHIFT; 1389 else 1390 rxdctl |= (ring->count / 128) << WX_PX_RR_CFG_RR_SIZE_SHIFT; 1391 1392 rxdctl |= 0x1 << WX_PX_RR_CFG_RR_THER_SHIFT; 1393 wr32(wx, WX_PX_RR_CFG(reg_idx), rxdctl); 1394 1395 /* reset head and tail pointers */ 1396 wr32(wx, WX_PX_RR_RP(reg_idx), 0); 1397 wr32(wx, WX_PX_RR_WP(reg_idx), 0); 1398 ring->tail = wx->hw_addr + WX_PX_RR_WP(reg_idx); 1399 1400 wx_configure_srrctl(wx, ring); 1401 1402 /* initialize rx_buffer_info */ 1403 memset(ring->rx_buffer_info, 0, 1404 sizeof(struct wx_rx_buffer) * ring->count); 1405 1406 /* initialize Rx descriptor 0 */ 1407 rx_desc = WX_RX_DESC(ring, 0); 1408 rx_desc->wb.upper.length = 0; 1409 1410 /* enable receive descriptor ring */ 1411 wr32m(wx, WX_PX_RR_CFG(reg_idx), 1412 WX_PX_RR_CFG_RR_EN, WX_PX_RR_CFG_RR_EN); 1413 1414 wx_enable_rx_queue(wx, ring); 1415 wx_alloc_rx_buffers(ring, wx_desc_unused(ring)); 1416 } 1417 1418 /** 1419 * wx_configure_tx - Configure Transmit Unit after Reset 1420 * @wx: pointer to private structure 1421 * 1422 * Configure the Tx unit of the MAC after a reset. 1423 **/ 1424 static void wx_configure_tx(struct wx *wx) 1425 { 1426 u32 i; 1427 1428 /* TDM_CTL.TE must be before Tx queues are enabled */ 1429 wr32m(wx, WX_TDM_CTL, 1430 WX_TDM_CTL_TE, WX_TDM_CTL_TE); 1431 1432 /* Setup the HW Tx Head and Tail descriptor pointers */ 1433 for (i = 0; i < wx->num_tx_queues; i++) 1434 wx_configure_tx_ring(wx, wx->tx_ring[i]); 1435 1436 wr32m(wx, WX_TSC_BUF_AE, WX_TSC_BUF_AE_THR, 0x10); 1437 1438 if (wx->mac.type == wx_mac_em) 1439 wr32m(wx, WX_TSC_CTL, WX_TSC_CTL_TX_DIS | WX_TSC_CTL_TSEC_DIS, 0x1); 1440 1441 /* enable mac transmitter */ 1442 wr32m(wx, WX_MAC_TX_CFG, 1443 WX_MAC_TX_CFG_TE, WX_MAC_TX_CFG_TE); 1444 } 1445 1446 /** 1447 * wx_configure_rx - Configure Receive Unit after Reset 1448 * @wx: pointer to private structure 1449 * 1450 * Configure the Rx unit of the MAC after a reset. 1451 **/ 1452 static void wx_configure_rx(struct wx *wx) 1453 { 1454 u32 psrtype, i; 1455 int ret; 1456 1457 wx_disable_rx(wx); 1458 1459 psrtype = WX_RDB_PL_CFG_L4HDR | 1460 WX_RDB_PL_CFG_L3HDR | 1461 WX_RDB_PL_CFG_L2HDR | 1462 WX_RDB_PL_CFG_TUN_TUNHDR | 1463 WX_RDB_PL_CFG_TUN_TUNHDR; 1464 wr32(wx, WX_RDB_PL_CFG(0), psrtype); 1465 1466 /* enable hw crc stripping */ 1467 wr32m(wx, WX_RSC_CTL, WX_RSC_CTL_CRC_STRIP, WX_RSC_CTL_CRC_STRIP); 1468 1469 if (wx->mac.type == wx_mac_sp) { 1470 u32 psrctl; 1471 1472 /* RSC Setup */ 1473 psrctl = rd32(wx, WX_PSR_CTL); 1474 psrctl |= WX_PSR_CTL_RSC_ACK; /* Disable RSC for ACK packets */ 1475 psrctl |= WX_PSR_CTL_RSC_DIS; 1476 wr32(wx, WX_PSR_CTL, psrctl); 1477 } 1478 1479 /* set_rx_buffer_len must be called before ring initialization */ 1480 wx_set_rx_buffer_len(wx); 1481 1482 /* Setup the HW Rx Head and Tail Descriptor Pointers and 1483 * the Base and Length of the Rx Descriptor Ring 1484 */ 1485 for (i = 0; i < wx->num_rx_queues; i++) 1486 wx_configure_rx_ring(wx, wx->rx_ring[i]); 1487 1488 /* Enable all receives, disable security engine prior to block traffic */ 1489 ret = wx_disable_sec_rx_path(wx); 1490 if (ret < 0) 1491 wx_err(wx, "The register status is abnormal, please check device."); 1492 1493 wx_enable_rx(wx); 1494 wx_enable_sec_rx_path(wx); 1495 } 1496 1497 static void wx_configure_isb(struct wx *wx) 1498 { 1499 /* set ISB Address */ 1500 wr32(wx, WX_PX_ISB_ADDR_L, wx->isb_dma & DMA_BIT_MASK(32)); 1501 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 1502 wr32(wx, WX_PX_ISB_ADDR_H, upper_32_bits(wx->isb_dma)); 1503 } 1504 1505 void wx_configure(struct wx *wx) 1506 { 1507 wx_set_rxpba(wx); 1508 wx_configure_port(wx); 1509 1510 wx_set_rx_mode(wx->netdev); 1511 1512 wx_enable_sec_rx_path(wx); 1513 1514 wx_configure_tx(wx); 1515 wx_configure_rx(wx); 1516 wx_configure_isb(wx); 1517 } 1518 EXPORT_SYMBOL(wx_configure); 1519 1520 /** 1521 * wx_disable_pcie_master - Disable PCI-express master access 1522 * @wx: pointer to hardware structure 1523 * 1524 * Disables PCI-Express master access and verifies there are no pending 1525 * requests. 1526 **/ 1527 int wx_disable_pcie_master(struct wx *wx) 1528 { 1529 int status = 0; 1530 u32 val; 1531 1532 /* Always set this bit to ensure any future transactions are blocked */ 1533 pci_clear_master(wx->pdev); 1534 1535 /* Exit if master requests are blocked */ 1536 if (!(rd32(wx, WX_PX_TRANSACTION_PENDING))) 1537 return 0; 1538 1539 /* Poll for master request bit to clear */ 1540 status = read_poll_timeout(rd32, val, !val, 100, WX_PCI_MASTER_DISABLE_TIMEOUT, 1541 false, wx, WX_PX_TRANSACTION_PENDING); 1542 if (status < 0) 1543 wx_err(wx, "PCIe transaction pending bit did not clear.\n"); 1544 1545 return status; 1546 } 1547 EXPORT_SYMBOL(wx_disable_pcie_master); 1548 1549 /** 1550 * wx_stop_adapter - Generic stop Tx/Rx units 1551 * @wx: pointer to hardware structure 1552 * 1553 * Sets the adapter_stopped flag within wx_hw struct. Clears interrupts, 1554 * disables transmit and receive units. The adapter_stopped flag is used by 1555 * the shared code and drivers to determine if the adapter is in a stopped 1556 * state and should not touch the hardware. 1557 **/ 1558 int wx_stop_adapter(struct wx *wx) 1559 { 1560 u16 i; 1561 1562 /* Set the adapter_stopped flag so other driver functions stop touching 1563 * the hardware 1564 */ 1565 wx->adapter_stopped = true; 1566 1567 /* Disable the receive unit */ 1568 wx_disable_rx(wx); 1569 1570 /* Set interrupt mask to stop interrupts from being generated */ 1571 wx_intr_disable(wx, WX_INTR_ALL); 1572 1573 /* Clear any pending interrupts, flush previous writes */ 1574 wr32(wx, WX_PX_MISC_IC, 0xffffffff); 1575 wr32(wx, WX_BME_CTL, 0x3); 1576 1577 /* Disable the transmit unit. Each queue must be disabled. */ 1578 for (i = 0; i < wx->mac.max_tx_queues; i++) { 1579 wr32m(wx, WX_PX_TR_CFG(i), 1580 WX_PX_TR_CFG_SWFLSH | WX_PX_TR_CFG_ENABLE, 1581 WX_PX_TR_CFG_SWFLSH); 1582 } 1583 1584 /* Disable the receive unit by stopping each queue */ 1585 for (i = 0; i < wx->mac.max_rx_queues; i++) { 1586 wr32m(wx, WX_PX_RR_CFG(i), 1587 WX_PX_RR_CFG_RR_EN, 0); 1588 } 1589 1590 /* flush all queues disables */ 1591 WX_WRITE_FLUSH(wx); 1592 1593 /* Prevent the PCI-E bus from hanging by disabling PCI-E master 1594 * access and verify no pending requests 1595 */ 1596 return wx_disable_pcie_master(wx); 1597 } 1598 EXPORT_SYMBOL(wx_stop_adapter); 1599 1600 void wx_reset_misc(struct wx *wx) 1601 { 1602 int i; 1603 1604 /* receive packets that size > 2048 */ 1605 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_JE, WX_MAC_RX_CFG_JE); 1606 1607 /* clear counters on read */ 1608 wr32m(wx, WX_MMC_CONTROL, 1609 WX_MMC_CONTROL_RSTONRD, WX_MMC_CONTROL_RSTONRD); 1610 1611 wr32m(wx, WX_MAC_RX_FLOW_CTRL, 1612 WX_MAC_RX_FLOW_CTRL_RFE, WX_MAC_RX_FLOW_CTRL_RFE); 1613 1614 wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR); 1615 1616 wr32m(wx, WX_MIS_RST_ST, 1617 WX_MIS_RST_ST_RST_INIT, 0x1E00); 1618 1619 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/ 1620 wr32(wx, WX_PSR_MNG_FLEX_SEL, 0); 1621 for (i = 0; i < 16; i++) { 1622 wr32(wx, WX_PSR_MNG_FLEX_DW_L(i), 0); 1623 wr32(wx, WX_PSR_MNG_FLEX_DW_H(i), 0); 1624 wr32(wx, WX_PSR_MNG_FLEX_MSK(i), 0); 1625 } 1626 wr32(wx, WX_PSR_LAN_FLEX_SEL, 0); 1627 for (i = 0; i < 16; i++) { 1628 wr32(wx, WX_PSR_LAN_FLEX_DW_L(i), 0); 1629 wr32(wx, WX_PSR_LAN_FLEX_DW_H(i), 0); 1630 wr32(wx, WX_PSR_LAN_FLEX_MSK(i), 0); 1631 } 1632 1633 /* set pause frame dst mac addr */ 1634 wr32(wx, WX_RDB_PFCMACDAL, 0xC2000001); 1635 wr32(wx, WX_RDB_PFCMACDAH, 0x0180); 1636 } 1637 EXPORT_SYMBOL(wx_reset_misc); 1638 1639 /** 1640 * wx_get_pcie_msix_counts - Gets MSI-X vector count 1641 * @wx: pointer to hardware structure 1642 * @msix_count: number of MSI interrupts that can be obtained 1643 * @max_msix_count: number of MSI interrupts that mac need 1644 * 1645 * Read PCIe configuration space, and get the MSI-X vector count from 1646 * the capabilities table. 1647 **/ 1648 int wx_get_pcie_msix_counts(struct wx *wx, u16 *msix_count, u16 max_msix_count) 1649 { 1650 struct pci_dev *pdev = wx->pdev; 1651 struct device *dev = &pdev->dev; 1652 int pos; 1653 1654 *msix_count = 1; 1655 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 1656 if (!pos) { 1657 dev_err(dev, "Unable to find MSI-X Capabilities\n"); 1658 return -EINVAL; 1659 } 1660 pci_read_config_word(pdev, 1661 pos + PCI_MSIX_FLAGS, 1662 msix_count); 1663 *msix_count &= WX_PCIE_MSIX_TBL_SZ_MASK; 1664 /* MSI-X count is zero-based in HW */ 1665 *msix_count += 1; 1666 1667 if (*msix_count > max_msix_count) 1668 *msix_count = max_msix_count; 1669 1670 return 0; 1671 } 1672 EXPORT_SYMBOL(wx_get_pcie_msix_counts); 1673 1674 int wx_sw_init(struct wx *wx) 1675 { 1676 struct pci_dev *pdev = wx->pdev; 1677 u32 ssid = 0; 1678 int err = 0; 1679 1680 wx->vendor_id = pdev->vendor; 1681 wx->device_id = pdev->device; 1682 wx->revision_id = pdev->revision; 1683 wx->oem_svid = pdev->subsystem_vendor; 1684 wx->oem_ssid = pdev->subsystem_device; 1685 wx->bus.device = PCI_SLOT(pdev->devfn); 1686 wx->bus.func = PCI_FUNC(pdev->devfn); 1687 1688 if (wx->oem_svid == PCI_VENDOR_ID_WANGXUN) { 1689 wx->subsystem_vendor_id = pdev->subsystem_vendor; 1690 wx->subsystem_device_id = pdev->subsystem_device; 1691 } else { 1692 err = wx_flash_read_dword(wx, 0xfffdc, &ssid); 1693 if (!err) 1694 wx->subsystem_device_id = swab16((u16)ssid); 1695 1696 return err; 1697 } 1698 1699 wx->mac_table = kcalloc(wx->mac.num_rar_entries, 1700 sizeof(struct wx_mac_addr), 1701 GFP_KERNEL); 1702 if (!wx->mac_table) { 1703 wx_err(wx, "mac_table allocation failed\n"); 1704 return -ENOMEM; 1705 } 1706 1707 return 0; 1708 } 1709 EXPORT_SYMBOL(wx_sw_init); 1710 1711 MODULE_LICENSE("GPL"); 1712