1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/if_ether.h> 6 #include <linux/iopoll.h> 7 #include <linux/pci.h> 8 9 #include "wx_type.h" 10 #include "wx_hw.h" 11 12 static void wx_intr_disable(struct wx_hw *wxhw, u64 qmask) 13 { 14 u32 mask; 15 16 mask = (qmask & 0xFFFFFFFF); 17 if (mask) 18 wr32(wxhw, WX_PX_IMS(0), mask); 19 20 if (wxhw->mac.type == wx_mac_sp) { 21 mask = (qmask >> 32); 22 if (mask) 23 wr32(wxhw, WX_PX_IMS(1), mask); 24 } 25 } 26 27 /* cmd_addr is used for some special command: 28 * 1. to be sector address, when implemented erase sector command 29 * 2. to be flash address when implemented read, write flash address 30 */ 31 static int wx_fmgr_cmd_op(struct wx_hw *wxhw, u32 cmd, u32 cmd_addr) 32 { 33 u32 cmd_val = 0, val = 0; 34 35 cmd_val = WX_SPI_CMD_CMD(cmd) | 36 WX_SPI_CMD_CLK(WX_SPI_CLK_DIV) | 37 cmd_addr; 38 wr32(wxhw, WX_SPI_CMD, cmd_val); 39 40 return read_poll_timeout(rd32, val, (val & 0x1), 10, 100000, 41 false, wxhw, WX_SPI_STATUS); 42 } 43 44 static int wx_flash_read_dword(struct wx_hw *wxhw, u32 addr, u32 *data) 45 { 46 int ret = 0; 47 48 ret = wx_fmgr_cmd_op(wxhw, WX_SPI_CMD_READ_DWORD, addr); 49 if (ret < 0) 50 return ret; 51 52 *data = rd32(wxhw, WX_SPI_DATA); 53 54 return ret; 55 } 56 57 int wx_check_flash_load(struct wx_hw *hw, u32 check_bit) 58 { 59 u32 reg = 0; 60 int err = 0; 61 62 /* if there's flash existing */ 63 if (!(rd32(hw, WX_SPI_STATUS) & 64 WX_SPI_STATUS_FLASH_BYPASS)) { 65 /* wait hw load flash done */ 66 err = read_poll_timeout(rd32, reg, !(reg & check_bit), 20000, 2000000, 67 false, hw, WX_SPI_ILDR_STATUS); 68 if (err < 0) 69 wx_err(hw, "Check flash load timeout.\n"); 70 } 71 72 return err; 73 } 74 EXPORT_SYMBOL(wx_check_flash_load); 75 76 void wx_control_hw(struct wx_hw *wxhw, bool drv) 77 { 78 if (drv) { 79 /* Let firmware know the driver has taken over */ 80 wr32m(wxhw, WX_CFG_PORT_CTL, 81 WX_CFG_PORT_CTL_DRV_LOAD, WX_CFG_PORT_CTL_DRV_LOAD); 82 } else { 83 /* Let firmware take over control of hw */ 84 wr32m(wxhw, WX_CFG_PORT_CTL, 85 WX_CFG_PORT_CTL_DRV_LOAD, 0); 86 } 87 } 88 EXPORT_SYMBOL(wx_control_hw); 89 90 /** 91 * wx_mng_present - returns 0 when management capability is present 92 * @wxhw: pointer to hardware structure 93 */ 94 int wx_mng_present(struct wx_hw *wxhw) 95 { 96 u32 fwsm; 97 98 fwsm = rd32(wxhw, WX_MIS_ST); 99 if (fwsm & WX_MIS_ST_MNG_INIT_DN) 100 return 0; 101 else 102 return -EACCES; 103 } 104 EXPORT_SYMBOL(wx_mng_present); 105 106 /* Software lock to be held while software semaphore is being accessed. */ 107 static DEFINE_MUTEX(wx_sw_sync_lock); 108 109 /** 110 * wx_release_sw_sync - Release SW semaphore 111 * @wxhw: pointer to hardware structure 112 * @mask: Mask to specify which semaphore to release 113 * 114 * Releases the SW semaphore for the specified 115 * function (CSR, PHY0, PHY1, EEPROM, Flash) 116 **/ 117 static void wx_release_sw_sync(struct wx_hw *wxhw, u32 mask) 118 { 119 mutex_lock(&wx_sw_sync_lock); 120 wr32m(wxhw, WX_MNG_SWFW_SYNC, mask, 0); 121 mutex_unlock(&wx_sw_sync_lock); 122 } 123 124 /** 125 * wx_acquire_sw_sync - Acquire SW semaphore 126 * @wxhw: pointer to hardware structure 127 * @mask: Mask to specify which semaphore to acquire 128 * 129 * Acquires the SW semaphore for the specified 130 * function (CSR, PHY0, PHY1, EEPROM, Flash) 131 **/ 132 static int wx_acquire_sw_sync(struct wx_hw *wxhw, u32 mask) 133 { 134 u32 sem = 0; 135 int ret = 0; 136 137 mutex_lock(&wx_sw_sync_lock); 138 ret = read_poll_timeout(rd32, sem, !(sem & mask), 139 5000, 2000000, false, wxhw, WX_MNG_SWFW_SYNC); 140 if (!ret) { 141 sem |= mask; 142 wr32(wxhw, WX_MNG_SWFW_SYNC, sem); 143 } else { 144 wx_err(wxhw, "SW Semaphore not granted: 0x%x.\n", sem); 145 } 146 mutex_unlock(&wx_sw_sync_lock); 147 148 return ret; 149 } 150 151 /** 152 * wx_host_interface_command - Issue command to manageability block 153 * @wxhw: pointer to the HW structure 154 * @buffer: contains the command to write and where the return status will 155 * be placed 156 * @length: length of buffer, must be multiple of 4 bytes 157 * @timeout: time in ms to wait for command completion 158 * @return_data: read and return data from the buffer (true) or not (false) 159 * Needed because FW structures are big endian and decoding of 160 * these fields can be 8 bit or 16 bit based on command. Decoding 161 * is not easily understood without making a table of commands. 162 * So we will leave this up to the caller to read back the data 163 * in these cases. 164 **/ 165 int wx_host_interface_command(struct wx_hw *wxhw, u32 *buffer, 166 u32 length, u32 timeout, bool return_data) 167 { 168 u32 hdr_size = sizeof(struct wx_hic_hdr); 169 u32 hicr, i, bi, buf[64] = {}; 170 int status = 0; 171 u32 dword_len; 172 u16 buf_len; 173 174 if (length == 0 || length > WX_HI_MAX_BLOCK_BYTE_LENGTH) { 175 wx_err(wxhw, "Buffer length failure buffersize=%d.\n", length); 176 return -EINVAL; 177 } 178 179 status = wx_acquire_sw_sync(wxhw, WX_MNG_SWFW_SYNC_SW_MB); 180 if (status != 0) 181 return status; 182 183 /* Calculate length in DWORDs. We must be DWORD aligned */ 184 if ((length % (sizeof(u32))) != 0) { 185 wx_err(wxhw, "Buffer length failure, not aligned to dword"); 186 status = -EINVAL; 187 goto rel_out; 188 } 189 190 dword_len = length >> 2; 191 192 /* The device driver writes the relevant command block 193 * into the ram area. 194 */ 195 for (i = 0; i < dword_len; i++) { 196 wr32a(wxhw, WX_MNG_MBOX, i, (__force u32)cpu_to_le32(buffer[i])); 197 /* write flush */ 198 buf[i] = rd32a(wxhw, WX_MNG_MBOX, i); 199 } 200 /* Setting this bit tells the ARC that a new command is pending. */ 201 wr32m(wxhw, WX_MNG_MBOX_CTL, 202 WX_MNG_MBOX_CTL_SWRDY, WX_MNG_MBOX_CTL_SWRDY); 203 204 status = read_poll_timeout(rd32, hicr, hicr & WX_MNG_MBOX_CTL_FWRDY, 1000, 205 timeout * 1000, false, wxhw, WX_MNG_MBOX_CTL); 206 if (status) 207 goto rel_out; 208 209 /* Check command completion */ 210 if (status) { 211 wx_dbg(wxhw, "Command has failed with no status valid.\n"); 212 213 buf[0] = rd32(wxhw, WX_MNG_MBOX); 214 if ((buffer[0] & 0xff) != (~buf[0] >> 24)) { 215 status = -EINVAL; 216 goto rel_out; 217 } 218 if ((buf[0] & 0xff0000) >> 16 == 0x80) { 219 wx_dbg(wxhw, "It's unknown cmd.\n"); 220 status = -EINVAL; 221 goto rel_out; 222 } 223 224 wx_dbg(wxhw, "write value:\n"); 225 for (i = 0; i < dword_len; i++) 226 wx_dbg(wxhw, "%x ", buffer[i]); 227 wx_dbg(wxhw, "read value:\n"); 228 for (i = 0; i < dword_len; i++) 229 wx_dbg(wxhw, "%x ", buf[i]); 230 } 231 232 if (!return_data) 233 goto rel_out; 234 235 /* Calculate length in DWORDs */ 236 dword_len = hdr_size >> 2; 237 238 /* first pull in the header so we know the buffer length */ 239 for (bi = 0; bi < dword_len; bi++) { 240 buffer[bi] = rd32a(wxhw, WX_MNG_MBOX, bi); 241 le32_to_cpus(&buffer[bi]); 242 } 243 244 /* If there is any thing in data position pull it in */ 245 buf_len = ((struct wx_hic_hdr *)buffer)->buf_len; 246 if (buf_len == 0) 247 goto rel_out; 248 249 if (length < buf_len + hdr_size) { 250 wx_err(wxhw, "Buffer not large enough for reply message.\n"); 251 status = -EFAULT; 252 goto rel_out; 253 } 254 255 /* Calculate length in DWORDs, add 3 for odd lengths */ 256 dword_len = (buf_len + 3) >> 2; 257 258 /* Pull in the rest of the buffer (bi is where we left off) */ 259 for (; bi <= dword_len; bi++) { 260 buffer[bi] = rd32a(wxhw, WX_MNG_MBOX, bi); 261 le32_to_cpus(&buffer[bi]); 262 } 263 264 rel_out: 265 wx_release_sw_sync(wxhw, WX_MNG_SWFW_SYNC_SW_MB); 266 return status; 267 } 268 EXPORT_SYMBOL(wx_host_interface_command); 269 270 /** 271 * wx_read_ee_hostif_data - Read EEPROM word using a host interface cmd 272 * assuming that the semaphore is already obtained. 273 * @wxhw: pointer to hardware structure 274 * @offset: offset of word in the EEPROM to read 275 * @data: word read from the EEPROM 276 * 277 * Reads a 16 bit word from the EEPROM using the hostif. 278 **/ 279 static int wx_read_ee_hostif_data(struct wx_hw *wxhw, u16 offset, u16 *data) 280 { 281 struct wx_hic_read_shadow_ram buffer; 282 int status; 283 284 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 285 buffer.hdr.req.buf_lenh = 0; 286 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 287 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 288 289 /* convert offset from words to bytes */ 290 buffer.address = (__force u32)cpu_to_be32(offset * 2); 291 /* one word */ 292 buffer.length = (__force u16)cpu_to_be16(sizeof(u16)); 293 294 status = wx_host_interface_command(wxhw, (u32 *)&buffer, sizeof(buffer), 295 WX_HI_COMMAND_TIMEOUT, false); 296 297 if (status != 0) 298 return status; 299 300 *data = (u16)rd32a(wxhw, WX_MNG_MBOX, FW_NVM_DATA_OFFSET); 301 302 return status; 303 } 304 305 /** 306 * wx_read_ee_hostif - Read EEPROM word using a host interface cmd 307 * @wxhw: pointer to hardware structure 308 * @offset: offset of word in the EEPROM to read 309 * @data: word read from the EEPROM 310 * 311 * Reads a 16 bit word from the EEPROM using the hostif. 312 **/ 313 int wx_read_ee_hostif(struct wx_hw *wxhw, u16 offset, u16 *data) 314 { 315 int status = 0; 316 317 status = wx_acquire_sw_sync(wxhw, WX_MNG_SWFW_SYNC_SW_FLASH); 318 if (status == 0) { 319 status = wx_read_ee_hostif_data(wxhw, offset, data); 320 wx_release_sw_sync(wxhw, WX_MNG_SWFW_SYNC_SW_FLASH); 321 } 322 323 return status; 324 } 325 EXPORT_SYMBOL(wx_read_ee_hostif); 326 327 /** 328 * wx_read_ee_hostif_buffer- Read EEPROM word(s) using hostif 329 * @wxhw: pointer to hardware structure 330 * @offset: offset of word in the EEPROM to read 331 * @words: number of words 332 * @data: word(s) read from the EEPROM 333 * 334 * Reads a 16 bit word(s) from the EEPROM using the hostif. 335 **/ 336 int wx_read_ee_hostif_buffer(struct wx_hw *wxhw, 337 u16 offset, u16 words, u16 *data) 338 { 339 struct wx_hic_read_shadow_ram buffer; 340 u32 current_word = 0; 341 u16 words_to_read; 342 u32 value = 0; 343 int status; 344 u32 i; 345 346 /* Take semaphore for the entire operation. */ 347 status = wx_acquire_sw_sync(wxhw, WX_MNG_SWFW_SYNC_SW_FLASH); 348 if (status != 0) 349 return status; 350 351 while (words) { 352 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 353 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 354 else 355 words_to_read = words; 356 357 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 358 buffer.hdr.req.buf_lenh = 0; 359 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 360 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 361 362 /* convert offset from words to bytes */ 363 buffer.address = (__force u32)cpu_to_be32((offset + current_word) * 2); 364 buffer.length = (__force u16)cpu_to_be16(words_to_read * 2); 365 366 status = wx_host_interface_command(wxhw, (u32 *)&buffer, 367 sizeof(buffer), 368 WX_HI_COMMAND_TIMEOUT, 369 false); 370 371 if (status != 0) { 372 wx_err(wxhw, "Host interface command failed\n"); 373 goto out; 374 } 375 376 for (i = 0; i < words_to_read; i++) { 377 u32 reg = WX_MNG_MBOX + (FW_NVM_DATA_OFFSET << 2) + 2 * i; 378 379 value = rd32(wxhw, reg); 380 data[current_word] = (u16)(value & 0xffff); 381 current_word++; 382 i++; 383 if (i < words_to_read) { 384 value >>= 16; 385 data[current_word] = (u16)(value & 0xffff); 386 current_word++; 387 } 388 } 389 words -= words_to_read; 390 } 391 392 out: 393 wx_release_sw_sync(wxhw, WX_MNG_SWFW_SYNC_SW_FLASH); 394 return status; 395 } 396 EXPORT_SYMBOL(wx_read_ee_hostif_buffer); 397 398 /** 399 * wx_calculate_checksum - Calculate checksum for buffer 400 * @buffer: pointer to EEPROM 401 * @length: size of EEPROM to calculate a checksum for 402 * Calculates the checksum for some buffer on a specified length. The 403 * checksum calculated is returned. 404 **/ 405 static u8 wx_calculate_checksum(u8 *buffer, u32 length) 406 { 407 u8 sum = 0; 408 u32 i; 409 410 if (!buffer) 411 return 0; 412 413 for (i = 0; i < length; i++) 414 sum += buffer[i]; 415 416 return (u8)(0 - sum); 417 } 418 419 /** 420 * wx_reset_hostif - send reset cmd to fw 421 * @wxhw: pointer to hardware structure 422 * 423 * Sends reset cmd to firmware through the manageability 424 * block. 425 **/ 426 int wx_reset_hostif(struct wx_hw *wxhw) 427 { 428 struct wx_hic_reset reset_cmd; 429 int ret_val = 0; 430 int i; 431 432 reset_cmd.hdr.cmd = FW_RESET_CMD; 433 reset_cmd.hdr.buf_len = FW_RESET_LEN; 434 reset_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 435 reset_cmd.lan_id = wxhw->bus.func; 436 reset_cmd.reset_type = (u16)wxhw->reset_type; 437 reset_cmd.hdr.checksum = 0; 438 reset_cmd.hdr.checksum = wx_calculate_checksum((u8 *)&reset_cmd, 439 (FW_CEM_HDR_LEN + 440 reset_cmd.hdr.buf_len)); 441 442 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 443 ret_val = wx_host_interface_command(wxhw, (u32 *)&reset_cmd, 444 sizeof(reset_cmd), 445 WX_HI_COMMAND_TIMEOUT, 446 true); 447 if (ret_val != 0) 448 continue; 449 450 if (reset_cmd.hdr.cmd_or_resp.ret_status == 451 FW_CEM_RESP_STATUS_SUCCESS) 452 ret_val = 0; 453 else 454 ret_val = -EFAULT; 455 456 break; 457 } 458 459 return ret_val; 460 } 461 EXPORT_SYMBOL(wx_reset_hostif); 462 463 /** 464 * wx_init_eeprom_params - Initialize EEPROM params 465 * @wxhw: pointer to hardware structure 466 * 467 * Initializes the EEPROM parameters wx_eeprom_info within the 468 * wx_hw struct in order to set up EEPROM access. 469 **/ 470 void wx_init_eeprom_params(struct wx_hw *wxhw) 471 { 472 struct wx_eeprom_info *eeprom = &wxhw->eeprom; 473 u16 eeprom_size; 474 u16 data = 0x80; 475 476 if (eeprom->type == wx_eeprom_uninitialized) { 477 eeprom->semaphore_delay = 10; 478 eeprom->type = wx_eeprom_none; 479 480 if (!(rd32(wxhw, WX_SPI_STATUS) & 481 WX_SPI_STATUS_FLASH_BYPASS)) { 482 eeprom->type = wx_flash; 483 484 eeprom_size = 4096; 485 eeprom->word_size = eeprom_size >> 1; 486 487 wx_dbg(wxhw, "Eeprom params: type = %d, size = %d\n", 488 eeprom->type, eeprom->word_size); 489 } 490 } 491 492 if (wxhw->mac.type == wx_mac_sp) { 493 if (wx_read_ee_hostif(wxhw, WX_SW_REGION_PTR, &data)) { 494 wx_err(wxhw, "NVM Read Error\n"); 495 return; 496 } 497 data = data >> 1; 498 } 499 500 eeprom->sw_region_offset = data; 501 } 502 EXPORT_SYMBOL(wx_init_eeprom_params); 503 504 /** 505 * wx_get_mac_addr - Generic get MAC address 506 * @wxhw: pointer to hardware structure 507 * @mac_addr: Adapter MAC address 508 * 509 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 510 * A reset of the adapter must be performed prior to calling this function 511 * in order for the MAC address to have been loaded from the EEPROM into RAR0 512 **/ 513 void wx_get_mac_addr(struct wx_hw *wxhw, u8 *mac_addr) 514 { 515 u32 rar_high; 516 u32 rar_low; 517 u16 i; 518 519 wr32(wxhw, WX_PSR_MAC_SWC_IDX, 0); 520 rar_high = rd32(wxhw, WX_PSR_MAC_SWC_AD_H); 521 rar_low = rd32(wxhw, WX_PSR_MAC_SWC_AD_L); 522 523 for (i = 0; i < 2; i++) 524 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8); 525 526 for (i = 0; i < 4; i++) 527 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8); 528 } 529 EXPORT_SYMBOL(wx_get_mac_addr); 530 531 /** 532 * wx_set_rar - Set Rx address register 533 * @wxhw: pointer to hardware structure 534 * @index: Receive address register to write 535 * @addr: Address to put into receive address register 536 * @pools: VMDq "set" or "pool" index 537 * @enable_addr: set flag that address is active 538 * 539 * Puts an ethernet address into a receive address register. 540 **/ 541 int wx_set_rar(struct wx_hw *wxhw, u32 index, u8 *addr, u64 pools, 542 u32 enable_addr) 543 { 544 u32 rar_entries = wxhw->mac.num_rar_entries; 545 u32 rar_low, rar_high; 546 547 /* Make sure we are using a valid rar index range */ 548 if (index >= rar_entries) { 549 wx_err(wxhw, "RAR index %d is out of range.\n", index); 550 return -EINVAL; 551 } 552 553 /* select the MAC address */ 554 wr32(wxhw, WX_PSR_MAC_SWC_IDX, index); 555 556 /* setup VMDq pool mapping */ 557 wr32(wxhw, WX_PSR_MAC_SWC_VM_L, pools & 0xFFFFFFFF); 558 if (wxhw->mac.type == wx_mac_sp) 559 wr32(wxhw, WX_PSR_MAC_SWC_VM_H, pools >> 32); 560 561 /* HW expects these in little endian so we reverse the byte 562 * order from network order (big endian) to little endian 563 * 564 * Some parts put the VMDq setting in the extra RAH bits, 565 * so save everything except the lower 16 bits that hold part 566 * of the address and the address valid bit. 567 */ 568 rar_low = ((u32)addr[5] | 569 ((u32)addr[4] << 8) | 570 ((u32)addr[3] << 16) | 571 ((u32)addr[2] << 24)); 572 rar_high = ((u32)addr[1] | 573 ((u32)addr[0] << 8)); 574 if (enable_addr != 0) 575 rar_high |= WX_PSR_MAC_SWC_AD_H_AV; 576 577 wr32(wxhw, WX_PSR_MAC_SWC_AD_L, rar_low); 578 wr32m(wxhw, WX_PSR_MAC_SWC_AD_H, 579 (WX_PSR_MAC_SWC_AD_H_AD(~0) | 580 WX_PSR_MAC_SWC_AD_H_ADTYPE(~0) | 581 WX_PSR_MAC_SWC_AD_H_AV), 582 rar_high); 583 584 return 0; 585 } 586 EXPORT_SYMBOL(wx_set_rar); 587 588 /** 589 * wx_clear_rar - Remove Rx address register 590 * @wxhw: pointer to hardware structure 591 * @index: Receive address register to write 592 * 593 * Clears an ethernet address from a receive address register. 594 **/ 595 int wx_clear_rar(struct wx_hw *wxhw, u32 index) 596 { 597 u32 rar_entries = wxhw->mac.num_rar_entries; 598 599 /* Make sure we are using a valid rar index range */ 600 if (index >= rar_entries) { 601 wx_err(wxhw, "RAR index %d is out of range.\n", index); 602 return -EINVAL; 603 } 604 605 /* Some parts put the VMDq setting in the extra RAH bits, 606 * so save everything except the lower 16 bits that hold part 607 * of the address and the address valid bit. 608 */ 609 wr32(wxhw, WX_PSR_MAC_SWC_IDX, index); 610 611 wr32(wxhw, WX_PSR_MAC_SWC_VM_L, 0); 612 wr32(wxhw, WX_PSR_MAC_SWC_VM_H, 0); 613 614 wr32(wxhw, WX_PSR_MAC_SWC_AD_L, 0); 615 wr32m(wxhw, WX_PSR_MAC_SWC_AD_H, 616 (WX_PSR_MAC_SWC_AD_H_AD(~0) | 617 WX_PSR_MAC_SWC_AD_H_ADTYPE(~0) | 618 WX_PSR_MAC_SWC_AD_H_AV), 619 0); 620 621 return 0; 622 } 623 EXPORT_SYMBOL(wx_clear_rar); 624 625 /** 626 * wx_clear_vmdq - Disassociate a VMDq pool index from a rx address 627 * @wxhw: pointer to hardware struct 628 * @rar: receive address register index to disassociate 629 * @vmdq: VMDq pool index to remove from the rar 630 **/ 631 static int wx_clear_vmdq(struct wx_hw *wxhw, u32 rar, u32 __maybe_unused vmdq) 632 { 633 u32 rar_entries = wxhw->mac.num_rar_entries; 634 u32 mpsar_lo, mpsar_hi; 635 636 /* Make sure we are using a valid rar index range */ 637 if (rar >= rar_entries) { 638 wx_err(wxhw, "RAR index %d is out of range.\n", rar); 639 return -EINVAL; 640 } 641 642 wr32(wxhw, WX_PSR_MAC_SWC_IDX, rar); 643 mpsar_lo = rd32(wxhw, WX_PSR_MAC_SWC_VM_L); 644 mpsar_hi = rd32(wxhw, WX_PSR_MAC_SWC_VM_H); 645 646 if (!mpsar_lo && !mpsar_hi) 647 return 0; 648 649 /* was that the last pool using this rar? */ 650 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) 651 wx_clear_rar(wxhw, rar); 652 653 return 0; 654 } 655 656 /** 657 * wx_init_uta_tables - Initialize the Unicast Table Array 658 * @wxhw: pointer to hardware structure 659 **/ 660 static void wx_init_uta_tables(struct wx_hw *wxhw) 661 { 662 int i; 663 664 wx_dbg(wxhw, " Clearing UTA\n"); 665 666 for (i = 0; i < 128; i++) 667 wr32(wxhw, WX_PSR_UC_TBL(i), 0); 668 } 669 670 /** 671 * wx_init_rx_addrs - Initializes receive address filters. 672 * @wxhw: pointer to hardware structure 673 * 674 * Places the MAC address in receive address register 0 and clears the rest 675 * of the receive address registers. Clears the multicast table. Assumes 676 * the receiver is in reset when the routine is called. 677 **/ 678 void wx_init_rx_addrs(struct wx_hw *wxhw) 679 { 680 u32 rar_entries = wxhw->mac.num_rar_entries; 681 u32 psrctl; 682 int i; 683 684 /* If the current mac address is valid, assume it is a software override 685 * to the permanent address. 686 * Otherwise, use the permanent address from the eeprom. 687 */ 688 if (!is_valid_ether_addr(wxhw->mac.addr)) { 689 /* Get the MAC address from the RAR0 for later reference */ 690 wx_get_mac_addr(wxhw, wxhw->mac.addr); 691 wx_dbg(wxhw, "Keeping Current RAR0 Addr = %pM\n", wxhw->mac.addr); 692 } else { 693 /* Setup the receive address. */ 694 wx_dbg(wxhw, "Overriding MAC Address in RAR[0]\n"); 695 wx_dbg(wxhw, "New MAC Addr = %pM\n", wxhw->mac.addr); 696 697 wx_set_rar(wxhw, 0, wxhw->mac.addr, 0, WX_PSR_MAC_SWC_AD_H_AV); 698 699 if (wxhw->mac.type == wx_mac_sp) { 700 /* clear VMDq pool/queue selection for RAR 0 */ 701 wx_clear_vmdq(wxhw, 0, WX_CLEAR_VMDQ_ALL); 702 } 703 } 704 705 /* Zero out the other receive addresses. */ 706 wx_dbg(wxhw, "Clearing RAR[1-%d]\n", rar_entries - 1); 707 for (i = 1; i < rar_entries; i++) { 708 wr32(wxhw, WX_PSR_MAC_SWC_IDX, i); 709 wr32(wxhw, WX_PSR_MAC_SWC_AD_L, 0); 710 wr32(wxhw, WX_PSR_MAC_SWC_AD_H, 0); 711 } 712 713 /* Clear the MTA */ 714 wxhw->addr_ctrl.mta_in_use = 0; 715 psrctl = rd32(wxhw, WX_PSR_CTL); 716 psrctl &= ~(WX_PSR_CTL_MO | WX_PSR_CTL_MFE); 717 psrctl |= wxhw->mac.mc_filter_type << WX_PSR_CTL_MO_SHIFT; 718 wr32(wxhw, WX_PSR_CTL, psrctl); 719 wx_dbg(wxhw, " Clearing MTA\n"); 720 for (i = 0; i < wxhw->mac.mcft_size; i++) 721 wr32(wxhw, WX_PSR_MC_TBL(i), 0); 722 723 wx_init_uta_tables(wxhw); 724 } 725 EXPORT_SYMBOL(wx_init_rx_addrs); 726 727 void wx_disable_rx(struct wx_hw *wxhw) 728 { 729 u32 pfdtxgswc; 730 u32 rxctrl; 731 732 rxctrl = rd32(wxhw, WX_RDB_PB_CTL); 733 if (rxctrl & WX_RDB_PB_CTL_RXEN) { 734 pfdtxgswc = rd32(wxhw, WX_PSR_CTL); 735 if (pfdtxgswc & WX_PSR_CTL_SW_EN) { 736 pfdtxgswc &= ~WX_PSR_CTL_SW_EN; 737 wr32(wxhw, WX_PSR_CTL, pfdtxgswc); 738 wxhw->mac.set_lben = true; 739 } else { 740 wxhw->mac.set_lben = false; 741 } 742 rxctrl &= ~WX_RDB_PB_CTL_RXEN; 743 wr32(wxhw, WX_RDB_PB_CTL, rxctrl); 744 745 if (!(((wxhw->subsystem_device_id & WX_NCSI_MASK) == WX_NCSI_SUP) || 746 ((wxhw->subsystem_device_id & WX_WOL_MASK) == WX_WOL_SUP))) { 747 /* disable mac receiver */ 748 wr32m(wxhw, WX_MAC_RX_CFG, 749 WX_MAC_RX_CFG_RE, 0); 750 } 751 } 752 } 753 EXPORT_SYMBOL(wx_disable_rx); 754 755 /** 756 * wx_disable_pcie_master - Disable PCI-express master access 757 * @wxhw: pointer to hardware structure 758 * 759 * Disables PCI-Express master access and verifies there are no pending 760 * requests. 761 **/ 762 int wx_disable_pcie_master(struct wx_hw *wxhw) 763 { 764 int status = 0; 765 u32 val; 766 767 /* Always set this bit to ensure any future transactions are blocked */ 768 pci_clear_master(wxhw->pdev); 769 770 /* Exit if master requests are blocked */ 771 if (!(rd32(wxhw, WX_PX_TRANSACTION_PENDING))) 772 return 0; 773 774 /* Poll for master request bit to clear */ 775 status = read_poll_timeout(rd32, val, !val, 100, WX_PCI_MASTER_DISABLE_TIMEOUT, 776 false, wxhw, WX_PX_TRANSACTION_PENDING); 777 if (status < 0) 778 wx_err(wxhw, "PCIe transaction pending bit did not clear.\n"); 779 780 return status; 781 } 782 EXPORT_SYMBOL(wx_disable_pcie_master); 783 784 /** 785 * wx_stop_adapter - Generic stop Tx/Rx units 786 * @wxhw: pointer to hardware structure 787 * 788 * Sets the adapter_stopped flag within wx_hw struct. Clears interrupts, 789 * disables transmit and receive units. The adapter_stopped flag is used by 790 * the shared code and drivers to determine if the adapter is in a stopped 791 * state and should not touch the hardware. 792 **/ 793 int wx_stop_adapter(struct wx_hw *wxhw) 794 { 795 u16 i; 796 797 /* Set the adapter_stopped flag so other driver functions stop touching 798 * the hardware 799 */ 800 wxhw->adapter_stopped = true; 801 802 /* Disable the receive unit */ 803 wx_disable_rx(wxhw); 804 805 /* Set interrupt mask to stop interrupts from being generated */ 806 wx_intr_disable(wxhw, WX_INTR_ALL); 807 808 /* Clear any pending interrupts, flush previous writes */ 809 wr32(wxhw, WX_PX_MISC_IC, 0xffffffff); 810 wr32(wxhw, WX_BME_CTL, 0x3); 811 812 /* Disable the transmit unit. Each queue must be disabled. */ 813 for (i = 0; i < wxhw->mac.max_tx_queues; i++) { 814 wr32m(wxhw, WX_PX_TR_CFG(i), 815 WX_PX_TR_CFG_SWFLSH | WX_PX_TR_CFG_ENABLE, 816 WX_PX_TR_CFG_SWFLSH); 817 } 818 819 /* Disable the receive unit by stopping each queue */ 820 for (i = 0; i < wxhw->mac.max_rx_queues; i++) { 821 wr32m(wxhw, WX_PX_RR_CFG(i), 822 WX_PX_RR_CFG_RR_EN, 0); 823 } 824 825 /* flush all queues disables */ 826 WX_WRITE_FLUSH(wxhw); 827 828 /* Prevent the PCI-E bus from hanging by disabling PCI-E master 829 * access and verify no pending requests 830 */ 831 return wx_disable_pcie_master(wxhw); 832 } 833 EXPORT_SYMBOL(wx_stop_adapter); 834 835 void wx_reset_misc(struct wx_hw *wxhw) 836 { 837 int i; 838 839 /* receive packets that size > 2048 */ 840 wr32m(wxhw, WX_MAC_RX_CFG, WX_MAC_RX_CFG_JE, WX_MAC_RX_CFG_JE); 841 842 /* clear counters on read */ 843 wr32m(wxhw, WX_MMC_CONTROL, 844 WX_MMC_CONTROL_RSTONRD, WX_MMC_CONTROL_RSTONRD); 845 846 wr32m(wxhw, WX_MAC_RX_FLOW_CTRL, 847 WX_MAC_RX_FLOW_CTRL_RFE, WX_MAC_RX_FLOW_CTRL_RFE); 848 849 wr32(wxhw, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR); 850 851 wr32m(wxhw, WX_MIS_RST_ST, 852 WX_MIS_RST_ST_RST_INIT, 0x1E00); 853 854 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/ 855 wr32(wxhw, WX_PSR_MNG_FLEX_SEL, 0); 856 for (i = 0; i < 16; i++) { 857 wr32(wxhw, WX_PSR_MNG_FLEX_DW_L(i), 0); 858 wr32(wxhw, WX_PSR_MNG_FLEX_DW_H(i), 0); 859 wr32(wxhw, WX_PSR_MNG_FLEX_MSK(i), 0); 860 } 861 wr32(wxhw, WX_PSR_LAN_FLEX_SEL, 0); 862 for (i = 0; i < 16; i++) { 863 wr32(wxhw, WX_PSR_LAN_FLEX_DW_L(i), 0); 864 wr32(wxhw, WX_PSR_LAN_FLEX_DW_H(i), 0); 865 wr32(wxhw, WX_PSR_LAN_FLEX_MSK(i), 0); 866 } 867 868 /* set pause frame dst mac addr */ 869 wr32(wxhw, WX_RDB_PFCMACDAL, 0xC2000001); 870 wr32(wxhw, WX_RDB_PFCMACDAH, 0x0180); 871 } 872 EXPORT_SYMBOL(wx_reset_misc); 873 874 /** 875 * wx_get_pcie_msix_counts - Gets MSI-X vector count 876 * @wxhw: pointer to hardware structure 877 * @msix_count: number of MSI interrupts that can be obtained 878 * @max_msix_count: number of MSI interrupts that mac need 879 * 880 * Read PCIe configuration space, and get the MSI-X vector count from 881 * the capabilities table. 882 **/ 883 int wx_get_pcie_msix_counts(struct wx_hw *wxhw, u16 *msix_count, u16 max_msix_count) 884 { 885 struct pci_dev *pdev = wxhw->pdev; 886 struct device *dev = &pdev->dev; 887 int pos; 888 889 *msix_count = 1; 890 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 891 if (!pos) { 892 dev_err(dev, "Unable to find MSI-X Capabilities\n"); 893 return -EINVAL; 894 } 895 pci_read_config_word(pdev, 896 pos + PCI_MSIX_FLAGS, 897 msix_count); 898 *msix_count &= WX_PCIE_MSIX_TBL_SZ_MASK; 899 /* MSI-X count is zero-based in HW */ 900 *msix_count += 1; 901 902 if (*msix_count > max_msix_count) 903 *msix_count = max_msix_count; 904 905 return 0; 906 } 907 EXPORT_SYMBOL(wx_get_pcie_msix_counts); 908 909 int wx_sw_init(struct wx_hw *wxhw) 910 { 911 struct pci_dev *pdev = wxhw->pdev; 912 u32 ssid = 0; 913 int err = 0; 914 915 wxhw->vendor_id = pdev->vendor; 916 wxhw->device_id = pdev->device; 917 wxhw->revision_id = pdev->revision; 918 wxhw->oem_svid = pdev->subsystem_vendor; 919 wxhw->oem_ssid = pdev->subsystem_device; 920 wxhw->bus.device = PCI_SLOT(pdev->devfn); 921 wxhw->bus.func = PCI_FUNC(pdev->devfn); 922 923 if (wxhw->oem_svid == PCI_VENDOR_ID_WANGXUN) { 924 wxhw->subsystem_vendor_id = pdev->subsystem_vendor; 925 wxhw->subsystem_device_id = pdev->subsystem_device; 926 } else { 927 err = wx_flash_read_dword(wxhw, 0xfffdc, &ssid); 928 if (!err) 929 wxhw->subsystem_device_id = swab16((u16)ssid); 930 931 return err; 932 } 933 934 return 0; 935 } 936 EXPORT_SYMBOL(wx_sw_init); 937 938 MODULE_LICENSE("GPL"); 939