1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/netdevice.h> 6 #include <linux/if_ether.h> 7 #include <linux/iopoll.h> 8 #include <linux/pci.h> 9 10 #include "wx_type.h" 11 #include "wx_hw.h" 12 13 static void wx_intr_disable(struct wx *wx, u64 qmask) 14 { 15 u32 mask; 16 17 mask = (qmask & 0xFFFFFFFF); 18 if (mask) 19 wr32(wx, WX_PX_IMS(0), mask); 20 21 if (wx->mac.type == wx_mac_sp) { 22 mask = (qmask >> 32); 23 if (mask) 24 wr32(wx, WX_PX_IMS(1), mask); 25 } 26 } 27 28 /* cmd_addr is used for some special command: 29 * 1. to be sector address, when implemented erase sector command 30 * 2. to be flash address when implemented read, write flash address 31 */ 32 static int wx_fmgr_cmd_op(struct wx *wx, u32 cmd, u32 cmd_addr) 33 { 34 u32 cmd_val = 0, val = 0; 35 36 cmd_val = WX_SPI_CMD_CMD(cmd) | 37 WX_SPI_CMD_CLK(WX_SPI_CLK_DIV) | 38 cmd_addr; 39 wr32(wx, WX_SPI_CMD, cmd_val); 40 41 return read_poll_timeout(rd32, val, (val & 0x1), 10, 100000, 42 false, wx, WX_SPI_STATUS); 43 } 44 45 static int wx_flash_read_dword(struct wx *wx, u32 addr, u32 *data) 46 { 47 int ret = 0; 48 49 ret = wx_fmgr_cmd_op(wx, WX_SPI_CMD_READ_DWORD, addr); 50 if (ret < 0) 51 return ret; 52 53 *data = rd32(wx, WX_SPI_DATA); 54 55 return ret; 56 } 57 58 int wx_check_flash_load(struct wx *hw, u32 check_bit) 59 { 60 u32 reg = 0; 61 int err = 0; 62 63 /* if there's flash existing */ 64 if (!(rd32(hw, WX_SPI_STATUS) & 65 WX_SPI_STATUS_FLASH_BYPASS)) { 66 /* wait hw load flash done */ 67 err = read_poll_timeout(rd32, reg, !(reg & check_bit), 20000, 2000000, 68 false, hw, WX_SPI_ILDR_STATUS); 69 if (err < 0) 70 wx_err(hw, "Check flash load timeout.\n"); 71 } 72 73 return err; 74 } 75 EXPORT_SYMBOL(wx_check_flash_load); 76 77 void wx_control_hw(struct wx *wx, bool drv) 78 { 79 /* True : Let firmware know the driver has taken over 80 * False : Let firmware take over control of hw 81 */ 82 wr32m(wx, WX_CFG_PORT_CTL, WX_CFG_PORT_CTL_DRV_LOAD, 83 drv ? WX_CFG_PORT_CTL_DRV_LOAD : 0); 84 } 85 EXPORT_SYMBOL(wx_control_hw); 86 87 /** 88 * wx_mng_present - returns 0 when management capability is present 89 * @wx: pointer to hardware structure 90 */ 91 int wx_mng_present(struct wx *wx) 92 { 93 u32 fwsm; 94 95 fwsm = rd32(wx, WX_MIS_ST); 96 if (fwsm & WX_MIS_ST_MNG_INIT_DN) 97 return 0; 98 else 99 return -EACCES; 100 } 101 EXPORT_SYMBOL(wx_mng_present); 102 103 /* Software lock to be held while software semaphore is being accessed. */ 104 static DEFINE_MUTEX(wx_sw_sync_lock); 105 106 /** 107 * wx_release_sw_sync - Release SW semaphore 108 * @wx: pointer to hardware structure 109 * @mask: Mask to specify which semaphore to release 110 * 111 * Releases the SW semaphore for the specified 112 * function (CSR, PHY0, PHY1, EEPROM, Flash) 113 **/ 114 static void wx_release_sw_sync(struct wx *wx, u32 mask) 115 { 116 mutex_lock(&wx_sw_sync_lock); 117 wr32m(wx, WX_MNG_SWFW_SYNC, mask, 0); 118 mutex_unlock(&wx_sw_sync_lock); 119 } 120 121 /** 122 * wx_acquire_sw_sync - Acquire SW semaphore 123 * @wx: pointer to hardware structure 124 * @mask: Mask to specify which semaphore to acquire 125 * 126 * Acquires the SW semaphore for the specified 127 * function (CSR, PHY0, PHY1, EEPROM, Flash) 128 **/ 129 static int wx_acquire_sw_sync(struct wx *wx, u32 mask) 130 { 131 u32 sem = 0; 132 int ret = 0; 133 134 mutex_lock(&wx_sw_sync_lock); 135 ret = read_poll_timeout(rd32, sem, !(sem & mask), 136 5000, 2000000, false, wx, WX_MNG_SWFW_SYNC); 137 if (!ret) { 138 sem |= mask; 139 wr32(wx, WX_MNG_SWFW_SYNC, sem); 140 } else { 141 wx_err(wx, "SW Semaphore not granted: 0x%x.\n", sem); 142 } 143 mutex_unlock(&wx_sw_sync_lock); 144 145 return ret; 146 } 147 148 /** 149 * wx_host_interface_command - Issue command to manageability block 150 * @wx: pointer to the HW structure 151 * @buffer: contains the command to write and where the return status will 152 * be placed 153 * @length: length of buffer, must be multiple of 4 bytes 154 * @timeout: time in ms to wait for command completion 155 * @return_data: read and return data from the buffer (true) or not (false) 156 * Needed because FW structures are big endian and decoding of 157 * these fields can be 8 bit or 16 bit based on command. Decoding 158 * is not easily understood without making a table of commands. 159 * So we will leave this up to the caller to read back the data 160 * in these cases. 161 **/ 162 int wx_host_interface_command(struct wx *wx, u32 *buffer, 163 u32 length, u32 timeout, bool return_data) 164 { 165 u32 hdr_size = sizeof(struct wx_hic_hdr); 166 u32 hicr, i, bi, buf[64] = {}; 167 int status = 0; 168 u32 dword_len; 169 u16 buf_len; 170 171 if (length == 0 || length > WX_HI_MAX_BLOCK_BYTE_LENGTH) { 172 wx_err(wx, "Buffer length failure buffersize=%d.\n", length); 173 return -EINVAL; 174 } 175 176 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_MB); 177 if (status != 0) 178 return status; 179 180 /* Calculate length in DWORDs. We must be DWORD aligned */ 181 if ((length % (sizeof(u32))) != 0) { 182 wx_err(wx, "Buffer length failure, not aligned to dword"); 183 status = -EINVAL; 184 goto rel_out; 185 } 186 187 dword_len = length >> 2; 188 189 /* The device driver writes the relevant command block 190 * into the ram area. 191 */ 192 for (i = 0; i < dword_len; i++) { 193 wr32a(wx, WX_MNG_MBOX, i, (__force u32)cpu_to_le32(buffer[i])); 194 /* write flush */ 195 buf[i] = rd32a(wx, WX_MNG_MBOX, i); 196 } 197 /* Setting this bit tells the ARC that a new command is pending. */ 198 wr32m(wx, WX_MNG_MBOX_CTL, 199 WX_MNG_MBOX_CTL_SWRDY, WX_MNG_MBOX_CTL_SWRDY); 200 201 status = read_poll_timeout(rd32, hicr, hicr & WX_MNG_MBOX_CTL_FWRDY, 1000, 202 timeout * 1000, false, wx, WX_MNG_MBOX_CTL); 203 204 /* Check command completion */ 205 if (status) { 206 wx_dbg(wx, "Command has failed with no status valid.\n"); 207 208 buf[0] = rd32(wx, WX_MNG_MBOX); 209 if ((buffer[0] & 0xff) != (~buf[0] >> 24)) { 210 status = -EINVAL; 211 goto rel_out; 212 } 213 if ((buf[0] & 0xff0000) >> 16 == 0x80) { 214 wx_dbg(wx, "It's unknown cmd.\n"); 215 status = -EINVAL; 216 goto rel_out; 217 } 218 219 wx_dbg(wx, "write value:\n"); 220 for (i = 0; i < dword_len; i++) 221 wx_dbg(wx, "%x ", buffer[i]); 222 wx_dbg(wx, "read value:\n"); 223 for (i = 0; i < dword_len; i++) 224 wx_dbg(wx, "%x ", buf[i]); 225 } 226 227 if (!return_data) 228 goto rel_out; 229 230 /* Calculate length in DWORDs */ 231 dword_len = hdr_size >> 2; 232 233 /* first pull in the header so we know the buffer length */ 234 for (bi = 0; bi < dword_len; bi++) { 235 buffer[bi] = rd32a(wx, WX_MNG_MBOX, bi); 236 le32_to_cpus(&buffer[bi]); 237 } 238 239 /* If there is any thing in data position pull it in */ 240 buf_len = ((struct wx_hic_hdr *)buffer)->buf_len; 241 if (buf_len == 0) 242 goto rel_out; 243 244 if (length < buf_len + hdr_size) { 245 wx_err(wx, "Buffer not large enough for reply message.\n"); 246 status = -EFAULT; 247 goto rel_out; 248 } 249 250 /* Calculate length in DWORDs, add 3 for odd lengths */ 251 dword_len = (buf_len + 3) >> 2; 252 253 /* Pull in the rest of the buffer (bi is where we left off) */ 254 for (; bi <= dword_len; bi++) { 255 buffer[bi] = rd32a(wx, WX_MNG_MBOX, bi); 256 le32_to_cpus(&buffer[bi]); 257 } 258 259 rel_out: 260 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_MB); 261 return status; 262 } 263 EXPORT_SYMBOL(wx_host_interface_command); 264 265 /** 266 * wx_read_ee_hostif_data - Read EEPROM word using a host interface cmd 267 * assuming that the semaphore is already obtained. 268 * @wx: pointer to hardware structure 269 * @offset: offset of word in the EEPROM to read 270 * @data: word read from the EEPROM 271 * 272 * Reads a 16 bit word from the EEPROM using the hostif. 273 **/ 274 static int wx_read_ee_hostif_data(struct wx *wx, u16 offset, u16 *data) 275 { 276 struct wx_hic_read_shadow_ram buffer; 277 int status; 278 279 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 280 buffer.hdr.req.buf_lenh = 0; 281 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 282 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 283 284 /* convert offset from words to bytes */ 285 buffer.address = (__force u32)cpu_to_be32(offset * 2); 286 /* one word */ 287 buffer.length = (__force u16)cpu_to_be16(sizeof(u16)); 288 289 status = wx_host_interface_command(wx, (u32 *)&buffer, sizeof(buffer), 290 WX_HI_COMMAND_TIMEOUT, false); 291 292 if (status != 0) 293 return status; 294 295 *data = (u16)rd32a(wx, WX_MNG_MBOX, FW_NVM_DATA_OFFSET); 296 297 return status; 298 } 299 300 /** 301 * wx_read_ee_hostif - Read EEPROM word using a host interface cmd 302 * @wx: pointer to hardware structure 303 * @offset: offset of word in the EEPROM to read 304 * @data: word read from the EEPROM 305 * 306 * Reads a 16 bit word from the EEPROM using the hostif. 307 **/ 308 int wx_read_ee_hostif(struct wx *wx, u16 offset, u16 *data) 309 { 310 int status = 0; 311 312 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 313 if (status == 0) { 314 status = wx_read_ee_hostif_data(wx, offset, data); 315 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 316 } 317 318 return status; 319 } 320 EXPORT_SYMBOL(wx_read_ee_hostif); 321 322 /** 323 * wx_read_ee_hostif_buffer- Read EEPROM word(s) using hostif 324 * @wx: pointer to hardware structure 325 * @offset: offset of word in the EEPROM to read 326 * @words: number of words 327 * @data: word(s) read from the EEPROM 328 * 329 * Reads a 16 bit word(s) from the EEPROM using the hostif. 330 **/ 331 int wx_read_ee_hostif_buffer(struct wx *wx, 332 u16 offset, u16 words, u16 *data) 333 { 334 struct wx_hic_read_shadow_ram buffer; 335 u32 current_word = 0; 336 u16 words_to_read; 337 u32 value = 0; 338 int status; 339 u32 i; 340 341 /* Take semaphore for the entire operation. */ 342 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 343 if (status != 0) 344 return status; 345 346 while (words) { 347 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 348 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 349 else 350 words_to_read = words; 351 352 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 353 buffer.hdr.req.buf_lenh = 0; 354 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 355 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 356 357 /* convert offset from words to bytes */ 358 buffer.address = (__force u32)cpu_to_be32((offset + current_word) * 2); 359 buffer.length = (__force u16)cpu_to_be16(words_to_read * 2); 360 361 status = wx_host_interface_command(wx, (u32 *)&buffer, 362 sizeof(buffer), 363 WX_HI_COMMAND_TIMEOUT, 364 false); 365 366 if (status != 0) { 367 wx_err(wx, "Host interface command failed\n"); 368 goto out; 369 } 370 371 for (i = 0; i < words_to_read; i++) { 372 u32 reg = WX_MNG_MBOX + (FW_NVM_DATA_OFFSET << 2) + 2 * i; 373 374 value = rd32(wx, reg); 375 data[current_word] = (u16)(value & 0xffff); 376 current_word++; 377 i++; 378 if (i < words_to_read) { 379 value >>= 16; 380 data[current_word] = (u16)(value & 0xffff); 381 current_word++; 382 } 383 } 384 words -= words_to_read; 385 } 386 387 out: 388 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 389 return status; 390 } 391 EXPORT_SYMBOL(wx_read_ee_hostif_buffer); 392 393 /** 394 * wx_calculate_checksum - Calculate checksum for buffer 395 * @buffer: pointer to EEPROM 396 * @length: size of EEPROM to calculate a checksum for 397 * Calculates the checksum for some buffer on a specified length. The 398 * checksum calculated is returned. 399 **/ 400 static u8 wx_calculate_checksum(u8 *buffer, u32 length) 401 { 402 u8 sum = 0; 403 u32 i; 404 405 if (!buffer) 406 return 0; 407 408 for (i = 0; i < length; i++) 409 sum += buffer[i]; 410 411 return (u8)(0 - sum); 412 } 413 414 /** 415 * wx_reset_hostif - send reset cmd to fw 416 * @wx: pointer to hardware structure 417 * 418 * Sends reset cmd to firmware through the manageability 419 * block. 420 **/ 421 int wx_reset_hostif(struct wx *wx) 422 { 423 struct wx_hic_reset reset_cmd; 424 int ret_val = 0; 425 int i; 426 427 reset_cmd.hdr.cmd = FW_RESET_CMD; 428 reset_cmd.hdr.buf_len = FW_RESET_LEN; 429 reset_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 430 reset_cmd.lan_id = wx->bus.func; 431 reset_cmd.reset_type = (u16)wx->reset_type; 432 reset_cmd.hdr.checksum = 0; 433 reset_cmd.hdr.checksum = wx_calculate_checksum((u8 *)&reset_cmd, 434 (FW_CEM_HDR_LEN + 435 reset_cmd.hdr.buf_len)); 436 437 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 438 ret_val = wx_host_interface_command(wx, (u32 *)&reset_cmd, 439 sizeof(reset_cmd), 440 WX_HI_COMMAND_TIMEOUT, 441 true); 442 if (ret_val != 0) 443 continue; 444 445 if (reset_cmd.hdr.cmd_or_resp.ret_status == 446 FW_CEM_RESP_STATUS_SUCCESS) 447 ret_val = 0; 448 else 449 ret_val = -EFAULT; 450 451 break; 452 } 453 454 return ret_val; 455 } 456 EXPORT_SYMBOL(wx_reset_hostif); 457 458 /** 459 * wx_init_eeprom_params - Initialize EEPROM params 460 * @wx: pointer to hardware structure 461 * 462 * Initializes the EEPROM parameters wx_eeprom_info within the 463 * wx_hw struct in order to set up EEPROM access. 464 **/ 465 void wx_init_eeprom_params(struct wx *wx) 466 { 467 struct wx_eeprom_info *eeprom = &wx->eeprom; 468 u16 eeprom_size; 469 u16 data = 0x80; 470 471 if (eeprom->type == wx_eeprom_uninitialized) { 472 eeprom->semaphore_delay = 10; 473 eeprom->type = wx_eeprom_none; 474 475 if (!(rd32(wx, WX_SPI_STATUS) & 476 WX_SPI_STATUS_FLASH_BYPASS)) { 477 eeprom->type = wx_flash; 478 479 eeprom_size = 4096; 480 eeprom->word_size = eeprom_size >> 1; 481 482 wx_dbg(wx, "Eeprom params: type = %d, size = %d\n", 483 eeprom->type, eeprom->word_size); 484 } 485 } 486 487 if (wx->mac.type == wx_mac_sp) { 488 if (wx_read_ee_hostif(wx, WX_SW_REGION_PTR, &data)) { 489 wx_err(wx, "NVM Read Error\n"); 490 return; 491 } 492 data = data >> 1; 493 } 494 495 eeprom->sw_region_offset = data; 496 } 497 EXPORT_SYMBOL(wx_init_eeprom_params); 498 499 /** 500 * wx_get_mac_addr - Generic get MAC address 501 * @wx: pointer to hardware structure 502 * @mac_addr: Adapter MAC address 503 * 504 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 505 * A reset of the adapter must be performed prior to calling this function 506 * in order for the MAC address to have been loaded from the EEPROM into RAR0 507 **/ 508 void wx_get_mac_addr(struct wx *wx, u8 *mac_addr) 509 { 510 u32 rar_high; 511 u32 rar_low; 512 u16 i; 513 514 wr32(wx, WX_PSR_MAC_SWC_IDX, 0); 515 rar_high = rd32(wx, WX_PSR_MAC_SWC_AD_H); 516 rar_low = rd32(wx, WX_PSR_MAC_SWC_AD_L); 517 518 for (i = 0; i < 2; i++) 519 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8); 520 521 for (i = 0; i < 4; i++) 522 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8); 523 } 524 EXPORT_SYMBOL(wx_get_mac_addr); 525 526 /** 527 * wx_set_rar - Set Rx address register 528 * @wx: pointer to hardware structure 529 * @index: Receive address register to write 530 * @addr: Address to put into receive address register 531 * @pools: VMDq "set" or "pool" index 532 * @enable_addr: set flag that address is active 533 * 534 * Puts an ethernet address into a receive address register. 535 **/ 536 static int wx_set_rar(struct wx *wx, u32 index, u8 *addr, u64 pools, 537 u32 enable_addr) 538 { 539 u32 rar_entries = wx->mac.num_rar_entries; 540 u32 rar_low, rar_high; 541 542 /* Make sure we are using a valid rar index range */ 543 if (index >= rar_entries) { 544 wx_err(wx, "RAR index %d is out of range.\n", index); 545 return -EINVAL; 546 } 547 548 /* select the MAC address */ 549 wr32(wx, WX_PSR_MAC_SWC_IDX, index); 550 551 /* setup VMDq pool mapping */ 552 wr32(wx, WX_PSR_MAC_SWC_VM_L, pools & 0xFFFFFFFF); 553 if (wx->mac.type == wx_mac_sp) 554 wr32(wx, WX_PSR_MAC_SWC_VM_H, pools >> 32); 555 556 /* HW expects these in little endian so we reverse the byte 557 * order from network order (big endian) to little endian 558 * 559 * Some parts put the VMDq setting in the extra RAH bits, 560 * so save everything except the lower 16 bits that hold part 561 * of the address and the address valid bit. 562 */ 563 rar_low = ((u32)addr[5] | 564 ((u32)addr[4] << 8) | 565 ((u32)addr[3] << 16) | 566 ((u32)addr[2] << 24)); 567 rar_high = ((u32)addr[1] | 568 ((u32)addr[0] << 8)); 569 if (enable_addr != 0) 570 rar_high |= WX_PSR_MAC_SWC_AD_H_AV; 571 572 wr32(wx, WX_PSR_MAC_SWC_AD_L, rar_low); 573 wr32m(wx, WX_PSR_MAC_SWC_AD_H, 574 (WX_PSR_MAC_SWC_AD_H_AD(U16_MAX) | 575 WX_PSR_MAC_SWC_AD_H_ADTYPE(1) | 576 WX_PSR_MAC_SWC_AD_H_AV), 577 rar_high); 578 579 return 0; 580 } 581 582 /** 583 * wx_clear_rar - Remove Rx address register 584 * @wx: pointer to hardware structure 585 * @index: Receive address register to write 586 * 587 * Clears an ethernet address from a receive address register. 588 **/ 589 static int wx_clear_rar(struct wx *wx, u32 index) 590 { 591 u32 rar_entries = wx->mac.num_rar_entries; 592 593 /* Make sure we are using a valid rar index range */ 594 if (index >= rar_entries) { 595 wx_err(wx, "RAR index %d is out of range.\n", index); 596 return -EINVAL; 597 } 598 599 /* Some parts put the VMDq setting in the extra RAH bits, 600 * so save everything except the lower 16 bits that hold part 601 * of the address and the address valid bit. 602 */ 603 wr32(wx, WX_PSR_MAC_SWC_IDX, index); 604 605 wr32(wx, WX_PSR_MAC_SWC_VM_L, 0); 606 wr32(wx, WX_PSR_MAC_SWC_VM_H, 0); 607 608 wr32(wx, WX_PSR_MAC_SWC_AD_L, 0); 609 wr32m(wx, WX_PSR_MAC_SWC_AD_H, 610 (WX_PSR_MAC_SWC_AD_H_AD(U16_MAX) | 611 WX_PSR_MAC_SWC_AD_H_ADTYPE(1) | 612 WX_PSR_MAC_SWC_AD_H_AV), 613 0); 614 615 return 0; 616 } 617 618 /** 619 * wx_clear_vmdq - Disassociate a VMDq pool index from a rx address 620 * @wx: pointer to hardware struct 621 * @rar: receive address register index to disassociate 622 * @vmdq: VMDq pool index to remove from the rar 623 **/ 624 static int wx_clear_vmdq(struct wx *wx, u32 rar, u32 __maybe_unused vmdq) 625 { 626 u32 rar_entries = wx->mac.num_rar_entries; 627 u32 mpsar_lo, mpsar_hi; 628 629 /* Make sure we are using a valid rar index range */ 630 if (rar >= rar_entries) { 631 wx_err(wx, "RAR index %d is out of range.\n", rar); 632 return -EINVAL; 633 } 634 635 wr32(wx, WX_PSR_MAC_SWC_IDX, rar); 636 mpsar_lo = rd32(wx, WX_PSR_MAC_SWC_VM_L); 637 mpsar_hi = rd32(wx, WX_PSR_MAC_SWC_VM_H); 638 639 if (!mpsar_lo && !mpsar_hi) 640 return 0; 641 642 /* was that the last pool using this rar? */ 643 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) 644 wx_clear_rar(wx, rar); 645 646 return 0; 647 } 648 649 /** 650 * wx_init_uta_tables - Initialize the Unicast Table Array 651 * @wx: pointer to hardware structure 652 **/ 653 static void wx_init_uta_tables(struct wx *wx) 654 { 655 int i; 656 657 wx_dbg(wx, " Clearing UTA\n"); 658 659 for (i = 0; i < 128; i++) 660 wr32(wx, WX_PSR_UC_TBL(i), 0); 661 } 662 663 /** 664 * wx_init_rx_addrs - Initializes receive address filters. 665 * @wx: pointer to hardware structure 666 * 667 * Places the MAC address in receive address register 0 and clears the rest 668 * of the receive address registers. Clears the multicast table. Assumes 669 * the receiver is in reset when the routine is called. 670 **/ 671 void wx_init_rx_addrs(struct wx *wx) 672 { 673 u32 rar_entries = wx->mac.num_rar_entries; 674 u32 psrctl; 675 int i; 676 677 /* If the current mac address is valid, assume it is a software override 678 * to the permanent address. 679 * Otherwise, use the permanent address from the eeprom. 680 */ 681 if (!is_valid_ether_addr(wx->mac.addr)) { 682 /* Get the MAC address from the RAR0 for later reference */ 683 wx_get_mac_addr(wx, wx->mac.addr); 684 wx_dbg(wx, "Keeping Current RAR0 Addr = %pM\n", wx->mac.addr); 685 } else { 686 /* Setup the receive address. */ 687 wx_dbg(wx, "Overriding MAC Address in RAR[0]\n"); 688 wx_dbg(wx, "New MAC Addr = %pM\n", wx->mac.addr); 689 690 wx_set_rar(wx, 0, wx->mac.addr, 0, WX_PSR_MAC_SWC_AD_H_AV); 691 692 if (wx->mac.type == wx_mac_sp) { 693 /* clear VMDq pool/queue selection for RAR 0 */ 694 wx_clear_vmdq(wx, 0, WX_CLEAR_VMDQ_ALL); 695 } 696 } 697 698 /* Zero out the other receive addresses. */ 699 wx_dbg(wx, "Clearing RAR[1-%d]\n", rar_entries - 1); 700 for (i = 1; i < rar_entries; i++) { 701 wr32(wx, WX_PSR_MAC_SWC_IDX, i); 702 wr32(wx, WX_PSR_MAC_SWC_AD_L, 0); 703 wr32(wx, WX_PSR_MAC_SWC_AD_H, 0); 704 } 705 706 /* Clear the MTA */ 707 wx->addr_ctrl.mta_in_use = 0; 708 psrctl = rd32(wx, WX_PSR_CTL); 709 psrctl &= ~(WX_PSR_CTL_MO | WX_PSR_CTL_MFE); 710 psrctl |= wx->mac.mc_filter_type << WX_PSR_CTL_MO_SHIFT; 711 wr32(wx, WX_PSR_CTL, psrctl); 712 wx_dbg(wx, " Clearing MTA\n"); 713 for (i = 0; i < wx->mac.mcft_size; i++) 714 wr32(wx, WX_PSR_MC_TBL(i), 0); 715 716 wx_init_uta_tables(wx); 717 } 718 EXPORT_SYMBOL(wx_init_rx_addrs); 719 720 static void wx_sync_mac_table(struct wx *wx) 721 { 722 int i; 723 724 for (i = 0; i < wx->mac.num_rar_entries; i++) { 725 if (wx->mac_table[i].state & WX_MAC_STATE_MODIFIED) { 726 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) { 727 wx_set_rar(wx, i, 728 wx->mac_table[i].addr, 729 wx->mac_table[i].pools, 730 WX_PSR_MAC_SWC_AD_H_AV); 731 } else { 732 wx_clear_rar(wx, i); 733 } 734 wx->mac_table[i].state &= ~(WX_MAC_STATE_MODIFIED); 735 } 736 } 737 } 738 739 /* this function destroys the first RAR entry */ 740 void wx_mac_set_default_filter(struct wx *wx, u8 *addr) 741 { 742 memcpy(&wx->mac_table[0].addr, addr, ETH_ALEN); 743 wx->mac_table[0].pools = 1ULL; 744 wx->mac_table[0].state = (WX_MAC_STATE_DEFAULT | WX_MAC_STATE_IN_USE); 745 wx_set_rar(wx, 0, wx->mac_table[0].addr, 746 wx->mac_table[0].pools, 747 WX_PSR_MAC_SWC_AD_H_AV); 748 } 749 EXPORT_SYMBOL(wx_mac_set_default_filter); 750 751 void wx_flush_sw_mac_table(struct wx *wx) 752 { 753 u32 i; 754 755 for (i = 0; i < wx->mac.num_rar_entries; i++) { 756 if (!(wx->mac_table[i].state & WX_MAC_STATE_IN_USE)) 757 continue; 758 759 wx->mac_table[i].state |= WX_MAC_STATE_MODIFIED; 760 wx->mac_table[i].state &= ~WX_MAC_STATE_IN_USE; 761 memset(wx->mac_table[i].addr, 0, ETH_ALEN); 762 wx->mac_table[i].pools = 0; 763 } 764 wx_sync_mac_table(wx); 765 } 766 EXPORT_SYMBOL(wx_flush_sw_mac_table); 767 768 static int wx_del_mac_filter(struct wx *wx, u8 *addr, u16 pool) 769 { 770 u32 i; 771 772 if (is_zero_ether_addr(addr)) 773 return -EINVAL; 774 775 /* search table for addr, if found, set to 0 and sync */ 776 for (i = 0; i < wx->mac.num_rar_entries; i++) { 777 if (!ether_addr_equal(addr, wx->mac_table[i].addr)) 778 continue; 779 780 wx->mac_table[i].state |= WX_MAC_STATE_MODIFIED; 781 wx->mac_table[i].pools &= ~(1ULL << pool); 782 if (!wx->mac_table[i].pools) { 783 wx->mac_table[i].state &= ~WX_MAC_STATE_IN_USE; 784 memset(wx->mac_table[i].addr, 0, ETH_ALEN); 785 } 786 wx_sync_mac_table(wx); 787 return 0; 788 } 789 return -ENOMEM; 790 } 791 792 /** 793 * wx_set_mac - Change the Ethernet Address of the NIC 794 * @netdev: network interface device structure 795 * @p: pointer to an address structure 796 * 797 * Returns 0 on success, negative on failure 798 **/ 799 int wx_set_mac(struct net_device *netdev, void *p) 800 { 801 struct wx *wx = netdev_priv(netdev); 802 struct sockaddr *addr = p; 803 int retval; 804 805 retval = eth_prepare_mac_addr_change(netdev, addr); 806 if (retval) 807 return retval; 808 809 wx_del_mac_filter(wx, wx->mac.addr, 0); 810 eth_hw_addr_set(netdev, addr->sa_data); 811 memcpy(wx->mac.addr, addr->sa_data, netdev->addr_len); 812 813 wx_mac_set_default_filter(wx, wx->mac.addr); 814 815 return 0; 816 } 817 EXPORT_SYMBOL(wx_set_mac); 818 819 void wx_disable_rx(struct wx *wx) 820 { 821 u32 pfdtxgswc; 822 u32 rxctrl; 823 824 rxctrl = rd32(wx, WX_RDB_PB_CTL); 825 if (rxctrl & WX_RDB_PB_CTL_RXEN) { 826 pfdtxgswc = rd32(wx, WX_PSR_CTL); 827 if (pfdtxgswc & WX_PSR_CTL_SW_EN) { 828 pfdtxgswc &= ~WX_PSR_CTL_SW_EN; 829 wr32(wx, WX_PSR_CTL, pfdtxgswc); 830 wx->mac.set_lben = true; 831 } else { 832 wx->mac.set_lben = false; 833 } 834 rxctrl &= ~WX_RDB_PB_CTL_RXEN; 835 wr32(wx, WX_RDB_PB_CTL, rxctrl); 836 837 if (!(((wx->subsystem_device_id & WX_NCSI_MASK) == WX_NCSI_SUP) || 838 ((wx->subsystem_device_id & WX_WOL_MASK) == WX_WOL_SUP))) { 839 /* disable mac receiver */ 840 wr32m(wx, WX_MAC_RX_CFG, 841 WX_MAC_RX_CFG_RE, 0); 842 } 843 } 844 } 845 EXPORT_SYMBOL(wx_disable_rx); 846 847 /** 848 * wx_disable_pcie_master - Disable PCI-express master access 849 * @wx: pointer to hardware structure 850 * 851 * Disables PCI-Express master access and verifies there are no pending 852 * requests. 853 **/ 854 int wx_disable_pcie_master(struct wx *wx) 855 { 856 int status = 0; 857 u32 val; 858 859 /* Always set this bit to ensure any future transactions are blocked */ 860 pci_clear_master(wx->pdev); 861 862 /* Exit if master requests are blocked */ 863 if (!(rd32(wx, WX_PX_TRANSACTION_PENDING))) 864 return 0; 865 866 /* Poll for master request bit to clear */ 867 status = read_poll_timeout(rd32, val, !val, 100, WX_PCI_MASTER_DISABLE_TIMEOUT, 868 false, wx, WX_PX_TRANSACTION_PENDING); 869 if (status < 0) 870 wx_err(wx, "PCIe transaction pending bit did not clear.\n"); 871 872 return status; 873 } 874 EXPORT_SYMBOL(wx_disable_pcie_master); 875 876 /** 877 * wx_stop_adapter - Generic stop Tx/Rx units 878 * @wx: pointer to hardware structure 879 * 880 * Sets the adapter_stopped flag within wx_hw struct. Clears interrupts, 881 * disables transmit and receive units. The adapter_stopped flag is used by 882 * the shared code and drivers to determine if the adapter is in a stopped 883 * state and should not touch the hardware. 884 **/ 885 int wx_stop_adapter(struct wx *wx) 886 { 887 u16 i; 888 889 /* Set the adapter_stopped flag so other driver functions stop touching 890 * the hardware 891 */ 892 wx->adapter_stopped = true; 893 894 /* Disable the receive unit */ 895 wx_disable_rx(wx); 896 897 /* Set interrupt mask to stop interrupts from being generated */ 898 wx_intr_disable(wx, WX_INTR_ALL); 899 900 /* Clear any pending interrupts, flush previous writes */ 901 wr32(wx, WX_PX_MISC_IC, 0xffffffff); 902 wr32(wx, WX_BME_CTL, 0x3); 903 904 /* Disable the transmit unit. Each queue must be disabled. */ 905 for (i = 0; i < wx->mac.max_tx_queues; i++) { 906 wr32m(wx, WX_PX_TR_CFG(i), 907 WX_PX_TR_CFG_SWFLSH | WX_PX_TR_CFG_ENABLE, 908 WX_PX_TR_CFG_SWFLSH); 909 } 910 911 /* Disable the receive unit by stopping each queue */ 912 for (i = 0; i < wx->mac.max_rx_queues; i++) { 913 wr32m(wx, WX_PX_RR_CFG(i), 914 WX_PX_RR_CFG_RR_EN, 0); 915 } 916 917 /* flush all queues disables */ 918 WX_WRITE_FLUSH(wx); 919 920 /* Prevent the PCI-E bus from hanging by disabling PCI-E master 921 * access and verify no pending requests 922 */ 923 return wx_disable_pcie_master(wx); 924 } 925 EXPORT_SYMBOL(wx_stop_adapter); 926 927 void wx_reset_misc(struct wx *wx) 928 { 929 int i; 930 931 /* receive packets that size > 2048 */ 932 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_JE, WX_MAC_RX_CFG_JE); 933 934 /* clear counters on read */ 935 wr32m(wx, WX_MMC_CONTROL, 936 WX_MMC_CONTROL_RSTONRD, WX_MMC_CONTROL_RSTONRD); 937 938 wr32m(wx, WX_MAC_RX_FLOW_CTRL, 939 WX_MAC_RX_FLOW_CTRL_RFE, WX_MAC_RX_FLOW_CTRL_RFE); 940 941 wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR); 942 943 wr32m(wx, WX_MIS_RST_ST, 944 WX_MIS_RST_ST_RST_INIT, 0x1E00); 945 946 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/ 947 wr32(wx, WX_PSR_MNG_FLEX_SEL, 0); 948 for (i = 0; i < 16; i++) { 949 wr32(wx, WX_PSR_MNG_FLEX_DW_L(i), 0); 950 wr32(wx, WX_PSR_MNG_FLEX_DW_H(i), 0); 951 wr32(wx, WX_PSR_MNG_FLEX_MSK(i), 0); 952 } 953 wr32(wx, WX_PSR_LAN_FLEX_SEL, 0); 954 for (i = 0; i < 16; i++) { 955 wr32(wx, WX_PSR_LAN_FLEX_DW_L(i), 0); 956 wr32(wx, WX_PSR_LAN_FLEX_DW_H(i), 0); 957 wr32(wx, WX_PSR_LAN_FLEX_MSK(i), 0); 958 } 959 960 /* set pause frame dst mac addr */ 961 wr32(wx, WX_RDB_PFCMACDAL, 0xC2000001); 962 wr32(wx, WX_RDB_PFCMACDAH, 0x0180); 963 } 964 EXPORT_SYMBOL(wx_reset_misc); 965 966 /** 967 * wx_get_pcie_msix_counts - Gets MSI-X vector count 968 * @wx: pointer to hardware structure 969 * @msix_count: number of MSI interrupts that can be obtained 970 * @max_msix_count: number of MSI interrupts that mac need 971 * 972 * Read PCIe configuration space, and get the MSI-X vector count from 973 * the capabilities table. 974 **/ 975 int wx_get_pcie_msix_counts(struct wx *wx, u16 *msix_count, u16 max_msix_count) 976 { 977 struct pci_dev *pdev = wx->pdev; 978 struct device *dev = &pdev->dev; 979 int pos; 980 981 *msix_count = 1; 982 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 983 if (!pos) { 984 dev_err(dev, "Unable to find MSI-X Capabilities\n"); 985 return -EINVAL; 986 } 987 pci_read_config_word(pdev, 988 pos + PCI_MSIX_FLAGS, 989 msix_count); 990 *msix_count &= WX_PCIE_MSIX_TBL_SZ_MASK; 991 /* MSI-X count is zero-based in HW */ 992 *msix_count += 1; 993 994 if (*msix_count > max_msix_count) 995 *msix_count = max_msix_count; 996 997 return 0; 998 } 999 EXPORT_SYMBOL(wx_get_pcie_msix_counts); 1000 1001 int wx_sw_init(struct wx *wx) 1002 { 1003 struct pci_dev *pdev = wx->pdev; 1004 u32 ssid = 0; 1005 int err = 0; 1006 1007 wx->vendor_id = pdev->vendor; 1008 wx->device_id = pdev->device; 1009 wx->revision_id = pdev->revision; 1010 wx->oem_svid = pdev->subsystem_vendor; 1011 wx->oem_ssid = pdev->subsystem_device; 1012 wx->bus.device = PCI_SLOT(pdev->devfn); 1013 wx->bus.func = PCI_FUNC(pdev->devfn); 1014 1015 if (wx->oem_svid == PCI_VENDOR_ID_WANGXUN) { 1016 wx->subsystem_vendor_id = pdev->subsystem_vendor; 1017 wx->subsystem_device_id = pdev->subsystem_device; 1018 } else { 1019 err = wx_flash_read_dword(wx, 0xfffdc, &ssid); 1020 if (!err) 1021 wx->subsystem_device_id = swab16((u16)ssid); 1022 1023 return err; 1024 } 1025 1026 wx->mac_table = kcalloc(wx->mac.num_rar_entries, 1027 sizeof(struct wx_mac_addr), 1028 GFP_KERNEL); 1029 if (!wx->mac_table) { 1030 wx_err(wx, "mac_table allocation failed\n"); 1031 return -ENOMEM; 1032 } 1033 1034 return 0; 1035 } 1036 EXPORT_SYMBOL(wx_sw_init); 1037 1038 MODULE_LICENSE("GPL"); 1039