1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */
3 
4 #include <linux/etherdevice.h>
5 #include <linux/if_ether.h>
6 #include <linux/iopoll.h>
7 #include <linux/pci.h>
8 
9 #include "wx_type.h"
10 #include "wx_hw.h"
11 
12 static void wx_intr_disable(struct wx_hw *wxhw, u64 qmask)
13 {
14 	u32 mask;
15 
16 	mask = (qmask & 0xFFFFFFFF);
17 	if (mask)
18 		wr32(wxhw, WX_PX_IMS(0), mask);
19 
20 	if (wxhw->mac.type == wx_mac_sp) {
21 		mask = (qmask >> 32);
22 		if (mask)
23 			wr32(wxhw, WX_PX_IMS(1), mask);
24 	}
25 }
26 
27 /* cmd_addr is used for some special command:
28  * 1. to be sector address, when implemented erase sector command
29  * 2. to be flash address when implemented read, write flash address
30  */
31 static int wx_fmgr_cmd_op(struct wx_hw *wxhw, u32 cmd, u32 cmd_addr)
32 {
33 	u32 cmd_val = 0, val = 0;
34 
35 	cmd_val = WX_SPI_CMD_CMD(cmd) |
36 		  WX_SPI_CMD_CLK(WX_SPI_CLK_DIV) |
37 		  cmd_addr;
38 	wr32(wxhw, WX_SPI_CMD, cmd_val);
39 
40 	return read_poll_timeout(rd32, val, (val & 0x1), 10, 100000,
41 				 false, wxhw, WX_SPI_STATUS);
42 }
43 
44 static int wx_flash_read_dword(struct wx_hw *wxhw, u32 addr, u32 *data)
45 {
46 	int ret = 0;
47 
48 	ret = wx_fmgr_cmd_op(wxhw, WX_SPI_CMD_READ_DWORD, addr);
49 	if (ret < 0)
50 		return ret;
51 
52 	*data = rd32(wxhw, WX_SPI_DATA);
53 
54 	return ret;
55 }
56 
57 int wx_check_flash_load(struct wx_hw *hw, u32 check_bit)
58 {
59 	u32 reg = 0;
60 	int err = 0;
61 
62 	/* if there's flash existing */
63 	if (!(rd32(hw, WX_SPI_STATUS) &
64 	      WX_SPI_STATUS_FLASH_BYPASS)) {
65 		/* wait hw load flash done */
66 		err = read_poll_timeout(rd32, reg, !(reg & check_bit), 20000, 2000000,
67 					false, hw, WX_SPI_ILDR_STATUS);
68 		if (err < 0)
69 			wx_err(hw, "Check flash load timeout.\n");
70 	}
71 
72 	return err;
73 }
74 EXPORT_SYMBOL(wx_check_flash_load);
75 
76 void wx_control_hw(struct wx_hw *wxhw, bool drv)
77 {
78 	if (drv) {
79 		/* Let firmware know the driver has taken over */
80 		wr32m(wxhw, WX_CFG_PORT_CTL,
81 		      WX_CFG_PORT_CTL_DRV_LOAD, WX_CFG_PORT_CTL_DRV_LOAD);
82 	} else {
83 		/* Let firmware take over control of hw */
84 		wr32m(wxhw, WX_CFG_PORT_CTL,
85 		      WX_CFG_PORT_CTL_DRV_LOAD, 0);
86 	}
87 }
88 EXPORT_SYMBOL(wx_control_hw);
89 
90 /**
91  * wx_mng_present - returns 0 when management capability is present
92  * @wxhw: pointer to hardware structure
93  */
94 int wx_mng_present(struct wx_hw *wxhw)
95 {
96 	u32 fwsm;
97 
98 	fwsm = rd32(wxhw, WX_MIS_ST);
99 	if (fwsm & WX_MIS_ST_MNG_INIT_DN)
100 		return 0;
101 	else
102 		return -EACCES;
103 }
104 EXPORT_SYMBOL(wx_mng_present);
105 
106 /* Software lock to be held while software semaphore is being accessed. */
107 static DEFINE_MUTEX(wx_sw_sync_lock);
108 
109 /**
110  *  wx_release_sw_sync - Release SW semaphore
111  *  @wxhw: pointer to hardware structure
112  *  @mask: Mask to specify which semaphore to release
113  *
114  *  Releases the SW semaphore for the specified
115  *  function (CSR, PHY0, PHY1, EEPROM, Flash)
116  **/
117 static void wx_release_sw_sync(struct wx_hw *wxhw, u32 mask)
118 {
119 	mutex_lock(&wx_sw_sync_lock);
120 	wr32m(wxhw, WX_MNG_SWFW_SYNC, mask, 0);
121 	mutex_unlock(&wx_sw_sync_lock);
122 }
123 
124 /**
125  *  wx_acquire_sw_sync - Acquire SW semaphore
126  *  @wxhw: pointer to hardware structure
127  *  @mask: Mask to specify which semaphore to acquire
128  *
129  *  Acquires the SW semaphore for the specified
130  *  function (CSR, PHY0, PHY1, EEPROM, Flash)
131  **/
132 static int wx_acquire_sw_sync(struct wx_hw *wxhw, u32 mask)
133 {
134 	u32 sem = 0;
135 	int ret = 0;
136 
137 	mutex_lock(&wx_sw_sync_lock);
138 	ret = read_poll_timeout(rd32, sem, !(sem & mask),
139 				5000, 2000000, false, wxhw, WX_MNG_SWFW_SYNC);
140 	if (!ret) {
141 		sem |= mask;
142 		wr32(wxhw, WX_MNG_SWFW_SYNC, sem);
143 	} else {
144 		wx_err(wxhw, "SW Semaphore not granted: 0x%x.\n", sem);
145 	}
146 	mutex_unlock(&wx_sw_sync_lock);
147 
148 	return ret;
149 }
150 
151 /**
152  *  wx_host_interface_command - Issue command to manageability block
153  *  @wxhw: pointer to the HW structure
154  *  @buffer: contains the command to write and where the return status will
155  *   be placed
156  *  @length: length of buffer, must be multiple of 4 bytes
157  *  @timeout: time in ms to wait for command completion
158  *  @return_data: read and return data from the buffer (true) or not (false)
159  *   Needed because FW structures are big endian and decoding of
160  *   these fields can be 8 bit or 16 bit based on command. Decoding
161  *   is not easily understood without making a table of commands.
162  *   So we will leave this up to the caller to read back the data
163  *   in these cases.
164  **/
165 int wx_host_interface_command(struct wx_hw *wxhw, u32 *buffer,
166 			      u32 length, u32 timeout, bool return_data)
167 {
168 	u32 hdr_size = sizeof(struct wx_hic_hdr);
169 	u32 hicr, i, bi, buf[64] = {};
170 	int status = 0;
171 	u32 dword_len;
172 	u16 buf_len;
173 
174 	if (length == 0 || length > WX_HI_MAX_BLOCK_BYTE_LENGTH) {
175 		wx_err(wxhw, "Buffer length failure buffersize=%d.\n", length);
176 		return -EINVAL;
177 	}
178 
179 	status = wx_acquire_sw_sync(wxhw, WX_MNG_SWFW_SYNC_SW_MB);
180 	if (status != 0)
181 		return status;
182 
183 	/* Calculate length in DWORDs. We must be DWORD aligned */
184 	if ((length % (sizeof(u32))) != 0) {
185 		wx_err(wxhw, "Buffer length failure, not aligned to dword");
186 		status = -EINVAL;
187 		goto rel_out;
188 	}
189 
190 	dword_len = length >> 2;
191 
192 	/* The device driver writes the relevant command block
193 	 * into the ram area.
194 	 */
195 	for (i = 0; i < dword_len; i++) {
196 		wr32a(wxhw, WX_MNG_MBOX, i, (__force u32)cpu_to_le32(buffer[i]));
197 		/* write flush */
198 		buf[i] = rd32a(wxhw, WX_MNG_MBOX, i);
199 	}
200 	/* Setting this bit tells the ARC that a new command is pending. */
201 	wr32m(wxhw, WX_MNG_MBOX_CTL,
202 	      WX_MNG_MBOX_CTL_SWRDY, WX_MNG_MBOX_CTL_SWRDY);
203 
204 	status = read_poll_timeout(rd32, hicr, hicr & WX_MNG_MBOX_CTL_FWRDY, 1000,
205 				   timeout * 1000, false, wxhw, WX_MNG_MBOX_CTL);
206 
207 	/* Check command completion */
208 	if (status) {
209 		wx_dbg(wxhw, "Command has failed with no status valid.\n");
210 
211 		buf[0] = rd32(wxhw, WX_MNG_MBOX);
212 		if ((buffer[0] & 0xff) != (~buf[0] >> 24)) {
213 			status = -EINVAL;
214 			goto rel_out;
215 		}
216 		if ((buf[0] & 0xff0000) >> 16 == 0x80) {
217 			wx_dbg(wxhw, "It's unknown cmd.\n");
218 			status = -EINVAL;
219 			goto rel_out;
220 		}
221 
222 		wx_dbg(wxhw, "write value:\n");
223 		for (i = 0; i < dword_len; i++)
224 			wx_dbg(wxhw, "%x ", buffer[i]);
225 		wx_dbg(wxhw, "read value:\n");
226 		for (i = 0; i < dword_len; i++)
227 			wx_dbg(wxhw, "%x ", buf[i]);
228 	}
229 
230 	if (!return_data)
231 		goto rel_out;
232 
233 	/* Calculate length in DWORDs */
234 	dword_len = hdr_size >> 2;
235 
236 	/* first pull in the header so we know the buffer length */
237 	for (bi = 0; bi < dword_len; bi++) {
238 		buffer[bi] = rd32a(wxhw, WX_MNG_MBOX, bi);
239 		le32_to_cpus(&buffer[bi]);
240 	}
241 
242 	/* If there is any thing in data position pull it in */
243 	buf_len = ((struct wx_hic_hdr *)buffer)->buf_len;
244 	if (buf_len == 0)
245 		goto rel_out;
246 
247 	if (length < buf_len + hdr_size) {
248 		wx_err(wxhw, "Buffer not large enough for reply message.\n");
249 		status = -EFAULT;
250 		goto rel_out;
251 	}
252 
253 	/* Calculate length in DWORDs, add 3 for odd lengths */
254 	dword_len = (buf_len + 3) >> 2;
255 
256 	/* Pull in the rest of the buffer (bi is where we left off) */
257 	for (; bi <= dword_len; bi++) {
258 		buffer[bi] = rd32a(wxhw, WX_MNG_MBOX, bi);
259 		le32_to_cpus(&buffer[bi]);
260 	}
261 
262 rel_out:
263 	wx_release_sw_sync(wxhw, WX_MNG_SWFW_SYNC_SW_MB);
264 	return status;
265 }
266 EXPORT_SYMBOL(wx_host_interface_command);
267 
268 /**
269  *  wx_read_ee_hostif_data - Read EEPROM word using a host interface cmd
270  *  assuming that the semaphore is already obtained.
271  *  @wxhw: pointer to hardware structure
272  *  @offset: offset of  word in the EEPROM to read
273  *  @data: word read from the EEPROM
274  *
275  *  Reads a 16 bit word from the EEPROM using the hostif.
276  **/
277 static int wx_read_ee_hostif_data(struct wx_hw *wxhw, u16 offset, u16 *data)
278 {
279 	struct wx_hic_read_shadow_ram buffer;
280 	int status;
281 
282 	buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
283 	buffer.hdr.req.buf_lenh = 0;
284 	buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
285 	buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
286 
287 	/* convert offset from words to bytes */
288 	buffer.address = (__force u32)cpu_to_be32(offset * 2);
289 	/* one word */
290 	buffer.length = (__force u16)cpu_to_be16(sizeof(u16));
291 
292 	status = wx_host_interface_command(wxhw, (u32 *)&buffer, sizeof(buffer),
293 					   WX_HI_COMMAND_TIMEOUT, false);
294 
295 	if (status != 0)
296 		return status;
297 
298 	*data = (u16)rd32a(wxhw, WX_MNG_MBOX, FW_NVM_DATA_OFFSET);
299 
300 	return status;
301 }
302 
303 /**
304  *  wx_read_ee_hostif - Read EEPROM word using a host interface cmd
305  *  @wxhw: pointer to hardware structure
306  *  @offset: offset of  word in the EEPROM to read
307  *  @data: word read from the EEPROM
308  *
309  *  Reads a 16 bit word from the EEPROM using the hostif.
310  **/
311 int wx_read_ee_hostif(struct wx_hw *wxhw, u16 offset, u16 *data)
312 {
313 	int status = 0;
314 
315 	status = wx_acquire_sw_sync(wxhw, WX_MNG_SWFW_SYNC_SW_FLASH);
316 	if (status == 0) {
317 		status = wx_read_ee_hostif_data(wxhw, offset, data);
318 		wx_release_sw_sync(wxhw, WX_MNG_SWFW_SYNC_SW_FLASH);
319 	}
320 
321 	return status;
322 }
323 EXPORT_SYMBOL(wx_read_ee_hostif);
324 
325 /**
326  *  wx_read_ee_hostif_buffer- Read EEPROM word(s) using hostif
327  *  @wxhw: pointer to hardware structure
328  *  @offset: offset of  word in the EEPROM to read
329  *  @words: number of words
330  *  @data: word(s) read from the EEPROM
331  *
332  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
333  **/
334 int wx_read_ee_hostif_buffer(struct wx_hw *wxhw,
335 			     u16 offset, u16 words, u16 *data)
336 {
337 	struct wx_hic_read_shadow_ram buffer;
338 	u32 current_word = 0;
339 	u16 words_to_read;
340 	u32 value = 0;
341 	int status;
342 	u32 i;
343 
344 	/* Take semaphore for the entire operation. */
345 	status = wx_acquire_sw_sync(wxhw, WX_MNG_SWFW_SYNC_SW_FLASH);
346 	if (status != 0)
347 		return status;
348 
349 	while (words) {
350 		if (words > FW_MAX_READ_BUFFER_SIZE / 2)
351 			words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
352 		else
353 			words_to_read = words;
354 
355 		buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
356 		buffer.hdr.req.buf_lenh = 0;
357 		buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
358 		buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
359 
360 		/* convert offset from words to bytes */
361 		buffer.address = (__force u32)cpu_to_be32((offset + current_word) * 2);
362 		buffer.length = (__force u16)cpu_to_be16(words_to_read * 2);
363 
364 		status = wx_host_interface_command(wxhw, (u32 *)&buffer,
365 						   sizeof(buffer),
366 						   WX_HI_COMMAND_TIMEOUT,
367 						   false);
368 
369 		if (status != 0) {
370 			wx_err(wxhw, "Host interface command failed\n");
371 			goto out;
372 		}
373 
374 		for (i = 0; i < words_to_read; i++) {
375 			u32 reg = WX_MNG_MBOX + (FW_NVM_DATA_OFFSET << 2) + 2 * i;
376 
377 			value = rd32(wxhw, reg);
378 			data[current_word] = (u16)(value & 0xffff);
379 			current_word++;
380 			i++;
381 			if (i < words_to_read) {
382 				value >>= 16;
383 				data[current_word] = (u16)(value & 0xffff);
384 				current_word++;
385 			}
386 		}
387 		words -= words_to_read;
388 	}
389 
390 out:
391 	wx_release_sw_sync(wxhw, WX_MNG_SWFW_SYNC_SW_FLASH);
392 	return status;
393 }
394 EXPORT_SYMBOL(wx_read_ee_hostif_buffer);
395 
396 /**
397  *  wx_calculate_checksum - Calculate checksum for buffer
398  *  @buffer: pointer to EEPROM
399  *  @length: size of EEPROM to calculate a checksum for
400  *  Calculates the checksum for some buffer on a specified length.  The
401  *  checksum calculated is returned.
402  **/
403 static u8 wx_calculate_checksum(u8 *buffer, u32 length)
404 {
405 	u8 sum = 0;
406 	u32 i;
407 
408 	if (!buffer)
409 		return 0;
410 
411 	for (i = 0; i < length; i++)
412 		sum += buffer[i];
413 
414 	return (u8)(0 - sum);
415 }
416 
417 /**
418  *  wx_reset_hostif - send reset cmd to fw
419  *  @wxhw: pointer to hardware structure
420  *
421  *  Sends reset cmd to firmware through the manageability
422  *  block.
423  **/
424 int wx_reset_hostif(struct wx_hw *wxhw)
425 {
426 	struct wx_hic_reset reset_cmd;
427 	int ret_val = 0;
428 	int i;
429 
430 	reset_cmd.hdr.cmd = FW_RESET_CMD;
431 	reset_cmd.hdr.buf_len = FW_RESET_LEN;
432 	reset_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
433 	reset_cmd.lan_id = wxhw->bus.func;
434 	reset_cmd.reset_type = (u16)wxhw->reset_type;
435 	reset_cmd.hdr.checksum = 0;
436 	reset_cmd.hdr.checksum = wx_calculate_checksum((u8 *)&reset_cmd,
437 						       (FW_CEM_HDR_LEN +
438 							reset_cmd.hdr.buf_len));
439 
440 	for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
441 		ret_val = wx_host_interface_command(wxhw, (u32 *)&reset_cmd,
442 						    sizeof(reset_cmd),
443 						    WX_HI_COMMAND_TIMEOUT,
444 						    true);
445 		if (ret_val != 0)
446 			continue;
447 
448 		if (reset_cmd.hdr.cmd_or_resp.ret_status ==
449 		    FW_CEM_RESP_STATUS_SUCCESS)
450 			ret_val = 0;
451 		else
452 			ret_val = -EFAULT;
453 
454 		break;
455 	}
456 
457 	return ret_val;
458 }
459 EXPORT_SYMBOL(wx_reset_hostif);
460 
461 /**
462  *  wx_init_eeprom_params - Initialize EEPROM params
463  *  @wxhw: pointer to hardware structure
464  *
465  *  Initializes the EEPROM parameters wx_eeprom_info within the
466  *  wx_hw struct in order to set up EEPROM access.
467  **/
468 void wx_init_eeprom_params(struct wx_hw *wxhw)
469 {
470 	struct wx_eeprom_info *eeprom = &wxhw->eeprom;
471 	u16 eeprom_size;
472 	u16 data = 0x80;
473 
474 	if (eeprom->type == wx_eeprom_uninitialized) {
475 		eeprom->semaphore_delay = 10;
476 		eeprom->type = wx_eeprom_none;
477 
478 		if (!(rd32(wxhw, WX_SPI_STATUS) &
479 		      WX_SPI_STATUS_FLASH_BYPASS)) {
480 			eeprom->type = wx_flash;
481 
482 			eeprom_size = 4096;
483 			eeprom->word_size = eeprom_size >> 1;
484 
485 			wx_dbg(wxhw, "Eeprom params: type = %d, size = %d\n",
486 			       eeprom->type, eeprom->word_size);
487 		}
488 	}
489 
490 	if (wxhw->mac.type == wx_mac_sp) {
491 		if (wx_read_ee_hostif(wxhw, WX_SW_REGION_PTR, &data)) {
492 			wx_err(wxhw, "NVM Read Error\n");
493 			return;
494 		}
495 		data = data >> 1;
496 	}
497 
498 	eeprom->sw_region_offset = data;
499 }
500 EXPORT_SYMBOL(wx_init_eeprom_params);
501 
502 /**
503  *  wx_get_mac_addr - Generic get MAC address
504  *  @wxhw: pointer to hardware structure
505  *  @mac_addr: Adapter MAC address
506  *
507  *  Reads the adapter's MAC address from first Receive Address Register (RAR0)
508  *  A reset of the adapter must be performed prior to calling this function
509  *  in order for the MAC address to have been loaded from the EEPROM into RAR0
510  **/
511 void wx_get_mac_addr(struct wx_hw *wxhw, u8 *mac_addr)
512 {
513 	u32 rar_high;
514 	u32 rar_low;
515 	u16 i;
516 
517 	wr32(wxhw, WX_PSR_MAC_SWC_IDX, 0);
518 	rar_high = rd32(wxhw, WX_PSR_MAC_SWC_AD_H);
519 	rar_low = rd32(wxhw, WX_PSR_MAC_SWC_AD_L);
520 
521 	for (i = 0; i < 2; i++)
522 		mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
523 
524 	for (i = 0; i < 4; i++)
525 		mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
526 }
527 EXPORT_SYMBOL(wx_get_mac_addr);
528 
529 /**
530  *  wx_set_rar - Set Rx address register
531  *  @wxhw: pointer to hardware structure
532  *  @index: Receive address register to write
533  *  @addr: Address to put into receive address register
534  *  @pools: VMDq "set" or "pool" index
535  *  @enable_addr: set flag that address is active
536  *
537  *  Puts an ethernet address into a receive address register.
538  **/
539 int wx_set_rar(struct wx_hw *wxhw, u32 index, u8 *addr, u64 pools,
540 	       u32 enable_addr)
541 {
542 	u32 rar_entries = wxhw->mac.num_rar_entries;
543 	u32 rar_low, rar_high;
544 
545 	/* Make sure we are using a valid rar index range */
546 	if (index >= rar_entries) {
547 		wx_err(wxhw, "RAR index %d is out of range.\n", index);
548 		return -EINVAL;
549 	}
550 
551 	/* select the MAC address */
552 	wr32(wxhw, WX_PSR_MAC_SWC_IDX, index);
553 
554 	/* setup VMDq pool mapping */
555 	wr32(wxhw, WX_PSR_MAC_SWC_VM_L, pools & 0xFFFFFFFF);
556 	if (wxhw->mac.type == wx_mac_sp)
557 		wr32(wxhw, WX_PSR_MAC_SWC_VM_H, pools >> 32);
558 
559 	/* HW expects these in little endian so we reverse the byte
560 	 * order from network order (big endian) to little endian
561 	 *
562 	 * Some parts put the VMDq setting in the extra RAH bits,
563 	 * so save everything except the lower 16 bits that hold part
564 	 * of the address and the address valid bit.
565 	 */
566 	rar_low = ((u32)addr[5] |
567 		  ((u32)addr[4] << 8) |
568 		  ((u32)addr[3] << 16) |
569 		  ((u32)addr[2] << 24));
570 	rar_high = ((u32)addr[1] |
571 		   ((u32)addr[0] << 8));
572 	if (enable_addr != 0)
573 		rar_high |= WX_PSR_MAC_SWC_AD_H_AV;
574 
575 	wr32(wxhw, WX_PSR_MAC_SWC_AD_L, rar_low);
576 	wr32m(wxhw, WX_PSR_MAC_SWC_AD_H,
577 	      (WX_PSR_MAC_SWC_AD_H_AD(~0) |
578 	       WX_PSR_MAC_SWC_AD_H_ADTYPE(~0) |
579 	       WX_PSR_MAC_SWC_AD_H_AV),
580 	      rar_high);
581 
582 	return 0;
583 }
584 EXPORT_SYMBOL(wx_set_rar);
585 
586 /**
587  *  wx_clear_rar - Remove Rx address register
588  *  @wxhw: pointer to hardware structure
589  *  @index: Receive address register to write
590  *
591  *  Clears an ethernet address from a receive address register.
592  **/
593 int wx_clear_rar(struct wx_hw *wxhw, u32 index)
594 {
595 	u32 rar_entries = wxhw->mac.num_rar_entries;
596 
597 	/* Make sure we are using a valid rar index range */
598 	if (index >= rar_entries) {
599 		wx_err(wxhw, "RAR index %d is out of range.\n", index);
600 		return -EINVAL;
601 	}
602 
603 	/* Some parts put the VMDq setting in the extra RAH bits,
604 	 * so save everything except the lower 16 bits that hold part
605 	 * of the address and the address valid bit.
606 	 */
607 	wr32(wxhw, WX_PSR_MAC_SWC_IDX, index);
608 
609 	wr32(wxhw, WX_PSR_MAC_SWC_VM_L, 0);
610 	wr32(wxhw, WX_PSR_MAC_SWC_VM_H, 0);
611 
612 	wr32(wxhw, WX_PSR_MAC_SWC_AD_L, 0);
613 	wr32m(wxhw, WX_PSR_MAC_SWC_AD_H,
614 	      (WX_PSR_MAC_SWC_AD_H_AD(~0) |
615 	       WX_PSR_MAC_SWC_AD_H_ADTYPE(~0) |
616 	       WX_PSR_MAC_SWC_AD_H_AV),
617 	      0);
618 
619 	return 0;
620 }
621 EXPORT_SYMBOL(wx_clear_rar);
622 
623 /**
624  *  wx_clear_vmdq - Disassociate a VMDq pool index from a rx address
625  *  @wxhw: pointer to hardware struct
626  *  @rar: receive address register index to disassociate
627  *  @vmdq: VMDq pool index to remove from the rar
628  **/
629 static int wx_clear_vmdq(struct wx_hw *wxhw, u32 rar, u32 __maybe_unused vmdq)
630 {
631 	u32 rar_entries = wxhw->mac.num_rar_entries;
632 	u32 mpsar_lo, mpsar_hi;
633 
634 	/* Make sure we are using a valid rar index range */
635 	if (rar >= rar_entries) {
636 		wx_err(wxhw, "RAR index %d is out of range.\n", rar);
637 		return -EINVAL;
638 	}
639 
640 	wr32(wxhw, WX_PSR_MAC_SWC_IDX, rar);
641 	mpsar_lo = rd32(wxhw, WX_PSR_MAC_SWC_VM_L);
642 	mpsar_hi = rd32(wxhw, WX_PSR_MAC_SWC_VM_H);
643 
644 	if (!mpsar_lo && !mpsar_hi)
645 		return 0;
646 
647 	/* was that the last pool using this rar? */
648 	if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
649 		wx_clear_rar(wxhw, rar);
650 
651 	return 0;
652 }
653 
654 /**
655  *  wx_init_uta_tables - Initialize the Unicast Table Array
656  *  @wxhw: pointer to hardware structure
657  **/
658 static void wx_init_uta_tables(struct wx_hw *wxhw)
659 {
660 	int i;
661 
662 	wx_dbg(wxhw, " Clearing UTA\n");
663 
664 	for (i = 0; i < 128; i++)
665 		wr32(wxhw, WX_PSR_UC_TBL(i), 0);
666 }
667 
668 /**
669  *  wx_init_rx_addrs - Initializes receive address filters.
670  *  @wxhw: pointer to hardware structure
671  *
672  *  Places the MAC address in receive address register 0 and clears the rest
673  *  of the receive address registers. Clears the multicast table. Assumes
674  *  the receiver is in reset when the routine is called.
675  **/
676 void wx_init_rx_addrs(struct wx_hw *wxhw)
677 {
678 	u32 rar_entries = wxhw->mac.num_rar_entries;
679 	u32 psrctl;
680 	int i;
681 
682 	/* If the current mac address is valid, assume it is a software override
683 	 * to the permanent address.
684 	 * Otherwise, use the permanent address from the eeprom.
685 	 */
686 	if (!is_valid_ether_addr(wxhw->mac.addr)) {
687 		/* Get the MAC address from the RAR0 for later reference */
688 		wx_get_mac_addr(wxhw, wxhw->mac.addr);
689 		wx_dbg(wxhw, "Keeping Current RAR0 Addr = %pM\n", wxhw->mac.addr);
690 	} else {
691 		/* Setup the receive address. */
692 		wx_dbg(wxhw, "Overriding MAC Address in RAR[0]\n");
693 		wx_dbg(wxhw, "New MAC Addr = %pM\n", wxhw->mac.addr);
694 
695 		wx_set_rar(wxhw, 0, wxhw->mac.addr, 0, WX_PSR_MAC_SWC_AD_H_AV);
696 
697 		if (wxhw->mac.type == wx_mac_sp) {
698 			/* clear VMDq pool/queue selection for RAR 0 */
699 			wx_clear_vmdq(wxhw, 0, WX_CLEAR_VMDQ_ALL);
700 		}
701 	}
702 
703 	/* Zero out the other receive addresses. */
704 	wx_dbg(wxhw, "Clearing RAR[1-%d]\n", rar_entries - 1);
705 	for (i = 1; i < rar_entries; i++) {
706 		wr32(wxhw, WX_PSR_MAC_SWC_IDX, i);
707 		wr32(wxhw, WX_PSR_MAC_SWC_AD_L, 0);
708 		wr32(wxhw, WX_PSR_MAC_SWC_AD_H, 0);
709 	}
710 
711 	/* Clear the MTA */
712 	wxhw->addr_ctrl.mta_in_use = 0;
713 	psrctl = rd32(wxhw, WX_PSR_CTL);
714 	psrctl &= ~(WX_PSR_CTL_MO | WX_PSR_CTL_MFE);
715 	psrctl |= wxhw->mac.mc_filter_type << WX_PSR_CTL_MO_SHIFT;
716 	wr32(wxhw, WX_PSR_CTL, psrctl);
717 	wx_dbg(wxhw, " Clearing MTA\n");
718 	for (i = 0; i < wxhw->mac.mcft_size; i++)
719 		wr32(wxhw, WX_PSR_MC_TBL(i), 0);
720 
721 	wx_init_uta_tables(wxhw);
722 }
723 EXPORT_SYMBOL(wx_init_rx_addrs);
724 
725 void wx_disable_rx(struct wx_hw *wxhw)
726 {
727 	u32 pfdtxgswc;
728 	u32 rxctrl;
729 
730 	rxctrl = rd32(wxhw, WX_RDB_PB_CTL);
731 	if (rxctrl & WX_RDB_PB_CTL_RXEN) {
732 		pfdtxgswc = rd32(wxhw, WX_PSR_CTL);
733 		if (pfdtxgswc & WX_PSR_CTL_SW_EN) {
734 			pfdtxgswc &= ~WX_PSR_CTL_SW_EN;
735 			wr32(wxhw, WX_PSR_CTL, pfdtxgswc);
736 			wxhw->mac.set_lben = true;
737 		} else {
738 			wxhw->mac.set_lben = false;
739 		}
740 		rxctrl &= ~WX_RDB_PB_CTL_RXEN;
741 		wr32(wxhw, WX_RDB_PB_CTL, rxctrl);
742 
743 		if (!(((wxhw->subsystem_device_id & WX_NCSI_MASK) == WX_NCSI_SUP) ||
744 		      ((wxhw->subsystem_device_id & WX_WOL_MASK) == WX_WOL_SUP))) {
745 			/* disable mac receiver */
746 			wr32m(wxhw, WX_MAC_RX_CFG,
747 			      WX_MAC_RX_CFG_RE, 0);
748 		}
749 	}
750 }
751 EXPORT_SYMBOL(wx_disable_rx);
752 
753 /**
754  *  wx_disable_pcie_master - Disable PCI-express master access
755  *  @wxhw: pointer to hardware structure
756  *
757  *  Disables PCI-Express master access and verifies there are no pending
758  *  requests.
759  **/
760 int wx_disable_pcie_master(struct wx_hw *wxhw)
761 {
762 	int status = 0;
763 	u32 val;
764 
765 	/* Always set this bit to ensure any future transactions are blocked */
766 	pci_clear_master(wxhw->pdev);
767 
768 	/* Exit if master requests are blocked */
769 	if (!(rd32(wxhw, WX_PX_TRANSACTION_PENDING)))
770 		return 0;
771 
772 	/* Poll for master request bit to clear */
773 	status = read_poll_timeout(rd32, val, !val, 100, WX_PCI_MASTER_DISABLE_TIMEOUT,
774 				   false, wxhw, WX_PX_TRANSACTION_PENDING);
775 	if (status < 0)
776 		wx_err(wxhw, "PCIe transaction pending bit did not clear.\n");
777 
778 	return status;
779 }
780 EXPORT_SYMBOL(wx_disable_pcie_master);
781 
782 /**
783  *  wx_stop_adapter - Generic stop Tx/Rx units
784  *  @wxhw: pointer to hardware structure
785  *
786  *  Sets the adapter_stopped flag within wx_hw struct. Clears interrupts,
787  *  disables transmit and receive units. The adapter_stopped flag is used by
788  *  the shared code and drivers to determine if the adapter is in a stopped
789  *  state and should not touch the hardware.
790  **/
791 int wx_stop_adapter(struct wx_hw *wxhw)
792 {
793 	u16 i;
794 
795 	/* Set the adapter_stopped flag so other driver functions stop touching
796 	 * the hardware
797 	 */
798 	wxhw->adapter_stopped = true;
799 
800 	/* Disable the receive unit */
801 	wx_disable_rx(wxhw);
802 
803 	/* Set interrupt mask to stop interrupts from being generated */
804 	wx_intr_disable(wxhw, WX_INTR_ALL);
805 
806 	/* Clear any pending interrupts, flush previous writes */
807 	wr32(wxhw, WX_PX_MISC_IC, 0xffffffff);
808 	wr32(wxhw, WX_BME_CTL, 0x3);
809 
810 	/* Disable the transmit unit.  Each queue must be disabled. */
811 	for (i = 0; i < wxhw->mac.max_tx_queues; i++) {
812 		wr32m(wxhw, WX_PX_TR_CFG(i),
813 		      WX_PX_TR_CFG_SWFLSH | WX_PX_TR_CFG_ENABLE,
814 		      WX_PX_TR_CFG_SWFLSH);
815 	}
816 
817 	/* Disable the receive unit by stopping each queue */
818 	for (i = 0; i < wxhw->mac.max_rx_queues; i++) {
819 		wr32m(wxhw, WX_PX_RR_CFG(i),
820 		      WX_PX_RR_CFG_RR_EN, 0);
821 	}
822 
823 	/* flush all queues disables */
824 	WX_WRITE_FLUSH(wxhw);
825 
826 	/* Prevent the PCI-E bus from hanging by disabling PCI-E master
827 	 * access and verify no pending requests
828 	 */
829 	return wx_disable_pcie_master(wxhw);
830 }
831 EXPORT_SYMBOL(wx_stop_adapter);
832 
833 void wx_reset_misc(struct wx_hw *wxhw)
834 {
835 	int i;
836 
837 	/* receive packets that size > 2048 */
838 	wr32m(wxhw, WX_MAC_RX_CFG, WX_MAC_RX_CFG_JE, WX_MAC_RX_CFG_JE);
839 
840 	/* clear counters on read */
841 	wr32m(wxhw, WX_MMC_CONTROL,
842 	      WX_MMC_CONTROL_RSTONRD, WX_MMC_CONTROL_RSTONRD);
843 
844 	wr32m(wxhw, WX_MAC_RX_FLOW_CTRL,
845 	      WX_MAC_RX_FLOW_CTRL_RFE, WX_MAC_RX_FLOW_CTRL_RFE);
846 
847 	wr32(wxhw, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR);
848 
849 	wr32m(wxhw, WX_MIS_RST_ST,
850 	      WX_MIS_RST_ST_RST_INIT, 0x1E00);
851 
852 	/* errata 4: initialize mng flex tbl and wakeup flex tbl*/
853 	wr32(wxhw, WX_PSR_MNG_FLEX_SEL, 0);
854 	for (i = 0; i < 16; i++) {
855 		wr32(wxhw, WX_PSR_MNG_FLEX_DW_L(i), 0);
856 		wr32(wxhw, WX_PSR_MNG_FLEX_DW_H(i), 0);
857 		wr32(wxhw, WX_PSR_MNG_FLEX_MSK(i), 0);
858 	}
859 	wr32(wxhw, WX_PSR_LAN_FLEX_SEL, 0);
860 	for (i = 0; i < 16; i++) {
861 		wr32(wxhw, WX_PSR_LAN_FLEX_DW_L(i), 0);
862 		wr32(wxhw, WX_PSR_LAN_FLEX_DW_H(i), 0);
863 		wr32(wxhw, WX_PSR_LAN_FLEX_MSK(i), 0);
864 	}
865 
866 	/* set pause frame dst mac addr */
867 	wr32(wxhw, WX_RDB_PFCMACDAL, 0xC2000001);
868 	wr32(wxhw, WX_RDB_PFCMACDAH, 0x0180);
869 }
870 EXPORT_SYMBOL(wx_reset_misc);
871 
872 /**
873  *  wx_get_pcie_msix_counts - Gets MSI-X vector count
874  *  @wxhw: pointer to hardware structure
875  *  @msix_count: number of MSI interrupts that can be obtained
876  *  @max_msix_count: number of MSI interrupts that mac need
877  *
878  *  Read PCIe configuration space, and get the MSI-X vector count from
879  *  the capabilities table.
880  **/
881 int wx_get_pcie_msix_counts(struct wx_hw *wxhw, u16 *msix_count, u16 max_msix_count)
882 {
883 	struct pci_dev *pdev = wxhw->pdev;
884 	struct device *dev = &pdev->dev;
885 	int pos;
886 
887 	*msix_count = 1;
888 	pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
889 	if (!pos) {
890 		dev_err(dev, "Unable to find MSI-X Capabilities\n");
891 		return -EINVAL;
892 	}
893 	pci_read_config_word(pdev,
894 			     pos + PCI_MSIX_FLAGS,
895 			     msix_count);
896 	*msix_count &= WX_PCIE_MSIX_TBL_SZ_MASK;
897 	/* MSI-X count is zero-based in HW */
898 	*msix_count += 1;
899 
900 	if (*msix_count > max_msix_count)
901 		*msix_count = max_msix_count;
902 
903 	return 0;
904 }
905 EXPORT_SYMBOL(wx_get_pcie_msix_counts);
906 
907 int wx_sw_init(struct wx_hw *wxhw)
908 {
909 	struct pci_dev *pdev = wxhw->pdev;
910 	u32 ssid = 0;
911 	int err = 0;
912 
913 	wxhw->vendor_id = pdev->vendor;
914 	wxhw->device_id = pdev->device;
915 	wxhw->revision_id = pdev->revision;
916 	wxhw->oem_svid = pdev->subsystem_vendor;
917 	wxhw->oem_ssid = pdev->subsystem_device;
918 	wxhw->bus.device = PCI_SLOT(pdev->devfn);
919 	wxhw->bus.func = PCI_FUNC(pdev->devfn);
920 
921 	if (wxhw->oem_svid == PCI_VENDOR_ID_WANGXUN) {
922 		wxhw->subsystem_vendor_id = pdev->subsystem_vendor;
923 		wxhw->subsystem_device_id = pdev->subsystem_device;
924 	} else {
925 		err = wx_flash_read_dword(wxhw, 0xfffdc, &ssid);
926 		if (!err)
927 			wxhw->subsystem_device_id = swab16((u16)ssid);
928 
929 		return err;
930 	}
931 
932 	return 0;
933 }
934 EXPORT_SYMBOL(wx_sw_init);
935 
936 MODULE_LICENSE("GPL");
937