1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. 4 * All rights reserved. 5 * 6 * File: via-velocity.h 7 * 8 * Purpose: Header file to define driver's private structures. 9 * 10 * Author: Chuang Liang-Shing, AJ Jiang 11 * 12 * Date: Jan 24, 2003 13 */ 14 15 16 #ifndef VELOCITY_H 17 #define VELOCITY_H 18 19 #define VELOCITY_TX_CSUM_SUPPORT 20 21 #define VELOCITY_NAME "via-velocity" 22 #define VELOCITY_FULL_DRV_NAM "VIA Networking Velocity Family Gigabit Ethernet Adapter Driver" 23 #define VELOCITY_VERSION "1.15" 24 25 #define VELOCITY_IO_SIZE 256 26 #define VELOCITY_NAPI_WEIGHT 64 27 28 #define PKT_BUF_SZ 1540 29 30 #define MAX_UNITS 8 31 #define OPTION_DEFAULT { [0 ... MAX_UNITS-1] = -1} 32 33 #define REV_ID_VT6110 (0) 34 35 #define BYTE_REG_BITS_ON(x,p) do { writeb(readb((p))|(x),(p));} while (0) 36 #define WORD_REG_BITS_ON(x,p) do { writew(readw((p))|(x),(p));} while (0) 37 #define DWORD_REG_BITS_ON(x,p) do { writel(readl((p))|(x),(p));} while (0) 38 39 #define BYTE_REG_BITS_IS_ON(x,p) (readb((p)) & (x)) 40 #define WORD_REG_BITS_IS_ON(x,p) (readw((p)) & (x)) 41 #define DWORD_REG_BITS_IS_ON(x,p) (readl((p)) & (x)) 42 43 #define BYTE_REG_BITS_OFF(x,p) do { writeb(readb((p)) & (~(x)),(p));} while (0) 44 #define WORD_REG_BITS_OFF(x,p) do { writew(readw((p)) & (~(x)),(p));} while (0) 45 #define DWORD_REG_BITS_OFF(x,p) do { writel(readl((p)) & (~(x)),(p));} while (0) 46 47 #define BYTE_REG_BITS_SET(x,m,p) do { writeb( (readb((p)) & (~(m))) |(x),(p));} while (0) 48 #define WORD_REG_BITS_SET(x,m,p) do { writew( (readw((p)) & (~(m))) |(x),(p));} while (0) 49 #define DWORD_REG_BITS_SET(x,m,p) do { writel( (readl((p)) & (~(m)))|(x),(p));} while (0) 50 51 #define VAR_USED(p) do {(p)=(p);} while (0) 52 53 /* 54 * Purpose: Structures for MAX RX/TX descriptors. 55 */ 56 57 58 #define B_OWNED_BY_CHIP 1 59 #define B_OWNED_BY_HOST 0 60 61 /* 62 * Bits in the RSR0 register 63 */ 64 65 #define RSR_DETAG cpu_to_le16(0x0080) 66 #define RSR_SNTAG cpu_to_le16(0x0040) 67 #define RSR_RXER cpu_to_le16(0x0020) 68 #define RSR_RL cpu_to_le16(0x0010) 69 #define RSR_CE cpu_to_le16(0x0008) 70 #define RSR_FAE cpu_to_le16(0x0004) 71 #define RSR_CRC cpu_to_le16(0x0002) 72 #define RSR_VIDM cpu_to_le16(0x0001) 73 74 /* 75 * Bits in the RSR1 register 76 */ 77 78 #define RSR_RXOK cpu_to_le16(0x8000) // rx OK 79 #define RSR_PFT cpu_to_le16(0x4000) // Perfect filtering address match 80 #define RSR_MAR cpu_to_le16(0x2000) // MAC accept multicast address packet 81 #define RSR_BAR cpu_to_le16(0x1000) // MAC accept broadcast address packet 82 #define RSR_PHY cpu_to_le16(0x0800) // MAC accept physical address packet 83 #define RSR_VTAG cpu_to_le16(0x0400) // 802.1p/1q tagging packet indicator 84 #define RSR_STP cpu_to_le16(0x0200) // start of packet 85 #define RSR_EDP cpu_to_le16(0x0100) // end of packet 86 87 /* 88 * Bits in the CSM register 89 */ 90 91 #define CSM_IPOK 0x40 //IP Checksum validation ok 92 #define CSM_TUPOK 0x20 //TCP/UDP Checksum validation ok 93 #define CSM_FRAG 0x10 //Fragment IP datagram 94 #define CSM_IPKT 0x04 //Received an IP packet 95 #define CSM_TCPKT 0x02 //Received a TCP packet 96 #define CSM_UDPKT 0x01 //Received a UDP packet 97 98 /* 99 * Bits in the TSR0 register 100 */ 101 102 #define TSR0_ABT cpu_to_le16(0x0080) // Tx abort because of excessive collision 103 #define TSR0_OWT cpu_to_le16(0x0040) // Jumbo frame Tx abort 104 #define TSR0_OWC cpu_to_le16(0x0020) // Out of window collision 105 #define TSR0_COLS cpu_to_le16(0x0010) // experience collision in this transmit event 106 #define TSR0_NCR3 cpu_to_le16(0x0008) // collision retry counter[3] 107 #define TSR0_NCR2 cpu_to_le16(0x0004) // collision retry counter[2] 108 #define TSR0_NCR1 cpu_to_le16(0x0002) // collision retry counter[1] 109 #define TSR0_NCR0 cpu_to_le16(0x0001) // collision retry counter[0] 110 #define TSR0_TERR cpu_to_le16(0x8000) // 111 #define TSR0_FDX cpu_to_le16(0x4000) // current transaction is serviced by full duplex mode 112 #define TSR0_GMII cpu_to_le16(0x2000) // current transaction is serviced by GMII mode 113 #define TSR0_LNKFL cpu_to_le16(0x1000) // packet serviced during link down 114 #define TSR0_SHDN cpu_to_le16(0x0400) // shutdown case 115 #define TSR0_CRS cpu_to_le16(0x0200) // carrier sense lost 116 #define TSR0_CDH cpu_to_le16(0x0100) // AQE test fail (CD heartbeat) 117 118 // 119 // Bits in the TCR0 register 120 // 121 #define TCR0_TIC 0x80 // assert interrupt immediately while descriptor has been send complete 122 #define TCR0_PIC 0x40 // priority interrupt request, INA# is issued over adaptive interrupt scheme 123 #define TCR0_VETAG 0x20 // enable VLAN tag 124 #define TCR0_IPCK 0x10 // request IP checksum calculation. 125 #define TCR0_UDPCK 0x08 // request UDP checksum calculation. 126 #define TCR0_TCPCK 0x04 // request TCP checksum calculation. 127 #define TCR0_JMBO 0x02 // indicate a jumbo packet in GMAC side 128 #define TCR0_CRC 0x01 // disable CRC generation 129 130 #define TCPLS_NORMAL 3 131 #define TCPLS_START 2 132 #define TCPLS_END 1 133 #define TCPLS_MED 0 134 135 136 // max transmit or receive buffer size 137 #define CB_RX_BUF_SIZE 2048UL // max buffer size 138 // NOTE: must be multiple of 4 139 140 #define CB_MAX_RD_NUM 512 // MAX # of RD 141 #define CB_MAX_TD_NUM 256 // MAX # of TD 142 143 #define CB_INIT_RD_NUM_3119 128 // init # of RD, for setup VT3119 144 #define CB_INIT_TD_NUM_3119 64 // init # of TD, for setup VT3119 145 146 #define CB_INIT_RD_NUM 128 // init # of RD, for setup default 147 #define CB_INIT_TD_NUM 64 // init # of TD, for setup default 148 149 // for 3119 150 #define CB_TD_RING_NUM 4 // # of TD rings. 151 #define CB_MAX_SEG_PER_PKT 7 // max data seg per packet (Tx) 152 153 154 /* 155 * If collisions excess 15 times , tx will abort, and 156 * if tx fifo underflow, tx will fail 157 * we should try to resend it 158 */ 159 160 #define CB_MAX_TX_ABORT_RETRY 3 161 162 /* 163 * Receive descriptor 164 */ 165 166 struct rdesc0 { 167 __le16 RSR; /* Receive status */ 168 __le16 len; /* bits 0--13; bit 15 - owner */ 169 }; 170 171 struct rdesc1 { 172 __le16 PQTAG; 173 u8 CSM; 174 u8 IPKT; 175 }; 176 177 enum { 178 RX_INTEN = cpu_to_le16(0x8000) 179 }; 180 181 struct rx_desc { 182 struct rdesc0 rdesc0; 183 struct rdesc1 rdesc1; 184 __le32 pa_low; /* Low 32 bit PCI address */ 185 __le16 pa_high; /* Next 16 bit PCI address (48 total) */ 186 __le16 size; /* bits 0--14 - frame size, bit 15 - enable int. */ 187 } __packed; 188 189 /* 190 * Transmit descriptor 191 */ 192 193 struct tdesc0 { 194 __le16 TSR; /* Transmit status register */ 195 __le16 len; /* bits 0--13 - size of frame, bit 15 - owner */ 196 }; 197 198 struct tdesc1 { 199 __le16 vlan; 200 u8 TCR; 201 u8 cmd; /* bits 0--1 - TCPLS, bits 4--7 - CMDZ */ 202 } __packed; 203 204 enum { 205 TD_QUEUE = cpu_to_le16(0x8000) 206 }; 207 208 struct td_buf { 209 __le32 pa_low; 210 __le16 pa_high; 211 __le16 size; /* bits 0--13 - size, bit 15 - queue */ 212 } __packed; 213 214 struct tx_desc { 215 struct tdesc0 tdesc0; 216 struct tdesc1 tdesc1; 217 struct td_buf td_buf[7]; 218 }; 219 220 struct velocity_rd_info { 221 struct sk_buff *skb; 222 dma_addr_t skb_dma; 223 }; 224 225 /* 226 * Used to track transmit side buffers. 227 */ 228 229 struct velocity_td_info { 230 struct sk_buff *skb; 231 int nskb_dma; 232 dma_addr_t skb_dma[7]; 233 }; 234 235 enum velocity_owner { 236 OWNED_BY_HOST = 0, 237 OWNED_BY_NIC = cpu_to_le16(0x8000) 238 }; 239 240 241 /* 242 * MAC registers and macros. 243 */ 244 245 246 #define MCAM_SIZE 64 247 #define VCAM_SIZE 64 248 #define TX_QUEUE_NO 4 249 250 #define MAX_HW_MIB_COUNTER 32 251 #define VELOCITY_MIN_MTU (64) 252 #define VELOCITY_MAX_MTU (9000) 253 254 /* 255 * Registers in the MAC 256 */ 257 258 #define MAC_REG_PAR 0x00 // physical address 259 #define MAC_REG_RCR 0x06 260 #define MAC_REG_TCR 0x07 261 #define MAC_REG_CR0_SET 0x08 262 #define MAC_REG_CR1_SET 0x09 263 #define MAC_REG_CR2_SET 0x0A 264 #define MAC_REG_CR3_SET 0x0B 265 #define MAC_REG_CR0_CLR 0x0C 266 #define MAC_REG_CR1_CLR 0x0D 267 #define MAC_REG_CR2_CLR 0x0E 268 #define MAC_REG_CR3_CLR 0x0F 269 #define MAC_REG_MAR 0x10 270 #define MAC_REG_CAM 0x10 271 #define MAC_REG_DEC_BASE_HI 0x18 272 #define MAC_REG_DBF_BASE_HI 0x1C 273 #define MAC_REG_ISR_CTL 0x20 274 #define MAC_REG_ISR_HOTMR 0x20 275 #define MAC_REG_ISR_TSUPTHR 0x20 276 #define MAC_REG_ISR_RSUPTHR 0x20 277 #define MAC_REG_ISR_CTL1 0x21 278 #define MAC_REG_TXE_SR 0x22 279 #define MAC_REG_RXE_SR 0x23 280 #define MAC_REG_ISR 0x24 281 #define MAC_REG_ISR0 0x24 282 #define MAC_REG_ISR1 0x25 283 #define MAC_REG_ISR2 0x26 284 #define MAC_REG_ISR3 0x27 285 #define MAC_REG_IMR 0x28 286 #define MAC_REG_IMR0 0x28 287 #define MAC_REG_IMR1 0x29 288 #define MAC_REG_IMR2 0x2A 289 #define MAC_REG_IMR3 0x2B 290 #define MAC_REG_TDCSR_SET 0x30 291 #define MAC_REG_RDCSR_SET 0x32 292 #define MAC_REG_TDCSR_CLR 0x34 293 #define MAC_REG_RDCSR_CLR 0x36 294 #define MAC_REG_RDBASE_LO 0x38 295 #define MAC_REG_RDINDX 0x3C 296 #define MAC_REG_TDBASE_LO 0x40 297 #define MAC_REG_RDCSIZE 0x50 298 #define MAC_REG_TDCSIZE 0x52 299 #define MAC_REG_TDINDX 0x54 300 #define MAC_REG_TDIDX0 0x54 301 #define MAC_REG_TDIDX1 0x56 302 #define MAC_REG_TDIDX2 0x58 303 #define MAC_REG_TDIDX3 0x5A 304 #define MAC_REG_PAUSE_TIMER 0x5C 305 #define MAC_REG_RBRDU 0x5E 306 #define MAC_REG_FIFO_TEST0 0x60 307 #define MAC_REG_FIFO_TEST1 0x64 308 #define MAC_REG_CAMADDR 0x68 309 #define MAC_REG_CAMCR 0x69 310 #define MAC_REG_GFTEST 0x6A 311 #define MAC_REG_FTSTCMD 0x6B 312 #define MAC_REG_MIICFG 0x6C 313 #define MAC_REG_MIISR 0x6D 314 #define MAC_REG_PHYSR0 0x6E 315 #define MAC_REG_PHYSR1 0x6F 316 #define MAC_REG_MIICR 0x70 317 #define MAC_REG_MIIADR 0x71 318 #define MAC_REG_MIIDATA 0x72 319 #define MAC_REG_SOFT_TIMER0 0x74 320 #define MAC_REG_SOFT_TIMER1 0x76 321 #define MAC_REG_CFGA 0x78 322 #define MAC_REG_CFGB 0x79 323 #define MAC_REG_CFGC 0x7A 324 #define MAC_REG_CFGD 0x7B 325 #define MAC_REG_DCFG0 0x7C 326 #define MAC_REG_DCFG1 0x7D 327 #define MAC_REG_MCFG0 0x7E 328 #define MAC_REG_MCFG1 0x7F 329 330 #define MAC_REG_TBIST 0x80 331 #define MAC_REG_RBIST 0x81 332 #define MAC_REG_PMCC 0x82 333 #define MAC_REG_STICKHW 0x83 334 #define MAC_REG_MIBCR 0x84 335 #define MAC_REG_EERSV 0x85 336 #define MAC_REG_REVID 0x86 337 #define MAC_REG_MIBREAD 0x88 338 #define MAC_REG_BPMA 0x8C 339 #define MAC_REG_EEWR_DATA 0x8C 340 #define MAC_REG_BPMD_WR 0x8F 341 #define MAC_REG_BPCMD 0x90 342 #define MAC_REG_BPMD_RD 0x91 343 #define MAC_REG_EECHKSUM 0x92 344 #define MAC_REG_EECSR 0x93 345 #define MAC_REG_EERD_DATA 0x94 346 #define MAC_REG_EADDR 0x96 347 #define MAC_REG_EMBCMD 0x97 348 #define MAC_REG_JMPSR0 0x98 349 #define MAC_REG_JMPSR1 0x99 350 #define MAC_REG_JMPSR2 0x9A 351 #define MAC_REG_JMPSR3 0x9B 352 #define MAC_REG_CHIPGSR 0x9C 353 #define MAC_REG_TESTCFG 0x9D 354 #define MAC_REG_DEBUG 0x9E 355 #define MAC_REG_CHIPGCR 0x9F /* Chip Operation and Diagnostic Control */ 356 #define MAC_REG_WOLCR0_SET 0xA0 357 #define MAC_REG_WOLCR1_SET 0xA1 358 #define MAC_REG_PWCFG_SET 0xA2 359 #define MAC_REG_WOLCFG_SET 0xA3 360 #define MAC_REG_WOLCR0_CLR 0xA4 361 #define MAC_REG_WOLCR1_CLR 0xA5 362 #define MAC_REG_PWCFG_CLR 0xA6 363 #define MAC_REG_WOLCFG_CLR 0xA7 364 #define MAC_REG_WOLSR0_SET 0xA8 365 #define MAC_REG_WOLSR1_SET 0xA9 366 #define MAC_REG_WOLSR0_CLR 0xAC 367 #define MAC_REG_WOLSR1_CLR 0xAD 368 #define MAC_REG_PATRN_CRC0 0xB0 369 #define MAC_REG_PATRN_CRC1 0xB2 370 #define MAC_REG_PATRN_CRC2 0xB4 371 #define MAC_REG_PATRN_CRC3 0xB6 372 #define MAC_REG_PATRN_CRC4 0xB8 373 #define MAC_REG_PATRN_CRC5 0xBA 374 #define MAC_REG_PATRN_CRC6 0xBC 375 #define MAC_REG_PATRN_CRC7 0xBE 376 #define MAC_REG_BYTEMSK0_0 0xC0 377 #define MAC_REG_BYTEMSK0_1 0xC4 378 #define MAC_REG_BYTEMSK0_2 0xC8 379 #define MAC_REG_BYTEMSK0_3 0xCC 380 #define MAC_REG_BYTEMSK1_0 0xD0 381 #define MAC_REG_BYTEMSK1_1 0xD4 382 #define MAC_REG_BYTEMSK1_2 0xD8 383 #define MAC_REG_BYTEMSK1_3 0xDC 384 #define MAC_REG_BYTEMSK2_0 0xE0 385 #define MAC_REG_BYTEMSK2_1 0xE4 386 #define MAC_REG_BYTEMSK2_2 0xE8 387 #define MAC_REG_BYTEMSK2_3 0xEC 388 #define MAC_REG_BYTEMSK3_0 0xF0 389 #define MAC_REG_BYTEMSK3_1 0xF4 390 #define MAC_REG_BYTEMSK3_2 0xF8 391 #define MAC_REG_BYTEMSK3_3 0xFC 392 393 /* 394 * Bits in the RCR register 395 */ 396 397 #define RCR_AS 0x80 398 #define RCR_AP 0x40 399 #define RCR_AL 0x20 400 #define RCR_PROM 0x10 401 #define RCR_AB 0x08 402 #define RCR_AM 0x04 403 #define RCR_AR 0x02 404 #define RCR_SEP 0x01 405 406 /* 407 * Bits in the TCR register 408 */ 409 410 #define TCR_TB2BDIS 0x80 411 #define TCR_COLTMC1 0x08 412 #define TCR_COLTMC0 0x04 413 #define TCR_LB1 0x02 /* loopback[1] */ 414 #define TCR_LB0 0x01 /* loopback[0] */ 415 416 /* 417 * Bits in the CR0 register 418 */ 419 420 #define CR0_TXON 0x00000008UL 421 #define CR0_RXON 0x00000004UL 422 #define CR0_STOP 0x00000002UL /* stop MAC, default = 1 */ 423 #define CR0_STRT 0x00000001UL /* start MAC */ 424 #define CR0_SFRST 0x00008000UL /* software reset */ 425 #define CR0_TM1EN 0x00004000UL 426 #define CR0_TM0EN 0x00002000UL 427 #define CR0_DPOLL 0x00000800UL /* disable rx/tx auto polling */ 428 #define CR0_DISAU 0x00000100UL 429 #define CR0_XONEN 0x00800000UL 430 #define CR0_FDXTFCEN 0x00400000UL /* full-duplex TX flow control enable */ 431 #define CR0_FDXRFCEN 0x00200000UL /* full-duplex RX flow control enable */ 432 #define CR0_HDXFCEN 0x00100000UL /* half-duplex flow control enable */ 433 #define CR0_XHITH1 0x00080000UL /* TX XON high threshold 1 */ 434 #define CR0_XHITH0 0x00040000UL /* TX XON high threshold 0 */ 435 #define CR0_XLTH1 0x00020000UL /* TX pause frame low threshold 1 */ 436 #define CR0_XLTH0 0x00010000UL /* TX pause frame low threshold 0 */ 437 #define CR0_GSPRST 0x80000000UL 438 #define CR0_FORSRST 0x40000000UL 439 #define CR0_FPHYRST 0x20000000UL 440 #define CR0_DIAG 0x10000000UL 441 #define CR0_INTPCTL 0x04000000UL 442 #define CR0_GINTMSK1 0x02000000UL 443 #define CR0_GINTMSK0 0x01000000UL 444 445 /* 446 * Bits in the CR1 register 447 */ 448 449 #define CR1_SFRST 0x80 /* software reset */ 450 #define CR1_TM1EN 0x40 451 #define CR1_TM0EN 0x20 452 #define CR1_DPOLL 0x08 /* disable rx/tx auto polling */ 453 #define CR1_DISAU 0x01 454 455 /* 456 * Bits in the CR2 register 457 */ 458 459 #define CR2_XONEN 0x80 460 #define CR2_FDXTFCEN 0x40 /* full-duplex TX flow control enable */ 461 #define CR2_FDXRFCEN 0x20 /* full-duplex RX flow control enable */ 462 #define CR2_HDXFCEN 0x10 /* half-duplex flow control enable */ 463 #define CR2_XHITH1 0x08 /* TX XON high threshold 1 */ 464 #define CR2_XHITH0 0x04 /* TX XON high threshold 0 */ 465 #define CR2_XLTH1 0x02 /* TX pause frame low threshold 1 */ 466 #define CR2_XLTH0 0x01 /* TX pause frame low threshold 0 */ 467 468 /* 469 * Bits in the CR3 register 470 */ 471 472 #define CR3_GSPRST 0x80 473 #define CR3_FORSRST 0x40 474 #define CR3_FPHYRST 0x20 475 #define CR3_DIAG 0x10 476 #define CR3_INTPCTL 0x04 477 #define CR3_GINTMSK1 0x02 478 #define CR3_GINTMSK0 0x01 479 480 #define ISRCTL_UDPINT 0x8000 481 #define ISRCTL_TSUPDIS 0x4000 482 #define ISRCTL_RSUPDIS 0x2000 483 #define ISRCTL_PMSK1 0x1000 484 #define ISRCTL_PMSK0 0x0800 485 #define ISRCTL_INTPD 0x0400 486 #define ISRCTL_HCRLD 0x0200 487 #define ISRCTL_SCRLD 0x0100 488 489 /* 490 * Bits in the ISR_CTL1 register 491 */ 492 493 #define ISRCTL1_UDPINT 0x80 494 #define ISRCTL1_TSUPDIS 0x40 495 #define ISRCTL1_RSUPDIS 0x20 496 #define ISRCTL1_PMSK1 0x10 497 #define ISRCTL1_PMSK0 0x08 498 #define ISRCTL1_INTPD 0x04 499 #define ISRCTL1_HCRLD 0x02 500 #define ISRCTL1_SCRLD 0x01 501 502 /* 503 * Bits in the TXE_SR register 504 */ 505 506 #define TXESR_TFDBS 0x08 507 #define TXESR_TDWBS 0x04 508 #define TXESR_TDRBS 0x02 509 #define TXESR_TDSTR 0x01 510 511 /* 512 * Bits in the RXE_SR register 513 */ 514 515 #define RXESR_RFDBS 0x08 516 #define RXESR_RDWBS 0x04 517 #define RXESR_RDRBS 0x02 518 #define RXESR_RDSTR 0x01 519 520 /* 521 * Bits in the ISR register 522 */ 523 524 #define ISR_ISR3 0x80000000UL 525 #define ISR_ISR2 0x40000000UL 526 #define ISR_ISR1 0x20000000UL 527 #define ISR_ISR0 0x10000000UL 528 #define ISR_TXSTLI 0x02000000UL 529 #define ISR_RXSTLI 0x01000000UL 530 #define ISR_HFLD 0x00800000UL 531 #define ISR_UDPI 0x00400000UL 532 #define ISR_MIBFI 0x00200000UL 533 #define ISR_SHDNI 0x00100000UL 534 #define ISR_PHYI 0x00080000UL 535 #define ISR_PWEI 0x00040000UL 536 #define ISR_TMR1I 0x00020000UL 537 #define ISR_TMR0I 0x00010000UL 538 #define ISR_SRCI 0x00008000UL 539 #define ISR_LSTPEI 0x00004000UL 540 #define ISR_LSTEI 0x00002000UL 541 #define ISR_OVFI 0x00001000UL 542 #define ISR_FLONI 0x00000800UL 543 #define ISR_RACEI 0x00000400UL 544 #define ISR_TXWB1I 0x00000200UL 545 #define ISR_TXWB0I 0x00000100UL 546 #define ISR_PTX3I 0x00000080UL 547 #define ISR_PTX2I 0x00000040UL 548 #define ISR_PTX1I 0x00000020UL 549 #define ISR_PTX0I 0x00000010UL 550 #define ISR_PTXI 0x00000008UL 551 #define ISR_PRXI 0x00000004UL 552 #define ISR_PPTXI 0x00000002UL 553 #define ISR_PPRXI 0x00000001UL 554 555 /* 556 * Bits in the IMR register 557 */ 558 559 #define IMR_TXSTLM 0x02000000UL 560 #define IMR_UDPIM 0x00400000UL 561 #define IMR_MIBFIM 0x00200000UL 562 #define IMR_SHDNIM 0x00100000UL 563 #define IMR_PHYIM 0x00080000UL 564 #define IMR_PWEIM 0x00040000UL 565 #define IMR_TMR1IM 0x00020000UL 566 #define IMR_TMR0IM 0x00010000UL 567 568 #define IMR_SRCIM 0x00008000UL 569 #define IMR_LSTPEIM 0x00004000UL 570 #define IMR_LSTEIM 0x00002000UL 571 #define IMR_OVFIM 0x00001000UL 572 #define IMR_FLONIM 0x00000800UL 573 #define IMR_RACEIM 0x00000400UL 574 #define IMR_TXWB1IM 0x00000200UL 575 #define IMR_TXWB0IM 0x00000100UL 576 577 #define IMR_PTX3IM 0x00000080UL 578 #define IMR_PTX2IM 0x00000040UL 579 #define IMR_PTX1IM 0x00000020UL 580 #define IMR_PTX0IM 0x00000010UL 581 #define IMR_PTXIM 0x00000008UL 582 #define IMR_PRXIM 0x00000004UL 583 #define IMR_PPTXIM 0x00000002UL 584 #define IMR_PPRXIM 0x00000001UL 585 586 /* 0x0013FB0FUL = initial value of IMR */ 587 588 #define INT_MASK_DEF (IMR_PPTXIM|IMR_PPRXIM|IMR_PTXIM|IMR_PRXIM|\ 589 IMR_PWEIM|IMR_TXWB0IM|IMR_TXWB1IM|IMR_FLONIM|\ 590 IMR_OVFIM|IMR_LSTEIM|IMR_LSTPEIM|IMR_SRCIM|IMR_MIBFIM|\ 591 IMR_SHDNIM|IMR_TMR1IM|IMR_TMR0IM|IMR_TXSTLM) 592 593 /* 594 * Bits in the TDCSR0/1, RDCSR0 register 595 */ 596 597 #define TRDCSR_DEAD 0x0008 598 #define TRDCSR_WAK 0x0004 599 #define TRDCSR_ACT 0x0002 600 #define TRDCSR_RUN 0x0001 601 602 /* 603 * Bits in the CAMADDR register 604 */ 605 606 #define CAMADDR_CAMEN 0x80 607 #define CAMADDR_VCAMSL 0x40 608 609 /* 610 * Bits in the CAMCR register 611 */ 612 613 #define CAMCR_PS1 0x80 614 #define CAMCR_PS0 0x40 615 #define CAMCR_AITRPKT 0x20 616 #define CAMCR_AITR16 0x10 617 #define CAMCR_CAMRD 0x08 618 #define CAMCR_CAMWR 0x04 619 #define CAMCR_PS_CAM_MASK 0x40 620 #define CAMCR_PS_CAM_DATA 0x80 621 #define CAMCR_PS_MAR 0x00 622 623 /* 624 * Bits in the MIICFG register 625 */ 626 627 #define MIICFG_MPO1 0x80 628 #define MIICFG_MPO0 0x40 629 #define MIICFG_MFDC 0x20 630 631 /* 632 * Bits in the MIISR register 633 */ 634 635 #define MIISR_MIDLE 0x80 636 637 /* 638 * Bits in the PHYSR0 register 639 */ 640 641 #define PHYSR0_PHYRST 0x80 642 #define PHYSR0_LINKGD 0x40 643 #define PHYSR0_FDPX 0x10 644 #define PHYSR0_SPDG 0x08 645 #define PHYSR0_SPD10 0x04 646 #define PHYSR0_RXFLC 0x02 647 #define PHYSR0_TXFLC 0x01 648 649 /* 650 * Bits in the PHYSR1 register 651 */ 652 653 #define PHYSR1_PHYTBI 0x01 654 655 /* 656 * Bits in the MIICR register 657 */ 658 659 #define MIICR_MAUTO 0x80 660 #define MIICR_RCMD 0x40 661 #define MIICR_WCMD 0x20 662 #define MIICR_MDPM 0x10 663 #define MIICR_MOUT 0x08 664 #define MIICR_MDO 0x04 665 #define MIICR_MDI 0x02 666 #define MIICR_MDC 0x01 667 668 /* 669 * Bits in the MIIADR register 670 */ 671 672 #define MIIADR_SWMPL 0x80 673 674 /* 675 * Bits in the CFGA register 676 */ 677 678 #define CFGA_PMHCTG 0x08 679 #define CFGA_GPIO1PD 0x04 680 #define CFGA_ABSHDN 0x02 681 #define CFGA_PACPI 0x01 682 683 /* 684 * Bits in the CFGB register 685 */ 686 687 #define CFGB_GTCKOPT 0x80 688 #define CFGB_MIIOPT 0x40 689 #define CFGB_CRSEOPT 0x20 690 #define CFGB_OFSET 0x10 691 #define CFGB_CRANDOM 0x08 692 #define CFGB_CAP 0x04 693 #define CFGB_MBA 0x02 694 #define CFGB_BAKOPT 0x01 695 696 /* 697 * Bits in the CFGC register 698 */ 699 700 #define CFGC_EELOAD 0x80 701 #define CFGC_BROPT 0x40 702 #define CFGC_DLYEN 0x20 703 #define CFGC_DTSEL 0x10 704 #define CFGC_BTSEL 0x08 705 #define CFGC_BPS2 0x04 /* bootrom select[2] */ 706 #define CFGC_BPS1 0x02 /* bootrom select[1] */ 707 #define CFGC_BPS0 0x01 /* bootrom select[0] */ 708 709 /* 710 * Bits in the CFGD register 711 */ 712 713 #define CFGD_IODIS 0x80 714 #define CFGD_MSLVDACEN 0x40 715 #define CFGD_CFGDACEN 0x20 716 #define CFGD_PCI64EN 0x10 717 #define CFGD_HTMRL4 0x08 718 719 /* 720 * Bits in the DCFG1 register 721 */ 722 723 #define DCFG_XMWI 0x8000 724 #define DCFG_XMRM 0x4000 725 #define DCFG_XMRL 0x2000 726 #define DCFG_PERDIS 0x1000 727 #define DCFG_MRWAIT 0x0400 728 #define DCFG_MWWAIT 0x0200 729 #define DCFG_LATMEN 0x0100 730 731 /* 732 * Bits in the MCFG0 register 733 */ 734 735 #define MCFG_RXARB 0x0080 736 #define MCFG_RFT1 0x0020 737 #define MCFG_RFT0 0x0010 738 #define MCFG_LOWTHOPT 0x0008 739 #define MCFG_PQEN 0x0004 740 #define MCFG_RTGOPT 0x0002 741 #define MCFG_VIDFR 0x0001 742 743 /* 744 * Bits in the MCFG1 register 745 */ 746 747 #define MCFG_TXARB 0x8000 748 #define MCFG_TXQBK1 0x0800 749 #define MCFG_TXQBK0 0x0400 750 #define MCFG_TXQNOBK 0x0200 751 #define MCFG_SNAPOPT 0x0100 752 753 /* 754 * Bits in the PMCC register 755 */ 756 757 #define PMCC_DSI 0x80 758 #define PMCC_D2_DIS 0x40 759 #define PMCC_D1_DIS 0x20 760 #define PMCC_D3C_EN 0x10 761 #define PMCC_D3H_EN 0x08 762 #define PMCC_D2_EN 0x04 763 #define PMCC_D1_EN 0x02 764 #define PMCC_D0_EN 0x01 765 766 /* 767 * Bits in STICKHW 768 */ 769 770 #define STICKHW_SWPTAG 0x10 771 #define STICKHW_WOLSR 0x08 772 #define STICKHW_WOLEN 0x04 773 #define STICKHW_DS1 0x02 /* R/W by software/cfg cycle */ 774 #define STICKHW_DS0 0x01 /* suspend well DS write port */ 775 776 /* 777 * Bits in the MIBCR register 778 */ 779 780 #define MIBCR_MIBISTOK 0x80 781 #define MIBCR_MIBISTGO 0x40 782 #define MIBCR_MIBINC 0x20 783 #define MIBCR_MIBHI 0x10 784 #define MIBCR_MIBFRZ 0x08 785 #define MIBCR_MIBFLSH 0x04 786 #define MIBCR_MPTRINI 0x02 787 #define MIBCR_MIBCLR 0x01 788 789 /* 790 * Bits in the EERSV register 791 */ 792 793 #define EERSV_BOOT_RPL ((u8) 0x01) /* Boot method selection for VT6110 */ 794 795 #define EERSV_BOOT_MASK ((u8) 0x06) 796 #define EERSV_BOOT_INT19 ((u8) 0x00) 797 #define EERSV_BOOT_INT18 ((u8) 0x02) 798 #define EERSV_BOOT_LOCAL ((u8) 0x04) 799 #define EERSV_BOOT_BEV ((u8) 0x06) 800 801 802 /* 803 * Bits in BPCMD 804 */ 805 806 #define BPCMD_BPDNE 0x80 807 #define BPCMD_EBPWR 0x02 808 #define BPCMD_EBPRD 0x01 809 810 /* 811 * Bits in the EECSR register 812 */ 813 814 #define EECSR_EMBP 0x40 /* eeprom embedded programming */ 815 #define EECSR_RELOAD 0x20 /* eeprom content reload */ 816 #define EECSR_DPM 0x10 /* eeprom direct programming */ 817 #define EECSR_ECS 0x08 /* eeprom CS pin */ 818 #define EECSR_ECK 0x04 /* eeprom CK pin */ 819 #define EECSR_EDI 0x02 /* eeprom DI pin */ 820 #define EECSR_EDO 0x01 /* eeprom DO pin */ 821 822 /* 823 * Bits in the EMBCMD register 824 */ 825 826 #define EMBCMD_EDONE 0x80 827 #define EMBCMD_EWDIS 0x08 828 #define EMBCMD_EWEN 0x04 829 #define EMBCMD_EWR 0x02 830 #define EMBCMD_ERD 0x01 831 832 /* 833 * Bits in TESTCFG register 834 */ 835 836 #define TESTCFG_HBDIS 0x80 837 838 /* 839 * Bits in CHIPGCR register 840 */ 841 842 #define CHIPGCR_FCGMII 0x80 /* force GMII (else MII only) */ 843 #define CHIPGCR_FCFDX 0x40 /* force full duplex */ 844 #define CHIPGCR_FCRESV 0x20 845 #define CHIPGCR_FCMODE 0x10 /* enable MAC forced mode */ 846 #define CHIPGCR_LPSOPT 0x08 847 #define CHIPGCR_TM1US 0x04 848 #define CHIPGCR_TM0US 0x02 849 #define CHIPGCR_PHYINTEN 0x01 850 851 /* 852 * Bits in WOLCR0 853 */ 854 855 #define WOLCR_MSWOLEN7 0x0080 /* enable pattern match filtering */ 856 #define WOLCR_MSWOLEN6 0x0040 857 #define WOLCR_MSWOLEN5 0x0020 858 #define WOLCR_MSWOLEN4 0x0010 859 #define WOLCR_MSWOLEN3 0x0008 860 #define WOLCR_MSWOLEN2 0x0004 861 #define WOLCR_MSWOLEN1 0x0002 862 #define WOLCR_MSWOLEN0 0x0001 863 #define WOLCR_ARP_EN 0x0001 864 865 /* 866 * Bits in WOLCR1 867 */ 868 869 #define WOLCR_LINKOFF_EN 0x0800 /* link off detected enable */ 870 #define WOLCR_LINKON_EN 0x0400 /* link on detected enable */ 871 #define WOLCR_MAGIC_EN 0x0200 /* magic packet filter enable */ 872 #define WOLCR_UNICAST_EN 0x0100 /* unicast filter enable */ 873 874 875 /* 876 * Bits in PWCFG 877 */ 878 879 #define PWCFG_PHYPWOPT 0x80 /* internal MII I/F timing */ 880 #define PWCFG_PCISTICK 0x40 /* PCI sticky R/W enable */ 881 #define PWCFG_WOLTYPE 0x20 /* pulse(1) or button (0) */ 882 #define PWCFG_LEGCY_WOL 0x10 883 #define PWCFG_PMCSR_PME_SR 0x08 884 #define PWCFG_PMCSR_PME_EN 0x04 /* control by PCISTICK */ 885 #define PWCFG_LEGACY_WOLSR 0x02 /* Legacy WOL_SR shadow */ 886 #define PWCFG_LEGACY_WOLEN 0x01 /* Legacy WOL_EN shadow */ 887 888 /* 889 * Bits in WOLCFG 890 */ 891 892 #define WOLCFG_PMEOVR 0x80 /* for legacy use, force PMEEN always */ 893 #define WOLCFG_SAM 0x20 /* accept multicast case reset, default=0 */ 894 #define WOLCFG_SAB 0x10 /* accept broadcast case reset, default=0 */ 895 #define WOLCFG_SMIIACC 0x08 /* ?? */ 896 #define WOLCFG_SGENWH 0x02 897 #define WOLCFG_PHYINTEN 0x01 /* 0:PHYINT trigger enable, 1:use internal MII 898 to report status change */ 899 /* 900 * Bits in WOLSR1 901 */ 902 903 #define WOLSR_LINKOFF_INT 0x0800 904 #define WOLSR_LINKON_INT 0x0400 905 #define WOLSR_MAGIC_INT 0x0200 906 #define WOLSR_UNICAST_INT 0x0100 907 908 /* 909 * Ethernet address filter type 910 */ 911 912 #define PKT_TYPE_NONE 0x0000 /* Turn off receiver */ 913 #define PKT_TYPE_DIRECTED 0x0001 /* obselete, directed address is always accepted */ 914 #define PKT_TYPE_MULTICAST 0x0002 915 #define PKT_TYPE_ALL_MULTICAST 0x0004 916 #define PKT_TYPE_BROADCAST 0x0008 917 #define PKT_TYPE_PROMISCUOUS 0x0020 918 #define PKT_TYPE_LONG 0x2000 /* NOTE.... the definition of LONG is >2048 bytes in our chip */ 919 #define PKT_TYPE_RUNT 0x4000 920 #define PKT_TYPE_ERROR 0x8000 /* Accept error packets, e.g. CRC error */ 921 922 /* 923 * Loopback mode 924 */ 925 926 #define MAC_LB_NONE 0x00 927 #define MAC_LB_INTERNAL 0x01 928 #define MAC_LB_EXTERNAL 0x02 929 930 /* 931 * Enabled mask value of irq 932 */ 933 934 #if defined(_SIM) 935 #define IMR_MASK_VALUE 0x0033FF0FUL /* initial value of IMR 936 set IMR0 to 0x0F according to spec */ 937 938 #else 939 #define IMR_MASK_VALUE 0x0013FB0FUL /* initial value of IMR 940 ignore MIBFI,RACEI to 941 reduce intr. frequency 942 NOTE.... do not enable NoBuf int mask at driver driver 943 when (1) NoBuf -> RxThreshold = SF 944 (2) OK -> RxThreshold = original value 945 */ 946 #endif 947 948 /* 949 * Revision id 950 */ 951 952 #define REV_ID_VT3119_A0 0x00 953 #define REV_ID_VT3119_A1 0x01 954 #define REV_ID_VT3216_A0 0x10 955 956 /* 957 * Max time out delay time 958 */ 959 960 #define W_MAX_TIMEOUT 0x0FFFU 961 962 963 /* 964 * MAC registers as a structure. Cannot be directly accessed this 965 * way but generates offsets for readl/writel() calls 966 */ 967 968 struct mac_regs { 969 volatile u8 PAR[6]; /* 0x00 */ 970 volatile u8 RCR; 971 volatile u8 TCR; 972 973 volatile __le32 CR0Set; /* 0x08 */ 974 volatile __le32 CR0Clr; /* 0x0C */ 975 976 volatile u8 MARCAM[8]; /* 0x10 */ 977 978 volatile __le32 DecBaseHi; /* 0x18 */ 979 volatile __le16 DbfBaseHi; /* 0x1C */ 980 volatile __le16 reserved_1E; 981 982 volatile __le16 ISRCTL; /* 0x20 */ 983 volatile u8 TXESR; 984 volatile u8 RXESR; 985 986 volatile __le32 ISR; /* 0x24 */ 987 volatile __le32 IMR; 988 989 volatile __le32 TDStatusPort; /* 0x2C */ 990 991 volatile __le16 TDCSRSet; /* 0x30 */ 992 volatile u8 RDCSRSet; 993 volatile u8 reserved_33; 994 volatile __le16 TDCSRClr; 995 volatile u8 RDCSRClr; 996 volatile u8 reserved_37; 997 998 volatile __le32 RDBaseLo; /* 0x38 */ 999 volatile __le16 RDIdx; /* 0x3C */ 1000 volatile u8 TQETMR; /* 0x3E, VT3216 and above only */ 1001 volatile u8 RQETMR; /* 0x3F, VT3216 and above only */ 1002 1003 volatile __le32 TDBaseLo[4]; /* 0x40 */ 1004 1005 volatile __le16 RDCSize; /* 0x50 */ 1006 volatile __le16 TDCSize; /* 0x52 */ 1007 volatile __le16 TDIdx[4]; /* 0x54 */ 1008 volatile __le16 tx_pause_timer; /* 0x5C */ 1009 volatile __le16 RBRDU; /* 0x5E */ 1010 1011 volatile __le32 FIFOTest0; /* 0x60 */ 1012 volatile __le32 FIFOTest1; /* 0x64 */ 1013 1014 volatile u8 CAMADDR; /* 0x68 */ 1015 volatile u8 CAMCR; /* 0x69 */ 1016 volatile u8 GFTEST; /* 0x6A */ 1017 volatile u8 FTSTCMD; /* 0x6B */ 1018 1019 volatile u8 MIICFG; /* 0x6C */ 1020 volatile u8 MIISR; 1021 volatile u8 PHYSR0; 1022 volatile u8 PHYSR1; 1023 volatile u8 MIICR; 1024 volatile u8 MIIADR; 1025 volatile __le16 MIIDATA; 1026 1027 volatile __le16 SoftTimer0; /* 0x74 */ 1028 volatile __le16 SoftTimer1; 1029 1030 volatile u8 CFGA; /* 0x78 */ 1031 volatile u8 CFGB; 1032 volatile u8 CFGC; 1033 volatile u8 CFGD; 1034 1035 volatile __le16 DCFG; /* 0x7C */ 1036 volatile __le16 MCFG; 1037 1038 volatile u8 TBIST; /* 0x80 */ 1039 volatile u8 RBIST; 1040 volatile u8 PMCPORT; 1041 volatile u8 STICKHW; 1042 1043 volatile u8 MIBCR; /* 0x84 */ 1044 volatile u8 reserved_85; 1045 volatile u8 rev_id; 1046 volatile u8 PORSTS; 1047 1048 volatile __le32 MIBData; /* 0x88 */ 1049 1050 volatile __le16 EEWrData; 1051 1052 volatile u8 reserved_8E; 1053 volatile u8 BPMDWr; 1054 volatile u8 BPCMD; 1055 volatile u8 BPMDRd; 1056 1057 volatile u8 EECHKSUM; /* 0x92 */ 1058 volatile u8 EECSR; 1059 1060 volatile __le16 EERdData; /* 0x94 */ 1061 volatile u8 EADDR; 1062 volatile u8 EMBCMD; 1063 1064 1065 volatile u8 JMPSR0; /* 0x98 */ 1066 volatile u8 JMPSR1; 1067 volatile u8 JMPSR2; 1068 volatile u8 JMPSR3; 1069 volatile u8 CHIPGSR; /* 0x9C */ 1070 volatile u8 TESTCFG; 1071 volatile u8 DEBUG; 1072 volatile u8 CHIPGCR; 1073 1074 volatile __le16 WOLCRSet; /* 0xA0 */ 1075 volatile u8 PWCFGSet; 1076 volatile u8 WOLCFGSet; 1077 1078 volatile __le16 WOLCRClr; /* 0xA4 */ 1079 volatile u8 PWCFGCLR; 1080 volatile u8 WOLCFGClr; 1081 1082 volatile __le16 WOLSRSet; /* 0xA8 */ 1083 volatile __le16 reserved_AA; 1084 1085 volatile __le16 WOLSRClr; /* 0xAC */ 1086 volatile __le16 reserved_AE; 1087 1088 volatile __le16 PatternCRC[8]; /* 0xB0 */ 1089 volatile __le32 ByteMask[4][4]; /* 0xC0 */ 1090 }; 1091 1092 1093 enum hw_mib { 1094 HW_MIB_ifRxAllPkts = 0, 1095 HW_MIB_ifRxOkPkts, 1096 HW_MIB_ifTxOkPkts, 1097 HW_MIB_ifRxErrorPkts, 1098 HW_MIB_ifRxRuntOkPkt, 1099 HW_MIB_ifRxRuntErrPkt, 1100 HW_MIB_ifRx64Pkts, 1101 HW_MIB_ifTx64Pkts, 1102 HW_MIB_ifRx65To127Pkts, 1103 HW_MIB_ifTx65To127Pkts, 1104 HW_MIB_ifRx128To255Pkts, 1105 HW_MIB_ifTx128To255Pkts, 1106 HW_MIB_ifRx256To511Pkts, 1107 HW_MIB_ifTx256To511Pkts, 1108 HW_MIB_ifRx512To1023Pkts, 1109 HW_MIB_ifTx512To1023Pkts, 1110 HW_MIB_ifRx1024To1518Pkts, 1111 HW_MIB_ifTx1024To1518Pkts, 1112 HW_MIB_ifTxEtherCollisions, 1113 HW_MIB_ifRxPktCRCE, 1114 HW_MIB_ifRxJumboPkts, 1115 HW_MIB_ifTxJumboPkts, 1116 HW_MIB_ifRxMacControlFrames, 1117 HW_MIB_ifTxMacControlFrames, 1118 HW_MIB_ifRxPktFAE, 1119 HW_MIB_ifRxLongOkPkt, 1120 HW_MIB_ifRxLongPktErrPkt, 1121 HW_MIB_ifTXSQEErrors, 1122 HW_MIB_ifRxNobuf, 1123 HW_MIB_ifRxSymbolErrors, 1124 HW_MIB_ifInRangeLengthErrors, 1125 HW_MIB_ifLateCollisions, 1126 HW_MIB_SIZE 1127 }; 1128 1129 enum chip_type { 1130 CHIP_TYPE_VT6110 = 1, 1131 }; 1132 1133 struct velocity_info_tbl { 1134 enum chip_type chip_id; 1135 const char *name; 1136 int txqueue; 1137 u32 flags; 1138 }; 1139 1140 #define mac_hw_mibs_init(regs) {\ 1141 BYTE_REG_BITS_ON(MIBCR_MIBFRZ,&((regs)->MIBCR));\ 1142 BYTE_REG_BITS_ON(MIBCR_MIBCLR,&((regs)->MIBCR));\ 1143 do {}\ 1144 while (BYTE_REG_BITS_IS_ON(MIBCR_MIBCLR,&((regs)->MIBCR)));\ 1145 BYTE_REG_BITS_OFF(MIBCR_MIBFRZ,&((regs)->MIBCR));\ 1146 } 1147 1148 #define mac_read_isr(regs) readl(&((regs)->ISR)) 1149 #define mac_write_isr(regs, x) writel((x),&((regs)->ISR)) 1150 #define mac_clear_isr(regs) writel(0xffffffffL,&((regs)->ISR)) 1151 1152 #define mac_write_int_mask(mask, regs) writel((mask),&((regs)->IMR)); 1153 #define mac_disable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Clr)) 1154 #define mac_enable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Set)) 1155 1156 #define mac_set_dma_length(regs, n) {\ 1157 BYTE_REG_BITS_SET((n),0x07,&((regs)->DCFG));\ 1158 } 1159 1160 #define mac_set_rx_thresh(regs, n) {\ 1161 BYTE_REG_BITS_SET((n),(MCFG_RFT0|MCFG_RFT1),&((regs)->MCFG));\ 1162 } 1163 1164 #define mac_rx_queue_run(regs) {\ 1165 writeb(TRDCSR_RUN, &((regs)->RDCSRSet));\ 1166 } 1167 1168 #define mac_rx_queue_wake(regs) {\ 1169 writeb(TRDCSR_WAK, &((regs)->RDCSRSet));\ 1170 } 1171 1172 #define mac_tx_queue_run(regs, n) {\ 1173 writew(TRDCSR_RUN<<((n)*4),&((regs)->TDCSRSet));\ 1174 } 1175 1176 #define mac_tx_queue_wake(regs, n) {\ 1177 writew(TRDCSR_WAK<<(n*4),&((regs)->TDCSRSet));\ 1178 } 1179 1180 static inline void mac_eeprom_reload(struct mac_regs __iomem * regs) { 1181 int i=0; 1182 1183 BYTE_REG_BITS_ON(EECSR_RELOAD,&(regs->EECSR)); 1184 do { 1185 udelay(10); 1186 if (i++>0x1000) 1187 break; 1188 } while (BYTE_REG_BITS_IS_ON(EECSR_RELOAD,&(regs->EECSR))); 1189 } 1190 1191 /* 1192 * Header for WOL definitions. Used to compute hashes 1193 */ 1194 1195 typedef u8 MCAM_ADDR[ETH_ALEN]; 1196 1197 struct arp_packet { 1198 u8 dest_mac[ETH_ALEN]; 1199 u8 src_mac[ETH_ALEN]; 1200 __be16 type; 1201 __be16 ar_hrd; 1202 __be16 ar_pro; 1203 u8 ar_hln; 1204 u8 ar_pln; 1205 __be16 ar_op; 1206 u8 ar_sha[ETH_ALEN]; 1207 u8 ar_sip[4]; 1208 u8 ar_tha[ETH_ALEN]; 1209 u8 ar_tip[4]; 1210 } __packed; 1211 1212 struct _magic_packet { 1213 u8 dest_mac[6]; 1214 u8 src_mac[6]; 1215 __be16 type; 1216 u8 MAC[16][6]; 1217 u8 password[6]; 1218 } __packed; 1219 1220 /* 1221 * Store for chip context when saving and restoring status. Not 1222 * all fields are saved/restored currently. 1223 */ 1224 1225 struct velocity_context { 1226 u8 mac_reg[256]; 1227 MCAM_ADDR cam_addr[MCAM_SIZE]; 1228 u16 vcam[VCAM_SIZE]; 1229 u32 cammask[2]; 1230 u32 patcrc[2]; 1231 u32 pattern[8]; 1232 }; 1233 1234 /* 1235 * Registers in the MII (offset unit is WORD) 1236 */ 1237 1238 // Marvell 88E1000/88E1000S 1239 #define MII_REG_PSCR 0x10 // PHY specific control register 1240 1241 // 1242 // Bits in the Silicon revision register 1243 // 1244 1245 #define TCSR_ECHODIS 0x2000 // 1246 #define AUXCR_MDPPS 0x0004 // 1247 1248 // Bits in the PLED register 1249 #define PLED_LALBE 0x0004 // 1250 1251 // Marvell 88E1000/88E1000S Bits in the PHY specific control register (10h) 1252 #define PSCR_ACRSTX 0x0800 // Assert CRS on Transmit 1253 1254 #define PHYID_CICADA_CS8201 0x000FC410UL 1255 #define PHYID_VT3216_32BIT 0x000FC610UL 1256 #define PHYID_VT3216_64BIT 0x000FC600UL 1257 #define PHYID_MARVELL_1000 0x01410C50UL 1258 #define PHYID_MARVELL_1000S 0x01410C40UL 1259 #define PHYID_ICPLUS_IP101A 0x02430C54UL 1260 #define PHYID_REV_ID_MASK 0x0000000FUL 1261 1262 #define PHYID_GET_PHY_ID(i) ((i) & ~PHYID_REV_ID_MASK) 1263 1264 #define MII_REG_BITS_ON(x,i,p) do {\ 1265 u16 w;\ 1266 velocity_mii_read((p),(i),&(w));\ 1267 (w)|=(x);\ 1268 velocity_mii_write((p),(i),(w));\ 1269 } while (0) 1270 1271 #define MII_REG_BITS_OFF(x,i,p) do {\ 1272 u16 w;\ 1273 velocity_mii_read((p),(i),&(w));\ 1274 (w)&=(~(x));\ 1275 velocity_mii_write((p),(i),(w));\ 1276 } while (0) 1277 1278 #define MII_REG_BITS_IS_ON(x,i,p) ({\ 1279 u16 w;\ 1280 velocity_mii_read((p),(i),&(w));\ 1281 ((int) ((w) & (x)));}) 1282 1283 #define MII_GET_PHY_ID(p) ({\ 1284 u32 id;\ 1285 velocity_mii_read((p),MII_PHYSID2,(u16 *) &id);\ 1286 velocity_mii_read((p),MII_PHYSID1,((u16 *) &id)+1);\ 1287 (id);}) 1288 1289 #define VELOCITY_WOL_MAGIC 0x00000000UL 1290 #define VELOCITY_WOL_PHY 0x00000001UL 1291 #define VELOCITY_WOL_ARP 0x00000002UL 1292 #define VELOCITY_WOL_UCAST 0x00000004UL 1293 #define VELOCITY_WOL_BCAST 0x00000010UL 1294 #define VELOCITY_WOL_MCAST 0x00000020UL 1295 #define VELOCITY_WOL_MAGIC_SEC 0x00000040UL 1296 1297 /* 1298 * Flags for options 1299 */ 1300 1301 #define VELOCITY_FLAGS_TAGGING 0x00000001UL 1302 #define VELOCITY_FLAGS_RX_CSUM 0x00000004UL 1303 #define VELOCITY_FLAGS_IP_ALIGN 0x00000008UL 1304 #define VELOCITY_FLAGS_VAL_PKT_LEN 0x00000010UL 1305 1306 #define VELOCITY_FLAGS_FLOW_CTRL 0x01000000UL 1307 1308 /* 1309 * Flags for driver status 1310 */ 1311 1312 #define VELOCITY_FLAGS_OPENED 0x00010000UL 1313 #define VELOCITY_FLAGS_VMNS_CONNECTED 0x00020000UL 1314 #define VELOCITY_FLAGS_VMNS_COMMITTED 0x00040000UL 1315 #define VELOCITY_FLAGS_WOL_ENABLED 0x00080000UL 1316 1317 /* 1318 * Flags for MII status 1319 */ 1320 1321 #define VELOCITY_LINK_FAIL 0x00000001UL 1322 #define VELOCITY_SPEED_10 0x00000002UL 1323 #define VELOCITY_SPEED_100 0x00000004UL 1324 #define VELOCITY_SPEED_1000 0x00000008UL 1325 #define VELOCITY_DUPLEX_FULL 0x00000010UL 1326 #define VELOCITY_AUTONEG_ENABLE 0x00000020UL 1327 #define VELOCITY_FORCED_BY_EEPROM 0x00000040UL 1328 1329 /* 1330 * For velocity_set_media_duplex 1331 */ 1332 1333 #define VELOCITY_LINK_CHANGE 0x00000001UL 1334 1335 enum speed_opt { 1336 SPD_DPX_AUTO = 0, 1337 SPD_DPX_100_HALF = 1, 1338 SPD_DPX_100_FULL = 2, 1339 SPD_DPX_10_HALF = 3, 1340 SPD_DPX_10_FULL = 4, 1341 SPD_DPX_1000_FULL = 5 1342 }; 1343 1344 enum velocity_init_type { 1345 VELOCITY_INIT_COLD = 0, 1346 VELOCITY_INIT_RESET, 1347 VELOCITY_INIT_WOL 1348 }; 1349 1350 enum velocity_flow_cntl_type { 1351 FLOW_CNTL_DEFAULT = 1, 1352 FLOW_CNTL_TX, 1353 FLOW_CNTL_RX, 1354 FLOW_CNTL_TX_RX, 1355 FLOW_CNTL_DISABLE, 1356 }; 1357 1358 struct velocity_opt { 1359 int numrx; /* Number of RX descriptors */ 1360 int numtx; /* Number of TX descriptors */ 1361 enum speed_opt spd_dpx; /* Media link mode */ 1362 1363 int DMA_length; /* DMA length */ 1364 int rx_thresh; /* RX_THRESH */ 1365 int flow_cntl; 1366 int wol_opts; /* Wake on lan options */ 1367 int td_int_count; 1368 int int_works; 1369 int rx_bandwidth_hi; 1370 int rx_bandwidth_lo; 1371 int rx_bandwidth_en; 1372 int rxqueue_timer; 1373 int txqueue_timer; 1374 int tx_intsup; 1375 int rx_intsup; 1376 u32 flags; 1377 }; 1378 1379 #define AVAIL_TD(p,q) ((p)->options.numtx-((p)->tx.used[(q)])) 1380 1381 #define GET_RD_BY_IDX(vptr, idx) (vptr->rd_ring[idx]) 1382 1383 struct velocity_info { 1384 struct device *dev; 1385 struct pci_dev *pdev; 1386 struct net_device *netdev; 1387 int no_eeprom; 1388 1389 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 1390 u8 ip_addr[4]; 1391 enum chip_type chip_id; 1392 1393 struct mac_regs __iomem * mac_regs; 1394 unsigned long memaddr; 1395 unsigned long ioaddr; 1396 1397 struct tx_info { 1398 int numq; 1399 1400 /* FIXME: the locality of the data seems rather poor. */ 1401 int used[TX_QUEUE_NO]; 1402 int curr[TX_QUEUE_NO]; 1403 int tail[TX_QUEUE_NO]; 1404 struct tx_desc *rings[TX_QUEUE_NO]; 1405 struct velocity_td_info *infos[TX_QUEUE_NO]; 1406 dma_addr_t pool_dma[TX_QUEUE_NO]; 1407 } tx; 1408 1409 struct rx_info { 1410 int buf_sz; 1411 1412 int dirty; 1413 int curr; 1414 u32 filled; 1415 struct rx_desc *ring; 1416 struct velocity_rd_info *info; /* It's an array */ 1417 dma_addr_t pool_dma; 1418 } rx; 1419 1420 u32 mib_counter[MAX_HW_MIB_COUNTER]; 1421 struct velocity_opt options; 1422 1423 u32 int_mask; 1424 1425 u32 flags; 1426 1427 u32 mii_status; 1428 u32 phy_id; 1429 int multicast_limit; 1430 1431 u8 vCAMmask[(VCAM_SIZE / 8)]; 1432 u8 mCAMmask[(MCAM_SIZE / 8)]; 1433 1434 spinlock_t lock; 1435 1436 int wol_opts; 1437 u8 wol_passwd[6]; 1438 1439 struct velocity_context context; 1440 1441 u32 ticks; 1442 u32 ethtool_ops_nesting; 1443 1444 u8 rev_id; 1445 1446 struct napi_struct napi; 1447 }; 1448 1449 /** 1450 * velocity_get_ip - find an IP address for the device 1451 * @vptr: Velocity to query 1452 * 1453 * Dig out an IP address for this interface so that we can 1454 * configure wakeup with WOL for ARP. If there are multiple IP 1455 * addresses on this chain then we use the first - multi-IP WOL is not 1456 * supported. 1457 * 1458 */ 1459 1460 static inline int velocity_get_ip(struct velocity_info *vptr) 1461 { 1462 struct in_device *in_dev; 1463 struct in_ifaddr *ifa; 1464 int res = -ENOENT; 1465 1466 rcu_read_lock(); 1467 in_dev = __in_dev_get_rcu(vptr->netdev); 1468 if (in_dev != NULL) { 1469 ifa = rcu_dereference(in_dev->ifa_list); 1470 if (ifa != NULL) { 1471 memcpy(vptr->ip_addr, &ifa->ifa_address, 4); 1472 res = 0; 1473 } 1474 } 1475 rcu_read_unlock(); 1476 return res; 1477 } 1478 1479 /** 1480 * velocity_update_hw_mibs - fetch MIB counters from chip 1481 * @vptr: velocity to update 1482 * 1483 * The velocity hardware keeps certain counters in the hardware 1484 * side. We need to read these when the user asks for statistics 1485 * or when they overflow (causing an interrupt). The read of the 1486 * statistic clears it, so we keep running master counters in user 1487 * space. 1488 */ 1489 1490 static inline void velocity_update_hw_mibs(struct velocity_info *vptr) 1491 { 1492 u32 tmp; 1493 int i; 1494 BYTE_REG_BITS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR)); 1495 1496 while (BYTE_REG_BITS_IS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR))); 1497 1498 BYTE_REG_BITS_ON(MIBCR_MPTRINI, &(vptr->mac_regs->MIBCR)); 1499 for (i = 0; i < HW_MIB_SIZE; i++) { 1500 tmp = readl(&(vptr->mac_regs->MIBData)) & 0x00FFFFFFUL; 1501 vptr->mib_counter[i] += tmp; 1502 } 1503 } 1504 1505 /** 1506 * init_flow_control_register - set up flow control 1507 * @vptr: velocity to configure 1508 * 1509 * Configure the flow control registers for this velocity device. 1510 */ 1511 1512 static inline void init_flow_control_register(struct velocity_info *vptr) 1513 { 1514 struct mac_regs __iomem * regs = vptr->mac_regs; 1515 1516 /* Set {XHITH1, XHITH0, XLTH1, XLTH0} in FlowCR1 to {1, 0, 1, 1} 1517 depend on RD=64, and Turn on XNOEN in FlowCR1 */ 1518 writel((CR0_XONEN | CR0_XHITH1 | CR0_XLTH1 | CR0_XLTH0), ®s->CR0Set); 1519 writel((CR0_FDXTFCEN | CR0_FDXRFCEN | CR0_HDXFCEN | CR0_XHITH0), ®s->CR0Clr); 1520 1521 /* Set TxPauseTimer to 0xFFFF */ 1522 writew(0xFFFF, ®s->tx_pause_timer); 1523 1524 /* Initialize RBRDU to Rx buffer count. */ 1525 writew(vptr->options.numrx, ®s->RBRDU); 1526 } 1527 1528 1529 #endif 1530