1 /* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */ 2 /* 3 Written 1998-2001 by Donald Becker. 4 5 Current Maintainer: Roger Luethi <rl@hellgate.ch> 6 7 This software may be used and distributed according to the terms of 8 the GNU General Public License (GPL), incorporated herein by reference. 9 Drivers based on or derived from this code fall under the GPL and must 10 retain the authorship, copyright and license notice. This file is not 11 a complete program and may only be used when the entire operating 12 system is licensed under the GPL. 13 14 This driver is designed for the VIA VT86C100A Rhine-I. 15 It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM 16 and management NIC 6105M). 17 18 The author may be reached as becker@scyld.com, or C/O 19 Scyld Computing Corporation 20 410 Severn Ave., Suite 210 21 Annapolis MD 21403 22 23 24 This driver contains some changes from the original Donald Becker 25 version. He may or may not be interested in bug reports on this 26 code. You can find his versions at: 27 http://www.scyld.com/network/via-rhine.html 28 [link no longer provides useful info -jgarzik] 29 30 */ 31 32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 33 34 #define DRV_NAME "via-rhine" 35 #define DRV_VERSION "1.5.1" 36 #define DRV_RELDATE "2010-10-09" 37 38 #include <linux/types.h> 39 40 /* A few user-configurable values. 41 These may be modified when a driver module is loaded. */ 42 static int debug = 0; 43 #define RHINE_MSG_DEFAULT \ 44 (0x0000) 45 46 /* Set the copy breakpoint for the copy-only-tiny-frames scheme. 47 Setting to > 1518 effectively disables this feature. */ 48 #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \ 49 defined(CONFIG_SPARC) || defined(__ia64__) || \ 50 defined(__sh__) || defined(__mips__) 51 static int rx_copybreak = 1518; 52 #else 53 static int rx_copybreak; 54 #endif 55 56 /* Work-around for broken BIOSes: they are unable to get the chip back out of 57 power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */ 58 static bool avoid_D3; 59 60 /* 61 * In case you are looking for 'options[]' or 'full_duplex[]', they 62 * are gone. Use ethtool(8) instead. 63 */ 64 65 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast). 66 The Rhine has a 64 element 8390-like hash table. */ 67 static const int multicast_filter_limit = 32; 68 69 70 /* Operational parameters that are set at compile time. */ 71 72 /* Keep the ring sizes a power of two for compile efficiency. 73 The compiler will convert <unsigned>'%'<2^N> into a bit mask. 74 Making the Tx ring too large decreases the effectiveness of channel 75 bonding and packet priority. 76 There are no ill effects from too-large receive rings. */ 77 #define TX_RING_SIZE 16 78 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */ 79 #define RX_RING_SIZE 64 80 81 /* Operational parameters that usually are not changed. */ 82 83 /* Time in jiffies before concluding the transmitter is hung. */ 84 #define TX_TIMEOUT (2*HZ) 85 86 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ 87 88 #include <linux/module.h> 89 #include <linux/moduleparam.h> 90 #include <linux/kernel.h> 91 #include <linux/string.h> 92 #include <linux/timer.h> 93 #include <linux/errno.h> 94 #include <linux/ioport.h> 95 #include <linux/interrupt.h> 96 #include <linux/pci.h> 97 #include <linux/dma-mapping.h> 98 #include <linux/netdevice.h> 99 #include <linux/etherdevice.h> 100 #include <linux/skbuff.h> 101 #include <linux/init.h> 102 #include <linux/delay.h> 103 #include <linux/mii.h> 104 #include <linux/ethtool.h> 105 #include <linux/crc32.h> 106 #include <linux/if_vlan.h> 107 #include <linux/bitops.h> 108 #include <linux/workqueue.h> 109 #include <asm/processor.h> /* Processor type for cache alignment. */ 110 #include <asm/io.h> 111 #include <asm/irq.h> 112 #include <asm/uaccess.h> 113 #include <linux/dmi.h> 114 115 /* These identify the driver base version and may not be removed. */ 116 static const char version[] = 117 "v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker"; 118 119 /* This driver was written to use PCI memory space. Some early versions 120 of the Rhine may only work correctly with I/O space accesses. */ 121 #ifdef CONFIG_VIA_RHINE_MMIO 122 #define USE_MMIO 123 #else 124 #endif 125 126 MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); 127 MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver"); 128 MODULE_LICENSE("GPL"); 129 130 module_param(debug, int, 0); 131 module_param(rx_copybreak, int, 0); 132 module_param(avoid_D3, bool, 0); 133 MODULE_PARM_DESC(debug, "VIA Rhine debug message flags"); 134 MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames"); 135 MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)"); 136 137 #define MCAM_SIZE 32 138 #define VCAM_SIZE 32 139 140 /* 141 Theory of Operation 142 143 I. Board Compatibility 144 145 This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet 146 controller. 147 148 II. Board-specific settings 149 150 Boards with this chip are functional only in a bus-master PCI slot. 151 152 Many operational settings are loaded from the EEPROM to the Config word at 153 offset 0x78. For most of these settings, this driver assumes that they are 154 correct. 155 If this driver is compiled to use PCI memory space operations the EEPROM 156 must be configured to enable memory ops. 157 158 III. Driver operation 159 160 IIIa. Ring buffers 161 162 This driver uses two statically allocated fixed-size descriptor lists 163 formed into rings by a branch from the final descriptor to the beginning of 164 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE. 165 166 IIIb/c. Transmit/Receive Structure 167 168 This driver attempts to use a zero-copy receive and transmit scheme. 169 170 Alas, all data buffers are required to start on a 32 bit boundary, so 171 the driver must often copy transmit packets into bounce buffers. 172 173 The driver allocates full frame size skbuffs for the Rx ring buffers at 174 open() time and passes the skb->data field to the chip as receive data 175 buffers. When an incoming frame is less than RX_COPYBREAK bytes long, 176 a fresh skbuff is allocated and the frame is copied to the new skbuff. 177 When the incoming frame is larger, the skbuff is passed directly up the 178 protocol stack. Buffers consumed this way are replaced by newly allocated 179 skbuffs in the last phase of rhine_rx(). 180 181 The RX_COPYBREAK value is chosen to trade-off the memory wasted by 182 using a full-sized skbuff for small frames vs. the copying costs of larger 183 frames. New boards are typically used in generously configured machines 184 and the underfilled buffers have negligible impact compared to the benefit of 185 a single allocation size, so the default value of zero results in never 186 copying packets. When copying is done, the cost is usually mitigated by using 187 a combined copy/checksum routine. Copying also preloads the cache, which is 188 most useful with small frames. 189 190 Since the VIA chips are only able to transfer data to buffers on 32 bit 191 boundaries, the IP header at offset 14 in an ethernet frame isn't 192 longword aligned for further processing. Copying these unaligned buffers 193 has the beneficial effect of 16-byte aligning the IP header. 194 195 IIId. Synchronization 196 197 The driver runs as two independent, single-threaded flows of control. One 198 is the send-packet routine, which enforces single-threaded use by the 199 netdev_priv(dev)->lock spinlock. The other thread is the interrupt handler, 200 which is single threaded by the hardware and interrupt handling software. 201 202 The send packet thread has partial control over the Tx ring. It locks the 203 netdev_priv(dev)->lock whenever it's queuing a Tx packet. If the next slot in 204 the ring is not available it stops the transmit queue by 205 calling netif_stop_queue. 206 207 The interrupt handler has exclusive control over the Rx ring and records stats 208 from the Tx ring. After reaping the stats, it marks the Tx queue entry as 209 empty by incrementing the dirty_tx mark. If at least half of the entries in 210 the Rx ring are available the transmit queue is woken up if it was stopped. 211 212 IV. Notes 213 214 IVb. References 215 216 Preliminary VT86C100A manual from http://www.via.com.tw/ 217 http://www.scyld.com/expert/100mbps.html 218 http://www.scyld.com/expert/NWay.html 219 ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf 220 ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF 221 222 223 IVc. Errata 224 225 The VT86C100A manual is not reliable information. 226 The 3043 chip does not handle unaligned transmit or receive buffers, resulting 227 in significant performance degradation for bounce buffer copies on transmit 228 and unaligned IP headers on receive. 229 The chip does not pad to minimum transmit length. 230 231 */ 232 233 234 /* This table drives the PCI probe routines. It's mostly boilerplate in all 235 of the drivers, and will likely be provided by some future kernel. 236 Note the matching code -- the first table entry matchs all 56** cards but 237 second only the 1234 card. 238 */ 239 240 enum rhine_revs { 241 VT86C100A = 0x00, 242 VTunknown0 = 0x20, 243 VT6102 = 0x40, 244 VT8231 = 0x50, /* Integrated MAC */ 245 VT8233 = 0x60, /* Integrated MAC */ 246 VT8235 = 0x74, /* Integrated MAC */ 247 VT8237 = 0x78, /* Integrated MAC */ 248 VTunknown1 = 0x7C, 249 VT6105 = 0x80, 250 VT6105_B0 = 0x83, 251 VT6105L = 0x8A, 252 VT6107 = 0x8C, 253 VTunknown2 = 0x8E, 254 VT6105M = 0x90, /* Management adapter */ 255 }; 256 257 enum rhine_quirks { 258 rqWOL = 0x0001, /* Wake-On-LAN support */ 259 rqForceReset = 0x0002, 260 rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */ 261 rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */ 262 rqRhineI = 0x0100, /* See comment below */ 263 }; 264 /* 265 * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable 266 * MMIO as well as for the collision counter and the Tx FIFO underflow 267 * indicator. In addition, Tx and Rx buffers need to 4 byte aligned. 268 */ 269 270 /* Beware of PCI posted writes */ 271 #define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0) 272 273 static DEFINE_PCI_DEVICE_TABLE(rhine_pci_tbl) = { 274 { 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, }, /* VT86C100A */ 275 { 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6102 */ 276 { 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, }, /* 6105{,L,LOM} */ 277 { 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6105M */ 278 { } /* terminate list */ 279 }; 280 MODULE_DEVICE_TABLE(pci, rhine_pci_tbl); 281 282 283 /* Offsets to the device registers. */ 284 enum register_offsets { 285 StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08, 286 ChipCmd1=0x09, TQWake=0x0A, 287 IntrStatus=0x0C, IntrEnable=0x0E, 288 MulticastFilter0=0x10, MulticastFilter1=0x14, 289 RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54, 290 MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E, PCIBusConfig1=0x6F, 291 MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74, 292 ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B, 293 RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81, 294 StickyHW=0x83, IntrStatus2=0x84, 295 CamMask=0x88, CamCon=0x92, CamAddr=0x93, 296 WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4, 297 WOLcrClr1=0xA6, WOLcgClr=0xA7, 298 PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD, 299 }; 300 301 /* Bits in ConfigD */ 302 enum backoff_bits { 303 BackOptional=0x01, BackModify=0x02, 304 BackCaptureEffect=0x04, BackRandom=0x08 305 }; 306 307 /* Bits in the TxConfig (TCR) register */ 308 enum tcr_bits { 309 TCR_PQEN=0x01, 310 TCR_LB0=0x02, /* loopback[0] */ 311 TCR_LB1=0x04, /* loopback[1] */ 312 TCR_OFSET=0x08, 313 TCR_RTGOPT=0x10, 314 TCR_RTFT0=0x20, 315 TCR_RTFT1=0x40, 316 TCR_RTSF=0x80, 317 }; 318 319 /* Bits in the CamCon (CAMC) register */ 320 enum camcon_bits { 321 CAMC_CAMEN=0x01, 322 CAMC_VCAMSL=0x02, 323 CAMC_CAMWR=0x04, 324 CAMC_CAMRD=0x08, 325 }; 326 327 /* Bits in the PCIBusConfig1 (BCR1) register */ 328 enum bcr1_bits { 329 BCR1_POT0=0x01, 330 BCR1_POT1=0x02, 331 BCR1_POT2=0x04, 332 BCR1_CTFT0=0x08, 333 BCR1_CTFT1=0x10, 334 BCR1_CTSF=0x20, 335 BCR1_TXQNOBK=0x40, /* for VT6105 */ 336 BCR1_VIDFR=0x80, /* for VT6105 */ 337 BCR1_MED0=0x40, /* for VT6102 */ 338 BCR1_MED1=0x80, /* for VT6102 */ 339 }; 340 341 #ifdef USE_MMIO 342 /* Registers we check that mmio and reg are the same. */ 343 static const int mmio_verify_registers[] = { 344 RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD, 345 0 346 }; 347 #endif 348 349 /* Bits in the interrupt status/mask registers. */ 350 enum intr_status_bits { 351 IntrRxDone = 0x0001, 352 IntrTxDone = 0x0002, 353 IntrRxErr = 0x0004, 354 IntrTxError = 0x0008, 355 IntrRxEmpty = 0x0020, 356 IntrPCIErr = 0x0040, 357 IntrStatsMax = 0x0080, 358 IntrRxEarly = 0x0100, 359 IntrTxUnderrun = 0x0210, 360 IntrRxOverflow = 0x0400, 361 IntrRxDropped = 0x0800, 362 IntrRxNoBuf = 0x1000, 363 IntrTxAborted = 0x2000, 364 IntrLinkChange = 0x4000, 365 IntrRxWakeUp = 0x8000, 366 IntrTxDescRace = 0x080000, /* mapped from IntrStatus2 */ 367 IntrNormalSummary = IntrRxDone | IntrTxDone, 368 IntrTxErrSummary = IntrTxDescRace | IntrTxAborted | IntrTxError | 369 IntrTxUnderrun, 370 }; 371 372 /* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */ 373 enum wol_bits { 374 WOLucast = 0x10, 375 WOLmagic = 0x20, 376 WOLbmcast = 0x30, 377 WOLlnkon = 0x40, 378 WOLlnkoff = 0x80, 379 }; 380 381 /* The Rx and Tx buffer descriptors. */ 382 struct rx_desc { 383 __le32 rx_status; 384 __le32 desc_length; /* Chain flag, Buffer/frame length */ 385 __le32 addr; 386 __le32 next_desc; 387 }; 388 struct tx_desc { 389 __le32 tx_status; 390 __le32 desc_length; /* Chain flag, Tx Config, Frame length */ 391 __le32 addr; 392 __le32 next_desc; 393 }; 394 395 /* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */ 396 #define TXDESC 0x00e08000 397 398 enum rx_status_bits { 399 RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F 400 }; 401 402 /* Bits in *_desc.*_status */ 403 enum desc_status_bits { 404 DescOwn=0x80000000 405 }; 406 407 /* Bits in *_desc.*_length */ 408 enum desc_length_bits { 409 DescTag=0x00010000 410 }; 411 412 /* Bits in ChipCmd. */ 413 enum chip_cmd_bits { 414 CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08, 415 CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40, 416 Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04, 417 Cmd1NoTxPoll=0x08, Cmd1Reset=0x80, 418 }; 419 420 struct rhine_stats { 421 u64 packets; 422 u64 bytes; 423 struct u64_stats_sync syncp; 424 }; 425 426 struct rhine_private { 427 /* Bit mask for configured VLAN ids */ 428 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 429 430 /* Descriptor rings */ 431 struct rx_desc *rx_ring; 432 struct tx_desc *tx_ring; 433 dma_addr_t rx_ring_dma; 434 dma_addr_t tx_ring_dma; 435 436 /* The addresses of receive-in-place skbuffs. */ 437 struct sk_buff *rx_skbuff[RX_RING_SIZE]; 438 dma_addr_t rx_skbuff_dma[RX_RING_SIZE]; 439 440 /* The saved address of a sent-in-place packet/buffer, for later free(). */ 441 struct sk_buff *tx_skbuff[TX_RING_SIZE]; 442 dma_addr_t tx_skbuff_dma[TX_RING_SIZE]; 443 444 /* Tx bounce buffers (Rhine-I only) */ 445 unsigned char *tx_buf[TX_RING_SIZE]; 446 unsigned char *tx_bufs; 447 dma_addr_t tx_bufs_dma; 448 449 struct pci_dev *pdev; 450 long pioaddr; 451 struct net_device *dev; 452 struct napi_struct napi; 453 spinlock_t lock; 454 struct mutex task_lock; 455 bool task_enable; 456 struct work_struct slow_event_task; 457 struct work_struct reset_task; 458 459 u32 msg_enable; 460 461 /* Frequently used values: keep some adjacent for cache effect. */ 462 u32 quirks; 463 struct rx_desc *rx_head_desc; 464 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */ 465 unsigned int cur_tx, dirty_tx; 466 unsigned int rx_buf_sz; /* Based on MTU+slack. */ 467 struct rhine_stats rx_stats; 468 struct rhine_stats tx_stats; 469 u8 wolopts; 470 471 u8 tx_thresh, rx_thresh; 472 473 struct mii_if_info mii_if; 474 void __iomem *base; 475 }; 476 477 #define BYTE_REG_BITS_ON(x, p) do { iowrite8((ioread8((p))|(x)), (p)); } while (0) 478 #define WORD_REG_BITS_ON(x, p) do { iowrite16((ioread16((p))|(x)), (p)); } while (0) 479 #define DWORD_REG_BITS_ON(x, p) do { iowrite32((ioread32((p))|(x)), (p)); } while (0) 480 481 #define BYTE_REG_BITS_IS_ON(x, p) (ioread8((p)) & (x)) 482 #define WORD_REG_BITS_IS_ON(x, p) (ioread16((p)) & (x)) 483 #define DWORD_REG_BITS_IS_ON(x, p) (ioread32((p)) & (x)) 484 485 #define BYTE_REG_BITS_OFF(x, p) do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0) 486 #define WORD_REG_BITS_OFF(x, p) do { iowrite16(ioread16((p)) & (~(x)), (p)); } while (0) 487 #define DWORD_REG_BITS_OFF(x, p) do { iowrite32(ioread32((p)) & (~(x)), (p)); } while (0) 488 489 #define BYTE_REG_BITS_SET(x, m, p) do { iowrite8((ioread8((p)) & (~(m)))|(x), (p)); } while (0) 490 #define WORD_REG_BITS_SET(x, m, p) do { iowrite16((ioread16((p)) & (~(m)))|(x), (p)); } while (0) 491 #define DWORD_REG_BITS_SET(x, m, p) do { iowrite32((ioread32((p)) & (~(m)))|(x), (p)); } while (0) 492 493 494 static int mdio_read(struct net_device *dev, int phy_id, int location); 495 static void mdio_write(struct net_device *dev, int phy_id, int location, int value); 496 static int rhine_open(struct net_device *dev); 497 static void rhine_reset_task(struct work_struct *work); 498 static void rhine_slow_event_task(struct work_struct *work); 499 static void rhine_tx_timeout(struct net_device *dev); 500 static netdev_tx_t rhine_start_tx(struct sk_buff *skb, 501 struct net_device *dev); 502 static irqreturn_t rhine_interrupt(int irq, void *dev_instance); 503 static void rhine_tx(struct net_device *dev); 504 static int rhine_rx(struct net_device *dev, int limit); 505 static void rhine_set_rx_mode(struct net_device *dev); 506 static struct rtnl_link_stats64 *rhine_get_stats64(struct net_device *dev, 507 struct rtnl_link_stats64 *stats); 508 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 509 static const struct ethtool_ops netdev_ethtool_ops; 510 static int rhine_close(struct net_device *dev); 511 static int rhine_vlan_rx_add_vid(struct net_device *dev, 512 __be16 proto, u16 vid); 513 static int rhine_vlan_rx_kill_vid(struct net_device *dev, 514 __be16 proto, u16 vid); 515 static void rhine_restart_tx(struct net_device *dev); 516 517 static void rhine_wait_bit(struct rhine_private *rp, u8 reg, u8 mask, bool low) 518 { 519 void __iomem *ioaddr = rp->base; 520 int i; 521 522 for (i = 0; i < 1024; i++) { 523 bool has_mask_bits = !!(ioread8(ioaddr + reg) & mask); 524 525 if (low ^ has_mask_bits) 526 break; 527 udelay(10); 528 } 529 if (i > 64) { 530 netif_dbg(rp, hw, rp->dev, "%s bit wait (%02x/%02x) cycle " 531 "count: %04d\n", low ? "low" : "high", reg, mask, i); 532 } 533 } 534 535 static void rhine_wait_bit_high(struct rhine_private *rp, u8 reg, u8 mask) 536 { 537 rhine_wait_bit(rp, reg, mask, false); 538 } 539 540 static void rhine_wait_bit_low(struct rhine_private *rp, u8 reg, u8 mask) 541 { 542 rhine_wait_bit(rp, reg, mask, true); 543 } 544 545 static u32 rhine_get_events(struct rhine_private *rp) 546 { 547 void __iomem *ioaddr = rp->base; 548 u32 intr_status; 549 550 intr_status = ioread16(ioaddr + IntrStatus); 551 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */ 552 if (rp->quirks & rqStatusWBRace) 553 intr_status |= ioread8(ioaddr + IntrStatus2) << 16; 554 return intr_status; 555 } 556 557 static void rhine_ack_events(struct rhine_private *rp, u32 mask) 558 { 559 void __iomem *ioaddr = rp->base; 560 561 if (rp->quirks & rqStatusWBRace) 562 iowrite8(mask >> 16, ioaddr + IntrStatus2); 563 iowrite16(mask, ioaddr + IntrStatus); 564 mmiowb(); 565 } 566 567 /* 568 * Get power related registers into sane state. 569 * Notify user about past WOL event. 570 */ 571 static void rhine_power_init(struct net_device *dev) 572 { 573 struct rhine_private *rp = netdev_priv(dev); 574 void __iomem *ioaddr = rp->base; 575 u16 wolstat; 576 577 if (rp->quirks & rqWOL) { 578 /* Make sure chip is in power state D0 */ 579 iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW); 580 581 /* Disable "force PME-enable" */ 582 iowrite8(0x80, ioaddr + WOLcgClr); 583 584 /* Clear power-event config bits (WOL) */ 585 iowrite8(0xFF, ioaddr + WOLcrClr); 586 /* More recent cards can manage two additional patterns */ 587 if (rp->quirks & rq6patterns) 588 iowrite8(0x03, ioaddr + WOLcrClr1); 589 590 /* Save power-event status bits */ 591 wolstat = ioread8(ioaddr + PwrcsrSet); 592 if (rp->quirks & rq6patterns) 593 wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8; 594 595 /* Clear power-event status bits */ 596 iowrite8(0xFF, ioaddr + PwrcsrClr); 597 if (rp->quirks & rq6patterns) 598 iowrite8(0x03, ioaddr + PwrcsrClr1); 599 600 if (wolstat) { 601 char *reason; 602 switch (wolstat) { 603 case WOLmagic: 604 reason = "Magic packet"; 605 break; 606 case WOLlnkon: 607 reason = "Link went up"; 608 break; 609 case WOLlnkoff: 610 reason = "Link went down"; 611 break; 612 case WOLucast: 613 reason = "Unicast packet"; 614 break; 615 case WOLbmcast: 616 reason = "Multicast/broadcast packet"; 617 break; 618 default: 619 reason = "Unknown"; 620 } 621 netdev_info(dev, "Woke system up. Reason: %s\n", 622 reason); 623 } 624 } 625 } 626 627 static void rhine_chip_reset(struct net_device *dev) 628 { 629 struct rhine_private *rp = netdev_priv(dev); 630 void __iomem *ioaddr = rp->base; 631 u8 cmd1; 632 633 iowrite8(Cmd1Reset, ioaddr + ChipCmd1); 634 IOSYNC; 635 636 if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) { 637 netdev_info(dev, "Reset not complete yet. Trying harder.\n"); 638 639 /* Force reset */ 640 if (rp->quirks & rqForceReset) 641 iowrite8(0x40, ioaddr + MiscCmd); 642 643 /* Reset can take somewhat longer (rare) */ 644 rhine_wait_bit_low(rp, ChipCmd1, Cmd1Reset); 645 } 646 647 cmd1 = ioread8(ioaddr + ChipCmd1); 648 netif_info(rp, hw, dev, "Reset %s\n", (cmd1 & Cmd1Reset) ? 649 "failed" : "succeeded"); 650 } 651 652 #ifdef USE_MMIO 653 static void enable_mmio(long pioaddr, u32 quirks) 654 { 655 int n; 656 if (quirks & rqRhineI) { 657 /* More recent docs say that this bit is reserved ... */ 658 n = inb(pioaddr + ConfigA) | 0x20; 659 outb(n, pioaddr + ConfigA); 660 } else { 661 n = inb(pioaddr + ConfigD) | 0x80; 662 outb(n, pioaddr + ConfigD); 663 } 664 } 665 #endif 666 667 /* 668 * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM 669 * (plus 0x6C for Rhine-I/II) 670 */ 671 static void rhine_reload_eeprom(long pioaddr, struct net_device *dev) 672 { 673 struct rhine_private *rp = netdev_priv(dev); 674 void __iomem *ioaddr = rp->base; 675 int i; 676 677 outb(0x20, pioaddr + MACRegEEcsr); 678 for (i = 0; i < 1024; i++) { 679 if (!(inb(pioaddr + MACRegEEcsr) & 0x20)) 680 break; 681 } 682 if (i > 512) 683 pr_info("%4d cycles used @ %s:%d\n", i, __func__, __LINE__); 684 685 #ifdef USE_MMIO 686 /* 687 * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable 688 * MMIO. If reloading EEPROM was done first this could be avoided, but 689 * it is not known if that still works with the "win98-reboot" problem. 690 */ 691 enable_mmio(pioaddr, rp->quirks); 692 #endif 693 694 /* Turn off EEPROM-controlled wake-up (magic packet) */ 695 if (rp->quirks & rqWOL) 696 iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA); 697 698 } 699 700 #ifdef CONFIG_NET_POLL_CONTROLLER 701 static void rhine_poll(struct net_device *dev) 702 { 703 struct rhine_private *rp = netdev_priv(dev); 704 const int irq = rp->pdev->irq; 705 706 disable_irq(irq); 707 rhine_interrupt(irq, dev); 708 enable_irq(irq); 709 } 710 #endif 711 712 static void rhine_kick_tx_threshold(struct rhine_private *rp) 713 { 714 if (rp->tx_thresh < 0xe0) { 715 void __iomem *ioaddr = rp->base; 716 717 rp->tx_thresh += 0x20; 718 BYTE_REG_BITS_SET(rp->tx_thresh, 0x80, ioaddr + TxConfig); 719 } 720 } 721 722 static void rhine_tx_err(struct rhine_private *rp, u32 status) 723 { 724 struct net_device *dev = rp->dev; 725 726 if (status & IntrTxAborted) { 727 netif_info(rp, tx_err, dev, 728 "Abort %08x, frame dropped\n", status); 729 } 730 731 if (status & IntrTxUnderrun) { 732 rhine_kick_tx_threshold(rp); 733 netif_info(rp, tx_err ,dev, "Transmitter underrun, " 734 "Tx threshold now %02x\n", rp->tx_thresh); 735 } 736 737 if (status & IntrTxDescRace) 738 netif_info(rp, tx_err, dev, "Tx descriptor write-back race\n"); 739 740 if ((status & IntrTxError) && 741 (status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace)) == 0) { 742 rhine_kick_tx_threshold(rp); 743 netif_info(rp, tx_err, dev, "Unspecified error. " 744 "Tx threshold now %02x\n", rp->tx_thresh); 745 } 746 747 rhine_restart_tx(dev); 748 } 749 750 static void rhine_update_rx_crc_and_missed_errord(struct rhine_private *rp) 751 { 752 void __iomem *ioaddr = rp->base; 753 struct net_device_stats *stats = &rp->dev->stats; 754 755 stats->rx_crc_errors += ioread16(ioaddr + RxCRCErrs); 756 stats->rx_missed_errors += ioread16(ioaddr + RxMissed); 757 758 /* 759 * Clears the "tally counters" for CRC errors and missed frames(?). 760 * It has been reported that some chips need a write of 0 to clear 761 * these, for others the counters are set to 1 when written to and 762 * instead cleared when read. So we clear them both ways ... 763 */ 764 iowrite32(0, ioaddr + RxMissed); 765 ioread16(ioaddr + RxCRCErrs); 766 ioread16(ioaddr + RxMissed); 767 } 768 769 #define RHINE_EVENT_NAPI_RX (IntrRxDone | \ 770 IntrRxErr | \ 771 IntrRxEmpty | \ 772 IntrRxOverflow | \ 773 IntrRxDropped | \ 774 IntrRxNoBuf | \ 775 IntrRxWakeUp) 776 777 #define RHINE_EVENT_NAPI_TX_ERR (IntrTxError | \ 778 IntrTxAborted | \ 779 IntrTxUnderrun | \ 780 IntrTxDescRace) 781 #define RHINE_EVENT_NAPI_TX (IntrTxDone | RHINE_EVENT_NAPI_TX_ERR) 782 783 #define RHINE_EVENT_NAPI (RHINE_EVENT_NAPI_RX | \ 784 RHINE_EVENT_NAPI_TX | \ 785 IntrStatsMax) 786 #define RHINE_EVENT_SLOW (IntrPCIErr | IntrLinkChange) 787 #define RHINE_EVENT (RHINE_EVENT_NAPI | RHINE_EVENT_SLOW) 788 789 static int rhine_napipoll(struct napi_struct *napi, int budget) 790 { 791 struct rhine_private *rp = container_of(napi, struct rhine_private, napi); 792 struct net_device *dev = rp->dev; 793 void __iomem *ioaddr = rp->base; 794 u16 enable_mask = RHINE_EVENT & 0xffff; 795 int work_done = 0; 796 u32 status; 797 798 status = rhine_get_events(rp); 799 rhine_ack_events(rp, status & ~RHINE_EVENT_SLOW); 800 801 if (status & RHINE_EVENT_NAPI_RX) 802 work_done += rhine_rx(dev, budget); 803 804 if (status & RHINE_EVENT_NAPI_TX) { 805 if (status & RHINE_EVENT_NAPI_TX_ERR) { 806 /* Avoid scavenging before Tx engine turned off */ 807 rhine_wait_bit_low(rp, ChipCmd, CmdTxOn); 808 if (ioread8(ioaddr + ChipCmd) & CmdTxOn) 809 netif_warn(rp, tx_err, dev, "Tx still on\n"); 810 } 811 812 rhine_tx(dev); 813 814 if (status & RHINE_EVENT_NAPI_TX_ERR) 815 rhine_tx_err(rp, status); 816 } 817 818 if (status & IntrStatsMax) { 819 spin_lock(&rp->lock); 820 rhine_update_rx_crc_and_missed_errord(rp); 821 spin_unlock(&rp->lock); 822 } 823 824 if (status & RHINE_EVENT_SLOW) { 825 enable_mask &= ~RHINE_EVENT_SLOW; 826 schedule_work(&rp->slow_event_task); 827 } 828 829 if (work_done < budget) { 830 napi_complete(napi); 831 iowrite16(enable_mask, ioaddr + IntrEnable); 832 mmiowb(); 833 } 834 return work_done; 835 } 836 837 static void rhine_hw_init(struct net_device *dev, long pioaddr) 838 { 839 struct rhine_private *rp = netdev_priv(dev); 840 841 /* Reset the chip to erase previous misconfiguration. */ 842 rhine_chip_reset(dev); 843 844 /* Rhine-I needs extra time to recuperate before EEPROM reload */ 845 if (rp->quirks & rqRhineI) 846 msleep(5); 847 848 /* Reload EEPROM controlled bytes cleared by soft reset */ 849 rhine_reload_eeprom(pioaddr, dev); 850 } 851 852 static const struct net_device_ops rhine_netdev_ops = { 853 .ndo_open = rhine_open, 854 .ndo_stop = rhine_close, 855 .ndo_start_xmit = rhine_start_tx, 856 .ndo_get_stats64 = rhine_get_stats64, 857 .ndo_set_rx_mode = rhine_set_rx_mode, 858 .ndo_change_mtu = eth_change_mtu, 859 .ndo_validate_addr = eth_validate_addr, 860 .ndo_set_mac_address = eth_mac_addr, 861 .ndo_do_ioctl = netdev_ioctl, 862 .ndo_tx_timeout = rhine_tx_timeout, 863 .ndo_vlan_rx_add_vid = rhine_vlan_rx_add_vid, 864 .ndo_vlan_rx_kill_vid = rhine_vlan_rx_kill_vid, 865 #ifdef CONFIG_NET_POLL_CONTROLLER 866 .ndo_poll_controller = rhine_poll, 867 #endif 868 }; 869 870 static int rhine_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 871 { 872 struct net_device *dev; 873 struct rhine_private *rp; 874 int i, rc; 875 u32 quirks; 876 long pioaddr; 877 long memaddr; 878 void __iomem *ioaddr; 879 int io_size, phy_id; 880 const char *name; 881 #ifdef USE_MMIO 882 int bar = 1; 883 #else 884 int bar = 0; 885 #endif 886 887 /* when built into the kernel, we only print version if device is found */ 888 #ifndef MODULE 889 pr_info_once("%s\n", version); 890 #endif 891 892 io_size = 256; 893 phy_id = 0; 894 quirks = 0; 895 name = "Rhine"; 896 if (pdev->revision < VTunknown0) { 897 quirks = rqRhineI; 898 io_size = 128; 899 } 900 else if (pdev->revision >= VT6102) { 901 quirks = rqWOL | rqForceReset; 902 if (pdev->revision < VT6105) { 903 name = "Rhine II"; 904 quirks |= rqStatusWBRace; /* Rhine-II exclusive */ 905 } 906 else { 907 phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */ 908 if (pdev->revision >= VT6105_B0) 909 quirks |= rq6patterns; 910 if (pdev->revision < VT6105M) 911 name = "Rhine III"; 912 else 913 name = "Rhine III (Management Adapter)"; 914 } 915 } 916 917 rc = pci_enable_device(pdev); 918 if (rc) 919 goto err_out; 920 921 /* this should always be supported */ 922 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 923 if (rc) { 924 dev_err(&pdev->dev, 925 "32-bit PCI DMA addresses not supported by the card!?\n"); 926 goto err_out; 927 } 928 929 /* sanity check */ 930 if ((pci_resource_len(pdev, 0) < io_size) || 931 (pci_resource_len(pdev, 1) < io_size)) { 932 rc = -EIO; 933 dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n"); 934 goto err_out; 935 } 936 937 pioaddr = pci_resource_start(pdev, 0); 938 memaddr = pci_resource_start(pdev, 1); 939 940 pci_set_master(pdev); 941 942 dev = alloc_etherdev(sizeof(struct rhine_private)); 943 if (!dev) { 944 rc = -ENOMEM; 945 goto err_out; 946 } 947 SET_NETDEV_DEV(dev, &pdev->dev); 948 949 rp = netdev_priv(dev); 950 rp->dev = dev; 951 rp->quirks = quirks; 952 rp->pioaddr = pioaddr; 953 rp->pdev = pdev; 954 rp->msg_enable = netif_msg_init(debug, RHINE_MSG_DEFAULT); 955 956 rc = pci_request_regions(pdev, DRV_NAME); 957 if (rc) 958 goto err_out_free_netdev; 959 960 ioaddr = pci_iomap(pdev, bar, io_size); 961 if (!ioaddr) { 962 rc = -EIO; 963 dev_err(&pdev->dev, 964 "ioremap failed for device %s, region 0x%X @ 0x%lX\n", 965 pci_name(pdev), io_size, memaddr); 966 goto err_out_free_res; 967 } 968 969 #ifdef USE_MMIO 970 enable_mmio(pioaddr, quirks); 971 972 /* Check that selected MMIO registers match the PIO ones */ 973 i = 0; 974 while (mmio_verify_registers[i]) { 975 int reg = mmio_verify_registers[i++]; 976 unsigned char a = inb(pioaddr+reg); 977 unsigned char b = readb(ioaddr+reg); 978 if (a != b) { 979 rc = -EIO; 980 dev_err(&pdev->dev, 981 "MMIO do not match PIO [%02x] (%02x != %02x)\n", 982 reg, a, b); 983 goto err_out_unmap; 984 } 985 } 986 #endif /* USE_MMIO */ 987 988 rp->base = ioaddr; 989 990 u64_stats_init(&rp->tx_stats.syncp); 991 u64_stats_init(&rp->rx_stats.syncp); 992 993 /* Get chip registers into a sane state */ 994 rhine_power_init(dev); 995 rhine_hw_init(dev, pioaddr); 996 997 for (i = 0; i < 6; i++) 998 dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i); 999 1000 if (!is_valid_ether_addr(dev->dev_addr)) { 1001 /* Report it and use a random ethernet address instead */ 1002 netdev_err(dev, "Invalid MAC address: %pM\n", dev->dev_addr); 1003 eth_hw_addr_random(dev); 1004 netdev_info(dev, "Using random MAC address: %pM\n", 1005 dev->dev_addr); 1006 } 1007 1008 /* For Rhine-I/II, phy_id is loaded from EEPROM */ 1009 if (!phy_id) 1010 phy_id = ioread8(ioaddr + 0x6C); 1011 1012 spin_lock_init(&rp->lock); 1013 mutex_init(&rp->task_lock); 1014 INIT_WORK(&rp->reset_task, rhine_reset_task); 1015 INIT_WORK(&rp->slow_event_task, rhine_slow_event_task); 1016 1017 rp->mii_if.dev = dev; 1018 rp->mii_if.mdio_read = mdio_read; 1019 rp->mii_if.mdio_write = mdio_write; 1020 rp->mii_if.phy_id_mask = 0x1f; 1021 rp->mii_if.reg_num_mask = 0x1f; 1022 1023 /* The chip-specific entries in the device structure. */ 1024 dev->netdev_ops = &rhine_netdev_ops; 1025 dev->ethtool_ops = &netdev_ethtool_ops, 1026 dev->watchdog_timeo = TX_TIMEOUT; 1027 1028 netif_napi_add(dev, &rp->napi, rhine_napipoll, 64); 1029 1030 if (rp->quirks & rqRhineI) 1031 dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM; 1032 1033 if (pdev->revision >= VT6105M) 1034 dev->features |= NETIF_F_HW_VLAN_CTAG_TX | 1035 NETIF_F_HW_VLAN_CTAG_RX | 1036 NETIF_F_HW_VLAN_CTAG_FILTER; 1037 1038 /* dev->name not defined before register_netdev()! */ 1039 rc = register_netdev(dev); 1040 if (rc) 1041 goto err_out_unmap; 1042 1043 netdev_info(dev, "VIA %s at 0x%lx, %pM, IRQ %d\n", 1044 name, 1045 #ifdef USE_MMIO 1046 memaddr, 1047 #else 1048 (long)ioaddr, 1049 #endif 1050 dev->dev_addr, pdev->irq); 1051 1052 pci_set_drvdata(pdev, dev); 1053 1054 { 1055 u16 mii_cmd; 1056 int mii_status = mdio_read(dev, phy_id, 1); 1057 mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE; 1058 mdio_write(dev, phy_id, MII_BMCR, mii_cmd); 1059 if (mii_status != 0xffff && mii_status != 0x0000) { 1060 rp->mii_if.advertising = mdio_read(dev, phy_id, 4); 1061 netdev_info(dev, 1062 "MII PHY found at address %d, status 0x%04x advertising %04x Link %04x\n", 1063 phy_id, 1064 mii_status, rp->mii_if.advertising, 1065 mdio_read(dev, phy_id, 5)); 1066 1067 /* set IFF_RUNNING */ 1068 if (mii_status & BMSR_LSTATUS) 1069 netif_carrier_on(dev); 1070 else 1071 netif_carrier_off(dev); 1072 1073 } 1074 } 1075 rp->mii_if.phy_id = phy_id; 1076 if (avoid_D3) 1077 netif_info(rp, probe, dev, "No D3 power state at shutdown\n"); 1078 1079 return 0; 1080 1081 err_out_unmap: 1082 pci_iounmap(pdev, ioaddr); 1083 err_out_free_res: 1084 pci_release_regions(pdev); 1085 err_out_free_netdev: 1086 free_netdev(dev); 1087 err_out: 1088 return rc; 1089 } 1090 1091 static int alloc_ring(struct net_device* dev) 1092 { 1093 struct rhine_private *rp = netdev_priv(dev); 1094 void *ring; 1095 dma_addr_t ring_dma; 1096 1097 ring = pci_alloc_consistent(rp->pdev, 1098 RX_RING_SIZE * sizeof(struct rx_desc) + 1099 TX_RING_SIZE * sizeof(struct tx_desc), 1100 &ring_dma); 1101 if (!ring) { 1102 netdev_err(dev, "Could not allocate DMA memory\n"); 1103 return -ENOMEM; 1104 } 1105 if (rp->quirks & rqRhineI) { 1106 rp->tx_bufs = pci_alloc_consistent(rp->pdev, 1107 PKT_BUF_SZ * TX_RING_SIZE, 1108 &rp->tx_bufs_dma); 1109 if (rp->tx_bufs == NULL) { 1110 pci_free_consistent(rp->pdev, 1111 RX_RING_SIZE * sizeof(struct rx_desc) + 1112 TX_RING_SIZE * sizeof(struct tx_desc), 1113 ring, ring_dma); 1114 return -ENOMEM; 1115 } 1116 } 1117 1118 rp->rx_ring = ring; 1119 rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc); 1120 rp->rx_ring_dma = ring_dma; 1121 rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc); 1122 1123 return 0; 1124 } 1125 1126 static void free_ring(struct net_device* dev) 1127 { 1128 struct rhine_private *rp = netdev_priv(dev); 1129 1130 pci_free_consistent(rp->pdev, 1131 RX_RING_SIZE * sizeof(struct rx_desc) + 1132 TX_RING_SIZE * sizeof(struct tx_desc), 1133 rp->rx_ring, rp->rx_ring_dma); 1134 rp->tx_ring = NULL; 1135 1136 if (rp->tx_bufs) 1137 pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE, 1138 rp->tx_bufs, rp->tx_bufs_dma); 1139 1140 rp->tx_bufs = NULL; 1141 1142 } 1143 1144 static void alloc_rbufs(struct net_device *dev) 1145 { 1146 struct rhine_private *rp = netdev_priv(dev); 1147 dma_addr_t next; 1148 int i; 1149 1150 rp->dirty_rx = rp->cur_rx = 0; 1151 1152 rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32); 1153 rp->rx_head_desc = &rp->rx_ring[0]; 1154 next = rp->rx_ring_dma; 1155 1156 /* Init the ring entries */ 1157 for (i = 0; i < RX_RING_SIZE; i++) { 1158 rp->rx_ring[i].rx_status = 0; 1159 rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz); 1160 next += sizeof(struct rx_desc); 1161 rp->rx_ring[i].next_desc = cpu_to_le32(next); 1162 rp->rx_skbuff[i] = NULL; 1163 } 1164 /* Mark the last entry as wrapping the ring. */ 1165 rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma); 1166 1167 /* Fill in the Rx buffers. Handle allocation failure gracefully. */ 1168 for (i = 0; i < RX_RING_SIZE; i++) { 1169 struct sk_buff *skb = netdev_alloc_skb(dev, rp->rx_buf_sz); 1170 rp->rx_skbuff[i] = skb; 1171 if (skb == NULL) 1172 break; 1173 1174 rp->rx_skbuff_dma[i] = 1175 pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz, 1176 PCI_DMA_FROMDEVICE); 1177 if (dma_mapping_error(&rp->pdev->dev, rp->rx_skbuff_dma[i])) { 1178 rp->rx_skbuff_dma[i] = 0; 1179 dev_kfree_skb(skb); 1180 break; 1181 } 1182 rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]); 1183 rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn); 1184 } 1185 rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE); 1186 } 1187 1188 static void free_rbufs(struct net_device* dev) 1189 { 1190 struct rhine_private *rp = netdev_priv(dev); 1191 int i; 1192 1193 /* Free all the skbuffs in the Rx queue. */ 1194 for (i = 0; i < RX_RING_SIZE; i++) { 1195 rp->rx_ring[i].rx_status = 0; 1196 rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */ 1197 if (rp->rx_skbuff[i]) { 1198 pci_unmap_single(rp->pdev, 1199 rp->rx_skbuff_dma[i], 1200 rp->rx_buf_sz, PCI_DMA_FROMDEVICE); 1201 dev_kfree_skb(rp->rx_skbuff[i]); 1202 } 1203 rp->rx_skbuff[i] = NULL; 1204 } 1205 } 1206 1207 static void alloc_tbufs(struct net_device* dev) 1208 { 1209 struct rhine_private *rp = netdev_priv(dev); 1210 dma_addr_t next; 1211 int i; 1212 1213 rp->dirty_tx = rp->cur_tx = 0; 1214 next = rp->tx_ring_dma; 1215 for (i = 0; i < TX_RING_SIZE; i++) { 1216 rp->tx_skbuff[i] = NULL; 1217 rp->tx_ring[i].tx_status = 0; 1218 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC); 1219 next += sizeof(struct tx_desc); 1220 rp->tx_ring[i].next_desc = cpu_to_le32(next); 1221 if (rp->quirks & rqRhineI) 1222 rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ]; 1223 } 1224 rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma); 1225 1226 } 1227 1228 static void free_tbufs(struct net_device* dev) 1229 { 1230 struct rhine_private *rp = netdev_priv(dev); 1231 int i; 1232 1233 for (i = 0; i < TX_RING_SIZE; i++) { 1234 rp->tx_ring[i].tx_status = 0; 1235 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC); 1236 rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */ 1237 if (rp->tx_skbuff[i]) { 1238 if (rp->tx_skbuff_dma[i]) { 1239 pci_unmap_single(rp->pdev, 1240 rp->tx_skbuff_dma[i], 1241 rp->tx_skbuff[i]->len, 1242 PCI_DMA_TODEVICE); 1243 } 1244 dev_kfree_skb(rp->tx_skbuff[i]); 1245 } 1246 rp->tx_skbuff[i] = NULL; 1247 rp->tx_buf[i] = NULL; 1248 } 1249 } 1250 1251 static void rhine_check_media(struct net_device *dev, unsigned int init_media) 1252 { 1253 struct rhine_private *rp = netdev_priv(dev); 1254 void __iomem *ioaddr = rp->base; 1255 1256 mii_check_media(&rp->mii_if, netif_msg_link(rp), init_media); 1257 1258 if (rp->mii_if.full_duplex) 1259 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex, 1260 ioaddr + ChipCmd1); 1261 else 1262 iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex, 1263 ioaddr + ChipCmd1); 1264 1265 netif_info(rp, link, dev, "force_media %d, carrier %d\n", 1266 rp->mii_if.force_media, netif_carrier_ok(dev)); 1267 } 1268 1269 /* Called after status of force_media possibly changed */ 1270 static void rhine_set_carrier(struct mii_if_info *mii) 1271 { 1272 struct net_device *dev = mii->dev; 1273 struct rhine_private *rp = netdev_priv(dev); 1274 1275 if (mii->force_media) { 1276 /* autoneg is off: Link is always assumed to be up */ 1277 if (!netif_carrier_ok(dev)) 1278 netif_carrier_on(dev); 1279 } else /* Let MMI library update carrier status */ 1280 rhine_check_media(dev, 0); 1281 1282 netif_info(rp, link, dev, "force_media %d, carrier %d\n", 1283 mii->force_media, netif_carrier_ok(dev)); 1284 } 1285 1286 /** 1287 * rhine_set_cam - set CAM multicast filters 1288 * @ioaddr: register block of this Rhine 1289 * @idx: multicast CAM index [0..MCAM_SIZE-1] 1290 * @addr: multicast address (6 bytes) 1291 * 1292 * Load addresses into multicast filters. 1293 */ 1294 static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr) 1295 { 1296 int i; 1297 1298 iowrite8(CAMC_CAMEN, ioaddr + CamCon); 1299 wmb(); 1300 1301 /* Paranoid -- idx out of range should never happen */ 1302 idx &= (MCAM_SIZE - 1); 1303 1304 iowrite8((u8) idx, ioaddr + CamAddr); 1305 1306 for (i = 0; i < 6; i++, addr++) 1307 iowrite8(*addr, ioaddr + MulticastFilter0 + i); 1308 udelay(10); 1309 wmb(); 1310 1311 iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon); 1312 udelay(10); 1313 1314 iowrite8(0, ioaddr + CamCon); 1315 } 1316 1317 /** 1318 * rhine_set_vlan_cam - set CAM VLAN filters 1319 * @ioaddr: register block of this Rhine 1320 * @idx: VLAN CAM index [0..VCAM_SIZE-1] 1321 * @addr: VLAN ID (2 bytes) 1322 * 1323 * Load addresses into VLAN filters. 1324 */ 1325 static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr) 1326 { 1327 iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon); 1328 wmb(); 1329 1330 /* Paranoid -- idx out of range should never happen */ 1331 idx &= (VCAM_SIZE - 1); 1332 1333 iowrite8((u8) idx, ioaddr + CamAddr); 1334 1335 iowrite16(*((u16 *) addr), ioaddr + MulticastFilter0 + 6); 1336 udelay(10); 1337 wmb(); 1338 1339 iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon); 1340 udelay(10); 1341 1342 iowrite8(0, ioaddr + CamCon); 1343 } 1344 1345 /** 1346 * rhine_set_cam_mask - set multicast CAM mask 1347 * @ioaddr: register block of this Rhine 1348 * @mask: multicast CAM mask 1349 * 1350 * Mask sets multicast filters active/inactive. 1351 */ 1352 static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask) 1353 { 1354 iowrite8(CAMC_CAMEN, ioaddr + CamCon); 1355 wmb(); 1356 1357 /* write mask */ 1358 iowrite32(mask, ioaddr + CamMask); 1359 1360 /* disable CAMEN */ 1361 iowrite8(0, ioaddr + CamCon); 1362 } 1363 1364 /** 1365 * rhine_set_vlan_cam_mask - set VLAN CAM mask 1366 * @ioaddr: register block of this Rhine 1367 * @mask: VLAN CAM mask 1368 * 1369 * Mask sets VLAN filters active/inactive. 1370 */ 1371 static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask) 1372 { 1373 iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon); 1374 wmb(); 1375 1376 /* write mask */ 1377 iowrite32(mask, ioaddr + CamMask); 1378 1379 /* disable CAMEN */ 1380 iowrite8(0, ioaddr + CamCon); 1381 } 1382 1383 /** 1384 * rhine_init_cam_filter - initialize CAM filters 1385 * @dev: network device 1386 * 1387 * Initialize (disable) hardware VLAN and multicast support on this 1388 * Rhine. 1389 */ 1390 static void rhine_init_cam_filter(struct net_device *dev) 1391 { 1392 struct rhine_private *rp = netdev_priv(dev); 1393 void __iomem *ioaddr = rp->base; 1394 1395 /* Disable all CAMs */ 1396 rhine_set_vlan_cam_mask(ioaddr, 0); 1397 rhine_set_cam_mask(ioaddr, 0); 1398 1399 /* disable hardware VLAN support */ 1400 BYTE_REG_BITS_ON(TCR_PQEN, ioaddr + TxConfig); 1401 BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1); 1402 } 1403 1404 /** 1405 * rhine_update_vcam - update VLAN CAM filters 1406 * @rp: rhine_private data of this Rhine 1407 * 1408 * Update VLAN CAM filters to match configuration change. 1409 */ 1410 static void rhine_update_vcam(struct net_device *dev) 1411 { 1412 struct rhine_private *rp = netdev_priv(dev); 1413 void __iomem *ioaddr = rp->base; 1414 u16 vid; 1415 u32 vCAMmask = 0; /* 32 vCAMs (6105M and better) */ 1416 unsigned int i = 0; 1417 1418 for_each_set_bit(vid, rp->active_vlans, VLAN_N_VID) { 1419 rhine_set_vlan_cam(ioaddr, i, (u8 *)&vid); 1420 vCAMmask |= 1 << i; 1421 if (++i >= VCAM_SIZE) 1422 break; 1423 } 1424 rhine_set_vlan_cam_mask(ioaddr, vCAMmask); 1425 } 1426 1427 static int rhine_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) 1428 { 1429 struct rhine_private *rp = netdev_priv(dev); 1430 1431 spin_lock_bh(&rp->lock); 1432 set_bit(vid, rp->active_vlans); 1433 rhine_update_vcam(dev); 1434 spin_unlock_bh(&rp->lock); 1435 return 0; 1436 } 1437 1438 static int rhine_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) 1439 { 1440 struct rhine_private *rp = netdev_priv(dev); 1441 1442 spin_lock_bh(&rp->lock); 1443 clear_bit(vid, rp->active_vlans); 1444 rhine_update_vcam(dev); 1445 spin_unlock_bh(&rp->lock); 1446 return 0; 1447 } 1448 1449 static void init_registers(struct net_device *dev) 1450 { 1451 struct rhine_private *rp = netdev_priv(dev); 1452 void __iomem *ioaddr = rp->base; 1453 int i; 1454 1455 for (i = 0; i < 6; i++) 1456 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i); 1457 1458 /* Initialize other registers. */ 1459 iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */ 1460 /* Configure initial FIFO thresholds. */ 1461 iowrite8(0x20, ioaddr + TxConfig); 1462 rp->tx_thresh = 0x20; 1463 rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */ 1464 1465 iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr); 1466 iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr); 1467 1468 rhine_set_rx_mode(dev); 1469 1470 if (rp->pdev->revision >= VT6105M) 1471 rhine_init_cam_filter(dev); 1472 1473 napi_enable(&rp->napi); 1474 1475 iowrite16(RHINE_EVENT & 0xffff, ioaddr + IntrEnable); 1476 1477 iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8), 1478 ioaddr + ChipCmd); 1479 rhine_check_media(dev, 1); 1480 } 1481 1482 /* Enable MII link status auto-polling (required for IntrLinkChange) */ 1483 static void rhine_enable_linkmon(struct rhine_private *rp) 1484 { 1485 void __iomem *ioaddr = rp->base; 1486 1487 iowrite8(0, ioaddr + MIICmd); 1488 iowrite8(MII_BMSR, ioaddr + MIIRegAddr); 1489 iowrite8(0x80, ioaddr + MIICmd); 1490 1491 rhine_wait_bit_high(rp, MIIRegAddr, 0x20); 1492 1493 iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr); 1494 } 1495 1496 /* Disable MII link status auto-polling (required for MDIO access) */ 1497 static void rhine_disable_linkmon(struct rhine_private *rp) 1498 { 1499 void __iomem *ioaddr = rp->base; 1500 1501 iowrite8(0, ioaddr + MIICmd); 1502 1503 if (rp->quirks & rqRhineI) { 1504 iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR 1505 1506 /* Can be called from ISR. Evil. */ 1507 mdelay(1); 1508 1509 /* 0x80 must be set immediately before turning it off */ 1510 iowrite8(0x80, ioaddr + MIICmd); 1511 1512 rhine_wait_bit_high(rp, MIIRegAddr, 0x20); 1513 1514 /* Heh. Now clear 0x80 again. */ 1515 iowrite8(0, ioaddr + MIICmd); 1516 } 1517 else 1518 rhine_wait_bit_high(rp, MIIRegAddr, 0x80); 1519 } 1520 1521 /* Read and write over the MII Management Data I/O (MDIO) interface. */ 1522 1523 static int mdio_read(struct net_device *dev, int phy_id, int regnum) 1524 { 1525 struct rhine_private *rp = netdev_priv(dev); 1526 void __iomem *ioaddr = rp->base; 1527 int result; 1528 1529 rhine_disable_linkmon(rp); 1530 1531 /* rhine_disable_linkmon already cleared MIICmd */ 1532 iowrite8(phy_id, ioaddr + MIIPhyAddr); 1533 iowrite8(regnum, ioaddr + MIIRegAddr); 1534 iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */ 1535 rhine_wait_bit_low(rp, MIICmd, 0x40); 1536 result = ioread16(ioaddr + MIIData); 1537 1538 rhine_enable_linkmon(rp); 1539 return result; 1540 } 1541 1542 static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value) 1543 { 1544 struct rhine_private *rp = netdev_priv(dev); 1545 void __iomem *ioaddr = rp->base; 1546 1547 rhine_disable_linkmon(rp); 1548 1549 /* rhine_disable_linkmon already cleared MIICmd */ 1550 iowrite8(phy_id, ioaddr + MIIPhyAddr); 1551 iowrite8(regnum, ioaddr + MIIRegAddr); 1552 iowrite16(value, ioaddr + MIIData); 1553 iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */ 1554 rhine_wait_bit_low(rp, MIICmd, 0x20); 1555 1556 rhine_enable_linkmon(rp); 1557 } 1558 1559 static void rhine_task_disable(struct rhine_private *rp) 1560 { 1561 mutex_lock(&rp->task_lock); 1562 rp->task_enable = false; 1563 mutex_unlock(&rp->task_lock); 1564 1565 cancel_work_sync(&rp->slow_event_task); 1566 cancel_work_sync(&rp->reset_task); 1567 } 1568 1569 static void rhine_task_enable(struct rhine_private *rp) 1570 { 1571 mutex_lock(&rp->task_lock); 1572 rp->task_enable = true; 1573 mutex_unlock(&rp->task_lock); 1574 } 1575 1576 static int rhine_open(struct net_device *dev) 1577 { 1578 struct rhine_private *rp = netdev_priv(dev); 1579 void __iomem *ioaddr = rp->base; 1580 int rc; 1581 1582 rc = request_irq(rp->pdev->irq, rhine_interrupt, IRQF_SHARED, dev->name, 1583 dev); 1584 if (rc) 1585 return rc; 1586 1587 netif_dbg(rp, ifup, dev, "%s() irq %d\n", __func__, rp->pdev->irq); 1588 1589 rc = alloc_ring(dev); 1590 if (rc) { 1591 free_irq(rp->pdev->irq, dev); 1592 return rc; 1593 } 1594 alloc_rbufs(dev); 1595 alloc_tbufs(dev); 1596 rhine_chip_reset(dev); 1597 rhine_task_enable(rp); 1598 init_registers(dev); 1599 1600 netif_dbg(rp, ifup, dev, "%s() Done - status %04x MII status: %04x\n", 1601 __func__, ioread16(ioaddr + ChipCmd), 1602 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR)); 1603 1604 netif_start_queue(dev); 1605 1606 return 0; 1607 } 1608 1609 static void rhine_reset_task(struct work_struct *work) 1610 { 1611 struct rhine_private *rp = container_of(work, struct rhine_private, 1612 reset_task); 1613 struct net_device *dev = rp->dev; 1614 1615 mutex_lock(&rp->task_lock); 1616 1617 if (!rp->task_enable) 1618 goto out_unlock; 1619 1620 napi_disable(&rp->napi); 1621 spin_lock_bh(&rp->lock); 1622 1623 /* clear all descriptors */ 1624 free_tbufs(dev); 1625 free_rbufs(dev); 1626 alloc_tbufs(dev); 1627 alloc_rbufs(dev); 1628 1629 /* Reinitialize the hardware. */ 1630 rhine_chip_reset(dev); 1631 init_registers(dev); 1632 1633 spin_unlock_bh(&rp->lock); 1634 1635 dev->trans_start = jiffies; /* prevent tx timeout */ 1636 dev->stats.tx_errors++; 1637 netif_wake_queue(dev); 1638 1639 out_unlock: 1640 mutex_unlock(&rp->task_lock); 1641 } 1642 1643 static void rhine_tx_timeout(struct net_device *dev) 1644 { 1645 struct rhine_private *rp = netdev_priv(dev); 1646 void __iomem *ioaddr = rp->base; 1647 1648 netdev_warn(dev, "Transmit timed out, status %04x, PHY status %04x, resetting...\n", 1649 ioread16(ioaddr + IntrStatus), 1650 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR)); 1651 1652 schedule_work(&rp->reset_task); 1653 } 1654 1655 static netdev_tx_t rhine_start_tx(struct sk_buff *skb, 1656 struct net_device *dev) 1657 { 1658 struct rhine_private *rp = netdev_priv(dev); 1659 void __iomem *ioaddr = rp->base; 1660 unsigned entry; 1661 1662 /* Caution: the write order is important here, set the field 1663 with the "ownership" bits last. */ 1664 1665 /* Calculate the next Tx descriptor entry. */ 1666 entry = rp->cur_tx % TX_RING_SIZE; 1667 1668 if (skb_padto(skb, ETH_ZLEN)) 1669 return NETDEV_TX_OK; 1670 1671 rp->tx_skbuff[entry] = skb; 1672 1673 if ((rp->quirks & rqRhineI) && 1674 (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) { 1675 /* Must use alignment buffer. */ 1676 if (skb->len > PKT_BUF_SZ) { 1677 /* packet too long, drop it */ 1678 dev_kfree_skb(skb); 1679 rp->tx_skbuff[entry] = NULL; 1680 dev->stats.tx_dropped++; 1681 return NETDEV_TX_OK; 1682 } 1683 1684 /* Padding is not copied and so must be redone. */ 1685 skb_copy_and_csum_dev(skb, rp->tx_buf[entry]); 1686 if (skb->len < ETH_ZLEN) 1687 memset(rp->tx_buf[entry] + skb->len, 0, 1688 ETH_ZLEN - skb->len); 1689 rp->tx_skbuff_dma[entry] = 0; 1690 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma + 1691 (rp->tx_buf[entry] - 1692 rp->tx_bufs)); 1693 } else { 1694 rp->tx_skbuff_dma[entry] = 1695 pci_map_single(rp->pdev, skb->data, skb->len, 1696 PCI_DMA_TODEVICE); 1697 if (dma_mapping_error(&rp->pdev->dev, rp->tx_skbuff_dma[entry])) { 1698 dev_kfree_skb(skb); 1699 rp->tx_skbuff_dma[entry] = 0; 1700 dev->stats.tx_dropped++; 1701 return NETDEV_TX_OK; 1702 } 1703 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]); 1704 } 1705 1706 rp->tx_ring[entry].desc_length = 1707 cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN)); 1708 1709 if (unlikely(vlan_tx_tag_present(skb))) { 1710 u16 vid_pcp = vlan_tx_tag_get(skb); 1711 1712 /* drop CFI/DEI bit, register needs VID and PCP */ 1713 vid_pcp = (vid_pcp & VLAN_VID_MASK) | 1714 ((vid_pcp & VLAN_PRIO_MASK) >> 1); 1715 rp->tx_ring[entry].tx_status = cpu_to_le32((vid_pcp) << 16); 1716 /* request tagging */ 1717 rp->tx_ring[entry].desc_length |= cpu_to_le32(0x020000); 1718 } 1719 else 1720 rp->tx_ring[entry].tx_status = 0; 1721 1722 /* lock eth irq */ 1723 wmb(); 1724 rp->tx_ring[entry].tx_status |= cpu_to_le32(DescOwn); 1725 wmb(); 1726 1727 rp->cur_tx++; 1728 1729 /* Non-x86 Todo: explicitly flush cache lines here. */ 1730 1731 if (vlan_tx_tag_present(skb)) 1732 /* Tx queues are bits 7-0 (first Tx queue: bit 7) */ 1733 BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake); 1734 1735 /* Wake the potentially-idle transmit channel */ 1736 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand, 1737 ioaddr + ChipCmd1); 1738 IOSYNC; 1739 1740 if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN) 1741 netif_stop_queue(dev); 1742 1743 netif_dbg(rp, tx_queued, dev, "Transmit frame #%d queued in slot %d\n", 1744 rp->cur_tx - 1, entry); 1745 1746 return NETDEV_TX_OK; 1747 } 1748 1749 static void rhine_irq_disable(struct rhine_private *rp) 1750 { 1751 iowrite16(0x0000, rp->base + IntrEnable); 1752 mmiowb(); 1753 } 1754 1755 /* The interrupt handler does all of the Rx thread work and cleans up 1756 after the Tx thread. */ 1757 static irqreturn_t rhine_interrupt(int irq, void *dev_instance) 1758 { 1759 struct net_device *dev = dev_instance; 1760 struct rhine_private *rp = netdev_priv(dev); 1761 u32 status; 1762 int handled = 0; 1763 1764 status = rhine_get_events(rp); 1765 1766 netif_dbg(rp, intr, dev, "Interrupt, status %08x\n", status); 1767 1768 if (status & RHINE_EVENT) { 1769 handled = 1; 1770 1771 rhine_irq_disable(rp); 1772 napi_schedule(&rp->napi); 1773 } 1774 1775 if (status & ~(IntrLinkChange | IntrStatsMax | RHINE_EVENT_NAPI)) { 1776 netif_err(rp, intr, dev, "Something Wicked happened! %08x\n", 1777 status); 1778 } 1779 1780 return IRQ_RETVAL(handled); 1781 } 1782 1783 /* This routine is logically part of the interrupt handler, but isolated 1784 for clarity. */ 1785 static void rhine_tx(struct net_device *dev) 1786 { 1787 struct rhine_private *rp = netdev_priv(dev); 1788 int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE; 1789 1790 /* find and cleanup dirty tx descriptors */ 1791 while (rp->dirty_tx != rp->cur_tx) { 1792 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status); 1793 netif_dbg(rp, tx_done, dev, "Tx scavenge %d status %08x\n", 1794 entry, txstatus); 1795 if (txstatus & DescOwn) 1796 break; 1797 if (txstatus & 0x8000) { 1798 netif_dbg(rp, tx_done, dev, 1799 "Transmit error, Tx status %08x\n", txstatus); 1800 dev->stats.tx_errors++; 1801 if (txstatus & 0x0400) 1802 dev->stats.tx_carrier_errors++; 1803 if (txstatus & 0x0200) 1804 dev->stats.tx_window_errors++; 1805 if (txstatus & 0x0100) 1806 dev->stats.tx_aborted_errors++; 1807 if (txstatus & 0x0080) 1808 dev->stats.tx_heartbeat_errors++; 1809 if (((rp->quirks & rqRhineI) && txstatus & 0x0002) || 1810 (txstatus & 0x0800) || (txstatus & 0x1000)) { 1811 dev->stats.tx_fifo_errors++; 1812 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn); 1813 break; /* Keep the skb - we try again */ 1814 } 1815 /* Transmitter restarted in 'abnormal' handler. */ 1816 } else { 1817 if (rp->quirks & rqRhineI) 1818 dev->stats.collisions += (txstatus >> 3) & 0x0F; 1819 else 1820 dev->stats.collisions += txstatus & 0x0F; 1821 netif_dbg(rp, tx_done, dev, "collisions: %1.1x:%1.1x\n", 1822 (txstatus >> 3) & 0xF, txstatus & 0xF); 1823 1824 u64_stats_update_begin(&rp->tx_stats.syncp); 1825 rp->tx_stats.bytes += rp->tx_skbuff[entry]->len; 1826 rp->tx_stats.packets++; 1827 u64_stats_update_end(&rp->tx_stats.syncp); 1828 } 1829 /* Free the original skb. */ 1830 if (rp->tx_skbuff_dma[entry]) { 1831 pci_unmap_single(rp->pdev, 1832 rp->tx_skbuff_dma[entry], 1833 rp->tx_skbuff[entry]->len, 1834 PCI_DMA_TODEVICE); 1835 } 1836 dev_kfree_skb(rp->tx_skbuff[entry]); 1837 rp->tx_skbuff[entry] = NULL; 1838 entry = (++rp->dirty_tx) % TX_RING_SIZE; 1839 } 1840 if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4) 1841 netif_wake_queue(dev); 1842 } 1843 1844 /** 1845 * rhine_get_vlan_tci - extract TCI from Rx data buffer 1846 * @skb: pointer to sk_buff 1847 * @data_size: used data area of the buffer including CRC 1848 * 1849 * If hardware VLAN tag extraction is enabled and the chip indicates a 802.1Q 1850 * packet, the extracted 802.1Q header (2 bytes TPID + 2 bytes TCI) is 4-byte 1851 * aligned following the CRC. 1852 */ 1853 static inline u16 rhine_get_vlan_tci(struct sk_buff *skb, int data_size) 1854 { 1855 u8 *trailer = (u8 *)skb->data + ((data_size + 3) & ~3) + 2; 1856 return be16_to_cpup((__be16 *)trailer); 1857 } 1858 1859 /* Process up to limit frames from receive ring */ 1860 static int rhine_rx(struct net_device *dev, int limit) 1861 { 1862 struct rhine_private *rp = netdev_priv(dev); 1863 int count; 1864 int entry = rp->cur_rx % RX_RING_SIZE; 1865 1866 netif_dbg(rp, rx_status, dev, "%s(), entry %d status %08x\n", __func__, 1867 entry, le32_to_cpu(rp->rx_head_desc->rx_status)); 1868 1869 /* If EOP is set on the next entry, it's a new packet. Send it up. */ 1870 for (count = 0; count < limit; ++count) { 1871 struct rx_desc *desc = rp->rx_head_desc; 1872 u32 desc_status = le32_to_cpu(desc->rx_status); 1873 u32 desc_length = le32_to_cpu(desc->desc_length); 1874 int data_size = desc_status >> 16; 1875 1876 if (desc_status & DescOwn) 1877 break; 1878 1879 netif_dbg(rp, rx_status, dev, "%s() status %08x\n", __func__, 1880 desc_status); 1881 1882 if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) { 1883 if ((desc_status & RxWholePkt) != RxWholePkt) { 1884 netdev_warn(dev, 1885 "Oversized Ethernet frame spanned multiple buffers, " 1886 "entry %#x length %d status %08x!\n", 1887 entry, data_size, 1888 desc_status); 1889 netdev_warn(dev, 1890 "Oversized Ethernet frame %p vs %p\n", 1891 rp->rx_head_desc, 1892 &rp->rx_ring[entry]); 1893 dev->stats.rx_length_errors++; 1894 } else if (desc_status & RxErr) { 1895 /* There was a error. */ 1896 netif_dbg(rp, rx_err, dev, 1897 "%s() Rx error %08x\n", __func__, 1898 desc_status); 1899 dev->stats.rx_errors++; 1900 if (desc_status & 0x0030) 1901 dev->stats.rx_length_errors++; 1902 if (desc_status & 0x0048) 1903 dev->stats.rx_fifo_errors++; 1904 if (desc_status & 0x0004) 1905 dev->stats.rx_frame_errors++; 1906 if (desc_status & 0x0002) { 1907 /* this can also be updated outside the interrupt handler */ 1908 spin_lock(&rp->lock); 1909 dev->stats.rx_crc_errors++; 1910 spin_unlock(&rp->lock); 1911 } 1912 } 1913 } else { 1914 struct sk_buff *skb = NULL; 1915 /* Length should omit the CRC */ 1916 int pkt_len = data_size - 4; 1917 u16 vlan_tci = 0; 1918 1919 /* Check if the packet is long enough to accept without 1920 copying to a minimally-sized skbuff. */ 1921 if (pkt_len < rx_copybreak) 1922 skb = netdev_alloc_skb_ip_align(dev, pkt_len); 1923 if (skb) { 1924 pci_dma_sync_single_for_cpu(rp->pdev, 1925 rp->rx_skbuff_dma[entry], 1926 rp->rx_buf_sz, 1927 PCI_DMA_FROMDEVICE); 1928 1929 skb_copy_to_linear_data(skb, 1930 rp->rx_skbuff[entry]->data, 1931 pkt_len); 1932 skb_put(skb, pkt_len); 1933 pci_dma_sync_single_for_device(rp->pdev, 1934 rp->rx_skbuff_dma[entry], 1935 rp->rx_buf_sz, 1936 PCI_DMA_FROMDEVICE); 1937 } else { 1938 skb = rp->rx_skbuff[entry]; 1939 if (skb == NULL) { 1940 netdev_err(dev, "Inconsistent Rx descriptor chain\n"); 1941 break; 1942 } 1943 rp->rx_skbuff[entry] = NULL; 1944 skb_put(skb, pkt_len); 1945 pci_unmap_single(rp->pdev, 1946 rp->rx_skbuff_dma[entry], 1947 rp->rx_buf_sz, 1948 PCI_DMA_FROMDEVICE); 1949 } 1950 1951 if (unlikely(desc_length & DescTag)) 1952 vlan_tci = rhine_get_vlan_tci(skb, data_size); 1953 1954 skb->protocol = eth_type_trans(skb, dev); 1955 1956 if (unlikely(desc_length & DescTag)) 1957 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci); 1958 netif_receive_skb(skb); 1959 1960 u64_stats_update_begin(&rp->rx_stats.syncp); 1961 rp->rx_stats.bytes += pkt_len; 1962 rp->rx_stats.packets++; 1963 u64_stats_update_end(&rp->rx_stats.syncp); 1964 } 1965 entry = (++rp->cur_rx) % RX_RING_SIZE; 1966 rp->rx_head_desc = &rp->rx_ring[entry]; 1967 } 1968 1969 /* Refill the Rx ring buffers. */ 1970 for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) { 1971 struct sk_buff *skb; 1972 entry = rp->dirty_rx % RX_RING_SIZE; 1973 if (rp->rx_skbuff[entry] == NULL) { 1974 skb = netdev_alloc_skb(dev, rp->rx_buf_sz); 1975 rp->rx_skbuff[entry] = skb; 1976 if (skb == NULL) 1977 break; /* Better luck next round. */ 1978 rp->rx_skbuff_dma[entry] = 1979 pci_map_single(rp->pdev, skb->data, 1980 rp->rx_buf_sz, 1981 PCI_DMA_FROMDEVICE); 1982 if (dma_mapping_error(&rp->pdev->dev, rp->rx_skbuff_dma[entry])) { 1983 dev_kfree_skb(skb); 1984 rp->rx_skbuff_dma[entry] = 0; 1985 break; 1986 } 1987 rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]); 1988 } 1989 rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn); 1990 } 1991 1992 return count; 1993 } 1994 1995 static void rhine_restart_tx(struct net_device *dev) { 1996 struct rhine_private *rp = netdev_priv(dev); 1997 void __iomem *ioaddr = rp->base; 1998 int entry = rp->dirty_tx % TX_RING_SIZE; 1999 u32 intr_status; 2000 2001 /* 2002 * If new errors occurred, we need to sort them out before doing Tx. 2003 * In that case the ISR will be back here RSN anyway. 2004 */ 2005 intr_status = rhine_get_events(rp); 2006 2007 if ((intr_status & IntrTxErrSummary) == 0) { 2008 2009 /* We know better than the chip where it should continue. */ 2010 iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc), 2011 ioaddr + TxRingPtr); 2012 2013 iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn, 2014 ioaddr + ChipCmd); 2015 2016 if (rp->tx_ring[entry].desc_length & cpu_to_le32(0x020000)) 2017 /* Tx queues are bits 7-0 (first Tx queue: bit 7) */ 2018 BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake); 2019 2020 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand, 2021 ioaddr + ChipCmd1); 2022 IOSYNC; 2023 } 2024 else { 2025 /* This should never happen */ 2026 netif_warn(rp, tx_err, dev, "another error occurred %08x\n", 2027 intr_status); 2028 } 2029 2030 } 2031 2032 static void rhine_slow_event_task(struct work_struct *work) 2033 { 2034 struct rhine_private *rp = 2035 container_of(work, struct rhine_private, slow_event_task); 2036 struct net_device *dev = rp->dev; 2037 u32 intr_status; 2038 2039 mutex_lock(&rp->task_lock); 2040 2041 if (!rp->task_enable) 2042 goto out_unlock; 2043 2044 intr_status = rhine_get_events(rp); 2045 rhine_ack_events(rp, intr_status & RHINE_EVENT_SLOW); 2046 2047 if (intr_status & IntrLinkChange) 2048 rhine_check_media(dev, 0); 2049 2050 if (intr_status & IntrPCIErr) 2051 netif_warn(rp, hw, dev, "PCI error\n"); 2052 2053 iowrite16(RHINE_EVENT & 0xffff, rp->base + IntrEnable); 2054 2055 out_unlock: 2056 mutex_unlock(&rp->task_lock); 2057 } 2058 2059 static struct rtnl_link_stats64 * 2060 rhine_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 2061 { 2062 struct rhine_private *rp = netdev_priv(dev); 2063 unsigned int start; 2064 2065 spin_lock_bh(&rp->lock); 2066 rhine_update_rx_crc_and_missed_errord(rp); 2067 spin_unlock_bh(&rp->lock); 2068 2069 netdev_stats_to_stats64(stats, &dev->stats); 2070 2071 do { 2072 start = u64_stats_fetch_begin_bh(&rp->rx_stats.syncp); 2073 stats->rx_packets = rp->rx_stats.packets; 2074 stats->rx_bytes = rp->rx_stats.bytes; 2075 } while (u64_stats_fetch_retry_bh(&rp->rx_stats.syncp, start)); 2076 2077 do { 2078 start = u64_stats_fetch_begin_bh(&rp->tx_stats.syncp); 2079 stats->tx_packets = rp->tx_stats.packets; 2080 stats->tx_bytes = rp->tx_stats.bytes; 2081 } while (u64_stats_fetch_retry_bh(&rp->tx_stats.syncp, start)); 2082 2083 return stats; 2084 } 2085 2086 static void rhine_set_rx_mode(struct net_device *dev) 2087 { 2088 struct rhine_private *rp = netdev_priv(dev); 2089 void __iomem *ioaddr = rp->base; 2090 u32 mc_filter[2]; /* Multicast hash filter */ 2091 u8 rx_mode = 0x0C; /* Note: 0x02=accept runt, 0x01=accept errs */ 2092 struct netdev_hw_addr *ha; 2093 2094 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ 2095 rx_mode = 0x1C; 2096 iowrite32(0xffffffff, ioaddr + MulticastFilter0); 2097 iowrite32(0xffffffff, ioaddr + MulticastFilter1); 2098 } else if ((netdev_mc_count(dev) > multicast_filter_limit) || 2099 (dev->flags & IFF_ALLMULTI)) { 2100 /* Too many to match, or accept all multicasts. */ 2101 iowrite32(0xffffffff, ioaddr + MulticastFilter0); 2102 iowrite32(0xffffffff, ioaddr + MulticastFilter1); 2103 } else if (rp->pdev->revision >= VT6105M) { 2104 int i = 0; 2105 u32 mCAMmask = 0; /* 32 mCAMs (6105M and better) */ 2106 netdev_for_each_mc_addr(ha, dev) { 2107 if (i == MCAM_SIZE) 2108 break; 2109 rhine_set_cam(ioaddr, i, ha->addr); 2110 mCAMmask |= 1 << i; 2111 i++; 2112 } 2113 rhine_set_cam_mask(ioaddr, mCAMmask); 2114 } else { 2115 memset(mc_filter, 0, sizeof(mc_filter)); 2116 netdev_for_each_mc_addr(ha, dev) { 2117 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2118 2119 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2120 } 2121 iowrite32(mc_filter[0], ioaddr + MulticastFilter0); 2122 iowrite32(mc_filter[1], ioaddr + MulticastFilter1); 2123 } 2124 /* enable/disable VLAN receive filtering */ 2125 if (rp->pdev->revision >= VT6105M) { 2126 if (dev->flags & IFF_PROMISC) 2127 BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1); 2128 else 2129 BYTE_REG_BITS_ON(BCR1_VIDFR, ioaddr + PCIBusConfig1); 2130 } 2131 BYTE_REG_BITS_ON(rx_mode, ioaddr + RxConfig); 2132 } 2133 2134 static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 2135 { 2136 struct rhine_private *rp = netdev_priv(dev); 2137 2138 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 2139 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 2140 strlcpy(info->bus_info, pci_name(rp->pdev), sizeof(info->bus_info)); 2141 } 2142 2143 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2144 { 2145 struct rhine_private *rp = netdev_priv(dev); 2146 int rc; 2147 2148 mutex_lock(&rp->task_lock); 2149 rc = mii_ethtool_gset(&rp->mii_if, cmd); 2150 mutex_unlock(&rp->task_lock); 2151 2152 return rc; 2153 } 2154 2155 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2156 { 2157 struct rhine_private *rp = netdev_priv(dev); 2158 int rc; 2159 2160 mutex_lock(&rp->task_lock); 2161 rc = mii_ethtool_sset(&rp->mii_if, cmd); 2162 rhine_set_carrier(&rp->mii_if); 2163 mutex_unlock(&rp->task_lock); 2164 2165 return rc; 2166 } 2167 2168 static int netdev_nway_reset(struct net_device *dev) 2169 { 2170 struct rhine_private *rp = netdev_priv(dev); 2171 2172 return mii_nway_restart(&rp->mii_if); 2173 } 2174 2175 static u32 netdev_get_link(struct net_device *dev) 2176 { 2177 struct rhine_private *rp = netdev_priv(dev); 2178 2179 return mii_link_ok(&rp->mii_if); 2180 } 2181 2182 static u32 netdev_get_msglevel(struct net_device *dev) 2183 { 2184 struct rhine_private *rp = netdev_priv(dev); 2185 2186 return rp->msg_enable; 2187 } 2188 2189 static void netdev_set_msglevel(struct net_device *dev, u32 value) 2190 { 2191 struct rhine_private *rp = netdev_priv(dev); 2192 2193 rp->msg_enable = value; 2194 } 2195 2196 static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2197 { 2198 struct rhine_private *rp = netdev_priv(dev); 2199 2200 if (!(rp->quirks & rqWOL)) 2201 return; 2202 2203 spin_lock_irq(&rp->lock); 2204 wol->supported = WAKE_PHY | WAKE_MAGIC | 2205 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */ 2206 wol->wolopts = rp->wolopts; 2207 spin_unlock_irq(&rp->lock); 2208 } 2209 2210 static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2211 { 2212 struct rhine_private *rp = netdev_priv(dev); 2213 u32 support = WAKE_PHY | WAKE_MAGIC | 2214 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */ 2215 2216 if (!(rp->quirks & rqWOL)) 2217 return -EINVAL; 2218 2219 if (wol->wolopts & ~support) 2220 return -EINVAL; 2221 2222 spin_lock_irq(&rp->lock); 2223 rp->wolopts = wol->wolopts; 2224 spin_unlock_irq(&rp->lock); 2225 2226 return 0; 2227 } 2228 2229 static const struct ethtool_ops netdev_ethtool_ops = { 2230 .get_drvinfo = netdev_get_drvinfo, 2231 .get_settings = netdev_get_settings, 2232 .set_settings = netdev_set_settings, 2233 .nway_reset = netdev_nway_reset, 2234 .get_link = netdev_get_link, 2235 .get_msglevel = netdev_get_msglevel, 2236 .set_msglevel = netdev_set_msglevel, 2237 .get_wol = rhine_get_wol, 2238 .set_wol = rhine_set_wol, 2239 }; 2240 2241 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2242 { 2243 struct rhine_private *rp = netdev_priv(dev); 2244 int rc; 2245 2246 if (!netif_running(dev)) 2247 return -EINVAL; 2248 2249 mutex_lock(&rp->task_lock); 2250 rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL); 2251 rhine_set_carrier(&rp->mii_if); 2252 mutex_unlock(&rp->task_lock); 2253 2254 return rc; 2255 } 2256 2257 static int rhine_close(struct net_device *dev) 2258 { 2259 struct rhine_private *rp = netdev_priv(dev); 2260 void __iomem *ioaddr = rp->base; 2261 2262 rhine_task_disable(rp); 2263 napi_disable(&rp->napi); 2264 netif_stop_queue(dev); 2265 2266 netif_dbg(rp, ifdown, dev, "Shutting down ethercard, status was %04x\n", 2267 ioread16(ioaddr + ChipCmd)); 2268 2269 /* Switch to loopback mode to avoid hardware races. */ 2270 iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig); 2271 2272 rhine_irq_disable(rp); 2273 2274 /* Stop the chip's Tx and Rx processes. */ 2275 iowrite16(CmdStop, ioaddr + ChipCmd); 2276 2277 free_irq(rp->pdev->irq, dev); 2278 free_rbufs(dev); 2279 free_tbufs(dev); 2280 free_ring(dev); 2281 2282 return 0; 2283 } 2284 2285 2286 static void rhine_remove_one(struct pci_dev *pdev) 2287 { 2288 struct net_device *dev = pci_get_drvdata(pdev); 2289 struct rhine_private *rp = netdev_priv(dev); 2290 2291 unregister_netdev(dev); 2292 2293 pci_iounmap(pdev, rp->base); 2294 pci_release_regions(pdev); 2295 2296 free_netdev(dev); 2297 pci_disable_device(pdev); 2298 } 2299 2300 static void rhine_shutdown (struct pci_dev *pdev) 2301 { 2302 struct net_device *dev = pci_get_drvdata(pdev); 2303 struct rhine_private *rp = netdev_priv(dev); 2304 void __iomem *ioaddr = rp->base; 2305 2306 if (!(rp->quirks & rqWOL)) 2307 return; /* Nothing to do for non-WOL adapters */ 2308 2309 rhine_power_init(dev); 2310 2311 /* Make sure we use pattern 0, 1 and not 4, 5 */ 2312 if (rp->quirks & rq6patterns) 2313 iowrite8(0x04, ioaddr + WOLcgClr); 2314 2315 spin_lock(&rp->lock); 2316 2317 if (rp->wolopts & WAKE_MAGIC) { 2318 iowrite8(WOLmagic, ioaddr + WOLcrSet); 2319 /* 2320 * Turn EEPROM-controlled wake-up back on -- some hardware may 2321 * not cooperate otherwise. 2322 */ 2323 iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA); 2324 } 2325 2326 if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST)) 2327 iowrite8(WOLbmcast, ioaddr + WOLcgSet); 2328 2329 if (rp->wolopts & WAKE_PHY) 2330 iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet); 2331 2332 if (rp->wolopts & WAKE_UCAST) 2333 iowrite8(WOLucast, ioaddr + WOLcrSet); 2334 2335 if (rp->wolopts) { 2336 /* Enable legacy WOL (for old motherboards) */ 2337 iowrite8(0x01, ioaddr + PwcfgSet); 2338 iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW); 2339 } 2340 2341 spin_unlock(&rp->lock); 2342 2343 if (system_state == SYSTEM_POWER_OFF && !avoid_D3) { 2344 iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW); 2345 2346 pci_wake_from_d3(pdev, true); 2347 pci_set_power_state(pdev, PCI_D3hot); 2348 } 2349 } 2350 2351 #ifdef CONFIG_PM_SLEEP 2352 static int rhine_suspend(struct device *device) 2353 { 2354 struct pci_dev *pdev = to_pci_dev(device); 2355 struct net_device *dev = pci_get_drvdata(pdev); 2356 struct rhine_private *rp = netdev_priv(dev); 2357 2358 if (!netif_running(dev)) 2359 return 0; 2360 2361 rhine_task_disable(rp); 2362 rhine_irq_disable(rp); 2363 napi_disable(&rp->napi); 2364 2365 netif_device_detach(dev); 2366 2367 rhine_shutdown(pdev); 2368 2369 return 0; 2370 } 2371 2372 static int rhine_resume(struct device *device) 2373 { 2374 struct pci_dev *pdev = to_pci_dev(device); 2375 struct net_device *dev = pci_get_drvdata(pdev); 2376 struct rhine_private *rp = netdev_priv(dev); 2377 2378 if (!netif_running(dev)) 2379 return 0; 2380 2381 #ifdef USE_MMIO 2382 enable_mmio(rp->pioaddr, rp->quirks); 2383 #endif 2384 rhine_power_init(dev); 2385 free_tbufs(dev); 2386 free_rbufs(dev); 2387 alloc_tbufs(dev); 2388 alloc_rbufs(dev); 2389 rhine_task_enable(rp); 2390 spin_lock_bh(&rp->lock); 2391 init_registers(dev); 2392 spin_unlock_bh(&rp->lock); 2393 2394 netif_device_attach(dev); 2395 2396 return 0; 2397 } 2398 2399 static SIMPLE_DEV_PM_OPS(rhine_pm_ops, rhine_suspend, rhine_resume); 2400 #define RHINE_PM_OPS (&rhine_pm_ops) 2401 2402 #else 2403 2404 #define RHINE_PM_OPS NULL 2405 2406 #endif /* !CONFIG_PM_SLEEP */ 2407 2408 static struct pci_driver rhine_driver = { 2409 .name = DRV_NAME, 2410 .id_table = rhine_pci_tbl, 2411 .probe = rhine_init_one, 2412 .remove = rhine_remove_one, 2413 .shutdown = rhine_shutdown, 2414 .driver.pm = RHINE_PM_OPS, 2415 }; 2416 2417 static struct dmi_system_id rhine_dmi_table[] __initdata = { 2418 { 2419 .ident = "EPIA-M", 2420 .matches = { 2421 DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."), 2422 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"), 2423 }, 2424 }, 2425 { 2426 .ident = "KV7", 2427 .matches = { 2428 DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"), 2429 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"), 2430 }, 2431 }, 2432 { NULL } 2433 }; 2434 2435 static int __init rhine_init(void) 2436 { 2437 /* when a module, this is printed whether or not devices are found in probe */ 2438 #ifdef MODULE 2439 pr_info("%s\n", version); 2440 #endif 2441 if (dmi_check_system(rhine_dmi_table)) { 2442 /* these BIOSes fail at PXE boot if chip is in D3 */ 2443 avoid_D3 = true; 2444 pr_warn("Broken BIOS detected, avoid_D3 enabled\n"); 2445 } 2446 else if (avoid_D3) 2447 pr_info("avoid_D3 set\n"); 2448 2449 return pci_register_driver(&rhine_driver); 2450 } 2451 2452 2453 static void __exit rhine_cleanup(void) 2454 { 2455 pci_unregister_driver(&rhine_driver); 2456 } 2457 2458 2459 module_init(rhine_init); 2460 module_exit(rhine_cleanup); 2461