1 /* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
2 /*
3 	Written 1998-2001 by Donald Becker.
4 
5 	Current Maintainer: Roger Luethi <rl@hellgate.ch>
6 
7 	This software may be used and distributed according to the terms of
8 	the GNU General Public License (GPL), incorporated herein by reference.
9 	Drivers based on or derived from this code fall under the GPL and must
10 	retain the authorship, copyright and license notice.  This file is not
11 	a complete program and may only be used when the entire operating
12 	system is licensed under the GPL.
13 
14 	This driver is designed for the VIA VT86C100A Rhine-I.
15 	It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
16 	and management NIC 6105M).
17 
18 	The author may be reached as becker@scyld.com, or C/O
19 	Scyld Computing Corporation
20 	410 Severn Ave., Suite 210
21 	Annapolis MD 21403
22 
23 
24 	This driver contains some changes from the original Donald Becker
25 	version. He may or may not be interested in bug reports on this
26 	code. You can find his versions at:
27 	http://www.scyld.com/network/via-rhine.html
28 	[link no longer provides useful info -jgarzik]
29 
30 */
31 
32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33 
34 #define DRV_NAME	"via-rhine"
35 #define DRV_VERSION	"1.5.1"
36 #define DRV_RELDATE	"2010-10-09"
37 
38 #include <linux/types.h>
39 
40 /* A few user-configurable values.
41    These may be modified when a driver module is loaded. */
42 static int debug = 0;
43 #define RHINE_MSG_DEFAULT \
44         (0x0000)
45 
46 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
47    Setting to > 1518 effectively disables this feature. */
48 #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \
49 	defined(CONFIG_SPARC) || defined(__ia64__) ||		   \
50 	defined(__sh__) || defined(__mips__)
51 static int rx_copybreak = 1518;
52 #else
53 static int rx_copybreak;
54 #endif
55 
56 /* Work-around for broken BIOSes: they are unable to get the chip back out of
57    power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */
58 static bool avoid_D3;
59 
60 /*
61  * In case you are looking for 'options[]' or 'full_duplex[]', they
62  * are gone. Use ethtool(8) instead.
63  */
64 
65 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
66    The Rhine has a 64 element 8390-like hash table. */
67 static const int multicast_filter_limit = 32;
68 
69 
70 /* Operational parameters that are set at compile time. */
71 
72 /* Keep the ring sizes a power of two for compile efficiency.
73  * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
74  * Making the Tx ring too large decreases the effectiveness of channel
75  * bonding and packet priority.
76  * With BQL support, we can increase TX ring safely.
77  * There are no ill effects from too-large receive rings.
78  */
79 #define TX_RING_SIZE	64
80 #define TX_QUEUE_LEN	(TX_RING_SIZE - 6)	/* Limit ring entries actually used. */
81 #define RX_RING_SIZE	64
82 
83 /* Operational parameters that usually are not changed. */
84 
85 /* Time in jiffies before concluding the transmitter is hung. */
86 #define TX_TIMEOUT	(2*HZ)
87 
88 #define PKT_BUF_SZ	1536	/* Size of each temporary Rx buffer.*/
89 
90 #include <linux/module.h>
91 #include <linux/moduleparam.h>
92 #include <linux/kernel.h>
93 #include <linux/string.h>
94 #include <linux/timer.h>
95 #include <linux/errno.h>
96 #include <linux/ioport.h>
97 #include <linux/interrupt.h>
98 #include <linux/pci.h>
99 #include <linux/of_device.h>
100 #include <linux/of_irq.h>
101 #include <linux/platform_device.h>
102 #include <linux/dma-mapping.h>
103 #include <linux/netdevice.h>
104 #include <linux/etherdevice.h>
105 #include <linux/skbuff.h>
106 #include <linux/init.h>
107 #include <linux/delay.h>
108 #include <linux/mii.h>
109 #include <linux/ethtool.h>
110 #include <linux/crc32.h>
111 #include <linux/if_vlan.h>
112 #include <linux/bitops.h>
113 #include <linux/workqueue.h>
114 #include <asm/processor.h>	/* Processor type for cache alignment. */
115 #include <asm/io.h>
116 #include <asm/irq.h>
117 #include <asm/uaccess.h>
118 #include <linux/dmi.h>
119 
120 /* These identify the driver base version and may not be removed. */
121 static const char version[] =
122 	"v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker";
123 
124 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
125 MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
126 MODULE_LICENSE("GPL");
127 
128 module_param(debug, int, 0);
129 module_param(rx_copybreak, int, 0);
130 module_param(avoid_D3, bool, 0);
131 MODULE_PARM_DESC(debug, "VIA Rhine debug message flags");
132 MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
133 MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");
134 
135 #define MCAM_SIZE	32
136 #define VCAM_SIZE	32
137 
138 /*
139 		Theory of Operation
140 
141 I. Board Compatibility
142 
143 This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
144 controller.
145 
146 II. Board-specific settings
147 
148 Boards with this chip are functional only in a bus-master PCI slot.
149 
150 Many operational settings are loaded from the EEPROM to the Config word at
151 offset 0x78. For most of these settings, this driver assumes that they are
152 correct.
153 If this driver is compiled to use PCI memory space operations the EEPROM
154 must be configured to enable memory ops.
155 
156 III. Driver operation
157 
158 IIIa. Ring buffers
159 
160 This driver uses two statically allocated fixed-size descriptor lists
161 formed into rings by a branch from the final descriptor to the beginning of
162 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
163 
164 IIIb/c. Transmit/Receive Structure
165 
166 This driver attempts to use a zero-copy receive and transmit scheme.
167 
168 Alas, all data buffers are required to start on a 32 bit boundary, so
169 the driver must often copy transmit packets into bounce buffers.
170 
171 The driver allocates full frame size skbuffs for the Rx ring buffers at
172 open() time and passes the skb->data field to the chip as receive data
173 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
174 a fresh skbuff is allocated and the frame is copied to the new skbuff.
175 When the incoming frame is larger, the skbuff is passed directly up the
176 protocol stack. Buffers consumed this way are replaced by newly allocated
177 skbuffs in the last phase of rhine_rx().
178 
179 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
180 using a full-sized skbuff for small frames vs. the copying costs of larger
181 frames. New boards are typically used in generously configured machines
182 and the underfilled buffers have negligible impact compared to the benefit of
183 a single allocation size, so the default value of zero results in never
184 copying packets. When copying is done, the cost is usually mitigated by using
185 a combined copy/checksum routine. Copying also preloads the cache, which is
186 most useful with small frames.
187 
188 Since the VIA chips are only able to transfer data to buffers on 32 bit
189 boundaries, the IP header at offset 14 in an ethernet frame isn't
190 longword aligned for further processing. Copying these unaligned buffers
191 has the beneficial effect of 16-byte aligning the IP header.
192 
193 IIId. Synchronization
194 
195 The driver runs as two independent, single-threaded flows of control. One
196 is the send-packet routine, which enforces single-threaded use by the
197 netdev_priv(dev)->lock spinlock. The other thread is the interrupt handler,
198 which is single threaded by the hardware and interrupt handling software.
199 
200 The send packet thread has partial control over the Tx ring. It locks the
201 netdev_priv(dev)->lock whenever it's queuing a Tx packet. If the next slot in
202 the ring is not available it stops the transmit queue by
203 calling netif_stop_queue.
204 
205 The interrupt handler has exclusive control over the Rx ring and records stats
206 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
207 empty by incrementing the dirty_tx mark. If at least half of the entries in
208 the Rx ring are available the transmit queue is woken up if it was stopped.
209 
210 IV. Notes
211 
212 IVb. References
213 
214 Preliminary VT86C100A manual from http://www.via.com.tw/
215 http://www.scyld.com/expert/100mbps.html
216 http://www.scyld.com/expert/NWay.html
217 ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
218 ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
219 
220 
221 IVc. Errata
222 
223 The VT86C100A manual is not reliable information.
224 The 3043 chip does not handle unaligned transmit or receive buffers, resulting
225 in significant performance degradation for bounce buffer copies on transmit
226 and unaligned IP headers on receive.
227 The chip does not pad to minimum transmit length.
228 
229 */
230 
231 
232 /* This table drives the PCI probe routines. It's mostly boilerplate in all
233    of the drivers, and will likely be provided by some future kernel.
234    Note the matching code -- the first table entry matchs all 56** cards but
235    second only the 1234 card.
236 */
237 
238 enum rhine_revs {
239 	VT86C100A	= 0x00,
240 	VTunknown0	= 0x20,
241 	VT6102		= 0x40,
242 	VT8231		= 0x50,	/* Integrated MAC */
243 	VT8233		= 0x60,	/* Integrated MAC */
244 	VT8235		= 0x74,	/* Integrated MAC */
245 	VT8237		= 0x78,	/* Integrated MAC */
246 	VTunknown1	= 0x7C,
247 	VT6105		= 0x80,
248 	VT6105_B0	= 0x83,
249 	VT6105L		= 0x8A,
250 	VT6107		= 0x8C,
251 	VTunknown2	= 0x8E,
252 	VT6105M		= 0x90,	/* Management adapter */
253 };
254 
255 enum rhine_quirks {
256 	rqWOL		= 0x0001,	/* Wake-On-LAN support */
257 	rqForceReset	= 0x0002,
258 	rq6patterns	= 0x0040,	/* 6 instead of 4 patterns for WOL */
259 	rqStatusWBRace	= 0x0080,	/* Tx Status Writeback Error possible */
260 	rqRhineI	= 0x0100,	/* See comment below */
261 	rqIntPHY	= 0x0200,	/* Integrated PHY */
262 	rqMgmt		= 0x0400,	/* Management adapter */
263 	rqNeedEnMMIO	= 0x0800,	/* Whether the core needs to be
264 					 * switched from PIO mode to MMIO
265 					 * (only applies to PCI)
266 					 */
267 };
268 /*
269  * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
270  * MMIO as well as for the collision counter and the Tx FIFO underflow
271  * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
272  */
273 
274 /* Beware of PCI posted writes */
275 #define IOSYNC	do { ioread8(ioaddr + StationAddr); } while (0)
276 
277 static const struct pci_device_id rhine_pci_tbl[] = {
278 	{ 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, },	/* VT86C100A */
279 	{ 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, },	/* VT6102 */
280 	{ 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, },	/* 6105{,L,LOM} */
281 	{ 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, },	/* VT6105M */
282 	{ }	/* terminate list */
283 };
284 MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
285 
286 /* OpenFirmware identifiers for platform-bus devices
287  * The .data field is currently only used to store quirks
288  */
289 static u32 vt8500_quirks = rqWOL | rqForceReset | rq6patterns;
290 static const struct of_device_id rhine_of_tbl[] = {
291 	{ .compatible = "via,vt8500-rhine", .data = &vt8500_quirks },
292 	{ }	/* terminate list */
293 };
294 MODULE_DEVICE_TABLE(of, rhine_of_tbl);
295 
296 /* Offsets to the device registers. */
297 enum register_offsets {
298 	StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
299 	ChipCmd1=0x09, TQWake=0x0A,
300 	IntrStatus=0x0C, IntrEnable=0x0E,
301 	MulticastFilter0=0x10, MulticastFilter1=0x14,
302 	RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
303 	MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E, PCIBusConfig1=0x6F,
304 	MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
305 	ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
306 	RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
307 	StickyHW=0x83, IntrStatus2=0x84,
308 	CamMask=0x88, CamCon=0x92, CamAddr=0x93,
309 	WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
310 	WOLcrClr1=0xA6, WOLcgClr=0xA7,
311 	PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
312 };
313 
314 /* Bits in ConfigD */
315 enum backoff_bits {
316 	BackOptional=0x01, BackModify=0x02,
317 	BackCaptureEffect=0x04, BackRandom=0x08
318 };
319 
320 /* Bits in the TxConfig (TCR) register */
321 enum tcr_bits {
322 	TCR_PQEN=0x01,
323 	TCR_LB0=0x02,		/* loopback[0] */
324 	TCR_LB1=0x04,		/* loopback[1] */
325 	TCR_OFSET=0x08,
326 	TCR_RTGOPT=0x10,
327 	TCR_RTFT0=0x20,
328 	TCR_RTFT1=0x40,
329 	TCR_RTSF=0x80,
330 };
331 
332 /* Bits in the CamCon (CAMC) register */
333 enum camcon_bits {
334 	CAMC_CAMEN=0x01,
335 	CAMC_VCAMSL=0x02,
336 	CAMC_CAMWR=0x04,
337 	CAMC_CAMRD=0x08,
338 };
339 
340 /* Bits in the PCIBusConfig1 (BCR1) register */
341 enum bcr1_bits {
342 	BCR1_POT0=0x01,
343 	BCR1_POT1=0x02,
344 	BCR1_POT2=0x04,
345 	BCR1_CTFT0=0x08,
346 	BCR1_CTFT1=0x10,
347 	BCR1_CTSF=0x20,
348 	BCR1_TXQNOBK=0x40,	/* for VT6105 */
349 	BCR1_VIDFR=0x80,	/* for VT6105 */
350 	BCR1_MED0=0x40,		/* for VT6102 */
351 	BCR1_MED1=0x80,		/* for VT6102 */
352 };
353 
354 /* Registers we check that mmio and reg are the same. */
355 static const int mmio_verify_registers[] = {
356 	RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
357 	0
358 };
359 
360 /* Bits in the interrupt status/mask registers. */
361 enum intr_status_bits {
362 	IntrRxDone	= 0x0001,
363 	IntrTxDone	= 0x0002,
364 	IntrRxErr	= 0x0004,
365 	IntrTxError	= 0x0008,
366 	IntrRxEmpty	= 0x0020,
367 	IntrPCIErr	= 0x0040,
368 	IntrStatsMax	= 0x0080,
369 	IntrRxEarly	= 0x0100,
370 	IntrTxUnderrun	= 0x0210,
371 	IntrRxOverflow	= 0x0400,
372 	IntrRxDropped	= 0x0800,
373 	IntrRxNoBuf	= 0x1000,
374 	IntrTxAborted	= 0x2000,
375 	IntrLinkChange	= 0x4000,
376 	IntrRxWakeUp	= 0x8000,
377 	IntrTxDescRace		= 0x080000,	/* mapped from IntrStatus2 */
378 	IntrNormalSummary	= IntrRxDone | IntrTxDone,
379 	IntrTxErrSummary	= IntrTxDescRace | IntrTxAborted | IntrTxError |
380 				  IntrTxUnderrun,
381 };
382 
383 /* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
384 enum wol_bits {
385 	WOLucast	= 0x10,
386 	WOLmagic	= 0x20,
387 	WOLbmcast	= 0x30,
388 	WOLlnkon	= 0x40,
389 	WOLlnkoff	= 0x80,
390 };
391 
392 /* The Rx and Tx buffer descriptors. */
393 struct rx_desc {
394 	__le32 rx_status;
395 	__le32 desc_length; /* Chain flag, Buffer/frame length */
396 	__le32 addr;
397 	__le32 next_desc;
398 };
399 struct tx_desc {
400 	__le32 tx_status;
401 	__le32 desc_length; /* Chain flag, Tx Config, Frame length */
402 	__le32 addr;
403 	__le32 next_desc;
404 };
405 
406 /* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
407 #define TXDESC		0x00e08000
408 
409 enum rx_status_bits {
410 	RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
411 };
412 
413 /* Bits in *_desc.*_status */
414 enum desc_status_bits {
415 	DescOwn=0x80000000
416 };
417 
418 /* Bits in *_desc.*_length */
419 enum desc_length_bits {
420 	DescTag=0x00010000
421 };
422 
423 /* Bits in ChipCmd. */
424 enum chip_cmd_bits {
425 	CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
426 	CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
427 	Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
428 	Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
429 };
430 
431 struct rhine_stats {
432 	u64		packets;
433 	u64		bytes;
434 	struct u64_stats_sync syncp;
435 };
436 
437 struct rhine_private {
438 	/* Bit mask for configured VLAN ids */
439 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
440 
441 	/* Descriptor rings */
442 	struct rx_desc *rx_ring;
443 	struct tx_desc *tx_ring;
444 	dma_addr_t rx_ring_dma;
445 	dma_addr_t tx_ring_dma;
446 
447 	/* The addresses of receive-in-place skbuffs. */
448 	struct sk_buff *rx_skbuff[RX_RING_SIZE];
449 	dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
450 
451 	/* The saved address of a sent-in-place packet/buffer, for later free(). */
452 	struct sk_buff *tx_skbuff[TX_RING_SIZE];
453 	dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
454 
455 	/* Tx bounce buffers (Rhine-I only) */
456 	unsigned char *tx_buf[TX_RING_SIZE];
457 	unsigned char *tx_bufs;
458 	dma_addr_t tx_bufs_dma;
459 
460 	int irq;
461 	long pioaddr;
462 	struct net_device *dev;
463 	struct napi_struct napi;
464 	spinlock_t lock;
465 	struct mutex task_lock;
466 	bool task_enable;
467 	struct work_struct slow_event_task;
468 	struct work_struct reset_task;
469 
470 	u32 msg_enable;
471 
472 	/* Frequently used values: keep some adjacent for cache effect. */
473 	u32 quirks;
474 	unsigned int cur_rx;
475 	unsigned int cur_tx, dirty_tx;
476 	unsigned int rx_buf_sz;		/* Based on MTU+slack. */
477 	struct rhine_stats rx_stats;
478 	struct rhine_stats tx_stats;
479 	u8 wolopts;
480 
481 	u8 tx_thresh, rx_thresh;
482 
483 	struct mii_if_info mii_if;
484 	void __iomem *base;
485 };
486 
487 #define BYTE_REG_BITS_ON(x, p)      do { iowrite8((ioread8((p))|(x)), (p)); } while (0)
488 #define WORD_REG_BITS_ON(x, p)      do { iowrite16((ioread16((p))|(x)), (p)); } while (0)
489 #define DWORD_REG_BITS_ON(x, p)     do { iowrite32((ioread32((p))|(x)), (p)); } while (0)
490 
491 #define BYTE_REG_BITS_IS_ON(x, p)   (ioread8((p)) & (x))
492 #define WORD_REG_BITS_IS_ON(x, p)   (ioread16((p)) & (x))
493 #define DWORD_REG_BITS_IS_ON(x, p)  (ioread32((p)) & (x))
494 
495 #define BYTE_REG_BITS_OFF(x, p)     do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0)
496 #define WORD_REG_BITS_OFF(x, p)     do { iowrite16(ioread16((p)) & (~(x)), (p)); } while (0)
497 #define DWORD_REG_BITS_OFF(x, p)    do { iowrite32(ioread32((p)) & (~(x)), (p)); } while (0)
498 
499 #define BYTE_REG_BITS_SET(x, m, p)   do { iowrite8((ioread8((p)) & (~(m)))|(x), (p)); } while (0)
500 #define WORD_REG_BITS_SET(x, m, p)   do { iowrite16((ioread16((p)) & (~(m)))|(x), (p)); } while (0)
501 #define DWORD_REG_BITS_SET(x, m, p)  do { iowrite32((ioread32((p)) & (~(m)))|(x), (p)); } while (0)
502 
503 
504 static int  mdio_read(struct net_device *dev, int phy_id, int location);
505 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
506 static int  rhine_open(struct net_device *dev);
507 static void rhine_reset_task(struct work_struct *work);
508 static void rhine_slow_event_task(struct work_struct *work);
509 static void rhine_tx_timeout(struct net_device *dev);
510 static netdev_tx_t rhine_start_tx(struct sk_buff *skb,
511 				  struct net_device *dev);
512 static irqreturn_t rhine_interrupt(int irq, void *dev_instance);
513 static void rhine_tx(struct net_device *dev);
514 static int rhine_rx(struct net_device *dev, int limit);
515 static void rhine_set_rx_mode(struct net_device *dev);
516 static struct rtnl_link_stats64 *rhine_get_stats64(struct net_device *dev,
517 	       struct rtnl_link_stats64 *stats);
518 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
519 static const struct ethtool_ops netdev_ethtool_ops;
520 static int  rhine_close(struct net_device *dev);
521 static int rhine_vlan_rx_add_vid(struct net_device *dev,
522 				 __be16 proto, u16 vid);
523 static int rhine_vlan_rx_kill_vid(struct net_device *dev,
524 				  __be16 proto, u16 vid);
525 static void rhine_restart_tx(struct net_device *dev);
526 
527 static void rhine_wait_bit(struct rhine_private *rp, u8 reg, u8 mask, bool low)
528 {
529 	void __iomem *ioaddr = rp->base;
530 	int i;
531 
532 	for (i = 0; i < 1024; i++) {
533 		bool has_mask_bits = !!(ioread8(ioaddr + reg) & mask);
534 
535 		if (low ^ has_mask_bits)
536 			break;
537 		udelay(10);
538 	}
539 	if (i > 64) {
540 		netif_dbg(rp, hw, rp->dev, "%s bit wait (%02x/%02x) cycle "
541 			  "count: %04d\n", low ? "low" : "high", reg, mask, i);
542 	}
543 }
544 
545 static void rhine_wait_bit_high(struct rhine_private *rp, u8 reg, u8 mask)
546 {
547 	rhine_wait_bit(rp, reg, mask, false);
548 }
549 
550 static void rhine_wait_bit_low(struct rhine_private *rp, u8 reg, u8 mask)
551 {
552 	rhine_wait_bit(rp, reg, mask, true);
553 }
554 
555 static u32 rhine_get_events(struct rhine_private *rp)
556 {
557 	void __iomem *ioaddr = rp->base;
558 	u32 intr_status;
559 
560 	intr_status = ioread16(ioaddr + IntrStatus);
561 	/* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
562 	if (rp->quirks & rqStatusWBRace)
563 		intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
564 	return intr_status;
565 }
566 
567 static void rhine_ack_events(struct rhine_private *rp, u32 mask)
568 {
569 	void __iomem *ioaddr = rp->base;
570 
571 	if (rp->quirks & rqStatusWBRace)
572 		iowrite8(mask >> 16, ioaddr + IntrStatus2);
573 	iowrite16(mask, ioaddr + IntrStatus);
574 	mmiowb();
575 }
576 
577 /*
578  * Get power related registers into sane state.
579  * Notify user about past WOL event.
580  */
581 static void rhine_power_init(struct net_device *dev)
582 {
583 	struct rhine_private *rp = netdev_priv(dev);
584 	void __iomem *ioaddr = rp->base;
585 	u16 wolstat;
586 
587 	if (rp->quirks & rqWOL) {
588 		/* Make sure chip is in power state D0 */
589 		iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
590 
591 		/* Disable "force PME-enable" */
592 		iowrite8(0x80, ioaddr + WOLcgClr);
593 
594 		/* Clear power-event config bits (WOL) */
595 		iowrite8(0xFF, ioaddr + WOLcrClr);
596 		/* More recent cards can manage two additional patterns */
597 		if (rp->quirks & rq6patterns)
598 			iowrite8(0x03, ioaddr + WOLcrClr1);
599 
600 		/* Save power-event status bits */
601 		wolstat = ioread8(ioaddr + PwrcsrSet);
602 		if (rp->quirks & rq6patterns)
603 			wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
604 
605 		/* Clear power-event status bits */
606 		iowrite8(0xFF, ioaddr + PwrcsrClr);
607 		if (rp->quirks & rq6patterns)
608 			iowrite8(0x03, ioaddr + PwrcsrClr1);
609 
610 		if (wolstat) {
611 			char *reason;
612 			switch (wolstat) {
613 			case WOLmagic:
614 				reason = "Magic packet";
615 				break;
616 			case WOLlnkon:
617 				reason = "Link went up";
618 				break;
619 			case WOLlnkoff:
620 				reason = "Link went down";
621 				break;
622 			case WOLucast:
623 				reason = "Unicast packet";
624 				break;
625 			case WOLbmcast:
626 				reason = "Multicast/broadcast packet";
627 				break;
628 			default:
629 				reason = "Unknown";
630 			}
631 			netdev_info(dev, "Woke system up. Reason: %s\n",
632 				    reason);
633 		}
634 	}
635 }
636 
637 static void rhine_chip_reset(struct net_device *dev)
638 {
639 	struct rhine_private *rp = netdev_priv(dev);
640 	void __iomem *ioaddr = rp->base;
641 	u8 cmd1;
642 
643 	iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
644 	IOSYNC;
645 
646 	if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
647 		netdev_info(dev, "Reset not complete yet. Trying harder.\n");
648 
649 		/* Force reset */
650 		if (rp->quirks & rqForceReset)
651 			iowrite8(0x40, ioaddr + MiscCmd);
652 
653 		/* Reset can take somewhat longer (rare) */
654 		rhine_wait_bit_low(rp, ChipCmd1, Cmd1Reset);
655 	}
656 
657 	cmd1 = ioread8(ioaddr + ChipCmd1);
658 	netif_info(rp, hw, dev, "Reset %s\n", (cmd1 & Cmd1Reset) ?
659 		   "failed" : "succeeded");
660 }
661 
662 static void enable_mmio(long pioaddr, u32 quirks)
663 {
664 	int n;
665 
666 	if (quirks & rqNeedEnMMIO) {
667 		if (quirks & rqRhineI) {
668 			/* More recent docs say that this bit is reserved */
669 			n = inb(pioaddr + ConfigA) | 0x20;
670 			outb(n, pioaddr + ConfigA);
671 		} else {
672 			n = inb(pioaddr + ConfigD) | 0x80;
673 			outb(n, pioaddr + ConfigD);
674 		}
675 	}
676 }
677 
678 static inline int verify_mmio(struct device *hwdev,
679 			      long pioaddr,
680 			      void __iomem *ioaddr,
681 			      u32 quirks)
682 {
683 	if (quirks & rqNeedEnMMIO) {
684 		int i = 0;
685 
686 		/* Check that selected MMIO registers match the PIO ones */
687 		while (mmio_verify_registers[i]) {
688 			int reg = mmio_verify_registers[i++];
689 			unsigned char a = inb(pioaddr+reg);
690 			unsigned char b = readb(ioaddr+reg);
691 
692 			if (a != b) {
693 				dev_err(hwdev,
694 					"MMIO do not match PIO [%02x] (%02x != %02x)\n",
695 					reg, a, b);
696 				return -EIO;
697 			}
698 		}
699 	}
700 	return 0;
701 }
702 
703 /*
704  * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
705  * (plus 0x6C for Rhine-I/II)
706  */
707 static void rhine_reload_eeprom(long pioaddr, struct net_device *dev)
708 {
709 	struct rhine_private *rp = netdev_priv(dev);
710 	void __iomem *ioaddr = rp->base;
711 	int i;
712 
713 	outb(0x20, pioaddr + MACRegEEcsr);
714 	for (i = 0; i < 1024; i++) {
715 		if (!(inb(pioaddr + MACRegEEcsr) & 0x20))
716 			break;
717 	}
718 	if (i > 512)
719 		pr_info("%4d cycles used @ %s:%d\n", i, __func__, __LINE__);
720 
721 	/*
722 	 * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
723 	 * MMIO. If reloading EEPROM was done first this could be avoided, but
724 	 * it is not known if that still works with the "win98-reboot" problem.
725 	 */
726 	enable_mmio(pioaddr, rp->quirks);
727 
728 	/* Turn off EEPROM-controlled wake-up (magic packet) */
729 	if (rp->quirks & rqWOL)
730 		iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
731 
732 }
733 
734 #ifdef CONFIG_NET_POLL_CONTROLLER
735 static void rhine_poll(struct net_device *dev)
736 {
737 	struct rhine_private *rp = netdev_priv(dev);
738 	const int irq = rp->irq;
739 
740 	disable_irq(irq);
741 	rhine_interrupt(irq, dev);
742 	enable_irq(irq);
743 }
744 #endif
745 
746 static void rhine_kick_tx_threshold(struct rhine_private *rp)
747 {
748 	if (rp->tx_thresh < 0xe0) {
749 		void __iomem *ioaddr = rp->base;
750 
751 		rp->tx_thresh += 0x20;
752 		BYTE_REG_BITS_SET(rp->tx_thresh, 0x80, ioaddr + TxConfig);
753 	}
754 }
755 
756 static void rhine_tx_err(struct rhine_private *rp, u32 status)
757 {
758 	struct net_device *dev = rp->dev;
759 
760 	if (status & IntrTxAborted) {
761 		netif_info(rp, tx_err, dev,
762 			   "Abort %08x, frame dropped\n", status);
763 	}
764 
765 	if (status & IntrTxUnderrun) {
766 		rhine_kick_tx_threshold(rp);
767 		netif_info(rp, tx_err ,dev, "Transmitter underrun, "
768 			   "Tx threshold now %02x\n", rp->tx_thresh);
769 	}
770 
771 	if (status & IntrTxDescRace)
772 		netif_info(rp, tx_err, dev, "Tx descriptor write-back race\n");
773 
774 	if ((status & IntrTxError) &&
775 	    (status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace)) == 0) {
776 		rhine_kick_tx_threshold(rp);
777 		netif_info(rp, tx_err, dev, "Unspecified error. "
778 			   "Tx threshold now %02x\n", rp->tx_thresh);
779 	}
780 
781 	rhine_restart_tx(dev);
782 }
783 
784 static void rhine_update_rx_crc_and_missed_errord(struct rhine_private *rp)
785 {
786 	void __iomem *ioaddr = rp->base;
787 	struct net_device_stats *stats = &rp->dev->stats;
788 
789 	stats->rx_crc_errors    += ioread16(ioaddr + RxCRCErrs);
790 	stats->rx_missed_errors += ioread16(ioaddr + RxMissed);
791 
792 	/*
793 	 * Clears the "tally counters" for CRC errors and missed frames(?).
794 	 * It has been reported that some chips need a write of 0 to clear
795 	 * these, for others the counters are set to 1 when written to and
796 	 * instead cleared when read. So we clear them both ways ...
797 	 */
798 	iowrite32(0, ioaddr + RxMissed);
799 	ioread16(ioaddr + RxCRCErrs);
800 	ioread16(ioaddr + RxMissed);
801 }
802 
803 #define RHINE_EVENT_NAPI_RX	(IntrRxDone | \
804 				 IntrRxErr | \
805 				 IntrRxEmpty | \
806 				 IntrRxOverflow	| \
807 				 IntrRxDropped | \
808 				 IntrRxNoBuf | \
809 				 IntrRxWakeUp)
810 
811 #define RHINE_EVENT_NAPI_TX_ERR	(IntrTxError | \
812 				 IntrTxAborted | \
813 				 IntrTxUnderrun | \
814 				 IntrTxDescRace)
815 #define RHINE_EVENT_NAPI_TX	(IntrTxDone | RHINE_EVENT_NAPI_TX_ERR)
816 
817 #define RHINE_EVENT_NAPI	(RHINE_EVENT_NAPI_RX | \
818 				 RHINE_EVENT_NAPI_TX | \
819 				 IntrStatsMax)
820 #define RHINE_EVENT_SLOW	(IntrPCIErr | IntrLinkChange)
821 #define RHINE_EVENT		(RHINE_EVENT_NAPI | RHINE_EVENT_SLOW)
822 
823 static int rhine_napipoll(struct napi_struct *napi, int budget)
824 {
825 	struct rhine_private *rp = container_of(napi, struct rhine_private, napi);
826 	struct net_device *dev = rp->dev;
827 	void __iomem *ioaddr = rp->base;
828 	u16 enable_mask = RHINE_EVENT & 0xffff;
829 	int work_done = 0;
830 	u32 status;
831 
832 	status = rhine_get_events(rp);
833 	rhine_ack_events(rp, status & ~RHINE_EVENT_SLOW);
834 
835 	if (status & RHINE_EVENT_NAPI_RX)
836 		work_done += rhine_rx(dev, budget);
837 
838 	if (status & RHINE_EVENT_NAPI_TX) {
839 		if (status & RHINE_EVENT_NAPI_TX_ERR) {
840 			/* Avoid scavenging before Tx engine turned off */
841 			rhine_wait_bit_low(rp, ChipCmd, CmdTxOn);
842 			if (ioread8(ioaddr + ChipCmd) & CmdTxOn)
843 				netif_warn(rp, tx_err, dev, "Tx still on\n");
844 		}
845 
846 		rhine_tx(dev);
847 
848 		if (status & RHINE_EVENT_NAPI_TX_ERR)
849 			rhine_tx_err(rp, status);
850 	}
851 
852 	if (status & IntrStatsMax) {
853 		spin_lock(&rp->lock);
854 		rhine_update_rx_crc_and_missed_errord(rp);
855 		spin_unlock(&rp->lock);
856 	}
857 
858 	if (status & RHINE_EVENT_SLOW) {
859 		enable_mask &= ~RHINE_EVENT_SLOW;
860 		schedule_work(&rp->slow_event_task);
861 	}
862 
863 	if (work_done < budget) {
864 		napi_complete(napi);
865 		iowrite16(enable_mask, ioaddr + IntrEnable);
866 		mmiowb();
867 	}
868 	return work_done;
869 }
870 
871 static void rhine_hw_init(struct net_device *dev, long pioaddr)
872 {
873 	struct rhine_private *rp = netdev_priv(dev);
874 
875 	/* Reset the chip to erase previous misconfiguration. */
876 	rhine_chip_reset(dev);
877 
878 	/* Rhine-I needs extra time to recuperate before EEPROM reload */
879 	if (rp->quirks & rqRhineI)
880 		msleep(5);
881 
882 	/* Reload EEPROM controlled bytes cleared by soft reset */
883 	if (dev_is_pci(dev->dev.parent))
884 		rhine_reload_eeprom(pioaddr, dev);
885 }
886 
887 static const struct net_device_ops rhine_netdev_ops = {
888 	.ndo_open		 = rhine_open,
889 	.ndo_stop		 = rhine_close,
890 	.ndo_start_xmit		 = rhine_start_tx,
891 	.ndo_get_stats64	 = rhine_get_stats64,
892 	.ndo_set_rx_mode	 = rhine_set_rx_mode,
893 	.ndo_change_mtu		 = eth_change_mtu,
894 	.ndo_validate_addr	 = eth_validate_addr,
895 	.ndo_set_mac_address 	 = eth_mac_addr,
896 	.ndo_do_ioctl		 = netdev_ioctl,
897 	.ndo_tx_timeout 	 = rhine_tx_timeout,
898 	.ndo_vlan_rx_add_vid	 = rhine_vlan_rx_add_vid,
899 	.ndo_vlan_rx_kill_vid	 = rhine_vlan_rx_kill_vid,
900 #ifdef CONFIG_NET_POLL_CONTROLLER
901 	.ndo_poll_controller	 = rhine_poll,
902 #endif
903 };
904 
905 static int rhine_init_one_common(struct device *hwdev, u32 quirks,
906 				 long pioaddr, void __iomem *ioaddr, int irq)
907 {
908 	struct net_device *dev;
909 	struct rhine_private *rp;
910 	int i, rc, phy_id;
911 	const char *name;
912 
913 	/* this should always be supported */
914 	rc = dma_set_mask(hwdev, DMA_BIT_MASK(32));
915 	if (rc) {
916 		dev_err(hwdev, "32-bit DMA addresses not supported by the card!?\n");
917 		goto err_out;
918 	}
919 
920 	dev = alloc_etherdev(sizeof(struct rhine_private));
921 	if (!dev) {
922 		rc = -ENOMEM;
923 		goto err_out;
924 	}
925 	SET_NETDEV_DEV(dev, hwdev);
926 
927 	rp = netdev_priv(dev);
928 	rp->dev = dev;
929 	rp->quirks = quirks;
930 	rp->pioaddr = pioaddr;
931 	rp->base = ioaddr;
932 	rp->irq = irq;
933 	rp->msg_enable = netif_msg_init(debug, RHINE_MSG_DEFAULT);
934 
935 	phy_id = rp->quirks & rqIntPHY ? 1 : 0;
936 
937 	u64_stats_init(&rp->tx_stats.syncp);
938 	u64_stats_init(&rp->rx_stats.syncp);
939 
940 	/* Get chip registers into a sane state */
941 	rhine_power_init(dev);
942 	rhine_hw_init(dev, pioaddr);
943 
944 	for (i = 0; i < 6; i++)
945 		dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
946 
947 	if (!is_valid_ether_addr(dev->dev_addr)) {
948 		/* Report it and use a random ethernet address instead */
949 		netdev_err(dev, "Invalid MAC address: %pM\n", dev->dev_addr);
950 		eth_hw_addr_random(dev);
951 		netdev_info(dev, "Using random MAC address: %pM\n",
952 			    dev->dev_addr);
953 	}
954 
955 	/* For Rhine-I/II, phy_id is loaded from EEPROM */
956 	if (!phy_id)
957 		phy_id = ioread8(ioaddr + 0x6C);
958 
959 	spin_lock_init(&rp->lock);
960 	mutex_init(&rp->task_lock);
961 	INIT_WORK(&rp->reset_task, rhine_reset_task);
962 	INIT_WORK(&rp->slow_event_task, rhine_slow_event_task);
963 
964 	rp->mii_if.dev = dev;
965 	rp->mii_if.mdio_read = mdio_read;
966 	rp->mii_if.mdio_write = mdio_write;
967 	rp->mii_if.phy_id_mask = 0x1f;
968 	rp->mii_if.reg_num_mask = 0x1f;
969 
970 	/* The chip-specific entries in the device structure. */
971 	dev->netdev_ops = &rhine_netdev_ops;
972 	dev->ethtool_ops = &netdev_ethtool_ops;
973 	dev->watchdog_timeo = TX_TIMEOUT;
974 
975 	netif_napi_add(dev, &rp->napi, rhine_napipoll, 64);
976 
977 	if (rp->quirks & rqRhineI)
978 		dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
979 
980 	if (rp->quirks & rqMgmt)
981 		dev->features |= NETIF_F_HW_VLAN_CTAG_TX |
982 				 NETIF_F_HW_VLAN_CTAG_RX |
983 				 NETIF_F_HW_VLAN_CTAG_FILTER;
984 
985 	/* dev->name not defined before register_netdev()! */
986 	rc = register_netdev(dev);
987 	if (rc)
988 		goto err_out_free_netdev;
989 
990 	if (rp->quirks & rqRhineI)
991 		name = "Rhine";
992 	else if (rp->quirks & rqStatusWBRace)
993 		name = "Rhine II";
994 	else if (rp->quirks & rqMgmt)
995 		name = "Rhine III (Management Adapter)";
996 	else
997 		name = "Rhine III";
998 
999 	netdev_info(dev, "VIA %s at 0x%lx, %pM, IRQ %d\n",
1000 		    name, (long)ioaddr, dev->dev_addr, rp->irq);
1001 
1002 	dev_set_drvdata(hwdev, dev);
1003 
1004 	{
1005 		u16 mii_cmd;
1006 		int mii_status = mdio_read(dev, phy_id, 1);
1007 		mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
1008 		mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
1009 		if (mii_status != 0xffff && mii_status != 0x0000) {
1010 			rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
1011 			netdev_info(dev,
1012 				    "MII PHY found at address %d, status 0x%04x advertising %04x Link %04x\n",
1013 				    phy_id,
1014 				    mii_status, rp->mii_if.advertising,
1015 				    mdio_read(dev, phy_id, 5));
1016 
1017 			/* set IFF_RUNNING */
1018 			if (mii_status & BMSR_LSTATUS)
1019 				netif_carrier_on(dev);
1020 			else
1021 				netif_carrier_off(dev);
1022 
1023 		}
1024 	}
1025 	rp->mii_if.phy_id = phy_id;
1026 	if (avoid_D3)
1027 		netif_info(rp, probe, dev, "No D3 power state at shutdown\n");
1028 
1029 	return 0;
1030 
1031 err_out_free_netdev:
1032 	free_netdev(dev);
1033 err_out:
1034 	return rc;
1035 }
1036 
1037 static int rhine_init_one_pci(struct pci_dev *pdev,
1038 			      const struct pci_device_id *ent)
1039 {
1040 	struct device *hwdev = &pdev->dev;
1041 	int rc;
1042 	long pioaddr, memaddr;
1043 	void __iomem *ioaddr;
1044 	int io_size = pdev->revision < VTunknown0 ? 128 : 256;
1045 
1046 /* This driver was written to use PCI memory space. Some early versions
1047  * of the Rhine may only work correctly with I/O space accesses.
1048  * TODO: determine for which revisions this is true and assign the flag
1049  *	 in code as opposed to this Kconfig option (???)
1050  */
1051 #ifdef CONFIG_VIA_RHINE_MMIO
1052 	u32 quirks = rqNeedEnMMIO;
1053 #else
1054 	u32 quirks = 0;
1055 #endif
1056 
1057 /* when built into the kernel, we only print version if device is found */
1058 #ifndef MODULE
1059 	pr_info_once("%s\n", version);
1060 #endif
1061 
1062 	rc = pci_enable_device(pdev);
1063 	if (rc)
1064 		goto err_out;
1065 
1066 	if (pdev->revision < VTunknown0) {
1067 		quirks |= rqRhineI;
1068 	} else if (pdev->revision >= VT6102) {
1069 		quirks |= rqWOL | rqForceReset;
1070 		if (pdev->revision < VT6105) {
1071 			quirks |= rqStatusWBRace;
1072 		} else {
1073 			quirks |= rqIntPHY;
1074 			if (pdev->revision >= VT6105_B0)
1075 				quirks |= rq6patterns;
1076 			if (pdev->revision >= VT6105M)
1077 				quirks |= rqMgmt;
1078 		}
1079 	}
1080 
1081 	/* sanity check */
1082 	if ((pci_resource_len(pdev, 0) < io_size) ||
1083 	    (pci_resource_len(pdev, 1) < io_size)) {
1084 		rc = -EIO;
1085 		dev_err(hwdev, "Insufficient PCI resources, aborting\n");
1086 		goto err_out_pci_disable;
1087 	}
1088 
1089 	pioaddr = pci_resource_start(pdev, 0);
1090 	memaddr = pci_resource_start(pdev, 1);
1091 
1092 	pci_set_master(pdev);
1093 
1094 	rc = pci_request_regions(pdev, DRV_NAME);
1095 	if (rc)
1096 		goto err_out_pci_disable;
1097 
1098 	ioaddr = pci_iomap(pdev, (quirks & rqNeedEnMMIO ? 1 : 0), io_size);
1099 	if (!ioaddr) {
1100 		rc = -EIO;
1101 		dev_err(hwdev,
1102 			"ioremap failed for device %s, region 0x%X @ 0x%lX\n",
1103 			dev_name(hwdev), io_size, memaddr);
1104 		goto err_out_free_res;
1105 	}
1106 
1107 	enable_mmio(pioaddr, quirks);
1108 
1109 	rc = verify_mmio(hwdev, pioaddr, ioaddr, quirks);
1110 	if (rc)
1111 		goto err_out_unmap;
1112 
1113 	rc = rhine_init_one_common(&pdev->dev, quirks,
1114 				   pioaddr, ioaddr, pdev->irq);
1115 	if (!rc)
1116 		return 0;
1117 
1118 err_out_unmap:
1119 	pci_iounmap(pdev, ioaddr);
1120 err_out_free_res:
1121 	pci_release_regions(pdev);
1122 err_out_pci_disable:
1123 	pci_disable_device(pdev);
1124 err_out:
1125 	return rc;
1126 }
1127 
1128 static int rhine_init_one_platform(struct platform_device *pdev)
1129 {
1130 	const struct of_device_id *match;
1131 	const u32 *quirks;
1132 	int irq;
1133 	struct resource *res;
1134 	void __iomem *ioaddr;
1135 
1136 	match = of_match_device(rhine_of_tbl, &pdev->dev);
1137 	if (!match)
1138 		return -EINVAL;
1139 
1140 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1141 	ioaddr = devm_ioremap_resource(&pdev->dev, res);
1142 	if (IS_ERR(ioaddr))
1143 		return PTR_ERR(ioaddr);
1144 
1145 	irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1146 	if (!irq)
1147 		return -EINVAL;
1148 
1149 	quirks = match->data;
1150 	if (!quirks)
1151 		return -EINVAL;
1152 
1153 	return rhine_init_one_common(&pdev->dev, *quirks,
1154 				     (long)ioaddr, ioaddr, irq);
1155 }
1156 
1157 static int alloc_ring(struct net_device* dev)
1158 {
1159 	struct rhine_private *rp = netdev_priv(dev);
1160 	struct device *hwdev = dev->dev.parent;
1161 	void *ring;
1162 	dma_addr_t ring_dma;
1163 
1164 	ring = dma_alloc_coherent(hwdev,
1165 				  RX_RING_SIZE * sizeof(struct rx_desc) +
1166 				  TX_RING_SIZE * sizeof(struct tx_desc),
1167 				  &ring_dma,
1168 				  GFP_ATOMIC);
1169 	if (!ring) {
1170 		netdev_err(dev, "Could not allocate DMA memory\n");
1171 		return -ENOMEM;
1172 	}
1173 	if (rp->quirks & rqRhineI) {
1174 		rp->tx_bufs = dma_alloc_coherent(hwdev,
1175 						 PKT_BUF_SZ * TX_RING_SIZE,
1176 						 &rp->tx_bufs_dma,
1177 						 GFP_ATOMIC);
1178 		if (rp->tx_bufs == NULL) {
1179 			dma_free_coherent(hwdev,
1180 					  RX_RING_SIZE * sizeof(struct rx_desc) +
1181 					  TX_RING_SIZE * sizeof(struct tx_desc),
1182 					  ring, ring_dma);
1183 			return -ENOMEM;
1184 		}
1185 	}
1186 
1187 	rp->rx_ring = ring;
1188 	rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
1189 	rp->rx_ring_dma = ring_dma;
1190 	rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
1191 
1192 	return 0;
1193 }
1194 
1195 static void free_ring(struct net_device* dev)
1196 {
1197 	struct rhine_private *rp = netdev_priv(dev);
1198 	struct device *hwdev = dev->dev.parent;
1199 
1200 	dma_free_coherent(hwdev,
1201 			  RX_RING_SIZE * sizeof(struct rx_desc) +
1202 			  TX_RING_SIZE * sizeof(struct tx_desc),
1203 			  rp->rx_ring, rp->rx_ring_dma);
1204 	rp->tx_ring = NULL;
1205 
1206 	if (rp->tx_bufs)
1207 		dma_free_coherent(hwdev, PKT_BUF_SZ * TX_RING_SIZE,
1208 				  rp->tx_bufs, rp->tx_bufs_dma);
1209 
1210 	rp->tx_bufs = NULL;
1211 
1212 }
1213 
1214 struct rhine_skb_dma {
1215 	struct sk_buff *skb;
1216 	dma_addr_t dma;
1217 };
1218 
1219 static inline int rhine_skb_dma_init(struct net_device *dev,
1220 				     struct rhine_skb_dma *sd)
1221 {
1222 	struct rhine_private *rp = netdev_priv(dev);
1223 	struct device *hwdev = dev->dev.parent;
1224 	const int size = rp->rx_buf_sz;
1225 
1226 	sd->skb = netdev_alloc_skb(dev, size);
1227 	if (!sd->skb)
1228 		return -ENOMEM;
1229 
1230 	sd->dma = dma_map_single(hwdev, sd->skb->data, size, DMA_FROM_DEVICE);
1231 	if (unlikely(dma_mapping_error(hwdev, sd->dma))) {
1232 		netif_err(rp, drv, dev, "Rx DMA mapping failure\n");
1233 		dev_kfree_skb_any(sd->skb);
1234 		return -EIO;
1235 	}
1236 
1237 	return 0;
1238 }
1239 
1240 static void rhine_reset_rbufs(struct rhine_private *rp)
1241 {
1242 	int i;
1243 
1244 	rp->cur_rx = 0;
1245 
1246 	for (i = 0; i < RX_RING_SIZE; i++)
1247 		rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
1248 }
1249 
1250 static inline void rhine_skb_dma_nic_store(struct rhine_private *rp,
1251 					   struct rhine_skb_dma *sd, int entry)
1252 {
1253 	rp->rx_skbuff_dma[entry] = sd->dma;
1254 	rp->rx_skbuff[entry] = sd->skb;
1255 
1256 	rp->rx_ring[entry].addr = cpu_to_le32(sd->dma);
1257 	dma_wmb();
1258 }
1259 
1260 static void free_rbufs(struct net_device* dev);
1261 
1262 static int alloc_rbufs(struct net_device *dev)
1263 {
1264 	struct rhine_private *rp = netdev_priv(dev);
1265 	dma_addr_t next;
1266 	int rc, i;
1267 
1268 	rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1269 	next = rp->rx_ring_dma;
1270 
1271 	/* Init the ring entries */
1272 	for (i = 0; i < RX_RING_SIZE; i++) {
1273 		rp->rx_ring[i].rx_status = 0;
1274 		rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
1275 		next += sizeof(struct rx_desc);
1276 		rp->rx_ring[i].next_desc = cpu_to_le32(next);
1277 		rp->rx_skbuff[i] = NULL;
1278 	}
1279 	/* Mark the last entry as wrapping the ring. */
1280 	rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
1281 
1282 	/* Fill in the Rx buffers.  Handle allocation failure gracefully. */
1283 	for (i = 0; i < RX_RING_SIZE; i++) {
1284 		struct rhine_skb_dma sd;
1285 
1286 		rc = rhine_skb_dma_init(dev, &sd);
1287 		if (rc < 0) {
1288 			free_rbufs(dev);
1289 			goto out;
1290 		}
1291 
1292 		rhine_skb_dma_nic_store(rp, &sd, i);
1293 	}
1294 
1295 	rhine_reset_rbufs(rp);
1296 out:
1297 	return rc;
1298 }
1299 
1300 static void free_rbufs(struct net_device* dev)
1301 {
1302 	struct rhine_private *rp = netdev_priv(dev);
1303 	struct device *hwdev = dev->dev.parent;
1304 	int i;
1305 
1306 	/* Free all the skbuffs in the Rx queue. */
1307 	for (i = 0; i < RX_RING_SIZE; i++) {
1308 		rp->rx_ring[i].rx_status = 0;
1309 		rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1310 		if (rp->rx_skbuff[i]) {
1311 			dma_unmap_single(hwdev,
1312 					 rp->rx_skbuff_dma[i],
1313 					 rp->rx_buf_sz, DMA_FROM_DEVICE);
1314 			dev_kfree_skb(rp->rx_skbuff[i]);
1315 		}
1316 		rp->rx_skbuff[i] = NULL;
1317 	}
1318 }
1319 
1320 static void alloc_tbufs(struct net_device* dev)
1321 {
1322 	struct rhine_private *rp = netdev_priv(dev);
1323 	dma_addr_t next;
1324 	int i;
1325 
1326 	rp->dirty_tx = rp->cur_tx = 0;
1327 	next = rp->tx_ring_dma;
1328 	for (i = 0; i < TX_RING_SIZE; i++) {
1329 		rp->tx_skbuff[i] = NULL;
1330 		rp->tx_ring[i].tx_status = 0;
1331 		rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
1332 		next += sizeof(struct tx_desc);
1333 		rp->tx_ring[i].next_desc = cpu_to_le32(next);
1334 		if (rp->quirks & rqRhineI)
1335 			rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
1336 	}
1337 	rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
1338 
1339 	netdev_reset_queue(dev);
1340 }
1341 
1342 static void free_tbufs(struct net_device* dev)
1343 {
1344 	struct rhine_private *rp = netdev_priv(dev);
1345 	struct device *hwdev = dev->dev.parent;
1346 	int i;
1347 
1348 	for (i = 0; i < TX_RING_SIZE; i++) {
1349 		rp->tx_ring[i].tx_status = 0;
1350 		rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
1351 		rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1352 		if (rp->tx_skbuff[i]) {
1353 			if (rp->tx_skbuff_dma[i]) {
1354 				dma_unmap_single(hwdev,
1355 						 rp->tx_skbuff_dma[i],
1356 						 rp->tx_skbuff[i]->len,
1357 						 DMA_TO_DEVICE);
1358 			}
1359 			dev_kfree_skb(rp->tx_skbuff[i]);
1360 		}
1361 		rp->tx_skbuff[i] = NULL;
1362 		rp->tx_buf[i] = NULL;
1363 	}
1364 }
1365 
1366 static void rhine_check_media(struct net_device *dev, unsigned int init_media)
1367 {
1368 	struct rhine_private *rp = netdev_priv(dev);
1369 	void __iomem *ioaddr = rp->base;
1370 
1371 	if (!rp->mii_if.force_media)
1372 		mii_check_media(&rp->mii_if, netif_msg_link(rp), init_media);
1373 
1374 	if (rp->mii_if.full_duplex)
1375 	    iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
1376 		   ioaddr + ChipCmd1);
1377 	else
1378 	    iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
1379 		   ioaddr + ChipCmd1);
1380 
1381 	netif_info(rp, link, dev, "force_media %d, carrier %d\n",
1382 		   rp->mii_if.force_media, netif_carrier_ok(dev));
1383 }
1384 
1385 /* Called after status of force_media possibly changed */
1386 static void rhine_set_carrier(struct mii_if_info *mii)
1387 {
1388 	struct net_device *dev = mii->dev;
1389 	struct rhine_private *rp = netdev_priv(dev);
1390 
1391 	if (mii->force_media) {
1392 		/* autoneg is off: Link is always assumed to be up */
1393 		if (!netif_carrier_ok(dev))
1394 			netif_carrier_on(dev);
1395 	}
1396 
1397 	rhine_check_media(dev, 0);
1398 
1399 	netif_info(rp, link, dev, "force_media %d, carrier %d\n",
1400 		   mii->force_media, netif_carrier_ok(dev));
1401 }
1402 
1403 /**
1404  * rhine_set_cam - set CAM multicast filters
1405  * @ioaddr: register block of this Rhine
1406  * @idx: multicast CAM index [0..MCAM_SIZE-1]
1407  * @addr: multicast address (6 bytes)
1408  *
1409  * Load addresses into multicast filters.
1410  */
1411 static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr)
1412 {
1413 	int i;
1414 
1415 	iowrite8(CAMC_CAMEN, ioaddr + CamCon);
1416 	wmb();
1417 
1418 	/* Paranoid -- idx out of range should never happen */
1419 	idx &= (MCAM_SIZE - 1);
1420 
1421 	iowrite8((u8) idx, ioaddr + CamAddr);
1422 
1423 	for (i = 0; i < 6; i++, addr++)
1424 		iowrite8(*addr, ioaddr + MulticastFilter0 + i);
1425 	udelay(10);
1426 	wmb();
1427 
1428 	iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
1429 	udelay(10);
1430 
1431 	iowrite8(0, ioaddr + CamCon);
1432 }
1433 
1434 /**
1435  * rhine_set_vlan_cam - set CAM VLAN filters
1436  * @ioaddr: register block of this Rhine
1437  * @idx: VLAN CAM index [0..VCAM_SIZE-1]
1438  * @addr: VLAN ID (2 bytes)
1439  *
1440  * Load addresses into VLAN filters.
1441  */
1442 static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr)
1443 {
1444 	iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
1445 	wmb();
1446 
1447 	/* Paranoid -- idx out of range should never happen */
1448 	idx &= (VCAM_SIZE - 1);
1449 
1450 	iowrite8((u8) idx, ioaddr + CamAddr);
1451 
1452 	iowrite16(*((u16 *) addr), ioaddr + MulticastFilter0 + 6);
1453 	udelay(10);
1454 	wmb();
1455 
1456 	iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
1457 	udelay(10);
1458 
1459 	iowrite8(0, ioaddr + CamCon);
1460 }
1461 
1462 /**
1463  * rhine_set_cam_mask - set multicast CAM mask
1464  * @ioaddr: register block of this Rhine
1465  * @mask: multicast CAM mask
1466  *
1467  * Mask sets multicast filters active/inactive.
1468  */
1469 static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask)
1470 {
1471 	iowrite8(CAMC_CAMEN, ioaddr + CamCon);
1472 	wmb();
1473 
1474 	/* write mask */
1475 	iowrite32(mask, ioaddr + CamMask);
1476 
1477 	/* disable CAMEN */
1478 	iowrite8(0, ioaddr + CamCon);
1479 }
1480 
1481 /**
1482  * rhine_set_vlan_cam_mask - set VLAN CAM mask
1483  * @ioaddr: register block of this Rhine
1484  * @mask: VLAN CAM mask
1485  *
1486  * Mask sets VLAN filters active/inactive.
1487  */
1488 static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask)
1489 {
1490 	iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
1491 	wmb();
1492 
1493 	/* write mask */
1494 	iowrite32(mask, ioaddr + CamMask);
1495 
1496 	/* disable CAMEN */
1497 	iowrite8(0, ioaddr + CamCon);
1498 }
1499 
1500 /**
1501  * rhine_init_cam_filter - initialize CAM filters
1502  * @dev: network device
1503  *
1504  * Initialize (disable) hardware VLAN and multicast support on this
1505  * Rhine.
1506  */
1507 static void rhine_init_cam_filter(struct net_device *dev)
1508 {
1509 	struct rhine_private *rp = netdev_priv(dev);
1510 	void __iomem *ioaddr = rp->base;
1511 
1512 	/* Disable all CAMs */
1513 	rhine_set_vlan_cam_mask(ioaddr, 0);
1514 	rhine_set_cam_mask(ioaddr, 0);
1515 
1516 	/* disable hardware VLAN support */
1517 	BYTE_REG_BITS_ON(TCR_PQEN, ioaddr + TxConfig);
1518 	BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
1519 }
1520 
1521 /**
1522  * rhine_update_vcam - update VLAN CAM filters
1523  * @rp: rhine_private data of this Rhine
1524  *
1525  * Update VLAN CAM filters to match configuration change.
1526  */
1527 static void rhine_update_vcam(struct net_device *dev)
1528 {
1529 	struct rhine_private *rp = netdev_priv(dev);
1530 	void __iomem *ioaddr = rp->base;
1531 	u16 vid;
1532 	u32 vCAMmask = 0;	/* 32 vCAMs (6105M and better) */
1533 	unsigned int i = 0;
1534 
1535 	for_each_set_bit(vid, rp->active_vlans, VLAN_N_VID) {
1536 		rhine_set_vlan_cam(ioaddr, i, (u8 *)&vid);
1537 		vCAMmask |= 1 << i;
1538 		if (++i >= VCAM_SIZE)
1539 			break;
1540 	}
1541 	rhine_set_vlan_cam_mask(ioaddr, vCAMmask);
1542 }
1543 
1544 static int rhine_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
1545 {
1546 	struct rhine_private *rp = netdev_priv(dev);
1547 
1548 	spin_lock_bh(&rp->lock);
1549 	set_bit(vid, rp->active_vlans);
1550 	rhine_update_vcam(dev);
1551 	spin_unlock_bh(&rp->lock);
1552 	return 0;
1553 }
1554 
1555 static int rhine_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
1556 {
1557 	struct rhine_private *rp = netdev_priv(dev);
1558 
1559 	spin_lock_bh(&rp->lock);
1560 	clear_bit(vid, rp->active_vlans);
1561 	rhine_update_vcam(dev);
1562 	spin_unlock_bh(&rp->lock);
1563 	return 0;
1564 }
1565 
1566 static void init_registers(struct net_device *dev)
1567 {
1568 	struct rhine_private *rp = netdev_priv(dev);
1569 	void __iomem *ioaddr = rp->base;
1570 	int i;
1571 
1572 	for (i = 0; i < 6; i++)
1573 		iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
1574 
1575 	/* Initialize other registers. */
1576 	iowrite16(0x0006, ioaddr + PCIBusConfig);	/* Tune configuration??? */
1577 	/* Configure initial FIFO thresholds. */
1578 	iowrite8(0x20, ioaddr + TxConfig);
1579 	rp->tx_thresh = 0x20;
1580 	rp->rx_thresh = 0x60;		/* Written in rhine_set_rx_mode(). */
1581 
1582 	iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
1583 	iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
1584 
1585 	rhine_set_rx_mode(dev);
1586 
1587 	if (rp->quirks & rqMgmt)
1588 		rhine_init_cam_filter(dev);
1589 
1590 	napi_enable(&rp->napi);
1591 
1592 	iowrite16(RHINE_EVENT & 0xffff, ioaddr + IntrEnable);
1593 
1594 	iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),
1595 	       ioaddr + ChipCmd);
1596 	rhine_check_media(dev, 1);
1597 }
1598 
1599 /* Enable MII link status auto-polling (required for IntrLinkChange) */
1600 static void rhine_enable_linkmon(struct rhine_private *rp)
1601 {
1602 	void __iomem *ioaddr = rp->base;
1603 
1604 	iowrite8(0, ioaddr + MIICmd);
1605 	iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
1606 	iowrite8(0x80, ioaddr + MIICmd);
1607 
1608 	rhine_wait_bit_high(rp, MIIRegAddr, 0x20);
1609 
1610 	iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
1611 }
1612 
1613 /* Disable MII link status auto-polling (required for MDIO access) */
1614 static void rhine_disable_linkmon(struct rhine_private *rp)
1615 {
1616 	void __iomem *ioaddr = rp->base;
1617 
1618 	iowrite8(0, ioaddr + MIICmd);
1619 
1620 	if (rp->quirks & rqRhineI) {
1621 		iowrite8(0x01, ioaddr + MIIRegAddr);	// MII_BMSR
1622 
1623 		/* Can be called from ISR. Evil. */
1624 		mdelay(1);
1625 
1626 		/* 0x80 must be set immediately before turning it off */
1627 		iowrite8(0x80, ioaddr + MIICmd);
1628 
1629 		rhine_wait_bit_high(rp, MIIRegAddr, 0x20);
1630 
1631 		/* Heh. Now clear 0x80 again. */
1632 		iowrite8(0, ioaddr + MIICmd);
1633 	}
1634 	else
1635 		rhine_wait_bit_high(rp, MIIRegAddr, 0x80);
1636 }
1637 
1638 /* Read and write over the MII Management Data I/O (MDIO) interface. */
1639 
1640 static int mdio_read(struct net_device *dev, int phy_id, int regnum)
1641 {
1642 	struct rhine_private *rp = netdev_priv(dev);
1643 	void __iomem *ioaddr = rp->base;
1644 	int result;
1645 
1646 	rhine_disable_linkmon(rp);
1647 
1648 	/* rhine_disable_linkmon already cleared MIICmd */
1649 	iowrite8(phy_id, ioaddr + MIIPhyAddr);
1650 	iowrite8(regnum, ioaddr + MIIRegAddr);
1651 	iowrite8(0x40, ioaddr + MIICmd);		/* Trigger read */
1652 	rhine_wait_bit_low(rp, MIICmd, 0x40);
1653 	result = ioread16(ioaddr + MIIData);
1654 
1655 	rhine_enable_linkmon(rp);
1656 	return result;
1657 }
1658 
1659 static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)
1660 {
1661 	struct rhine_private *rp = netdev_priv(dev);
1662 	void __iomem *ioaddr = rp->base;
1663 
1664 	rhine_disable_linkmon(rp);
1665 
1666 	/* rhine_disable_linkmon already cleared MIICmd */
1667 	iowrite8(phy_id, ioaddr + MIIPhyAddr);
1668 	iowrite8(regnum, ioaddr + MIIRegAddr);
1669 	iowrite16(value, ioaddr + MIIData);
1670 	iowrite8(0x20, ioaddr + MIICmd);		/* Trigger write */
1671 	rhine_wait_bit_low(rp, MIICmd, 0x20);
1672 
1673 	rhine_enable_linkmon(rp);
1674 }
1675 
1676 static void rhine_task_disable(struct rhine_private *rp)
1677 {
1678 	mutex_lock(&rp->task_lock);
1679 	rp->task_enable = false;
1680 	mutex_unlock(&rp->task_lock);
1681 
1682 	cancel_work_sync(&rp->slow_event_task);
1683 	cancel_work_sync(&rp->reset_task);
1684 }
1685 
1686 static void rhine_task_enable(struct rhine_private *rp)
1687 {
1688 	mutex_lock(&rp->task_lock);
1689 	rp->task_enable = true;
1690 	mutex_unlock(&rp->task_lock);
1691 }
1692 
1693 static int rhine_open(struct net_device *dev)
1694 {
1695 	struct rhine_private *rp = netdev_priv(dev);
1696 	void __iomem *ioaddr = rp->base;
1697 	int rc;
1698 
1699 	rc = request_irq(rp->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev);
1700 	if (rc)
1701 		goto out;
1702 
1703 	netif_dbg(rp, ifup, dev, "%s() irq %d\n", __func__, rp->irq);
1704 
1705 	rc = alloc_ring(dev);
1706 	if (rc < 0)
1707 		goto out_free_irq;
1708 
1709 	rc = alloc_rbufs(dev);
1710 	if (rc < 0)
1711 		goto out_free_ring;
1712 
1713 	alloc_tbufs(dev);
1714 	rhine_chip_reset(dev);
1715 	rhine_task_enable(rp);
1716 	init_registers(dev);
1717 
1718 	netif_dbg(rp, ifup, dev, "%s() Done - status %04x MII status: %04x\n",
1719 		  __func__, ioread16(ioaddr + ChipCmd),
1720 		  mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1721 
1722 	netif_start_queue(dev);
1723 
1724 out:
1725 	return rc;
1726 
1727 out_free_ring:
1728 	free_ring(dev);
1729 out_free_irq:
1730 	free_irq(rp->irq, dev);
1731 	goto out;
1732 }
1733 
1734 static void rhine_reset_task(struct work_struct *work)
1735 {
1736 	struct rhine_private *rp = container_of(work, struct rhine_private,
1737 						reset_task);
1738 	struct net_device *dev = rp->dev;
1739 
1740 	mutex_lock(&rp->task_lock);
1741 
1742 	if (!rp->task_enable)
1743 		goto out_unlock;
1744 
1745 	napi_disable(&rp->napi);
1746 	netif_tx_disable(dev);
1747 	spin_lock_bh(&rp->lock);
1748 
1749 	/* clear all descriptors */
1750 	free_tbufs(dev);
1751 	alloc_tbufs(dev);
1752 
1753 	rhine_reset_rbufs(rp);
1754 
1755 	/* Reinitialize the hardware. */
1756 	rhine_chip_reset(dev);
1757 	init_registers(dev);
1758 
1759 	spin_unlock_bh(&rp->lock);
1760 
1761 	netif_trans_update(dev); /* prevent tx timeout */
1762 	dev->stats.tx_errors++;
1763 	netif_wake_queue(dev);
1764 
1765 out_unlock:
1766 	mutex_unlock(&rp->task_lock);
1767 }
1768 
1769 static void rhine_tx_timeout(struct net_device *dev)
1770 {
1771 	struct rhine_private *rp = netdev_priv(dev);
1772 	void __iomem *ioaddr = rp->base;
1773 
1774 	netdev_warn(dev, "Transmit timed out, status %04x, PHY status %04x, resetting...\n",
1775 		    ioread16(ioaddr + IntrStatus),
1776 		    mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1777 
1778 	schedule_work(&rp->reset_task);
1779 }
1780 
1781 static inline bool rhine_tx_queue_full(struct rhine_private *rp)
1782 {
1783 	return (rp->cur_tx - rp->dirty_tx) >= TX_QUEUE_LEN;
1784 }
1785 
1786 static netdev_tx_t rhine_start_tx(struct sk_buff *skb,
1787 				  struct net_device *dev)
1788 {
1789 	struct rhine_private *rp = netdev_priv(dev);
1790 	struct device *hwdev = dev->dev.parent;
1791 	void __iomem *ioaddr = rp->base;
1792 	unsigned entry;
1793 
1794 	/* Caution: the write order is important here, set the field
1795 	   with the "ownership" bits last. */
1796 
1797 	/* Calculate the next Tx descriptor entry. */
1798 	entry = rp->cur_tx % TX_RING_SIZE;
1799 
1800 	if (skb_padto(skb, ETH_ZLEN))
1801 		return NETDEV_TX_OK;
1802 
1803 	rp->tx_skbuff[entry] = skb;
1804 
1805 	if ((rp->quirks & rqRhineI) &&
1806 	    (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) {
1807 		/* Must use alignment buffer. */
1808 		if (skb->len > PKT_BUF_SZ) {
1809 			/* packet too long, drop it */
1810 			dev_kfree_skb_any(skb);
1811 			rp->tx_skbuff[entry] = NULL;
1812 			dev->stats.tx_dropped++;
1813 			return NETDEV_TX_OK;
1814 		}
1815 
1816 		/* Padding is not copied and so must be redone. */
1817 		skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
1818 		if (skb->len < ETH_ZLEN)
1819 			memset(rp->tx_buf[entry] + skb->len, 0,
1820 			       ETH_ZLEN - skb->len);
1821 		rp->tx_skbuff_dma[entry] = 0;
1822 		rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
1823 						      (rp->tx_buf[entry] -
1824 						       rp->tx_bufs));
1825 	} else {
1826 		rp->tx_skbuff_dma[entry] =
1827 			dma_map_single(hwdev, skb->data, skb->len,
1828 				       DMA_TO_DEVICE);
1829 		if (dma_mapping_error(hwdev, rp->tx_skbuff_dma[entry])) {
1830 			dev_kfree_skb_any(skb);
1831 			rp->tx_skbuff_dma[entry] = 0;
1832 			dev->stats.tx_dropped++;
1833 			return NETDEV_TX_OK;
1834 		}
1835 		rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
1836 	}
1837 
1838 	rp->tx_ring[entry].desc_length =
1839 		cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1840 
1841 	if (unlikely(skb_vlan_tag_present(skb))) {
1842 		u16 vid_pcp = skb_vlan_tag_get(skb);
1843 
1844 		/* drop CFI/DEI bit, register needs VID and PCP */
1845 		vid_pcp = (vid_pcp & VLAN_VID_MASK) |
1846 			  ((vid_pcp & VLAN_PRIO_MASK) >> 1);
1847 		rp->tx_ring[entry].tx_status = cpu_to_le32((vid_pcp) << 16);
1848 		/* request tagging */
1849 		rp->tx_ring[entry].desc_length |= cpu_to_le32(0x020000);
1850 	}
1851 	else
1852 		rp->tx_ring[entry].tx_status = 0;
1853 
1854 	netdev_sent_queue(dev, skb->len);
1855 	/* lock eth irq */
1856 	dma_wmb();
1857 	rp->tx_ring[entry].tx_status |= cpu_to_le32(DescOwn);
1858 	wmb();
1859 
1860 	rp->cur_tx++;
1861 	/*
1862 	 * Nobody wants cur_tx write to rot for ages after the NIC will have
1863 	 * seen the transmit request, especially as the transmit completion
1864 	 * handler could miss it.
1865 	 */
1866 	smp_wmb();
1867 
1868 	/* Non-x86 Todo: explicitly flush cache lines here. */
1869 
1870 	if (skb_vlan_tag_present(skb))
1871 		/* Tx queues are bits 7-0 (first Tx queue: bit 7) */
1872 		BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
1873 
1874 	/* Wake the potentially-idle transmit channel */
1875 	iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1876 	       ioaddr + ChipCmd1);
1877 	IOSYNC;
1878 
1879 	/* dirty_tx may be pessimistically out-of-sync. See rhine_tx. */
1880 	if (rhine_tx_queue_full(rp)) {
1881 		netif_stop_queue(dev);
1882 		smp_rmb();
1883 		/* Rejuvenate. */
1884 		if (!rhine_tx_queue_full(rp))
1885 			netif_wake_queue(dev);
1886 	}
1887 
1888 	netif_dbg(rp, tx_queued, dev, "Transmit frame #%d queued in slot %d\n",
1889 		  rp->cur_tx - 1, entry);
1890 
1891 	return NETDEV_TX_OK;
1892 }
1893 
1894 static void rhine_irq_disable(struct rhine_private *rp)
1895 {
1896 	iowrite16(0x0000, rp->base + IntrEnable);
1897 	mmiowb();
1898 }
1899 
1900 /* The interrupt handler does all of the Rx thread work and cleans up
1901    after the Tx thread. */
1902 static irqreturn_t rhine_interrupt(int irq, void *dev_instance)
1903 {
1904 	struct net_device *dev = dev_instance;
1905 	struct rhine_private *rp = netdev_priv(dev);
1906 	u32 status;
1907 	int handled = 0;
1908 
1909 	status = rhine_get_events(rp);
1910 
1911 	netif_dbg(rp, intr, dev, "Interrupt, status %08x\n", status);
1912 
1913 	if (status & RHINE_EVENT) {
1914 		handled = 1;
1915 
1916 		rhine_irq_disable(rp);
1917 		napi_schedule(&rp->napi);
1918 	}
1919 
1920 	if (status & ~(IntrLinkChange | IntrStatsMax | RHINE_EVENT_NAPI)) {
1921 		netif_err(rp, intr, dev, "Something Wicked happened! %08x\n",
1922 			  status);
1923 	}
1924 
1925 	return IRQ_RETVAL(handled);
1926 }
1927 
1928 /* This routine is logically part of the interrupt handler, but isolated
1929    for clarity. */
1930 static void rhine_tx(struct net_device *dev)
1931 {
1932 	struct rhine_private *rp = netdev_priv(dev);
1933 	struct device *hwdev = dev->dev.parent;
1934 	unsigned int pkts_compl = 0, bytes_compl = 0;
1935 	unsigned int dirty_tx = rp->dirty_tx;
1936 	unsigned int cur_tx;
1937 	struct sk_buff *skb;
1938 
1939 	/*
1940 	 * The race with rhine_start_tx does not matter here as long as the
1941 	 * driver enforces a value of cur_tx that was relevant when the
1942 	 * packet was scheduled to the network chipset.
1943 	 * Executive summary: smp_rmb() balances smp_wmb() in rhine_start_tx.
1944 	 */
1945 	smp_rmb();
1946 	cur_tx = rp->cur_tx;
1947 	/* find and cleanup dirty tx descriptors */
1948 	while (dirty_tx != cur_tx) {
1949 		unsigned int entry = dirty_tx % TX_RING_SIZE;
1950 		u32 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
1951 
1952 		netif_dbg(rp, tx_done, dev, "Tx scavenge %d status %08x\n",
1953 			  entry, txstatus);
1954 		if (txstatus & DescOwn)
1955 			break;
1956 		skb = rp->tx_skbuff[entry];
1957 		if (txstatus & 0x8000) {
1958 			netif_dbg(rp, tx_done, dev,
1959 				  "Transmit error, Tx status %08x\n", txstatus);
1960 			dev->stats.tx_errors++;
1961 			if (txstatus & 0x0400)
1962 				dev->stats.tx_carrier_errors++;
1963 			if (txstatus & 0x0200)
1964 				dev->stats.tx_window_errors++;
1965 			if (txstatus & 0x0100)
1966 				dev->stats.tx_aborted_errors++;
1967 			if (txstatus & 0x0080)
1968 				dev->stats.tx_heartbeat_errors++;
1969 			if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
1970 			    (txstatus & 0x0800) || (txstatus & 0x1000)) {
1971 				dev->stats.tx_fifo_errors++;
1972 				rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1973 				break; /* Keep the skb - we try again */
1974 			}
1975 			/* Transmitter restarted in 'abnormal' handler. */
1976 		} else {
1977 			if (rp->quirks & rqRhineI)
1978 				dev->stats.collisions += (txstatus >> 3) & 0x0F;
1979 			else
1980 				dev->stats.collisions += txstatus & 0x0F;
1981 			netif_dbg(rp, tx_done, dev, "collisions: %1.1x:%1.1x\n",
1982 				  (txstatus >> 3) & 0xF, txstatus & 0xF);
1983 
1984 			u64_stats_update_begin(&rp->tx_stats.syncp);
1985 			rp->tx_stats.bytes += skb->len;
1986 			rp->tx_stats.packets++;
1987 			u64_stats_update_end(&rp->tx_stats.syncp);
1988 		}
1989 		/* Free the original skb. */
1990 		if (rp->tx_skbuff_dma[entry]) {
1991 			dma_unmap_single(hwdev,
1992 					 rp->tx_skbuff_dma[entry],
1993 					 skb->len,
1994 					 DMA_TO_DEVICE);
1995 		}
1996 		bytes_compl += skb->len;
1997 		pkts_compl++;
1998 		dev_consume_skb_any(skb);
1999 		rp->tx_skbuff[entry] = NULL;
2000 		dirty_tx++;
2001 	}
2002 
2003 	rp->dirty_tx = dirty_tx;
2004 	/* Pity we can't rely on the nearby BQL completion implicit barrier. */
2005 	smp_wmb();
2006 
2007 	netdev_completed_queue(dev, pkts_compl, bytes_compl);
2008 
2009 	/* cur_tx may be optimistically out-of-sync. See rhine_start_tx. */
2010 	if (!rhine_tx_queue_full(rp) && netif_queue_stopped(dev)) {
2011 		netif_wake_queue(dev);
2012 		smp_rmb();
2013 		/* Rejuvenate. */
2014 		if (rhine_tx_queue_full(rp))
2015 			netif_stop_queue(dev);
2016 	}
2017 }
2018 
2019 /**
2020  * rhine_get_vlan_tci - extract TCI from Rx data buffer
2021  * @skb: pointer to sk_buff
2022  * @data_size: used data area of the buffer including CRC
2023  *
2024  * If hardware VLAN tag extraction is enabled and the chip indicates a 802.1Q
2025  * packet, the extracted 802.1Q header (2 bytes TPID + 2 bytes TCI) is 4-byte
2026  * aligned following the CRC.
2027  */
2028 static inline u16 rhine_get_vlan_tci(struct sk_buff *skb, int data_size)
2029 {
2030 	u8 *trailer = (u8 *)skb->data + ((data_size + 3) & ~3) + 2;
2031 	return be16_to_cpup((__be16 *)trailer);
2032 }
2033 
2034 static inline void rhine_rx_vlan_tag(struct sk_buff *skb, struct rx_desc *desc,
2035 				     int data_size)
2036 {
2037 	dma_rmb();
2038 	if (unlikely(desc->desc_length & cpu_to_le32(DescTag))) {
2039 		u16 vlan_tci;
2040 
2041 		vlan_tci = rhine_get_vlan_tci(skb, data_size);
2042 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci);
2043 	}
2044 }
2045 
2046 /* Process up to limit frames from receive ring */
2047 static int rhine_rx(struct net_device *dev, int limit)
2048 {
2049 	struct rhine_private *rp = netdev_priv(dev);
2050 	struct device *hwdev = dev->dev.parent;
2051 	int entry = rp->cur_rx % RX_RING_SIZE;
2052 	int count;
2053 
2054 	netif_dbg(rp, rx_status, dev, "%s(), entry %d status %08x\n", __func__,
2055 		  entry, le32_to_cpu(rp->rx_ring[entry].rx_status));
2056 
2057 	/* If EOP is set on the next entry, it's a new packet. Send it up. */
2058 	for (count = 0; count < limit; ++count) {
2059 		struct rx_desc *desc = rp->rx_ring + entry;
2060 		u32 desc_status = le32_to_cpu(desc->rx_status);
2061 		int data_size = desc_status >> 16;
2062 
2063 		if (desc_status & DescOwn)
2064 			break;
2065 
2066 		netif_dbg(rp, rx_status, dev, "%s() status %08x\n", __func__,
2067 			  desc_status);
2068 
2069 		if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {
2070 			if ((desc_status & RxWholePkt) != RxWholePkt) {
2071 				netdev_warn(dev,
2072 	"Oversized Ethernet frame spanned multiple buffers, "
2073 	"entry %#x length %d status %08x!\n",
2074 					    entry, data_size,
2075 					    desc_status);
2076 				dev->stats.rx_length_errors++;
2077 			} else if (desc_status & RxErr) {
2078 				/* There was a error. */
2079 				netif_dbg(rp, rx_err, dev,
2080 					  "%s() Rx error %08x\n", __func__,
2081 					  desc_status);
2082 				dev->stats.rx_errors++;
2083 				if (desc_status & 0x0030)
2084 					dev->stats.rx_length_errors++;
2085 				if (desc_status & 0x0048)
2086 					dev->stats.rx_fifo_errors++;
2087 				if (desc_status & 0x0004)
2088 					dev->stats.rx_frame_errors++;
2089 				if (desc_status & 0x0002) {
2090 					/* this can also be updated outside the interrupt handler */
2091 					spin_lock(&rp->lock);
2092 					dev->stats.rx_crc_errors++;
2093 					spin_unlock(&rp->lock);
2094 				}
2095 			}
2096 		} else {
2097 			/* Length should omit the CRC */
2098 			int pkt_len = data_size - 4;
2099 			struct sk_buff *skb;
2100 
2101 			/* Check if the packet is long enough to accept without
2102 			   copying to a minimally-sized skbuff. */
2103 			if (pkt_len < rx_copybreak) {
2104 				skb = netdev_alloc_skb_ip_align(dev, pkt_len);
2105 				if (unlikely(!skb))
2106 					goto drop;
2107 
2108 				dma_sync_single_for_cpu(hwdev,
2109 							rp->rx_skbuff_dma[entry],
2110 							rp->rx_buf_sz,
2111 							DMA_FROM_DEVICE);
2112 
2113 				skb_copy_to_linear_data(skb,
2114 						 rp->rx_skbuff[entry]->data,
2115 						 pkt_len);
2116 
2117 				dma_sync_single_for_device(hwdev,
2118 							   rp->rx_skbuff_dma[entry],
2119 							   rp->rx_buf_sz,
2120 							   DMA_FROM_DEVICE);
2121 			} else {
2122 				struct rhine_skb_dma sd;
2123 
2124 				if (unlikely(rhine_skb_dma_init(dev, &sd) < 0))
2125 					goto drop;
2126 
2127 				skb = rp->rx_skbuff[entry];
2128 
2129 				dma_unmap_single(hwdev,
2130 						 rp->rx_skbuff_dma[entry],
2131 						 rp->rx_buf_sz,
2132 						 DMA_FROM_DEVICE);
2133 				rhine_skb_dma_nic_store(rp, &sd, entry);
2134 			}
2135 
2136 			skb_put(skb, pkt_len);
2137 
2138 			rhine_rx_vlan_tag(skb, desc, data_size);
2139 
2140 			skb->protocol = eth_type_trans(skb, dev);
2141 
2142 			netif_receive_skb(skb);
2143 
2144 			u64_stats_update_begin(&rp->rx_stats.syncp);
2145 			rp->rx_stats.bytes += pkt_len;
2146 			rp->rx_stats.packets++;
2147 			u64_stats_update_end(&rp->rx_stats.syncp);
2148 		}
2149 give_descriptor_to_nic:
2150 		desc->rx_status = cpu_to_le32(DescOwn);
2151 		entry = (++rp->cur_rx) % RX_RING_SIZE;
2152 	}
2153 
2154 	return count;
2155 
2156 drop:
2157 	dev->stats.rx_dropped++;
2158 	goto give_descriptor_to_nic;
2159 }
2160 
2161 static void rhine_restart_tx(struct net_device *dev) {
2162 	struct rhine_private *rp = netdev_priv(dev);
2163 	void __iomem *ioaddr = rp->base;
2164 	int entry = rp->dirty_tx % TX_RING_SIZE;
2165 	u32 intr_status;
2166 
2167 	/*
2168 	 * If new errors occurred, we need to sort them out before doing Tx.
2169 	 * In that case the ISR will be back here RSN anyway.
2170 	 */
2171 	intr_status = rhine_get_events(rp);
2172 
2173 	if ((intr_status & IntrTxErrSummary) == 0) {
2174 
2175 		/* We know better than the chip where it should continue. */
2176 		iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
2177 		       ioaddr + TxRingPtr);
2178 
2179 		iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
2180 		       ioaddr + ChipCmd);
2181 
2182 		if (rp->tx_ring[entry].desc_length & cpu_to_le32(0x020000))
2183 			/* Tx queues are bits 7-0 (first Tx queue: bit 7) */
2184 			BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
2185 
2186 		iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
2187 		       ioaddr + ChipCmd1);
2188 		IOSYNC;
2189 	}
2190 	else {
2191 		/* This should never happen */
2192 		netif_warn(rp, tx_err, dev, "another error occurred %08x\n",
2193 			   intr_status);
2194 	}
2195 
2196 }
2197 
2198 static void rhine_slow_event_task(struct work_struct *work)
2199 {
2200 	struct rhine_private *rp =
2201 		container_of(work, struct rhine_private, slow_event_task);
2202 	struct net_device *dev = rp->dev;
2203 	u32 intr_status;
2204 
2205 	mutex_lock(&rp->task_lock);
2206 
2207 	if (!rp->task_enable)
2208 		goto out_unlock;
2209 
2210 	intr_status = rhine_get_events(rp);
2211 	rhine_ack_events(rp, intr_status & RHINE_EVENT_SLOW);
2212 
2213 	if (intr_status & IntrLinkChange)
2214 		rhine_check_media(dev, 0);
2215 
2216 	if (intr_status & IntrPCIErr)
2217 		netif_warn(rp, hw, dev, "PCI error\n");
2218 
2219 	iowrite16(RHINE_EVENT & 0xffff, rp->base + IntrEnable);
2220 
2221 out_unlock:
2222 	mutex_unlock(&rp->task_lock);
2223 }
2224 
2225 static struct rtnl_link_stats64 *
2226 rhine_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
2227 {
2228 	struct rhine_private *rp = netdev_priv(dev);
2229 	unsigned int start;
2230 
2231 	spin_lock_bh(&rp->lock);
2232 	rhine_update_rx_crc_and_missed_errord(rp);
2233 	spin_unlock_bh(&rp->lock);
2234 
2235 	netdev_stats_to_stats64(stats, &dev->stats);
2236 
2237 	do {
2238 		start = u64_stats_fetch_begin_irq(&rp->rx_stats.syncp);
2239 		stats->rx_packets = rp->rx_stats.packets;
2240 		stats->rx_bytes = rp->rx_stats.bytes;
2241 	} while (u64_stats_fetch_retry_irq(&rp->rx_stats.syncp, start));
2242 
2243 	do {
2244 		start = u64_stats_fetch_begin_irq(&rp->tx_stats.syncp);
2245 		stats->tx_packets = rp->tx_stats.packets;
2246 		stats->tx_bytes = rp->tx_stats.bytes;
2247 	} while (u64_stats_fetch_retry_irq(&rp->tx_stats.syncp, start));
2248 
2249 	return stats;
2250 }
2251 
2252 static void rhine_set_rx_mode(struct net_device *dev)
2253 {
2254 	struct rhine_private *rp = netdev_priv(dev);
2255 	void __iomem *ioaddr = rp->base;
2256 	u32 mc_filter[2];	/* Multicast hash filter */
2257 	u8 rx_mode = 0x0C;	/* Note: 0x02=accept runt, 0x01=accept errs */
2258 	struct netdev_hw_addr *ha;
2259 
2260 	if (dev->flags & IFF_PROMISC) {		/* Set promiscuous. */
2261 		rx_mode = 0x1C;
2262 		iowrite32(0xffffffff, ioaddr + MulticastFilter0);
2263 		iowrite32(0xffffffff, ioaddr + MulticastFilter1);
2264 	} else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
2265 		   (dev->flags & IFF_ALLMULTI)) {
2266 		/* Too many to match, or accept all multicasts. */
2267 		iowrite32(0xffffffff, ioaddr + MulticastFilter0);
2268 		iowrite32(0xffffffff, ioaddr + MulticastFilter1);
2269 	} else if (rp->quirks & rqMgmt) {
2270 		int i = 0;
2271 		u32 mCAMmask = 0;	/* 32 mCAMs (6105M and better) */
2272 		netdev_for_each_mc_addr(ha, dev) {
2273 			if (i == MCAM_SIZE)
2274 				break;
2275 			rhine_set_cam(ioaddr, i, ha->addr);
2276 			mCAMmask |= 1 << i;
2277 			i++;
2278 		}
2279 		rhine_set_cam_mask(ioaddr, mCAMmask);
2280 	} else {
2281 		memset(mc_filter, 0, sizeof(mc_filter));
2282 		netdev_for_each_mc_addr(ha, dev) {
2283 			int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2284 
2285 			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2286 		}
2287 		iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
2288 		iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
2289 	}
2290 	/* enable/disable VLAN receive filtering */
2291 	if (rp->quirks & rqMgmt) {
2292 		if (dev->flags & IFF_PROMISC)
2293 			BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
2294 		else
2295 			BYTE_REG_BITS_ON(BCR1_VIDFR, ioaddr + PCIBusConfig1);
2296 	}
2297 	BYTE_REG_BITS_ON(rx_mode, ioaddr + RxConfig);
2298 }
2299 
2300 static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2301 {
2302 	struct device *hwdev = dev->dev.parent;
2303 
2304 	strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2305 	strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2306 	strlcpy(info->bus_info, dev_name(hwdev), sizeof(info->bus_info));
2307 }
2308 
2309 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2310 {
2311 	struct rhine_private *rp = netdev_priv(dev);
2312 	int rc;
2313 
2314 	mutex_lock(&rp->task_lock);
2315 	rc = mii_ethtool_gset(&rp->mii_if, cmd);
2316 	mutex_unlock(&rp->task_lock);
2317 
2318 	return rc;
2319 }
2320 
2321 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2322 {
2323 	struct rhine_private *rp = netdev_priv(dev);
2324 	int rc;
2325 
2326 	mutex_lock(&rp->task_lock);
2327 	rc = mii_ethtool_sset(&rp->mii_if, cmd);
2328 	rhine_set_carrier(&rp->mii_if);
2329 	mutex_unlock(&rp->task_lock);
2330 
2331 	return rc;
2332 }
2333 
2334 static int netdev_nway_reset(struct net_device *dev)
2335 {
2336 	struct rhine_private *rp = netdev_priv(dev);
2337 
2338 	return mii_nway_restart(&rp->mii_if);
2339 }
2340 
2341 static u32 netdev_get_link(struct net_device *dev)
2342 {
2343 	struct rhine_private *rp = netdev_priv(dev);
2344 
2345 	return mii_link_ok(&rp->mii_if);
2346 }
2347 
2348 static u32 netdev_get_msglevel(struct net_device *dev)
2349 {
2350 	struct rhine_private *rp = netdev_priv(dev);
2351 
2352 	return rp->msg_enable;
2353 }
2354 
2355 static void netdev_set_msglevel(struct net_device *dev, u32 value)
2356 {
2357 	struct rhine_private *rp = netdev_priv(dev);
2358 
2359 	rp->msg_enable = value;
2360 }
2361 
2362 static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2363 {
2364 	struct rhine_private *rp = netdev_priv(dev);
2365 
2366 	if (!(rp->quirks & rqWOL))
2367 		return;
2368 
2369 	spin_lock_irq(&rp->lock);
2370 	wol->supported = WAKE_PHY | WAKE_MAGIC |
2371 			 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;	/* Untested */
2372 	wol->wolopts = rp->wolopts;
2373 	spin_unlock_irq(&rp->lock);
2374 }
2375 
2376 static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2377 {
2378 	struct rhine_private *rp = netdev_priv(dev);
2379 	u32 support = WAKE_PHY | WAKE_MAGIC |
2380 		      WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;	/* Untested */
2381 
2382 	if (!(rp->quirks & rqWOL))
2383 		return -EINVAL;
2384 
2385 	if (wol->wolopts & ~support)
2386 		return -EINVAL;
2387 
2388 	spin_lock_irq(&rp->lock);
2389 	rp->wolopts = wol->wolopts;
2390 	spin_unlock_irq(&rp->lock);
2391 
2392 	return 0;
2393 }
2394 
2395 static const struct ethtool_ops netdev_ethtool_ops = {
2396 	.get_drvinfo		= netdev_get_drvinfo,
2397 	.get_settings		= netdev_get_settings,
2398 	.set_settings		= netdev_set_settings,
2399 	.nway_reset		= netdev_nway_reset,
2400 	.get_link		= netdev_get_link,
2401 	.get_msglevel		= netdev_get_msglevel,
2402 	.set_msglevel		= netdev_set_msglevel,
2403 	.get_wol		= rhine_get_wol,
2404 	.set_wol		= rhine_set_wol,
2405 };
2406 
2407 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2408 {
2409 	struct rhine_private *rp = netdev_priv(dev);
2410 	int rc;
2411 
2412 	if (!netif_running(dev))
2413 		return -EINVAL;
2414 
2415 	mutex_lock(&rp->task_lock);
2416 	rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
2417 	rhine_set_carrier(&rp->mii_if);
2418 	mutex_unlock(&rp->task_lock);
2419 
2420 	return rc;
2421 }
2422 
2423 static int rhine_close(struct net_device *dev)
2424 {
2425 	struct rhine_private *rp = netdev_priv(dev);
2426 	void __iomem *ioaddr = rp->base;
2427 
2428 	rhine_task_disable(rp);
2429 	napi_disable(&rp->napi);
2430 	netif_stop_queue(dev);
2431 
2432 	netif_dbg(rp, ifdown, dev, "Shutting down ethercard, status was %04x\n",
2433 		  ioread16(ioaddr + ChipCmd));
2434 
2435 	/* Switch to loopback mode to avoid hardware races. */
2436 	iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
2437 
2438 	rhine_irq_disable(rp);
2439 
2440 	/* Stop the chip's Tx and Rx processes. */
2441 	iowrite16(CmdStop, ioaddr + ChipCmd);
2442 
2443 	free_irq(rp->irq, dev);
2444 	free_rbufs(dev);
2445 	free_tbufs(dev);
2446 	free_ring(dev);
2447 
2448 	return 0;
2449 }
2450 
2451 
2452 static void rhine_remove_one_pci(struct pci_dev *pdev)
2453 {
2454 	struct net_device *dev = pci_get_drvdata(pdev);
2455 	struct rhine_private *rp = netdev_priv(dev);
2456 
2457 	unregister_netdev(dev);
2458 
2459 	pci_iounmap(pdev, rp->base);
2460 	pci_release_regions(pdev);
2461 
2462 	free_netdev(dev);
2463 	pci_disable_device(pdev);
2464 }
2465 
2466 static int rhine_remove_one_platform(struct platform_device *pdev)
2467 {
2468 	struct net_device *dev = platform_get_drvdata(pdev);
2469 	struct rhine_private *rp = netdev_priv(dev);
2470 
2471 	unregister_netdev(dev);
2472 
2473 	iounmap(rp->base);
2474 
2475 	free_netdev(dev);
2476 
2477 	return 0;
2478 }
2479 
2480 static void rhine_shutdown_pci(struct pci_dev *pdev)
2481 {
2482 	struct net_device *dev = pci_get_drvdata(pdev);
2483 	struct rhine_private *rp = netdev_priv(dev);
2484 	void __iomem *ioaddr = rp->base;
2485 
2486 	if (!(rp->quirks & rqWOL))
2487 		return; /* Nothing to do for non-WOL adapters */
2488 
2489 	rhine_power_init(dev);
2490 
2491 	/* Make sure we use pattern 0, 1 and not 4, 5 */
2492 	if (rp->quirks & rq6patterns)
2493 		iowrite8(0x04, ioaddr + WOLcgClr);
2494 
2495 	spin_lock(&rp->lock);
2496 
2497 	if (rp->wolopts & WAKE_MAGIC) {
2498 		iowrite8(WOLmagic, ioaddr + WOLcrSet);
2499 		/*
2500 		 * Turn EEPROM-controlled wake-up back on -- some hardware may
2501 		 * not cooperate otherwise.
2502 		 */
2503 		iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
2504 	}
2505 
2506 	if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
2507 		iowrite8(WOLbmcast, ioaddr + WOLcgSet);
2508 
2509 	if (rp->wolopts & WAKE_PHY)
2510 		iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
2511 
2512 	if (rp->wolopts & WAKE_UCAST)
2513 		iowrite8(WOLucast, ioaddr + WOLcrSet);
2514 
2515 	if (rp->wolopts) {
2516 		/* Enable legacy WOL (for old motherboards) */
2517 		iowrite8(0x01, ioaddr + PwcfgSet);
2518 		iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
2519 	}
2520 
2521 	spin_unlock(&rp->lock);
2522 
2523 	if (system_state == SYSTEM_POWER_OFF && !avoid_D3) {
2524 		iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);
2525 
2526 		pci_wake_from_d3(pdev, true);
2527 		pci_set_power_state(pdev, PCI_D3hot);
2528 	}
2529 }
2530 
2531 #ifdef CONFIG_PM_SLEEP
2532 static int rhine_suspend(struct device *device)
2533 {
2534 	struct net_device *dev = dev_get_drvdata(device);
2535 	struct rhine_private *rp = netdev_priv(dev);
2536 
2537 	if (!netif_running(dev))
2538 		return 0;
2539 
2540 	rhine_task_disable(rp);
2541 	rhine_irq_disable(rp);
2542 	napi_disable(&rp->napi);
2543 
2544 	netif_device_detach(dev);
2545 
2546 	if (dev_is_pci(device))
2547 		rhine_shutdown_pci(to_pci_dev(device));
2548 
2549 	return 0;
2550 }
2551 
2552 static int rhine_resume(struct device *device)
2553 {
2554 	struct net_device *dev = dev_get_drvdata(device);
2555 	struct rhine_private *rp = netdev_priv(dev);
2556 
2557 	if (!netif_running(dev))
2558 		return 0;
2559 
2560 	enable_mmio(rp->pioaddr, rp->quirks);
2561 	rhine_power_init(dev);
2562 	free_tbufs(dev);
2563 	alloc_tbufs(dev);
2564 	rhine_reset_rbufs(rp);
2565 	rhine_task_enable(rp);
2566 	spin_lock_bh(&rp->lock);
2567 	init_registers(dev);
2568 	spin_unlock_bh(&rp->lock);
2569 
2570 	netif_device_attach(dev);
2571 
2572 	return 0;
2573 }
2574 
2575 static SIMPLE_DEV_PM_OPS(rhine_pm_ops, rhine_suspend, rhine_resume);
2576 #define RHINE_PM_OPS	(&rhine_pm_ops)
2577 
2578 #else
2579 
2580 #define RHINE_PM_OPS	NULL
2581 
2582 #endif /* !CONFIG_PM_SLEEP */
2583 
2584 static struct pci_driver rhine_driver_pci = {
2585 	.name		= DRV_NAME,
2586 	.id_table	= rhine_pci_tbl,
2587 	.probe		= rhine_init_one_pci,
2588 	.remove		= rhine_remove_one_pci,
2589 	.shutdown	= rhine_shutdown_pci,
2590 	.driver.pm	= RHINE_PM_OPS,
2591 };
2592 
2593 static struct platform_driver rhine_driver_platform = {
2594 	.probe		= rhine_init_one_platform,
2595 	.remove		= rhine_remove_one_platform,
2596 	.driver = {
2597 		.name	= DRV_NAME,
2598 		.of_match_table	= rhine_of_tbl,
2599 		.pm		= RHINE_PM_OPS,
2600 	}
2601 };
2602 
2603 static struct dmi_system_id rhine_dmi_table[] __initdata = {
2604 	{
2605 		.ident = "EPIA-M",
2606 		.matches = {
2607 			DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."),
2608 			DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
2609 		},
2610 	},
2611 	{
2612 		.ident = "KV7",
2613 		.matches = {
2614 			DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
2615 			DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
2616 		},
2617 	},
2618 	{ NULL }
2619 };
2620 
2621 static int __init rhine_init(void)
2622 {
2623 	int ret_pci, ret_platform;
2624 
2625 /* when a module, this is printed whether or not devices are found in probe */
2626 #ifdef MODULE
2627 	pr_info("%s\n", version);
2628 #endif
2629 	if (dmi_check_system(rhine_dmi_table)) {
2630 		/* these BIOSes fail at PXE boot if chip is in D3 */
2631 		avoid_D3 = true;
2632 		pr_warn("Broken BIOS detected, avoid_D3 enabled\n");
2633 	}
2634 	else if (avoid_D3)
2635 		pr_info("avoid_D3 set\n");
2636 
2637 	ret_pci = pci_register_driver(&rhine_driver_pci);
2638 	ret_platform = platform_driver_register(&rhine_driver_platform);
2639 	if ((ret_pci < 0) && (ret_platform < 0))
2640 		return ret_pci;
2641 
2642 	return 0;
2643 }
2644 
2645 
2646 static void __exit rhine_cleanup(void)
2647 {
2648 	platform_driver_unregister(&rhine_driver_platform);
2649 	pci_unregister_driver(&rhine_driver_pci);
2650 }
2651 
2652 
2653 module_init(rhine_init);
2654 module_exit(rhine_cleanup);
2655