1 /******************************************************************************* 2 3 Copyright(c) 2006 Tundra Semiconductor Corporation. 4 5 This program is free software; you can redistribute it and/or modify it 6 under the terms of the GNU General Public License as published by the Free 7 Software Foundation; either version 2 of the License, or (at your option) 8 any later version. 9 10 This program is distributed in the hope that it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 59 17 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 18 19 *******************************************************************************/ 20 21 /* This driver is based on the driver code originally developed 22 * for the Intel IOC80314 (ForestLake) Gigabit Ethernet by 23 * scott.wood@timesys.com * Copyright (C) 2003 TimeSys Corporation 24 * 25 * Currently changes from original version are: 26 * - porting to Tsi108-based platform and kernel 2.6 (kong.lai@tundra.com) 27 * - modifications to handle two ports independently and support for 28 * additional PHY devices (alexandre.bounine@tundra.com) 29 * - Get hardware information from platform device. (tie-fei.zang@freescale.com) 30 * 31 */ 32 33 #include <linux/module.h> 34 #include <linux/types.h> 35 #include <linux/interrupt.h> 36 #include <linux/net.h> 37 #include <linux/netdevice.h> 38 #include <linux/etherdevice.h> 39 #include <linux/ethtool.h> 40 #include <linux/skbuff.h> 41 #include <linux/spinlock.h> 42 #include <linux/delay.h> 43 #include <linux/crc32.h> 44 #include <linux/mii.h> 45 #include <linux/device.h> 46 #include <linux/pci.h> 47 #include <linux/rtnetlink.h> 48 #include <linux/timer.h> 49 #include <linux/platform_device.h> 50 #include <linux/gfp.h> 51 52 #include <asm/io.h> 53 #include <asm/tsi108.h> 54 55 #include "tsi108_eth.h" 56 57 #define MII_READ_DELAY 10000 /* max link wait time in msec */ 58 59 #define TSI108_RXRING_LEN 256 60 61 /* NOTE: The driver currently does not support receiving packets 62 * larger than the buffer size, so don't decrease this (unless you 63 * want to add such support). 64 */ 65 #define TSI108_RXBUF_SIZE 1536 66 67 #define TSI108_TXRING_LEN 256 68 69 #define TSI108_TX_INT_FREQ 64 70 71 /* Check the phy status every half a second. */ 72 #define CHECK_PHY_INTERVAL (HZ/2) 73 74 static int tsi108_init_one(struct platform_device *pdev); 75 static int tsi108_ether_remove(struct platform_device *pdev); 76 77 struct tsi108_prv_data { 78 void __iomem *regs; /* Base of normal regs */ 79 void __iomem *phyregs; /* Base of register bank used for PHY access */ 80 81 struct net_device *dev; 82 struct napi_struct napi; 83 84 unsigned int phy; /* Index of PHY for this interface */ 85 unsigned int irq_num; 86 unsigned int id; 87 unsigned int phy_type; 88 89 struct timer_list timer;/* Timer that triggers the check phy function */ 90 unsigned int rxtail; /* Next entry in rxring to read */ 91 unsigned int rxhead; /* Next entry in rxring to give a new buffer */ 92 unsigned int rxfree; /* Number of free, allocated RX buffers */ 93 94 unsigned int rxpending; /* Non-zero if there are still descriptors 95 * to be processed from a previous descriptor 96 * interrupt condition that has been cleared */ 97 98 unsigned int txtail; /* Next TX descriptor to check status on */ 99 unsigned int txhead; /* Next TX descriptor to use */ 100 101 /* Number of free TX descriptors. This could be calculated from 102 * rxhead and rxtail if one descriptor were left unused to disambiguate 103 * full and empty conditions, but it's simpler to just keep track 104 * explicitly. */ 105 106 unsigned int txfree; 107 108 unsigned int phy_ok; /* The PHY is currently powered on. */ 109 110 /* PHY status (duplex is 1 for half, 2 for full, 111 * so that the default 0 indicates that neither has 112 * yet been configured). */ 113 114 unsigned int link_up; 115 unsigned int speed; 116 unsigned int duplex; 117 118 tx_desc *txring; 119 rx_desc *rxring; 120 struct sk_buff *txskbs[TSI108_TXRING_LEN]; 121 struct sk_buff *rxskbs[TSI108_RXRING_LEN]; 122 123 dma_addr_t txdma, rxdma; 124 125 /* txlock nests in misclock and phy_lock */ 126 127 spinlock_t txlock, misclock; 128 129 /* stats is used to hold the upper bits of each hardware counter, 130 * and tmpstats is used to hold the full values for returning 131 * to the caller of get_stats(). They must be separate in case 132 * an overflow interrupt occurs before the stats are consumed. 133 */ 134 135 struct net_device_stats stats; 136 struct net_device_stats tmpstats; 137 138 /* These stats are kept separate in hardware, thus require individual 139 * fields for handling carry. They are combined in get_stats. 140 */ 141 142 unsigned long rx_fcs; /* Add to rx_frame_errors */ 143 unsigned long rx_short_fcs; /* Add to rx_frame_errors */ 144 unsigned long rx_long_fcs; /* Add to rx_frame_errors */ 145 unsigned long rx_underruns; /* Add to rx_length_errors */ 146 unsigned long rx_overruns; /* Add to rx_length_errors */ 147 148 unsigned long tx_coll_abort; /* Add to tx_aborted_errors/collisions */ 149 unsigned long tx_pause_drop; /* Add to tx_aborted_errors */ 150 151 unsigned long mc_hash[16]; 152 u32 msg_enable; /* debug message level */ 153 struct mii_if_info mii_if; 154 unsigned int init_media; 155 }; 156 157 /* Structure for a device driver */ 158 159 static struct platform_driver tsi_eth_driver = { 160 .probe = tsi108_init_one, 161 .remove = tsi108_ether_remove, 162 .driver = { 163 .name = "tsi-ethernet", 164 .owner = THIS_MODULE, 165 }, 166 }; 167 168 static void tsi108_timed_checker(unsigned long dev_ptr); 169 170 static void dump_eth_one(struct net_device *dev) 171 { 172 struct tsi108_prv_data *data = netdev_priv(dev); 173 174 printk("Dumping %s...\n", dev->name); 175 printk("intstat %x intmask %x phy_ok %d" 176 " link %d speed %d duplex %d\n", 177 TSI_READ(TSI108_EC_INTSTAT), 178 TSI_READ(TSI108_EC_INTMASK), data->phy_ok, 179 data->link_up, data->speed, data->duplex); 180 181 printk("TX: head %d, tail %d, free %d, stat %x, estat %x, err %x\n", 182 data->txhead, data->txtail, data->txfree, 183 TSI_READ(TSI108_EC_TXSTAT), 184 TSI_READ(TSI108_EC_TXESTAT), 185 TSI_READ(TSI108_EC_TXERR)); 186 187 printk("RX: head %d, tail %d, free %d, stat %x," 188 " estat %x, err %x, pending %d\n\n", 189 data->rxhead, data->rxtail, data->rxfree, 190 TSI_READ(TSI108_EC_RXSTAT), 191 TSI_READ(TSI108_EC_RXESTAT), 192 TSI_READ(TSI108_EC_RXERR), data->rxpending); 193 } 194 195 /* Synchronization is needed between the thread and up/down events. 196 * Note that the PHY is accessed through the same registers for both 197 * interfaces, so this can't be made interface-specific. 198 */ 199 200 static DEFINE_SPINLOCK(phy_lock); 201 202 static int tsi108_read_mii(struct tsi108_prv_data *data, int reg) 203 { 204 unsigned i; 205 206 TSI_WRITE_PHY(TSI108_MAC_MII_ADDR, 207 (data->phy << TSI108_MAC_MII_ADDR_PHY) | 208 (reg << TSI108_MAC_MII_ADDR_REG)); 209 TSI_WRITE_PHY(TSI108_MAC_MII_CMD, 0); 210 TSI_WRITE_PHY(TSI108_MAC_MII_CMD, TSI108_MAC_MII_CMD_READ); 211 for (i = 0; i < 100; i++) { 212 if (!(TSI_READ_PHY(TSI108_MAC_MII_IND) & 213 (TSI108_MAC_MII_IND_NOTVALID | TSI108_MAC_MII_IND_BUSY))) 214 break; 215 udelay(10); 216 } 217 218 if (i == 100) 219 return 0xffff; 220 else 221 return TSI_READ_PHY(TSI108_MAC_MII_DATAIN); 222 } 223 224 static void tsi108_write_mii(struct tsi108_prv_data *data, 225 int reg, u16 val) 226 { 227 unsigned i = 100; 228 TSI_WRITE_PHY(TSI108_MAC_MII_ADDR, 229 (data->phy << TSI108_MAC_MII_ADDR_PHY) | 230 (reg << TSI108_MAC_MII_ADDR_REG)); 231 TSI_WRITE_PHY(TSI108_MAC_MII_DATAOUT, val); 232 while (i--) { 233 if(!(TSI_READ_PHY(TSI108_MAC_MII_IND) & 234 TSI108_MAC_MII_IND_BUSY)) 235 break; 236 udelay(10); 237 } 238 } 239 240 static int tsi108_mdio_read(struct net_device *dev, int addr, int reg) 241 { 242 struct tsi108_prv_data *data = netdev_priv(dev); 243 return tsi108_read_mii(data, reg); 244 } 245 246 static void tsi108_mdio_write(struct net_device *dev, int addr, int reg, int val) 247 { 248 struct tsi108_prv_data *data = netdev_priv(dev); 249 tsi108_write_mii(data, reg, val); 250 } 251 252 static inline void tsi108_write_tbi(struct tsi108_prv_data *data, 253 int reg, u16 val) 254 { 255 unsigned i = 1000; 256 TSI_WRITE(TSI108_MAC_MII_ADDR, 257 (0x1e << TSI108_MAC_MII_ADDR_PHY) 258 | (reg << TSI108_MAC_MII_ADDR_REG)); 259 TSI_WRITE(TSI108_MAC_MII_DATAOUT, val); 260 while(i--) { 261 if(!(TSI_READ(TSI108_MAC_MII_IND) & TSI108_MAC_MII_IND_BUSY)) 262 return; 263 udelay(10); 264 } 265 printk(KERN_ERR "%s function time out\n", __func__); 266 } 267 268 static int mii_speed(struct mii_if_info *mii) 269 { 270 int advert, lpa, val, media; 271 int lpa2 = 0; 272 int speed; 273 274 if (!mii_link_ok(mii)) 275 return 0; 276 277 val = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_BMSR); 278 if ((val & BMSR_ANEGCOMPLETE) == 0) 279 return 0; 280 281 advert = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_ADVERTISE); 282 lpa = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_LPA); 283 media = mii_nway_result(advert & lpa); 284 285 if (mii->supports_gmii) 286 lpa2 = mii->mdio_read(mii->dev, mii->phy_id, MII_STAT1000); 287 288 speed = lpa2 & (LPA_1000FULL | LPA_1000HALF) ? 1000 : 289 (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 100 : 10); 290 return speed; 291 } 292 293 static void tsi108_check_phy(struct net_device *dev) 294 { 295 struct tsi108_prv_data *data = netdev_priv(dev); 296 u32 mac_cfg2_reg, portctrl_reg; 297 u32 duplex; 298 u32 speed; 299 unsigned long flags; 300 301 spin_lock_irqsave(&phy_lock, flags); 302 303 if (!data->phy_ok) 304 goto out; 305 306 duplex = mii_check_media(&data->mii_if, netif_msg_link(data), data->init_media); 307 data->init_media = 0; 308 309 if (netif_carrier_ok(dev)) { 310 311 speed = mii_speed(&data->mii_if); 312 313 if ((speed != data->speed) || duplex) { 314 315 mac_cfg2_reg = TSI_READ(TSI108_MAC_CFG2); 316 portctrl_reg = TSI_READ(TSI108_EC_PORTCTRL); 317 318 mac_cfg2_reg &= ~TSI108_MAC_CFG2_IFACE_MASK; 319 320 if (speed == 1000) { 321 mac_cfg2_reg |= TSI108_MAC_CFG2_GIG; 322 portctrl_reg &= ~TSI108_EC_PORTCTRL_NOGIG; 323 } else { 324 mac_cfg2_reg |= TSI108_MAC_CFG2_NOGIG; 325 portctrl_reg |= TSI108_EC_PORTCTRL_NOGIG; 326 } 327 328 data->speed = speed; 329 330 if (data->mii_if.full_duplex) { 331 mac_cfg2_reg |= TSI108_MAC_CFG2_FULLDUPLEX; 332 portctrl_reg &= ~TSI108_EC_PORTCTRL_HALFDUPLEX; 333 data->duplex = 2; 334 } else { 335 mac_cfg2_reg &= ~TSI108_MAC_CFG2_FULLDUPLEX; 336 portctrl_reg |= TSI108_EC_PORTCTRL_HALFDUPLEX; 337 data->duplex = 1; 338 } 339 340 TSI_WRITE(TSI108_MAC_CFG2, mac_cfg2_reg); 341 TSI_WRITE(TSI108_EC_PORTCTRL, portctrl_reg); 342 } 343 344 if (data->link_up == 0) { 345 /* The manual says it can take 3-4 usecs for the speed change 346 * to take effect. 347 */ 348 udelay(5); 349 350 spin_lock(&data->txlock); 351 if (is_valid_ether_addr(dev->dev_addr) && data->txfree) 352 netif_wake_queue(dev); 353 354 data->link_up = 1; 355 spin_unlock(&data->txlock); 356 } 357 } else { 358 if (data->link_up == 1) { 359 netif_stop_queue(dev); 360 data->link_up = 0; 361 printk(KERN_NOTICE "%s : link is down\n", dev->name); 362 } 363 364 goto out; 365 } 366 367 368 out: 369 spin_unlock_irqrestore(&phy_lock, flags); 370 } 371 372 static inline void 373 tsi108_stat_carry_one(int carry, int carry_bit, int carry_shift, 374 unsigned long *upper) 375 { 376 if (carry & carry_bit) 377 *upper += carry_shift; 378 } 379 380 static void tsi108_stat_carry(struct net_device *dev) 381 { 382 struct tsi108_prv_data *data = netdev_priv(dev); 383 u32 carry1, carry2; 384 385 spin_lock_irq(&data->misclock); 386 387 carry1 = TSI_READ(TSI108_STAT_CARRY1); 388 carry2 = TSI_READ(TSI108_STAT_CARRY2); 389 390 TSI_WRITE(TSI108_STAT_CARRY1, carry1); 391 TSI_WRITE(TSI108_STAT_CARRY2, carry2); 392 393 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXBYTES, 394 TSI108_STAT_RXBYTES_CARRY, &data->stats.rx_bytes); 395 396 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXPKTS, 397 TSI108_STAT_RXPKTS_CARRY, 398 &data->stats.rx_packets); 399 400 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXFCS, 401 TSI108_STAT_RXFCS_CARRY, &data->rx_fcs); 402 403 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXMCAST, 404 TSI108_STAT_RXMCAST_CARRY, 405 &data->stats.multicast); 406 407 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXALIGN, 408 TSI108_STAT_RXALIGN_CARRY, 409 &data->stats.rx_frame_errors); 410 411 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXLENGTH, 412 TSI108_STAT_RXLENGTH_CARRY, 413 &data->stats.rx_length_errors); 414 415 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXRUNT, 416 TSI108_STAT_RXRUNT_CARRY, &data->rx_underruns); 417 418 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXJUMBO, 419 TSI108_STAT_RXJUMBO_CARRY, &data->rx_overruns); 420 421 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXFRAG, 422 TSI108_STAT_RXFRAG_CARRY, &data->rx_short_fcs); 423 424 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXJABBER, 425 TSI108_STAT_RXJABBER_CARRY, &data->rx_long_fcs); 426 427 tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXDROP, 428 TSI108_STAT_RXDROP_CARRY, 429 &data->stats.rx_missed_errors); 430 431 tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXBYTES, 432 TSI108_STAT_TXBYTES_CARRY, &data->stats.tx_bytes); 433 434 tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXPKTS, 435 TSI108_STAT_TXPKTS_CARRY, 436 &data->stats.tx_packets); 437 438 tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXEXDEF, 439 TSI108_STAT_TXEXDEF_CARRY, 440 &data->stats.tx_aborted_errors); 441 442 tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXEXCOL, 443 TSI108_STAT_TXEXCOL_CARRY, &data->tx_coll_abort); 444 445 tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXTCOL, 446 TSI108_STAT_TXTCOL_CARRY, 447 &data->stats.collisions); 448 449 tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXPAUSE, 450 TSI108_STAT_TXPAUSEDROP_CARRY, 451 &data->tx_pause_drop); 452 453 spin_unlock_irq(&data->misclock); 454 } 455 456 /* Read a stat counter atomically with respect to carries. 457 * data->misclock must be held. 458 */ 459 static inline unsigned long 460 tsi108_read_stat(struct tsi108_prv_data * data, int reg, int carry_bit, 461 int carry_shift, unsigned long *upper) 462 { 463 int carryreg; 464 unsigned long val; 465 466 if (reg < 0xb0) 467 carryreg = TSI108_STAT_CARRY1; 468 else 469 carryreg = TSI108_STAT_CARRY2; 470 471 again: 472 val = TSI_READ(reg) | *upper; 473 474 /* Check to see if it overflowed, but the interrupt hasn't 475 * been serviced yet. If so, handle the carry here, and 476 * try again. 477 */ 478 479 if (unlikely(TSI_READ(carryreg) & carry_bit)) { 480 *upper += carry_shift; 481 TSI_WRITE(carryreg, carry_bit); 482 goto again; 483 } 484 485 return val; 486 } 487 488 static struct net_device_stats *tsi108_get_stats(struct net_device *dev) 489 { 490 unsigned long excol; 491 492 struct tsi108_prv_data *data = netdev_priv(dev); 493 spin_lock_irq(&data->misclock); 494 495 data->tmpstats.rx_packets = 496 tsi108_read_stat(data, TSI108_STAT_RXPKTS, 497 TSI108_STAT_CARRY1_RXPKTS, 498 TSI108_STAT_RXPKTS_CARRY, &data->stats.rx_packets); 499 500 data->tmpstats.tx_packets = 501 tsi108_read_stat(data, TSI108_STAT_TXPKTS, 502 TSI108_STAT_CARRY2_TXPKTS, 503 TSI108_STAT_TXPKTS_CARRY, &data->stats.tx_packets); 504 505 data->tmpstats.rx_bytes = 506 tsi108_read_stat(data, TSI108_STAT_RXBYTES, 507 TSI108_STAT_CARRY1_RXBYTES, 508 TSI108_STAT_RXBYTES_CARRY, &data->stats.rx_bytes); 509 510 data->tmpstats.tx_bytes = 511 tsi108_read_stat(data, TSI108_STAT_TXBYTES, 512 TSI108_STAT_CARRY2_TXBYTES, 513 TSI108_STAT_TXBYTES_CARRY, &data->stats.tx_bytes); 514 515 data->tmpstats.multicast = 516 tsi108_read_stat(data, TSI108_STAT_RXMCAST, 517 TSI108_STAT_CARRY1_RXMCAST, 518 TSI108_STAT_RXMCAST_CARRY, &data->stats.multicast); 519 520 excol = tsi108_read_stat(data, TSI108_STAT_TXEXCOL, 521 TSI108_STAT_CARRY2_TXEXCOL, 522 TSI108_STAT_TXEXCOL_CARRY, 523 &data->tx_coll_abort); 524 525 data->tmpstats.collisions = 526 tsi108_read_stat(data, TSI108_STAT_TXTCOL, 527 TSI108_STAT_CARRY2_TXTCOL, 528 TSI108_STAT_TXTCOL_CARRY, &data->stats.collisions); 529 530 data->tmpstats.collisions += excol; 531 532 data->tmpstats.rx_length_errors = 533 tsi108_read_stat(data, TSI108_STAT_RXLENGTH, 534 TSI108_STAT_CARRY1_RXLENGTH, 535 TSI108_STAT_RXLENGTH_CARRY, 536 &data->stats.rx_length_errors); 537 538 data->tmpstats.rx_length_errors += 539 tsi108_read_stat(data, TSI108_STAT_RXRUNT, 540 TSI108_STAT_CARRY1_RXRUNT, 541 TSI108_STAT_RXRUNT_CARRY, &data->rx_underruns); 542 543 data->tmpstats.rx_length_errors += 544 tsi108_read_stat(data, TSI108_STAT_RXJUMBO, 545 TSI108_STAT_CARRY1_RXJUMBO, 546 TSI108_STAT_RXJUMBO_CARRY, &data->rx_overruns); 547 548 data->tmpstats.rx_frame_errors = 549 tsi108_read_stat(data, TSI108_STAT_RXALIGN, 550 TSI108_STAT_CARRY1_RXALIGN, 551 TSI108_STAT_RXALIGN_CARRY, 552 &data->stats.rx_frame_errors); 553 554 data->tmpstats.rx_frame_errors += 555 tsi108_read_stat(data, TSI108_STAT_RXFCS, 556 TSI108_STAT_CARRY1_RXFCS, TSI108_STAT_RXFCS_CARRY, 557 &data->rx_fcs); 558 559 data->tmpstats.rx_frame_errors += 560 tsi108_read_stat(data, TSI108_STAT_RXFRAG, 561 TSI108_STAT_CARRY1_RXFRAG, 562 TSI108_STAT_RXFRAG_CARRY, &data->rx_short_fcs); 563 564 data->tmpstats.rx_missed_errors = 565 tsi108_read_stat(data, TSI108_STAT_RXDROP, 566 TSI108_STAT_CARRY1_RXDROP, 567 TSI108_STAT_RXDROP_CARRY, 568 &data->stats.rx_missed_errors); 569 570 /* These three are maintained by software. */ 571 data->tmpstats.rx_fifo_errors = data->stats.rx_fifo_errors; 572 data->tmpstats.rx_crc_errors = data->stats.rx_crc_errors; 573 574 data->tmpstats.tx_aborted_errors = 575 tsi108_read_stat(data, TSI108_STAT_TXEXDEF, 576 TSI108_STAT_CARRY2_TXEXDEF, 577 TSI108_STAT_TXEXDEF_CARRY, 578 &data->stats.tx_aborted_errors); 579 580 data->tmpstats.tx_aborted_errors += 581 tsi108_read_stat(data, TSI108_STAT_TXPAUSEDROP, 582 TSI108_STAT_CARRY2_TXPAUSE, 583 TSI108_STAT_TXPAUSEDROP_CARRY, 584 &data->tx_pause_drop); 585 586 data->tmpstats.tx_aborted_errors += excol; 587 588 data->tmpstats.tx_errors = data->tmpstats.tx_aborted_errors; 589 data->tmpstats.rx_errors = data->tmpstats.rx_length_errors + 590 data->tmpstats.rx_crc_errors + 591 data->tmpstats.rx_frame_errors + 592 data->tmpstats.rx_fifo_errors + data->tmpstats.rx_missed_errors; 593 594 spin_unlock_irq(&data->misclock); 595 return &data->tmpstats; 596 } 597 598 static void tsi108_restart_rx(struct tsi108_prv_data * data, struct net_device *dev) 599 { 600 TSI_WRITE(TSI108_EC_RXQ_PTRHIGH, 601 TSI108_EC_RXQ_PTRHIGH_VALID); 602 603 TSI_WRITE(TSI108_EC_RXCTRL, TSI108_EC_RXCTRL_GO 604 | TSI108_EC_RXCTRL_QUEUE0); 605 } 606 607 static void tsi108_restart_tx(struct tsi108_prv_data * data) 608 { 609 TSI_WRITE(TSI108_EC_TXQ_PTRHIGH, 610 TSI108_EC_TXQ_PTRHIGH_VALID); 611 612 TSI_WRITE(TSI108_EC_TXCTRL, TSI108_EC_TXCTRL_IDLEINT | 613 TSI108_EC_TXCTRL_GO | TSI108_EC_TXCTRL_QUEUE0); 614 } 615 616 /* txlock must be held by caller, with IRQs disabled, and 617 * with permission to re-enable them when the lock is dropped. 618 */ 619 static void tsi108_complete_tx(struct net_device *dev) 620 { 621 struct tsi108_prv_data *data = netdev_priv(dev); 622 int tx; 623 struct sk_buff *skb; 624 int release = 0; 625 626 while (!data->txfree || data->txhead != data->txtail) { 627 tx = data->txtail; 628 629 if (data->txring[tx].misc & TSI108_TX_OWN) 630 break; 631 632 skb = data->txskbs[tx]; 633 634 if (!(data->txring[tx].misc & TSI108_TX_OK)) 635 printk("%s: bad tx packet, misc %x\n", 636 dev->name, data->txring[tx].misc); 637 638 data->txtail = (data->txtail + 1) % TSI108_TXRING_LEN; 639 data->txfree++; 640 641 if (data->txring[tx].misc & TSI108_TX_EOF) { 642 dev_kfree_skb_any(skb); 643 release++; 644 } 645 } 646 647 if (release) { 648 if (is_valid_ether_addr(dev->dev_addr) && data->link_up) 649 netif_wake_queue(dev); 650 } 651 } 652 653 static int tsi108_send_packet(struct sk_buff * skb, struct net_device *dev) 654 { 655 struct tsi108_prv_data *data = netdev_priv(dev); 656 int frags = skb_shinfo(skb)->nr_frags + 1; 657 int i; 658 659 if (!data->phy_ok && net_ratelimit()) 660 printk(KERN_ERR "%s: Transmit while PHY is down!\n", dev->name); 661 662 if (!data->link_up) { 663 printk(KERN_ERR "%s: Transmit while link is down!\n", 664 dev->name); 665 netif_stop_queue(dev); 666 return NETDEV_TX_BUSY; 667 } 668 669 if (data->txfree < MAX_SKB_FRAGS + 1) { 670 netif_stop_queue(dev); 671 672 if (net_ratelimit()) 673 printk(KERN_ERR "%s: Transmit with full tx ring!\n", 674 dev->name); 675 return NETDEV_TX_BUSY; 676 } 677 678 if (data->txfree - frags < MAX_SKB_FRAGS + 1) { 679 netif_stop_queue(dev); 680 } 681 682 spin_lock_irq(&data->txlock); 683 684 for (i = 0; i < frags; i++) { 685 int misc = 0; 686 int tx = data->txhead; 687 688 /* This is done to mark every TSI108_TX_INT_FREQ tx buffers with 689 * the interrupt bit. TX descriptor-complete interrupts are 690 * enabled when the queue fills up, and masked when there is 691 * still free space. This way, when saturating the outbound 692 * link, the tx interrupts are kept to a reasonable level. 693 * When the queue is not full, reclamation of skbs still occurs 694 * as new packets are transmitted, or on a queue-empty 695 * interrupt. 696 */ 697 698 if ((tx % TSI108_TX_INT_FREQ == 0) && 699 ((TSI108_TXRING_LEN - data->txfree) >= TSI108_TX_INT_FREQ)) 700 misc = TSI108_TX_INT; 701 702 data->txskbs[tx] = skb; 703 704 if (i == 0) { 705 data->txring[tx].buf0 = dma_map_single(NULL, skb->data, 706 skb_headlen(skb), DMA_TO_DEVICE); 707 data->txring[tx].len = skb_headlen(skb); 708 misc |= TSI108_TX_SOF; 709 } else { 710 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i - 1]; 711 712 data->txring[tx].buf0 = skb_frag_dma_map(NULL, frag, 713 0, 714 skb_frag_size(frag), 715 DMA_TO_DEVICE); 716 data->txring[tx].len = skb_frag_size(frag); 717 } 718 719 if (i == frags - 1) 720 misc |= TSI108_TX_EOF; 721 722 if (netif_msg_pktdata(data)) { 723 int i; 724 printk("%s: Tx Frame contents (%d)\n", dev->name, 725 skb->len); 726 for (i = 0; i < skb->len; i++) 727 printk(" %2.2x", skb->data[i]); 728 printk(".\n"); 729 } 730 data->txring[tx].misc = misc | TSI108_TX_OWN; 731 732 data->txhead = (data->txhead + 1) % TSI108_TXRING_LEN; 733 data->txfree--; 734 } 735 736 tsi108_complete_tx(dev); 737 738 /* This must be done after the check for completed tx descriptors, 739 * so that the tail pointer is correct. 740 */ 741 742 if (!(TSI_READ(TSI108_EC_TXSTAT) & TSI108_EC_TXSTAT_QUEUE0)) 743 tsi108_restart_tx(data); 744 745 spin_unlock_irq(&data->txlock); 746 return NETDEV_TX_OK; 747 } 748 749 static int tsi108_complete_rx(struct net_device *dev, int budget) 750 { 751 struct tsi108_prv_data *data = netdev_priv(dev); 752 int done = 0; 753 754 while (data->rxfree && done != budget) { 755 int rx = data->rxtail; 756 struct sk_buff *skb; 757 758 if (data->rxring[rx].misc & TSI108_RX_OWN) 759 break; 760 761 skb = data->rxskbs[rx]; 762 data->rxtail = (data->rxtail + 1) % TSI108_RXRING_LEN; 763 data->rxfree--; 764 done++; 765 766 if (data->rxring[rx].misc & TSI108_RX_BAD) { 767 spin_lock_irq(&data->misclock); 768 769 if (data->rxring[rx].misc & TSI108_RX_CRC) 770 data->stats.rx_crc_errors++; 771 if (data->rxring[rx].misc & TSI108_RX_OVER) 772 data->stats.rx_fifo_errors++; 773 774 spin_unlock_irq(&data->misclock); 775 776 dev_kfree_skb_any(skb); 777 continue; 778 } 779 if (netif_msg_pktdata(data)) { 780 int i; 781 printk("%s: Rx Frame contents (%d)\n", 782 dev->name, data->rxring[rx].len); 783 for (i = 0; i < data->rxring[rx].len; i++) 784 printk(" %2.2x", skb->data[i]); 785 printk(".\n"); 786 } 787 788 skb_put(skb, data->rxring[rx].len); 789 skb->protocol = eth_type_trans(skb, dev); 790 netif_receive_skb(skb); 791 } 792 793 return done; 794 } 795 796 static int tsi108_refill_rx(struct net_device *dev, int budget) 797 { 798 struct tsi108_prv_data *data = netdev_priv(dev); 799 int done = 0; 800 801 while (data->rxfree != TSI108_RXRING_LEN && done != budget) { 802 int rx = data->rxhead; 803 struct sk_buff *skb; 804 805 skb = netdev_alloc_skb_ip_align(dev, TSI108_RXBUF_SIZE); 806 data->rxskbs[rx] = skb; 807 if (!skb) 808 break; 809 810 data->rxring[rx].buf0 = dma_map_single(NULL, skb->data, 811 TSI108_RX_SKB_SIZE, 812 DMA_FROM_DEVICE); 813 814 /* Sometimes the hardware sets blen to zero after packet 815 * reception, even though the manual says that it's only ever 816 * modified by the driver. 817 */ 818 819 data->rxring[rx].blen = TSI108_RX_SKB_SIZE; 820 data->rxring[rx].misc = TSI108_RX_OWN | TSI108_RX_INT; 821 822 data->rxhead = (data->rxhead + 1) % TSI108_RXRING_LEN; 823 data->rxfree++; 824 done++; 825 } 826 827 if (done != 0 && !(TSI_READ(TSI108_EC_RXSTAT) & 828 TSI108_EC_RXSTAT_QUEUE0)) 829 tsi108_restart_rx(data, dev); 830 831 return done; 832 } 833 834 static int tsi108_poll(struct napi_struct *napi, int budget) 835 { 836 struct tsi108_prv_data *data = container_of(napi, struct tsi108_prv_data, napi); 837 struct net_device *dev = data->dev; 838 u32 estat = TSI_READ(TSI108_EC_RXESTAT); 839 u32 intstat = TSI_READ(TSI108_EC_INTSTAT); 840 int num_received = 0, num_filled = 0; 841 842 intstat &= TSI108_INT_RXQUEUE0 | TSI108_INT_RXTHRESH | 843 TSI108_INT_RXOVERRUN | TSI108_INT_RXERROR | TSI108_INT_RXWAIT; 844 845 TSI_WRITE(TSI108_EC_RXESTAT, estat); 846 TSI_WRITE(TSI108_EC_INTSTAT, intstat); 847 848 if (data->rxpending || (estat & TSI108_EC_RXESTAT_Q0_DESCINT)) 849 num_received = tsi108_complete_rx(dev, budget); 850 851 /* This should normally fill no more slots than the number of 852 * packets received in tsi108_complete_rx(). The exception 853 * is when we previously ran out of memory for RX SKBs. In that 854 * case, it's helpful to obey the budget, not only so that the 855 * CPU isn't hogged, but so that memory (which may still be low) 856 * is not hogged by one device. 857 * 858 * A work unit is considered to be two SKBs to allow us to catch 859 * up when the ring has shrunk due to out-of-memory but we're 860 * still removing the full budget's worth of packets each time. 861 */ 862 863 if (data->rxfree < TSI108_RXRING_LEN) 864 num_filled = tsi108_refill_rx(dev, budget * 2); 865 866 if (intstat & TSI108_INT_RXERROR) { 867 u32 err = TSI_READ(TSI108_EC_RXERR); 868 TSI_WRITE(TSI108_EC_RXERR, err); 869 870 if (err) { 871 if (net_ratelimit()) 872 printk(KERN_DEBUG "%s: RX error %x\n", 873 dev->name, err); 874 875 if (!(TSI_READ(TSI108_EC_RXSTAT) & 876 TSI108_EC_RXSTAT_QUEUE0)) 877 tsi108_restart_rx(data, dev); 878 } 879 } 880 881 if (intstat & TSI108_INT_RXOVERRUN) { 882 spin_lock_irq(&data->misclock); 883 data->stats.rx_fifo_errors++; 884 spin_unlock_irq(&data->misclock); 885 } 886 887 if (num_received < budget) { 888 data->rxpending = 0; 889 napi_complete(napi); 890 891 TSI_WRITE(TSI108_EC_INTMASK, 892 TSI_READ(TSI108_EC_INTMASK) 893 & ~(TSI108_INT_RXQUEUE0 894 | TSI108_INT_RXTHRESH | 895 TSI108_INT_RXOVERRUN | 896 TSI108_INT_RXERROR | 897 TSI108_INT_RXWAIT)); 898 } else { 899 data->rxpending = 1; 900 } 901 902 return num_received; 903 } 904 905 static void tsi108_rx_int(struct net_device *dev) 906 { 907 struct tsi108_prv_data *data = netdev_priv(dev); 908 909 /* A race could cause dev to already be scheduled, so it's not an 910 * error if that happens (and interrupts shouldn't be re-masked, 911 * because that can cause harmful races, if poll has already 912 * unmasked them but not cleared LINK_STATE_SCHED). 913 * 914 * This can happen if this code races with tsi108_poll(), which masks 915 * the interrupts after tsi108_irq_one() read the mask, but before 916 * napi_schedule is called. It could also happen due to calls 917 * from tsi108_check_rxring(). 918 */ 919 920 if (napi_schedule_prep(&data->napi)) { 921 /* Mask, rather than ack, the receive interrupts. The ack 922 * will happen in tsi108_poll(). 923 */ 924 925 TSI_WRITE(TSI108_EC_INTMASK, 926 TSI_READ(TSI108_EC_INTMASK) | 927 TSI108_INT_RXQUEUE0 928 | TSI108_INT_RXTHRESH | 929 TSI108_INT_RXOVERRUN | TSI108_INT_RXERROR | 930 TSI108_INT_RXWAIT); 931 __napi_schedule(&data->napi); 932 } else { 933 if (!netif_running(dev)) { 934 /* This can happen if an interrupt occurs while the 935 * interface is being brought down, as the START 936 * bit is cleared before the stop function is called. 937 * 938 * In this case, the interrupts must be masked, or 939 * they will continue indefinitely. 940 * 941 * There's a race here if the interface is brought down 942 * and then up in rapid succession, as the device could 943 * be made running after the above check and before 944 * the masking below. This will only happen if the IRQ 945 * thread has a lower priority than the task brining 946 * up the interface. Fixing this race would likely 947 * require changes in generic code. 948 */ 949 950 TSI_WRITE(TSI108_EC_INTMASK, 951 TSI_READ 952 (TSI108_EC_INTMASK) | 953 TSI108_INT_RXQUEUE0 | 954 TSI108_INT_RXTHRESH | 955 TSI108_INT_RXOVERRUN | 956 TSI108_INT_RXERROR | 957 TSI108_INT_RXWAIT); 958 } 959 } 960 } 961 962 /* If the RX ring has run out of memory, try periodically 963 * to allocate some more, as otherwise poll would never 964 * get called (apart from the initial end-of-queue condition). 965 * 966 * This is called once per second (by default) from the thread. 967 */ 968 969 static void tsi108_check_rxring(struct net_device *dev) 970 { 971 struct tsi108_prv_data *data = netdev_priv(dev); 972 973 /* A poll is scheduled, as opposed to caling tsi108_refill_rx 974 * directly, so as to keep the receive path single-threaded 975 * (and thus not needing a lock). 976 */ 977 978 if (netif_running(dev) && data->rxfree < TSI108_RXRING_LEN / 4) 979 tsi108_rx_int(dev); 980 } 981 982 static void tsi108_tx_int(struct net_device *dev) 983 { 984 struct tsi108_prv_data *data = netdev_priv(dev); 985 u32 estat = TSI_READ(TSI108_EC_TXESTAT); 986 987 TSI_WRITE(TSI108_EC_TXESTAT, estat); 988 TSI_WRITE(TSI108_EC_INTSTAT, TSI108_INT_TXQUEUE0 | 989 TSI108_INT_TXIDLE | TSI108_INT_TXERROR); 990 if (estat & TSI108_EC_TXESTAT_Q0_ERR) { 991 u32 err = TSI_READ(TSI108_EC_TXERR); 992 TSI_WRITE(TSI108_EC_TXERR, err); 993 994 if (err && net_ratelimit()) 995 printk(KERN_ERR "%s: TX error %x\n", dev->name, err); 996 } 997 998 if (estat & (TSI108_EC_TXESTAT_Q0_DESCINT | TSI108_EC_TXESTAT_Q0_EOQ)) { 999 spin_lock(&data->txlock); 1000 tsi108_complete_tx(dev); 1001 spin_unlock(&data->txlock); 1002 } 1003 } 1004 1005 1006 static irqreturn_t tsi108_irq(int irq, void *dev_id) 1007 { 1008 struct net_device *dev = dev_id; 1009 struct tsi108_prv_data *data = netdev_priv(dev); 1010 u32 stat = TSI_READ(TSI108_EC_INTSTAT); 1011 1012 if (!(stat & TSI108_INT_ANY)) 1013 return IRQ_NONE; /* Not our interrupt */ 1014 1015 stat &= ~TSI_READ(TSI108_EC_INTMASK); 1016 1017 if (stat & (TSI108_INT_TXQUEUE0 | TSI108_INT_TXIDLE | 1018 TSI108_INT_TXERROR)) 1019 tsi108_tx_int(dev); 1020 if (stat & (TSI108_INT_RXQUEUE0 | TSI108_INT_RXTHRESH | 1021 TSI108_INT_RXWAIT | TSI108_INT_RXOVERRUN | 1022 TSI108_INT_RXERROR)) 1023 tsi108_rx_int(dev); 1024 1025 if (stat & TSI108_INT_SFN) { 1026 if (net_ratelimit()) 1027 printk(KERN_DEBUG "%s: SFN error\n", dev->name); 1028 TSI_WRITE(TSI108_EC_INTSTAT, TSI108_INT_SFN); 1029 } 1030 1031 if (stat & TSI108_INT_STATCARRY) { 1032 tsi108_stat_carry(dev); 1033 TSI_WRITE(TSI108_EC_INTSTAT, TSI108_INT_STATCARRY); 1034 } 1035 1036 return IRQ_HANDLED; 1037 } 1038 1039 static void tsi108_stop_ethernet(struct net_device *dev) 1040 { 1041 struct tsi108_prv_data *data = netdev_priv(dev); 1042 int i = 1000; 1043 /* Disable all TX and RX queues ... */ 1044 TSI_WRITE(TSI108_EC_TXCTRL, 0); 1045 TSI_WRITE(TSI108_EC_RXCTRL, 0); 1046 1047 /* ...and wait for them to become idle */ 1048 while(i--) { 1049 if(!(TSI_READ(TSI108_EC_TXSTAT) & TSI108_EC_TXSTAT_ACTIVE)) 1050 break; 1051 udelay(10); 1052 } 1053 i = 1000; 1054 while(i--){ 1055 if(!(TSI_READ(TSI108_EC_RXSTAT) & TSI108_EC_RXSTAT_ACTIVE)) 1056 return; 1057 udelay(10); 1058 } 1059 printk(KERN_ERR "%s function time out\n", __func__); 1060 } 1061 1062 static void tsi108_reset_ether(struct tsi108_prv_data * data) 1063 { 1064 TSI_WRITE(TSI108_MAC_CFG1, TSI108_MAC_CFG1_SOFTRST); 1065 udelay(100); 1066 TSI_WRITE(TSI108_MAC_CFG1, 0); 1067 1068 TSI_WRITE(TSI108_EC_PORTCTRL, TSI108_EC_PORTCTRL_STATRST); 1069 udelay(100); 1070 TSI_WRITE(TSI108_EC_PORTCTRL, 1071 TSI_READ(TSI108_EC_PORTCTRL) & 1072 ~TSI108_EC_PORTCTRL_STATRST); 1073 1074 TSI_WRITE(TSI108_EC_TXCFG, TSI108_EC_TXCFG_RST); 1075 udelay(100); 1076 TSI_WRITE(TSI108_EC_TXCFG, 1077 TSI_READ(TSI108_EC_TXCFG) & 1078 ~TSI108_EC_TXCFG_RST); 1079 1080 TSI_WRITE(TSI108_EC_RXCFG, TSI108_EC_RXCFG_RST); 1081 udelay(100); 1082 TSI_WRITE(TSI108_EC_RXCFG, 1083 TSI_READ(TSI108_EC_RXCFG) & 1084 ~TSI108_EC_RXCFG_RST); 1085 1086 TSI_WRITE(TSI108_MAC_MII_MGMT_CFG, 1087 TSI_READ(TSI108_MAC_MII_MGMT_CFG) | 1088 TSI108_MAC_MII_MGMT_RST); 1089 udelay(100); 1090 TSI_WRITE(TSI108_MAC_MII_MGMT_CFG, 1091 (TSI_READ(TSI108_MAC_MII_MGMT_CFG) & 1092 ~(TSI108_MAC_MII_MGMT_RST | 1093 TSI108_MAC_MII_MGMT_CLK)) | 0x07); 1094 } 1095 1096 static int tsi108_get_mac(struct net_device *dev) 1097 { 1098 struct tsi108_prv_data *data = netdev_priv(dev); 1099 u32 word1 = TSI_READ(TSI108_MAC_ADDR1); 1100 u32 word2 = TSI_READ(TSI108_MAC_ADDR2); 1101 1102 /* Note that the octets are reversed from what the manual says, 1103 * producing an even weirder ordering... 1104 */ 1105 if (word2 == 0 && word1 == 0) { 1106 dev->dev_addr[0] = 0x00; 1107 dev->dev_addr[1] = 0x06; 1108 dev->dev_addr[2] = 0xd2; 1109 dev->dev_addr[3] = 0x00; 1110 dev->dev_addr[4] = 0x00; 1111 if (0x8 == data->phy) 1112 dev->dev_addr[5] = 0x01; 1113 else 1114 dev->dev_addr[5] = 0x02; 1115 1116 word2 = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 24); 1117 1118 word1 = (dev->dev_addr[2] << 0) | (dev->dev_addr[3] << 8) | 1119 (dev->dev_addr[4] << 16) | (dev->dev_addr[5] << 24); 1120 1121 TSI_WRITE(TSI108_MAC_ADDR1, word1); 1122 TSI_WRITE(TSI108_MAC_ADDR2, word2); 1123 } else { 1124 dev->dev_addr[0] = (word2 >> 16) & 0xff; 1125 dev->dev_addr[1] = (word2 >> 24) & 0xff; 1126 dev->dev_addr[2] = (word1 >> 0) & 0xff; 1127 dev->dev_addr[3] = (word1 >> 8) & 0xff; 1128 dev->dev_addr[4] = (word1 >> 16) & 0xff; 1129 dev->dev_addr[5] = (word1 >> 24) & 0xff; 1130 } 1131 1132 if (!is_valid_ether_addr(dev->dev_addr)) { 1133 printk(KERN_ERR 1134 "%s: Invalid MAC address. word1: %08x, word2: %08x\n", 1135 dev->name, word1, word2); 1136 return -EINVAL; 1137 } 1138 1139 return 0; 1140 } 1141 1142 static int tsi108_set_mac(struct net_device *dev, void *addr) 1143 { 1144 struct tsi108_prv_data *data = netdev_priv(dev); 1145 u32 word1, word2; 1146 int i; 1147 1148 if (!is_valid_ether_addr(addr)) 1149 return -EADDRNOTAVAIL; 1150 1151 for (i = 0; i < 6; i++) 1152 /* +2 is for the offset of the HW addr type */ 1153 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2]; 1154 1155 word2 = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 24); 1156 1157 word1 = (dev->dev_addr[2] << 0) | (dev->dev_addr[3] << 8) | 1158 (dev->dev_addr[4] << 16) | (dev->dev_addr[5] << 24); 1159 1160 spin_lock_irq(&data->misclock); 1161 TSI_WRITE(TSI108_MAC_ADDR1, word1); 1162 TSI_WRITE(TSI108_MAC_ADDR2, word2); 1163 spin_lock(&data->txlock); 1164 1165 if (data->txfree && data->link_up) 1166 netif_wake_queue(dev); 1167 1168 spin_unlock(&data->txlock); 1169 spin_unlock_irq(&data->misclock); 1170 return 0; 1171 } 1172 1173 /* Protected by dev->xmit_lock. */ 1174 static void tsi108_set_rx_mode(struct net_device *dev) 1175 { 1176 struct tsi108_prv_data *data = netdev_priv(dev); 1177 u32 rxcfg = TSI_READ(TSI108_EC_RXCFG); 1178 1179 if (dev->flags & IFF_PROMISC) { 1180 rxcfg &= ~(TSI108_EC_RXCFG_UC_HASH | TSI108_EC_RXCFG_MC_HASH); 1181 rxcfg |= TSI108_EC_RXCFG_UFE | TSI108_EC_RXCFG_MFE; 1182 goto out; 1183 } 1184 1185 rxcfg &= ~(TSI108_EC_RXCFG_UFE | TSI108_EC_RXCFG_MFE); 1186 1187 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) { 1188 int i; 1189 struct netdev_hw_addr *ha; 1190 rxcfg |= TSI108_EC_RXCFG_MFE | TSI108_EC_RXCFG_MC_HASH; 1191 1192 memset(data->mc_hash, 0, sizeof(data->mc_hash)); 1193 1194 netdev_for_each_mc_addr(ha, dev) { 1195 u32 hash, crc; 1196 1197 crc = ether_crc(6, ha->addr); 1198 hash = crc >> 23; 1199 __set_bit(hash, &data->mc_hash[0]); 1200 } 1201 1202 TSI_WRITE(TSI108_EC_HASHADDR, 1203 TSI108_EC_HASHADDR_AUTOINC | 1204 TSI108_EC_HASHADDR_MCAST); 1205 1206 for (i = 0; i < 16; i++) { 1207 /* The manual says that the hardware may drop 1208 * back-to-back writes to the data register. 1209 */ 1210 udelay(1); 1211 TSI_WRITE(TSI108_EC_HASHDATA, 1212 data->mc_hash[i]); 1213 } 1214 } 1215 1216 out: 1217 TSI_WRITE(TSI108_EC_RXCFG, rxcfg); 1218 } 1219 1220 static void tsi108_init_phy(struct net_device *dev) 1221 { 1222 struct tsi108_prv_data *data = netdev_priv(dev); 1223 u32 i = 0; 1224 u16 phyval = 0; 1225 unsigned long flags; 1226 1227 spin_lock_irqsave(&phy_lock, flags); 1228 1229 tsi108_write_mii(data, MII_BMCR, BMCR_RESET); 1230 while (--i) { 1231 if(!(tsi108_read_mii(data, MII_BMCR) & BMCR_RESET)) 1232 break; 1233 udelay(10); 1234 } 1235 if (i == 0) 1236 printk(KERN_ERR "%s function time out\n", __func__); 1237 1238 if (data->phy_type == TSI108_PHY_BCM54XX) { 1239 tsi108_write_mii(data, 0x09, 0x0300); 1240 tsi108_write_mii(data, 0x10, 0x1020); 1241 tsi108_write_mii(data, 0x1c, 0x8c00); 1242 } 1243 1244 tsi108_write_mii(data, 1245 MII_BMCR, 1246 BMCR_ANENABLE | BMCR_ANRESTART); 1247 while (tsi108_read_mii(data, MII_BMCR) & BMCR_ANRESTART) 1248 cpu_relax(); 1249 1250 /* Set G/MII mode and receive clock select in TBI control #2. The 1251 * second port won't work if this isn't done, even though we don't 1252 * use TBI mode. 1253 */ 1254 1255 tsi108_write_tbi(data, 0x11, 0x30); 1256 1257 /* FIXME: It seems to take more than 2 back-to-back reads to the 1258 * PHY_STAT register before the link up status bit is set. 1259 */ 1260 1261 data->link_up = 0; 1262 1263 while (!((phyval = tsi108_read_mii(data, MII_BMSR)) & 1264 BMSR_LSTATUS)) { 1265 if (i++ > (MII_READ_DELAY / 10)) { 1266 break; 1267 } 1268 spin_unlock_irqrestore(&phy_lock, flags); 1269 msleep(10); 1270 spin_lock_irqsave(&phy_lock, flags); 1271 } 1272 1273 data->mii_if.supports_gmii = mii_check_gmii_support(&data->mii_if); 1274 printk(KERN_DEBUG "PHY_STAT reg contains %08x\n", phyval); 1275 data->phy_ok = 1; 1276 data->init_media = 1; 1277 spin_unlock_irqrestore(&phy_lock, flags); 1278 } 1279 1280 static void tsi108_kill_phy(struct net_device *dev) 1281 { 1282 struct tsi108_prv_data *data = netdev_priv(dev); 1283 unsigned long flags; 1284 1285 spin_lock_irqsave(&phy_lock, flags); 1286 tsi108_write_mii(data, MII_BMCR, BMCR_PDOWN); 1287 data->phy_ok = 0; 1288 spin_unlock_irqrestore(&phy_lock, flags); 1289 } 1290 1291 static int tsi108_open(struct net_device *dev) 1292 { 1293 int i; 1294 struct tsi108_prv_data *data = netdev_priv(dev); 1295 unsigned int rxring_size = TSI108_RXRING_LEN * sizeof(rx_desc); 1296 unsigned int txring_size = TSI108_TXRING_LEN * sizeof(tx_desc); 1297 1298 i = request_irq(data->irq_num, tsi108_irq, 0, dev->name, dev); 1299 if (i != 0) { 1300 printk(KERN_ERR "tsi108_eth%d: Could not allocate IRQ%d.\n", 1301 data->id, data->irq_num); 1302 return i; 1303 } else { 1304 dev->irq = data->irq_num; 1305 printk(KERN_NOTICE 1306 "tsi108_open : Port %d Assigned IRQ %d to %s\n", 1307 data->id, dev->irq, dev->name); 1308 } 1309 1310 data->rxring = dma_zalloc_coherent(NULL, rxring_size, &data->rxdma, 1311 GFP_KERNEL); 1312 if (!data->rxring) 1313 return -ENOMEM; 1314 1315 data->txring = dma_zalloc_coherent(NULL, txring_size, &data->txdma, 1316 GFP_KERNEL); 1317 if (!data->txring) { 1318 pci_free_consistent(0, rxring_size, data->rxring, data->rxdma); 1319 return -ENOMEM; 1320 } 1321 1322 for (i = 0; i < TSI108_RXRING_LEN; i++) { 1323 data->rxring[i].next0 = data->rxdma + (i + 1) * sizeof(rx_desc); 1324 data->rxring[i].blen = TSI108_RXBUF_SIZE; 1325 data->rxring[i].vlan = 0; 1326 } 1327 1328 data->rxring[TSI108_RXRING_LEN - 1].next0 = data->rxdma; 1329 1330 data->rxtail = 0; 1331 data->rxhead = 0; 1332 1333 for (i = 0; i < TSI108_RXRING_LEN; i++) { 1334 struct sk_buff *skb; 1335 1336 skb = netdev_alloc_skb_ip_align(dev, TSI108_RXBUF_SIZE); 1337 if (!skb) { 1338 /* Bah. No memory for now, but maybe we'll get 1339 * some more later. 1340 * For now, we'll live with the smaller ring. 1341 */ 1342 printk(KERN_WARNING 1343 "%s: Could only allocate %d receive skb(s).\n", 1344 dev->name, i); 1345 data->rxhead = i; 1346 break; 1347 } 1348 1349 data->rxskbs[i] = skb; 1350 data->rxring[i].buf0 = virt_to_phys(data->rxskbs[i]->data); 1351 data->rxring[i].misc = TSI108_RX_OWN | TSI108_RX_INT; 1352 } 1353 1354 data->rxfree = i; 1355 TSI_WRITE(TSI108_EC_RXQ_PTRLOW, data->rxdma); 1356 1357 for (i = 0; i < TSI108_TXRING_LEN; i++) { 1358 data->txring[i].next0 = data->txdma + (i + 1) * sizeof(tx_desc); 1359 data->txring[i].misc = 0; 1360 } 1361 1362 data->txring[TSI108_TXRING_LEN - 1].next0 = data->txdma; 1363 data->txtail = 0; 1364 data->txhead = 0; 1365 data->txfree = TSI108_TXRING_LEN; 1366 TSI_WRITE(TSI108_EC_TXQ_PTRLOW, data->txdma); 1367 tsi108_init_phy(dev); 1368 1369 napi_enable(&data->napi); 1370 1371 setup_timer(&data->timer, tsi108_timed_checker, (unsigned long)dev); 1372 mod_timer(&data->timer, jiffies + 1); 1373 1374 tsi108_restart_rx(data, dev); 1375 1376 TSI_WRITE(TSI108_EC_INTSTAT, ~0); 1377 1378 TSI_WRITE(TSI108_EC_INTMASK, 1379 ~(TSI108_INT_TXQUEUE0 | TSI108_INT_RXERROR | 1380 TSI108_INT_RXTHRESH | TSI108_INT_RXQUEUE0 | 1381 TSI108_INT_RXOVERRUN | TSI108_INT_RXWAIT | 1382 TSI108_INT_SFN | TSI108_INT_STATCARRY)); 1383 1384 TSI_WRITE(TSI108_MAC_CFG1, 1385 TSI108_MAC_CFG1_RXEN | TSI108_MAC_CFG1_TXEN); 1386 netif_start_queue(dev); 1387 return 0; 1388 } 1389 1390 static int tsi108_close(struct net_device *dev) 1391 { 1392 struct tsi108_prv_data *data = netdev_priv(dev); 1393 1394 netif_stop_queue(dev); 1395 napi_disable(&data->napi); 1396 1397 del_timer_sync(&data->timer); 1398 1399 tsi108_stop_ethernet(dev); 1400 tsi108_kill_phy(dev); 1401 TSI_WRITE(TSI108_EC_INTMASK, ~0); 1402 TSI_WRITE(TSI108_MAC_CFG1, 0); 1403 1404 /* Check for any pending TX packets, and drop them. */ 1405 1406 while (!data->txfree || data->txhead != data->txtail) { 1407 int tx = data->txtail; 1408 struct sk_buff *skb; 1409 skb = data->txskbs[tx]; 1410 data->txtail = (data->txtail + 1) % TSI108_TXRING_LEN; 1411 data->txfree++; 1412 dev_kfree_skb(skb); 1413 } 1414 1415 free_irq(data->irq_num, dev); 1416 1417 /* Discard the RX ring. */ 1418 1419 while (data->rxfree) { 1420 int rx = data->rxtail; 1421 struct sk_buff *skb; 1422 1423 skb = data->rxskbs[rx]; 1424 data->rxtail = (data->rxtail + 1) % TSI108_RXRING_LEN; 1425 data->rxfree--; 1426 dev_kfree_skb(skb); 1427 } 1428 1429 dma_free_coherent(0, 1430 TSI108_RXRING_LEN * sizeof(rx_desc), 1431 data->rxring, data->rxdma); 1432 dma_free_coherent(0, 1433 TSI108_TXRING_LEN * sizeof(tx_desc), 1434 data->txring, data->txdma); 1435 1436 return 0; 1437 } 1438 1439 static void tsi108_init_mac(struct net_device *dev) 1440 { 1441 struct tsi108_prv_data *data = netdev_priv(dev); 1442 1443 TSI_WRITE(TSI108_MAC_CFG2, TSI108_MAC_CFG2_DFLT_PREAMBLE | 1444 TSI108_MAC_CFG2_PADCRC); 1445 1446 TSI_WRITE(TSI108_EC_TXTHRESH, 1447 (192 << TSI108_EC_TXTHRESH_STARTFILL) | 1448 (192 << TSI108_EC_TXTHRESH_STOPFILL)); 1449 1450 TSI_WRITE(TSI108_STAT_CARRYMASK1, 1451 ~(TSI108_STAT_CARRY1_RXBYTES | 1452 TSI108_STAT_CARRY1_RXPKTS | 1453 TSI108_STAT_CARRY1_RXFCS | 1454 TSI108_STAT_CARRY1_RXMCAST | 1455 TSI108_STAT_CARRY1_RXALIGN | 1456 TSI108_STAT_CARRY1_RXLENGTH | 1457 TSI108_STAT_CARRY1_RXRUNT | 1458 TSI108_STAT_CARRY1_RXJUMBO | 1459 TSI108_STAT_CARRY1_RXFRAG | 1460 TSI108_STAT_CARRY1_RXJABBER | 1461 TSI108_STAT_CARRY1_RXDROP)); 1462 1463 TSI_WRITE(TSI108_STAT_CARRYMASK2, 1464 ~(TSI108_STAT_CARRY2_TXBYTES | 1465 TSI108_STAT_CARRY2_TXPKTS | 1466 TSI108_STAT_CARRY2_TXEXDEF | 1467 TSI108_STAT_CARRY2_TXEXCOL | 1468 TSI108_STAT_CARRY2_TXTCOL | 1469 TSI108_STAT_CARRY2_TXPAUSE)); 1470 1471 TSI_WRITE(TSI108_EC_PORTCTRL, TSI108_EC_PORTCTRL_STATEN); 1472 TSI_WRITE(TSI108_MAC_CFG1, 0); 1473 1474 TSI_WRITE(TSI108_EC_RXCFG, 1475 TSI108_EC_RXCFG_SE | TSI108_EC_RXCFG_BFE); 1476 1477 TSI_WRITE(TSI108_EC_TXQ_CFG, TSI108_EC_TXQ_CFG_DESC_INT | 1478 TSI108_EC_TXQ_CFG_EOQ_OWN_INT | 1479 TSI108_EC_TXQ_CFG_WSWP | (TSI108_PBM_PORT << 1480 TSI108_EC_TXQ_CFG_SFNPORT)); 1481 1482 TSI_WRITE(TSI108_EC_RXQ_CFG, TSI108_EC_RXQ_CFG_DESC_INT | 1483 TSI108_EC_RXQ_CFG_EOQ_OWN_INT | 1484 TSI108_EC_RXQ_CFG_WSWP | (TSI108_PBM_PORT << 1485 TSI108_EC_RXQ_CFG_SFNPORT)); 1486 1487 TSI_WRITE(TSI108_EC_TXQ_BUFCFG, 1488 TSI108_EC_TXQ_BUFCFG_BURST256 | 1489 TSI108_EC_TXQ_BUFCFG_BSWP | (TSI108_PBM_PORT << 1490 TSI108_EC_TXQ_BUFCFG_SFNPORT)); 1491 1492 TSI_WRITE(TSI108_EC_RXQ_BUFCFG, 1493 TSI108_EC_RXQ_BUFCFG_BURST256 | 1494 TSI108_EC_RXQ_BUFCFG_BSWP | (TSI108_PBM_PORT << 1495 TSI108_EC_RXQ_BUFCFG_SFNPORT)); 1496 1497 TSI_WRITE(TSI108_EC_INTMASK, ~0); 1498 } 1499 1500 static int tsi108_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1501 { 1502 struct tsi108_prv_data *data = netdev_priv(dev); 1503 unsigned long flags; 1504 int rc; 1505 1506 spin_lock_irqsave(&data->txlock, flags); 1507 rc = mii_ethtool_gset(&data->mii_if, cmd); 1508 spin_unlock_irqrestore(&data->txlock, flags); 1509 1510 return rc; 1511 } 1512 1513 static int tsi108_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1514 { 1515 struct tsi108_prv_data *data = netdev_priv(dev); 1516 unsigned long flags; 1517 int rc; 1518 1519 spin_lock_irqsave(&data->txlock, flags); 1520 rc = mii_ethtool_sset(&data->mii_if, cmd); 1521 spin_unlock_irqrestore(&data->txlock, flags); 1522 1523 return rc; 1524 } 1525 1526 static int tsi108_do_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1527 { 1528 struct tsi108_prv_data *data = netdev_priv(dev); 1529 if (!netif_running(dev)) 1530 return -EINVAL; 1531 return generic_mii_ioctl(&data->mii_if, if_mii(rq), cmd, NULL); 1532 } 1533 1534 static const struct ethtool_ops tsi108_ethtool_ops = { 1535 .get_link = ethtool_op_get_link, 1536 .get_settings = tsi108_get_settings, 1537 .set_settings = tsi108_set_settings, 1538 }; 1539 1540 static const struct net_device_ops tsi108_netdev_ops = { 1541 .ndo_open = tsi108_open, 1542 .ndo_stop = tsi108_close, 1543 .ndo_start_xmit = tsi108_send_packet, 1544 .ndo_set_rx_mode = tsi108_set_rx_mode, 1545 .ndo_get_stats = tsi108_get_stats, 1546 .ndo_do_ioctl = tsi108_do_ioctl, 1547 .ndo_set_mac_address = tsi108_set_mac, 1548 .ndo_validate_addr = eth_validate_addr, 1549 .ndo_change_mtu = eth_change_mtu, 1550 }; 1551 1552 static int 1553 tsi108_init_one(struct platform_device *pdev) 1554 { 1555 struct net_device *dev = NULL; 1556 struct tsi108_prv_data *data = NULL; 1557 hw_info *einfo; 1558 int err = 0; 1559 1560 einfo = dev_get_platdata(&pdev->dev); 1561 1562 if (NULL == einfo) { 1563 printk(KERN_ERR "tsi-eth %d: Missing additional data!\n", 1564 pdev->id); 1565 return -ENODEV; 1566 } 1567 1568 /* Create an ethernet device instance */ 1569 1570 dev = alloc_etherdev(sizeof(struct tsi108_prv_data)); 1571 if (!dev) 1572 return -ENOMEM; 1573 1574 printk("tsi108_eth%d: probe...\n", pdev->id); 1575 data = netdev_priv(dev); 1576 data->dev = dev; 1577 1578 pr_debug("tsi108_eth%d:regs:phyresgs:phy:irq_num=0x%x:0x%x:0x%x:0x%x\n", 1579 pdev->id, einfo->regs, einfo->phyregs, 1580 einfo->phy, einfo->irq_num); 1581 1582 data->regs = ioremap(einfo->regs, 0x400); 1583 if (NULL == data->regs) { 1584 err = -ENOMEM; 1585 goto regs_fail; 1586 } 1587 1588 data->phyregs = ioremap(einfo->phyregs, 0x400); 1589 if (NULL == data->phyregs) { 1590 err = -ENOMEM; 1591 goto phyregs_fail; 1592 } 1593 /* MII setup */ 1594 data->mii_if.dev = dev; 1595 data->mii_if.mdio_read = tsi108_mdio_read; 1596 data->mii_if.mdio_write = tsi108_mdio_write; 1597 data->mii_if.phy_id = einfo->phy; 1598 data->mii_if.phy_id_mask = 0x1f; 1599 data->mii_if.reg_num_mask = 0x1f; 1600 1601 data->phy = einfo->phy; 1602 data->phy_type = einfo->phy_type; 1603 data->irq_num = einfo->irq_num; 1604 data->id = pdev->id; 1605 netif_napi_add(dev, &data->napi, tsi108_poll, 64); 1606 dev->netdev_ops = &tsi108_netdev_ops; 1607 dev->ethtool_ops = &tsi108_ethtool_ops; 1608 1609 /* Apparently, the Linux networking code won't use scatter-gather 1610 * if the hardware doesn't do checksums. However, it's faster 1611 * to checksum in place and use SG, as (among other reasons) 1612 * the cache won't be dirtied (which then has to be flushed 1613 * before DMA). The checksumming is done by the driver (via 1614 * a new function skb_csum_dev() in net/core/skbuff.c). 1615 */ 1616 1617 dev->features = NETIF_F_HIGHDMA; 1618 1619 spin_lock_init(&data->txlock); 1620 spin_lock_init(&data->misclock); 1621 1622 tsi108_reset_ether(data); 1623 tsi108_kill_phy(dev); 1624 1625 if ((err = tsi108_get_mac(dev)) != 0) { 1626 printk(KERN_ERR "%s: Invalid MAC address. Please correct.\n", 1627 dev->name); 1628 goto register_fail; 1629 } 1630 1631 tsi108_init_mac(dev); 1632 err = register_netdev(dev); 1633 if (err) { 1634 printk(KERN_ERR "%s: Cannot register net device, aborting.\n", 1635 dev->name); 1636 goto register_fail; 1637 } 1638 1639 platform_set_drvdata(pdev, dev); 1640 printk(KERN_INFO "%s: Tsi108 Gigabit Ethernet, MAC: %pM\n", 1641 dev->name, dev->dev_addr); 1642 #ifdef DEBUG 1643 data->msg_enable = DEBUG; 1644 dump_eth_one(dev); 1645 #endif 1646 1647 return 0; 1648 1649 register_fail: 1650 iounmap(data->phyregs); 1651 1652 phyregs_fail: 1653 iounmap(data->regs); 1654 1655 regs_fail: 1656 free_netdev(dev); 1657 return err; 1658 } 1659 1660 /* There's no way to either get interrupts from the PHY when 1661 * something changes, or to have the Tsi108 automatically communicate 1662 * with the PHY to reconfigure itself. 1663 * 1664 * Thus, we have to do it using a timer. 1665 */ 1666 1667 static void tsi108_timed_checker(unsigned long dev_ptr) 1668 { 1669 struct net_device *dev = (struct net_device *)dev_ptr; 1670 struct tsi108_prv_data *data = netdev_priv(dev); 1671 1672 tsi108_check_phy(dev); 1673 tsi108_check_rxring(dev); 1674 mod_timer(&data->timer, jiffies + CHECK_PHY_INTERVAL); 1675 } 1676 1677 static int tsi108_ether_remove(struct platform_device *pdev) 1678 { 1679 struct net_device *dev = platform_get_drvdata(pdev); 1680 struct tsi108_prv_data *priv = netdev_priv(dev); 1681 1682 unregister_netdev(dev); 1683 tsi108_stop_ethernet(dev); 1684 iounmap(priv->regs); 1685 iounmap(priv->phyregs); 1686 free_netdev(dev); 1687 1688 return 0; 1689 } 1690 module_platform_driver(tsi_eth_driver); 1691 1692 MODULE_AUTHOR("Tundra Semiconductor Corporation"); 1693 MODULE_DESCRIPTION("Tsi108 Gigabit Ethernet driver"); 1694 MODULE_LICENSE("GPL"); 1695 MODULE_ALIAS("platform:tsi-ethernet"); 1696