1 /*
2  * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
3  *
4  * Based on skelton.c by Donald Becker.
5  *
6  * This driver is a replacement of older and less maintained version.
7  * This is a header of the older version:
8  *	-----<snip>-----
9  *	Copyright 2001 MontaVista Software Inc.
10  *	Author: MontaVista Software, Inc.
11  *		ahennessy@mvista.com
12  *	Copyright (C) 2000-2001 Toshiba Corporation
13  *	static const char *version =
14  *		"tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n";
15  *	-----<snip>-----
16  *
17  * This file is subject to the terms and conditions of the GNU General Public
18  * License.  See the file "COPYING" in the main directory of this archive
19  * for more details.
20  *
21  * (C) Copyright TOSHIBA CORPORATION 2004-2005
22  * All Rights Reserved.
23  */
24 
25 #define DRV_VERSION	"1.39"
26 static const char version[] = "tc35815.c:v" DRV_VERSION "\n";
27 #define MODNAME			"tc35815"
28 
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/types.h>
32 #include <linux/fcntl.h>
33 #include <linux/interrupt.h>
34 #include <linux/ioport.h>
35 #include <linux/in.h>
36 #include <linux/if_vlan.h>
37 #include <linux/slab.h>
38 #include <linux/string.h>
39 #include <linux/spinlock.h>
40 #include <linux/errno.h>
41 #include <linux/netdevice.h>
42 #include <linux/etherdevice.h>
43 #include <linux/skbuff.h>
44 #include <linux/delay.h>
45 #include <linux/pci.h>
46 #include <linux/phy.h>
47 #include <linux/workqueue.h>
48 #include <linux/platform_device.h>
49 #include <linux/prefetch.h>
50 #include <asm/io.h>
51 #include <asm/byteorder.h>
52 
53 enum tc35815_chiptype {
54 	TC35815CF = 0,
55 	TC35815_NWU,
56 	TC35815_TX4939,
57 };
58 
59 /* indexed by tc35815_chiptype, above */
60 static const struct {
61 	const char *name;
62 } chip_info[] = {
63 	{ "TOSHIBA TC35815CF 10/100BaseTX" },
64 	{ "TOSHIBA TC35815 with Wake on LAN" },
65 	{ "TOSHIBA TC35815/TX4939" },
66 };
67 
68 static const struct pci_device_id tc35815_pci_tbl[] = {
69 	{PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF },
70 	{PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU },
71 	{PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 },
72 	{0,}
73 };
74 MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl);
75 
76 /* see MODULE_PARM_DESC */
77 static struct tc35815_options {
78 	int speed;
79 	int duplex;
80 } options;
81 
82 /*
83  * Registers
84  */
85 struct tc35815_regs {
86 	__u32 DMA_Ctl;		/* 0x00 */
87 	__u32 TxFrmPtr;
88 	__u32 TxThrsh;
89 	__u32 TxPollCtr;
90 	__u32 BLFrmPtr;
91 	__u32 RxFragSize;
92 	__u32 Int_En;
93 	__u32 FDA_Bas;
94 	__u32 FDA_Lim;		/* 0x20 */
95 	__u32 Int_Src;
96 	__u32 unused0[2];
97 	__u32 PauseCnt;
98 	__u32 RemPauCnt;
99 	__u32 TxCtlFrmStat;
100 	__u32 unused1;
101 	__u32 MAC_Ctl;		/* 0x40 */
102 	__u32 CAM_Ctl;
103 	__u32 Tx_Ctl;
104 	__u32 Tx_Stat;
105 	__u32 Rx_Ctl;
106 	__u32 Rx_Stat;
107 	__u32 MD_Data;
108 	__u32 MD_CA;
109 	__u32 CAM_Adr;		/* 0x60 */
110 	__u32 CAM_Data;
111 	__u32 CAM_Ena;
112 	__u32 PROM_Ctl;
113 	__u32 PROM_Data;
114 	__u32 Algn_Cnt;
115 	__u32 CRC_Cnt;
116 	__u32 Miss_Cnt;
117 };
118 
119 /*
120  * Bit assignments
121  */
122 /* DMA_Ctl bit assign ------------------------------------------------------- */
123 #define DMA_RxAlign	       0x00c00000 /* 1:Reception Alignment	     */
124 #define DMA_RxAlign_1	       0x00400000
125 #define DMA_RxAlign_2	       0x00800000
126 #define DMA_RxAlign_3	       0x00c00000
127 #define DMA_M66EnStat	       0x00080000 /* 1:66MHz Enable State	     */
128 #define DMA_IntMask	       0x00040000 /* 1:Interrupt mask		     */
129 #define DMA_SWIntReq	       0x00020000 /* 1:Software Interrupt request    */
130 #define DMA_TxWakeUp	       0x00010000 /* 1:Transmit Wake Up		     */
131 #define DMA_RxBigE	       0x00008000 /* 1:Receive Big Endian	     */
132 #define DMA_TxBigE	       0x00004000 /* 1:Transmit Big Endian	     */
133 #define DMA_TestMode	       0x00002000 /* 1:Test Mode		     */
134 #define DMA_PowrMgmnt	       0x00001000 /* 1:Power Management		     */
135 #define DMA_DmBurst_Mask       0x000001fc /* DMA Burst size		     */
136 
137 /* RxFragSize bit assign ---------------------------------------------------- */
138 #define RxFrag_EnPack	       0x00008000 /* 1:Enable Packing		     */
139 #define RxFrag_MinFragMask     0x00000ffc /* Minimum Fragment		     */
140 
141 /* MAC_Ctl bit assign ------------------------------------------------------- */
142 #define MAC_Link10	       0x00008000 /* 1:Link Status 10Mbits	     */
143 #define MAC_EnMissRoll	       0x00002000 /* 1:Enable Missed Roll	     */
144 #define MAC_MissRoll	       0x00000400 /* 1:Missed Roll		     */
145 #define MAC_Loop10	       0x00000080 /* 1:Loop 10 Mbps		     */
146 #define MAC_Conn_Auto	       0x00000000 /*00:Connection mode (Automatic)   */
147 #define MAC_Conn_10M	       0x00000020 /*01:		       (10Mbps endec)*/
148 #define MAC_Conn_Mll	       0x00000040 /*10:		       (Mll clock)   */
149 #define MAC_MacLoop	       0x00000010 /* 1:MAC Loopback		     */
150 #define MAC_FullDup	       0x00000008 /* 1:Full Duplex 0:Half Duplex     */
151 #define MAC_Reset	       0x00000004 /* 1:Software Reset		     */
152 #define MAC_HaltImm	       0x00000002 /* 1:Halt Immediate		     */
153 #define MAC_HaltReq	       0x00000001 /* 1:Halt request		     */
154 
155 /* PROM_Ctl bit assign ------------------------------------------------------ */
156 #define PROM_Busy	       0x00008000 /* 1:Busy (Start Operation)	     */
157 #define PROM_Read	       0x00004000 /*10:Read operation		     */
158 #define PROM_Write	       0x00002000 /*01:Write operation		     */
159 #define PROM_Erase	       0x00006000 /*11:Erase operation		     */
160 					  /*00:Enable or Disable Writting,   */
161 					  /*	  as specified in PROM_Addr. */
162 #define PROM_Addr_Ena	       0x00000030 /*11xxxx:PROM Write enable	     */
163 					  /*00xxxx:	      disable	     */
164 
165 /* CAM_Ctl bit assign ------------------------------------------------------- */
166 #define CAM_CompEn	       0x00000010 /* 1:CAM Compare Enable	     */
167 #define CAM_NegCAM	       0x00000008 /* 1:Reject packets CAM recognizes,*/
168 					  /*			accept other */
169 #define CAM_BroadAcc	       0x00000004 /* 1:Broadcast assept		     */
170 #define CAM_GroupAcc	       0x00000002 /* 1:Multicast assept		     */
171 #define CAM_StationAcc	       0x00000001 /* 1:unicast accept		     */
172 
173 /* CAM_Ena bit assign ------------------------------------------------------- */
174 #define CAM_ENTRY_MAX		       21   /* CAM Data entry max count	     */
175 #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits)  */
176 #define CAM_Ena_Bit(index)	(1 << (index))
177 #define CAM_ENTRY_DESTINATION	0
178 #define CAM_ENTRY_SOURCE	1
179 #define CAM_ENTRY_MACCTL	20
180 
181 /* Tx_Ctl bit assign -------------------------------------------------------- */
182 #define Tx_En		       0x00000001 /* 1:Transmit enable		     */
183 #define Tx_TxHalt	       0x00000002 /* 1:Transmit Halt Request	     */
184 #define Tx_NoPad	       0x00000004 /* 1:Suppress Padding		     */
185 #define Tx_NoCRC	       0x00000008 /* 1:Suppress Padding		     */
186 #define Tx_FBack	       0x00000010 /* 1:Fast Back-off		     */
187 #define Tx_EnUnder	       0x00000100 /* 1:Enable Underrun		     */
188 #define Tx_EnExDefer	       0x00000200 /* 1:Enable Excessive Deferral     */
189 #define Tx_EnLCarr	       0x00000400 /* 1:Enable Lost Carrier	     */
190 #define Tx_EnExColl	       0x00000800 /* 1:Enable Excessive Collision    */
191 #define Tx_EnLateColl	       0x00001000 /* 1:Enable Late Collision	     */
192 #define Tx_EnTxPar	       0x00002000 /* 1:Enable Transmit Parity	     */
193 #define Tx_EnComp	       0x00004000 /* 1:Enable Completion	     */
194 
195 /* Tx_Stat bit assign ------------------------------------------------------- */
196 #define Tx_TxColl_MASK	       0x0000000F /* Tx Collision Count		     */
197 #define Tx_ExColl	       0x00000010 /* Excessive Collision	     */
198 #define Tx_TXDefer	       0x00000020 /* Transmit Defered		     */
199 #define Tx_Paused	       0x00000040 /* Transmit Paused		     */
200 #define Tx_IntTx	       0x00000080 /* Interrupt on Tx		     */
201 #define Tx_Under	       0x00000100 /* Underrun			     */
202 #define Tx_Defer	       0x00000200 /* Deferral			     */
203 #define Tx_NCarr	       0x00000400 /* No Carrier			     */
204 #define Tx_10Stat	       0x00000800 /* 10Mbps Status		     */
205 #define Tx_LateColl	       0x00001000 /* Late Collision		     */
206 #define Tx_TxPar	       0x00002000 /* Tx Parity Error		     */
207 #define Tx_Comp		       0x00004000 /* Completion			     */
208 #define Tx_Halted	       0x00008000 /* Tx Halted			     */
209 #define Tx_SQErr	       0x00010000 /* Signal Quality Error(SQE)	     */
210 
211 /* Rx_Ctl bit assign -------------------------------------------------------- */
212 #define Rx_EnGood	       0x00004000 /* 1:Enable Good		     */
213 #define Rx_EnRxPar	       0x00002000 /* 1:Enable Receive Parity	     */
214 #define Rx_EnLongErr	       0x00000800 /* 1:Enable Long Error	     */
215 #define Rx_EnOver	       0x00000400 /* 1:Enable OverFlow		     */
216 #define Rx_EnCRCErr	       0x00000200 /* 1:Enable CRC Error		     */
217 #define Rx_EnAlign	       0x00000100 /* 1:Enable Alignment		     */
218 #define Rx_IgnoreCRC	       0x00000040 /* 1:Ignore CRC Value		     */
219 #define Rx_StripCRC	       0x00000010 /* 1:Strip CRC Value		     */
220 #define Rx_ShortEn	       0x00000008 /* 1:Short Enable		     */
221 #define Rx_LongEn	       0x00000004 /* 1:Long Enable		     */
222 #define Rx_RxHalt	       0x00000002 /* 1:Receive Halt Request	     */
223 #define Rx_RxEn		       0x00000001 /* 1:Receive Intrrupt Enable	     */
224 
225 /* Rx_Stat bit assign ------------------------------------------------------- */
226 #define Rx_Halted	       0x00008000 /* Rx Halted			     */
227 #define Rx_Good		       0x00004000 /* Rx Good			     */
228 #define Rx_RxPar	       0x00002000 /* Rx Parity Error		     */
229 #define Rx_TypePkt	       0x00001000 /* Rx Type Packet		     */
230 #define Rx_LongErr	       0x00000800 /* Rx Long Error		     */
231 #define Rx_Over		       0x00000400 /* Rx Overflow		     */
232 #define Rx_CRCErr	       0x00000200 /* Rx CRC Error		     */
233 #define Rx_Align	       0x00000100 /* Rx Alignment Error		     */
234 #define Rx_10Stat	       0x00000080 /* Rx 10Mbps Status		     */
235 #define Rx_IntRx	       0x00000040 /* Rx Interrupt		     */
236 #define Rx_CtlRecd	       0x00000020 /* Rx Control Receive		     */
237 #define Rx_InLenErr	       0x00000010 /* Rx In Range Frame Length Error  */
238 
239 #define Rx_Stat_Mask	       0x0000FFF0 /* Rx All Status Mask		     */
240 
241 /* Int_En bit assign -------------------------------------------------------- */
242 #define Int_NRAbtEn	       0x00000800 /* 1:Non-recoverable Abort Enable  */
243 #define Int_TxCtlCmpEn	       0x00000400 /* 1:Transmit Ctl Complete Enable  */
244 #define Int_DmParErrEn	       0x00000200 /* 1:DMA Parity Error Enable	     */
245 #define Int_DParDEn	       0x00000100 /* 1:Data Parity Error Enable	     */
246 #define Int_EarNotEn	       0x00000080 /* 1:Early Notify Enable	     */
247 #define Int_DParErrEn	       0x00000040 /* 1:Detected Parity Error Enable  */
248 #define Int_SSysErrEn	       0x00000020 /* 1:Signalled System Error Enable */
249 #define Int_RMasAbtEn	       0x00000010 /* 1:Received Master Abort Enable  */
250 #define Int_RTargAbtEn	       0x00000008 /* 1:Received Target Abort Enable  */
251 #define Int_STargAbtEn	       0x00000004 /* 1:Signalled Target Abort Enable */
252 #define Int_BLExEn	       0x00000002 /* 1:Buffer List Exhausted Enable  */
253 #define Int_FDAExEn	       0x00000001 /* 1:Free Descriptor Area	     */
254 					  /*		   Exhausted Enable  */
255 
256 /* Int_Src bit assign ------------------------------------------------------- */
257 #define Int_NRabt	       0x00004000 /* 1:Non Recoverable error	     */
258 #define Int_DmParErrStat       0x00002000 /* 1:DMA Parity Error & Clear	     */
259 #define Int_BLEx	       0x00001000 /* 1:Buffer List Empty & Clear     */
260 #define Int_FDAEx	       0x00000800 /* 1:FDA Empty & Clear	     */
261 #define Int_IntNRAbt	       0x00000400 /* 1:Non Recoverable Abort	     */
262 #define Int_IntCmp	       0x00000200 /* 1:MAC control packet complete   */
263 #define Int_IntExBD	       0x00000100 /* 1:Interrupt Extra BD & Clear    */
264 #define Int_DmParErr	       0x00000080 /* 1:DMA Parity Error & Clear	     */
265 #define Int_IntEarNot	       0x00000040 /* 1:Receive Data write & Clear    */
266 #define Int_SWInt	       0x00000020 /* 1:Software request & Clear	     */
267 #define Int_IntBLEx	       0x00000010 /* 1:Buffer List Empty & Clear     */
268 #define Int_IntFDAEx	       0x00000008 /* 1:FDA Empty & Clear	     */
269 #define Int_IntPCI	       0x00000004 /* 1:PCI controller & Clear	     */
270 #define Int_IntMacRx	       0x00000002 /* 1:Rx controller & Clear	     */
271 #define Int_IntMacTx	       0x00000001 /* 1:Tx controller & Clear	     */
272 
273 /* MD_CA bit assign --------------------------------------------------------- */
274 #define MD_CA_PreSup	       0x00001000 /* 1:Preamble Suppress		     */
275 #define MD_CA_Busy	       0x00000800 /* 1:Busy (Start Operation)	     */
276 #define MD_CA_Wr	       0x00000400 /* 1:Write 0:Read		     */
277 
278 
279 /*
280  * Descriptors
281  */
282 
283 /* Frame descriptor */
284 struct FDesc {
285 	volatile __u32 FDNext;
286 	volatile __u32 FDSystem;
287 	volatile __u32 FDStat;
288 	volatile __u32 FDCtl;
289 };
290 
291 /* Buffer descriptor */
292 struct BDesc {
293 	volatile __u32 BuffData;
294 	volatile __u32 BDCtl;
295 };
296 
297 #define FD_ALIGN	16
298 
299 /* Frame Descriptor bit assign ---------------------------------------------- */
300 #define FD_FDLength_MASK       0x0000FFFF /* Length MASK		     */
301 #define FD_BDCnt_MASK	       0x001F0000 /* BD count MASK in FD	     */
302 #define FD_FrmOpt_MASK	       0x7C000000 /* Frame option MASK		     */
303 #define FD_FrmOpt_BigEndian    0x40000000 /* Tx/Rx */
304 #define FD_FrmOpt_IntTx	       0x20000000 /* Tx only */
305 #define FD_FrmOpt_NoCRC	       0x10000000 /* Tx only */
306 #define FD_FrmOpt_NoPadding    0x08000000 /* Tx only */
307 #define FD_FrmOpt_Packing      0x04000000 /* Rx only */
308 #define FD_CownsFD	       0x80000000 /* FD Controller owner bit	     */
309 #define FD_Next_EOL	       0x00000001 /* FD EOL indicator		     */
310 #define FD_BDCnt_SHIFT	       16
311 
312 /* Buffer Descriptor bit assign --------------------------------------------- */
313 #define BD_BuffLength_MASK     0x0000FFFF /* Receive Data Size		     */
314 #define BD_RxBDID_MASK	       0x00FF0000 /* BD ID Number MASK		     */
315 #define BD_RxBDSeqN_MASK       0x7F000000 /* Rx BD Sequence Number	     */
316 #define BD_CownsBD	       0x80000000 /* BD Controller owner bit	     */
317 #define BD_RxBDID_SHIFT	       16
318 #define BD_RxBDSeqN_SHIFT      24
319 
320 
321 /* Some useful constants. */
322 
323 #define TX_CTL_CMD	(Tx_EnTxPar | Tx_EnLateColl | \
324 	Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
325 	Tx_En)	/* maybe  0x7b01 */
326 /* Do not use Rx_StripCRC -- it causes trouble on BLEx/FDAEx condition */
327 #define RX_CTL_CMD	(Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
328 	| Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */
329 #define INT_EN_CMD  (Int_NRAbtEn | \
330 	Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \
331 	Int_SSysErrEn  | Int_RMasAbtEn | Int_RTargAbtEn | \
332 	Int_STargAbtEn | \
333 	Int_BLExEn  | Int_FDAExEn) /* maybe 0xb7f*/
334 #define DMA_CTL_CMD	DMA_BURST_SIZE
335 #define HAVE_DMA_RXALIGN(lp)	likely((lp)->chiptype != TC35815CF)
336 
337 /* Tuning parameters */
338 #define DMA_BURST_SIZE	32
339 #define TX_THRESHOLD	1024
340 /* used threshold with packet max byte for low pci transfer ability.*/
341 #define TX_THRESHOLD_MAX 1536
342 /* setting threshold max value when overrun error occurred this count. */
343 #define TX_THRESHOLD_KEEP_LIMIT 10
344 
345 /* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */
346 #define FD_PAGE_NUM 4
347 #define RX_BUF_NUM	128	/* < 256 */
348 #define RX_FD_NUM	256	/* >= 32 */
349 #define TX_FD_NUM	128
350 #if RX_CTL_CMD & Rx_LongEn
351 #define RX_BUF_SIZE	PAGE_SIZE
352 #elif RX_CTL_CMD & Rx_StripCRC
353 #define RX_BUF_SIZE	\
354 	L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN)
355 #else
356 #define RX_BUF_SIZE	\
357 	L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN)
358 #endif
359 #define RX_FD_RESERVE	(2 / 2)	/* max 2 BD per RxFD */
360 #define NAPI_WEIGHT	16
361 
362 struct TxFD {
363 	struct FDesc fd;
364 	struct BDesc bd;
365 	struct BDesc unused;
366 };
367 
368 struct RxFD {
369 	struct FDesc fd;
370 	struct BDesc bd[0];	/* variable length */
371 };
372 
373 struct FrFD {
374 	struct FDesc fd;
375 	struct BDesc bd[RX_BUF_NUM];
376 };
377 
378 
379 #define tc_readl(addr)	ioread32(addr)
380 #define tc_writel(d, addr)	iowrite32(d, addr)
381 
382 #define TC35815_TX_TIMEOUT  msecs_to_jiffies(400)
383 
384 /* Information that need to be kept for each controller. */
385 struct tc35815_local {
386 	struct pci_dev *pci_dev;
387 
388 	struct net_device *dev;
389 	struct napi_struct napi;
390 
391 	/* statistics */
392 	struct {
393 		int max_tx_qlen;
394 		int tx_ints;
395 		int rx_ints;
396 		int tx_underrun;
397 	} lstats;
398 
399 	/* Tx control lock.  This protects the transmit buffer ring
400 	 * state along with the "tx full" state of the driver.  This
401 	 * means all netif_queue flow control actions are protected
402 	 * by this lock as well.
403 	 */
404 	spinlock_t lock;
405 	spinlock_t rx_lock;
406 
407 	struct mii_bus *mii_bus;
408 	int duplex;
409 	int speed;
410 	int link;
411 	struct work_struct restart_work;
412 
413 	/*
414 	 * Transmitting: Batch Mode.
415 	 *	1 BD in 1 TxFD.
416 	 * Receiving: Non-Packing Mode.
417 	 *	1 circular FD for Free Buffer List.
418 	 *	RX_BUF_NUM BD in Free Buffer FD.
419 	 *	One Free Buffer BD has ETH_FRAME_LEN data buffer.
420 	 */
421 	void *fd_buf;	/* for TxFD, RxFD, FrFD */
422 	dma_addr_t fd_buf_dma;
423 	struct TxFD *tfd_base;
424 	unsigned int tfd_start;
425 	unsigned int tfd_end;
426 	struct RxFD *rfd_base;
427 	struct RxFD *rfd_limit;
428 	struct RxFD *rfd_cur;
429 	struct FrFD *fbl_ptr;
430 	unsigned int fbl_count;
431 	struct {
432 		struct sk_buff *skb;
433 		dma_addr_t skb_dma;
434 	} tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM];
435 	u32 msg_enable;
436 	enum tc35815_chiptype chiptype;
437 };
438 
439 static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt)
440 {
441 	return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf);
442 }
443 #ifdef DEBUG
444 static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
445 {
446 	return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma));
447 }
448 #endif
449 static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev,
450 				       struct pci_dev *hwdev,
451 				       dma_addr_t *dma_handle)
452 {
453 	struct sk_buff *skb;
454 	skb = netdev_alloc_skb(dev, RX_BUF_SIZE);
455 	if (!skb)
456 		return NULL;
457 	*dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE,
458 				     PCI_DMA_FROMDEVICE);
459 	if (pci_dma_mapping_error(hwdev, *dma_handle)) {
460 		dev_kfree_skb_any(skb);
461 		return NULL;
462 	}
463 	skb_reserve(skb, 2);	/* make IP header 4byte aligned */
464 	return skb;
465 }
466 
467 static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle)
468 {
469 	pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE,
470 			 PCI_DMA_FROMDEVICE);
471 	dev_kfree_skb_any(skb);
472 }
473 
474 /* Index to functions, as function prototypes. */
475 
476 static int	tc35815_open(struct net_device *dev);
477 static netdev_tx_t	tc35815_send_packet(struct sk_buff *skb,
478 					    struct net_device *dev);
479 static irqreturn_t	tc35815_interrupt(int irq, void *dev_id);
480 static int	tc35815_rx(struct net_device *dev, int limit);
481 static int	tc35815_poll(struct napi_struct *napi, int budget);
482 static void	tc35815_txdone(struct net_device *dev);
483 static int	tc35815_close(struct net_device *dev);
484 static struct	net_device_stats *tc35815_get_stats(struct net_device *dev);
485 static void	tc35815_set_multicast_list(struct net_device *dev);
486 static void	tc35815_tx_timeout(struct net_device *dev);
487 static int	tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
488 #ifdef CONFIG_NET_POLL_CONTROLLER
489 static void	tc35815_poll_controller(struct net_device *dev);
490 #endif
491 static const struct ethtool_ops tc35815_ethtool_ops;
492 
493 /* Example routines you must write ;->. */
494 static void	tc35815_chip_reset(struct net_device *dev);
495 static void	tc35815_chip_init(struct net_device *dev);
496 
497 #ifdef DEBUG
498 static void	panic_queues(struct net_device *dev);
499 #endif
500 
501 static void tc35815_restart_work(struct work_struct *work);
502 
503 static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
504 {
505 	struct net_device *dev = bus->priv;
506 	struct tc35815_regs __iomem *tr =
507 		(struct tc35815_regs __iomem *)dev->base_addr;
508 	unsigned long timeout = jiffies + HZ;
509 
510 	tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
511 	udelay(12); /* it takes 32 x 400ns at least */
512 	while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
513 		if (time_after(jiffies, timeout))
514 			return -EIO;
515 		cpu_relax();
516 	}
517 	return tc_readl(&tr->MD_Data) & 0xffff;
518 }
519 
520 static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val)
521 {
522 	struct net_device *dev = bus->priv;
523 	struct tc35815_regs __iomem *tr =
524 		(struct tc35815_regs __iomem *)dev->base_addr;
525 	unsigned long timeout = jiffies + HZ;
526 
527 	tc_writel(val, &tr->MD_Data);
528 	tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
529 		  &tr->MD_CA);
530 	udelay(12); /* it takes 32 x 400ns at least */
531 	while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
532 		if (time_after(jiffies, timeout))
533 			return -EIO;
534 		cpu_relax();
535 	}
536 	return 0;
537 }
538 
539 static void tc_handle_link_change(struct net_device *dev)
540 {
541 	struct tc35815_local *lp = netdev_priv(dev);
542 	struct phy_device *phydev = dev->phydev;
543 	unsigned long flags;
544 	int status_change = 0;
545 
546 	spin_lock_irqsave(&lp->lock, flags);
547 	if (phydev->link &&
548 	    (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) {
549 		struct tc35815_regs __iomem *tr =
550 			(struct tc35815_regs __iomem *)dev->base_addr;
551 		u32 reg;
552 
553 		reg = tc_readl(&tr->MAC_Ctl);
554 		reg |= MAC_HaltReq;
555 		tc_writel(reg, &tr->MAC_Ctl);
556 		if (phydev->duplex == DUPLEX_FULL)
557 			reg |= MAC_FullDup;
558 		else
559 			reg &= ~MAC_FullDup;
560 		tc_writel(reg, &tr->MAC_Ctl);
561 		reg &= ~MAC_HaltReq;
562 		tc_writel(reg, &tr->MAC_Ctl);
563 
564 		/*
565 		 * TX4939 PCFG.SPEEDn bit will be changed on
566 		 * NETDEV_CHANGE event.
567 		 */
568 		/*
569 		 * WORKAROUND: enable LostCrS only if half duplex
570 		 * operation.
571 		 * (TX4939 does not have EnLCarr)
572 		 */
573 		if (phydev->duplex == DUPLEX_HALF &&
574 		    lp->chiptype != TC35815_TX4939)
575 			tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
576 				  &tr->Tx_Ctl);
577 
578 		lp->speed = phydev->speed;
579 		lp->duplex = phydev->duplex;
580 		status_change = 1;
581 	}
582 
583 	if (phydev->link != lp->link) {
584 		if (phydev->link) {
585 			/* delayed promiscuous enabling */
586 			if (dev->flags & IFF_PROMISC)
587 				tc35815_set_multicast_list(dev);
588 		} else {
589 			lp->speed = 0;
590 			lp->duplex = -1;
591 		}
592 		lp->link = phydev->link;
593 
594 		status_change = 1;
595 	}
596 	spin_unlock_irqrestore(&lp->lock, flags);
597 
598 	if (status_change && netif_msg_link(lp)) {
599 		phy_print_status(phydev);
600 		pr_debug("%s: MII BMCR %04x BMSR %04x LPA %04x\n",
601 			 dev->name,
602 			 phy_read(phydev, MII_BMCR),
603 			 phy_read(phydev, MII_BMSR),
604 			 phy_read(phydev, MII_LPA));
605 	}
606 }
607 
608 static int tc_mii_probe(struct net_device *dev)
609 {
610 	struct tc35815_local *lp = netdev_priv(dev);
611 	struct phy_device *phydev;
612 	u32 dropmask;
613 
614 	phydev = phy_find_first(lp->mii_bus);
615 	if (!phydev) {
616 		printk(KERN_ERR "%s: no PHY found\n", dev->name);
617 		return -ENODEV;
618 	}
619 
620 	/* attach the mac to the phy */
621 	phydev = phy_connect(dev, phydev_name(phydev),
622 			     &tc_handle_link_change,
623 			     lp->chiptype == TC35815_TX4939 ? PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII);
624 	if (IS_ERR(phydev)) {
625 		printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
626 		return PTR_ERR(phydev);
627 	}
628 
629 	phy_attached_info(phydev);
630 
631 	/* mask with MAC supported features */
632 	phy_set_max_speed(phydev, SPEED_100);
633 	dropmask = 0;
634 	if (options.speed == 10)
635 		dropmask |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
636 	else if (options.speed == 100)
637 		dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
638 	if (options.duplex == 1)
639 		dropmask |= SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full;
640 	else if (options.duplex == 2)
641 		dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half;
642 	phydev->supported &= ~dropmask;
643 	phydev->advertising = phydev->supported;
644 
645 	lp->link = 0;
646 	lp->speed = 0;
647 	lp->duplex = -1;
648 
649 	return 0;
650 }
651 
652 static int tc_mii_init(struct net_device *dev)
653 {
654 	struct tc35815_local *lp = netdev_priv(dev);
655 	int err;
656 
657 	lp->mii_bus = mdiobus_alloc();
658 	if (lp->mii_bus == NULL) {
659 		err = -ENOMEM;
660 		goto err_out;
661 	}
662 
663 	lp->mii_bus->name = "tc35815_mii_bus";
664 	lp->mii_bus->read = tc_mdio_read;
665 	lp->mii_bus->write = tc_mdio_write;
666 	snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x",
667 		 (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn);
668 	lp->mii_bus->priv = dev;
669 	lp->mii_bus->parent = &lp->pci_dev->dev;
670 	err = mdiobus_register(lp->mii_bus);
671 	if (err)
672 		goto err_out_free_mii_bus;
673 	err = tc_mii_probe(dev);
674 	if (err)
675 		goto err_out_unregister_bus;
676 	return 0;
677 
678 err_out_unregister_bus:
679 	mdiobus_unregister(lp->mii_bus);
680 err_out_free_mii_bus:
681 	mdiobus_free(lp->mii_bus);
682 err_out:
683 	return err;
684 }
685 
686 #ifdef CONFIG_CPU_TX49XX
687 /*
688  * Find a platform_device providing a MAC address.  The platform code
689  * should provide a "tc35815-mac" device with a MAC address in its
690  * platform_data.
691  */
692 static int tc35815_mac_match(struct device *dev, void *data)
693 {
694 	struct platform_device *plat_dev = to_platform_device(dev);
695 	struct pci_dev *pci_dev = data;
696 	unsigned int id = pci_dev->irq;
697 	return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id;
698 }
699 
700 static int tc35815_read_plat_dev_addr(struct net_device *dev)
701 {
702 	struct tc35815_local *lp = netdev_priv(dev);
703 	struct device *pd = bus_find_device(&platform_bus_type, NULL,
704 					    lp->pci_dev, tc35815_mac_match);
705 	if (pd) {
706 		if (pd->platform_data)
707 			memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN);
708 		put_device(pd);
709 		return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV;
710 	}
711 	return -ENODEV;
712 }
713 #else
714 static int tc35815_read_plat_dev_addr(struct net_device *dev)
715 {
716 	return -ENODEV;
717 }
718 #endif
719 
720 static int tc35815_init_dev_addr(struct net_device *dev)
721 {
722 	struct tc35815_regs __iomem *tr =
723 		(struct tc35815_regs __iomem *)dev->base_addr;
724 	int i;
725 
726 	while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
727 		;
728 	for (i = 0; i < 6; i += 2) {
729 		unsigned short data;
730 		tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
731 		while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
732 			;
733 		data = tc_readl(&tr->PROM_Data);
734 		dev->dev_addr[i] = data & 0xff;
735 		dev->dev_addr[i+1] = data >> 8;
736 	}
737 	if (!is_valid_ether_addr(dev->dev_addr))
738 		return tc35815_read_plat_dev_addr(dev);
739 	return 0;
740 }
741 
742 static const struct net_device_ops tc35815_netdev_ops = {
743 	.ndo_open		= tc35815_open,
744 	.ndo_stop		= tc35815_close,
745 	.ndo_start_xmit		= tc35815_send_packet,
746 	.ndo_get_stats		= tc35815_get_stats,
747 	.ndo_set_rx_mode	= tc35815_set_multicast_list,
748 	.ndo_tx_timeout		= tc35815_tx_timeout,
749 	.ndo_do_ioctl		= tc35815_ioctl,
750 	.ndo_validate_addr	= eth_validate_addr,
751 	.ndo_set_mac_address	= eth_mac_addr,
752 #ifdef CONFIG_NET_POLL_CONTROLLER
753 	.ndo_poll_controller	= tc35815_poll_controller,
754 #endif
755 };
756 
757 static int tc35815_init_one(struct pci_dev *pdev,
758 			    const struct pci_device_id *ent)
759 {
760 	void __iomem *ioaddr = NULL;
761 	struct net_device *dev;
762 	struct tc35815_local *lp;
763 	int rc;
764 
765 	static int printed_version;
766 	if (!printed_version++) {
767 		printk(version);
768 		dev_printk(KERN_DEBUG, &pdev->dev,
769 			   "speed:%d duplex:%d\n",
770 			   options.speed, options.duplex);
771 	}
772 
773 	if (!pdev->irq) {
774 		dev_warn(&pdev->dev, "no IRQ assigned.\n");
775 		return -ENODEV;
776 	}
777 
778 	/* dev zeroed in alloc_etherdev */
779 	dev = alloc_etherdev(sizeof(*lp));
780 	if (dev == NULL)
781 		return -ENOMEM;
782 
783 	SET_NETDEV_DEV(dev, &pdev->dev);
784 	lp = netdev_priv(dev);
785 	lp->dev = dev;
786 
787 	/* enable device (incl. PCI PM wakeup), and bus-mastering */
788 	rc = pcim_enable_device(pdev);
789 	if (rc)
790 		goto err_out;
791 	rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME);
792 	if (rc)
793 		goto err_out;
794 	pci_set_master(pdev);
795 	ioaddr = pcim_iomap_table(pdev)[1];
796 
797 	/* Initialize the device structure. */
798 	dev->netdev_ops = &tc35815_netdev_ops;
799 	dev->ethtool_ops = &tc35815_ethtool_ops;
800 	dev->watchdog_timeo = TC35815_TX_TIMEOUT;
801 	netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT);
802 
803 	dev->irq = pdev->irq;
804 	dev->base_addr = (unsigned long)ioaddr;
805 
806 	INIT_WORK(&lp->restart_work, tc35815_restart_work);
807 	spin_lock_init(&lp->lock);
808 	spin_lock_init(&lp->rx_lock);
809 	lp->pci_dev = pdev;
810 	lp->chiptype = ent->driver_data;
811 
812 	lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK;
813 	pci_set_drvdata(pdev, dev);
814 
815 	/* Soft reset the chip. */
816 	tc35815_chip_reset(dev);
817 
818 	/* Retrieve the ethernet address. */
819 	if (tc35815_init_dev_addr(dev)) {
820 		dev_warn(&pdev->dev, "not valid ether addr\n");
821 		eth_hw_addr_random(dev);
822 	}
823 
824 	rc = register_netdev(dev);
825 	if (rc)
826 		goto err_out;
827 
828 	printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n",
829 		dev->name,
830 		chip_info[ent->driver_data].name,
831 		dev->base_addr,
832 		dev->dev_addr,
833 		dev->irq);
834 
835 	rc = tc_mii_init(dev);
836 	if (rc)
837 		goto err_out_unregister;
838 
839 	return 0;
840 
841 err_out_unregister:
842 	unregister_netdev(dev);
843 err_out:
844 	free_netdev(dev);
845 	return rc;
846 }
847 
848 
849 static void tc35815_remove_one(struct pci_dev *pdev)
850 {
851 	struct net_device *dev = pci_get_drvdata(pdev);
852 	struct tc35815_local *lp = netdev_priv(dev);
853 
854 	phy_disconnect(dev->phydev);
855 	mdiobus_unregister(lp->mii_bus);
856 	mdiobus_free(lp->mii_bus);
857 	unregister_netdev(dev);
858 	free_netdev(dev);
859 }
860 
861 static int
862 tc35815_init_queues(struct net_device *dev)
863 {
864 	struct tc35815_local *lp = netdev_priv(dev);
865 	int i;
866 	unsigned long fd_addr;
867 
868 	if (!lp->fd_buf) {
869 		BUG_ON(sizeof(struct FDesc) +
870 		       sizeof(struct BDesc) * RX_BUF_NUM +
871 		       sizeof(struct FDesc) * RX_FD_NUM +
872 		       sizeof(struct TxFD) * TX_FD_NUM >
873 		       PAGE_SIZE * FD_PAGE_NUM);
874 
875 		lp->fd_buf = pci_alloc_consistent(lp->pci_dev,
876 						  PAGE_SIZE * FD_PAGE_NUM,
877 						  &lp->fd_buf_dma);
878 		if (!lp->fd_buf)
879 			return -ENOMEM;
880 		for (i = 0; i < RX_BUF_NUM; i++) {
881 			lp->rx_skbs[i].skb =
882 				alloc_rxbuf_skb(dev, lp->pci_dev,
883 						&lp->rx_skbs[i].skb_dma);
884 			if (!lp->rx_skbs[i].skb) {
885 				while (--i >= 0) {
886 					free_rxbuf_skb(lp->pci_dev,
887 						       lp->rx_skbs[i].skb,
888 						       lp->rx_skbs[i].skb_dma);
889 					lp->rx_skbs[i].skb = NULL;
890 				}
891 				pci_free_consistent(lp->pci_dev,
892 						    PAGE_SIZE * FD_PAGE_NUM,
893 						    lp->fd_buf,
894 						    lp->fd_buf_dma);
895 				lp->fd_buf = NULL;
896 				return -ENOMEM;
897 			}
898 		}
899 		printk(KERN_DEBUG "%s: FD buf %p DataBuf",
900 		       dev->name, lp->fd_buf);
901 		printk("\n");
902 	} else {
903 		for (i = 0; i < FD_PAGE_NUM; i++)
904 			clear_page((void *)((unsigned long)lp->fd_buf +
905 					    i * PAGE_SIZE));
906 	}
907 	fd_addr = (unsigned long)lp->fd_buf;
908 
909 	/* Free Descriptors (for Receive) */
910 	lp->rfd_base = (struct RxFD *)fd_addr;
911 	fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
912 	for (i = 0; i < RX_FD_NUM; i++)
913 		lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
914 	lp->rfd_cur = lp->rfd_base;
915 	lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1);
916 
917 	/* Transmit Descriptors */
918 	lp->tfd_base = (struct TxFD *)fd_addr;
919 	fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
920 	for (i = 0; i < TX_FD_NUM; i++) {
921 		lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1]));
922 		lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
923 		lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
924 	}
925 	lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0]));
926 	lp->tfd_start = 0;
927 	lp->tfd_end = 0;
928 
929 	/* Buffer List (for Receive) */
930 	lp->fbl_ptr = (struct FrFD *)fd_addr;
931 	lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr));
932 	lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD);
933 	/*
934 	 * move all allocated skbs to head of rx_skbs[] array.
935 	 * fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in
936 	 * tc35815_rx() had failed.
937 	 */
938 	lp->fbl_count = 0;
939 	for (i = 0; i < RX_BUF_NUM; i++) {
940 		if (lp->rx_skbs[i].skb) {
941 			if (i != lp->fbl_count) {
942 				lp->rx_skbs[lp->fbl_count].skb =
943 					lp->rx_skbs[i].skb;
944 				lp->rx_skbs[lp->fbl_count].skb_dma =
945 					lp->rx_skbs[i].skb_dma;
946 			}
947 			lp->fbl_count++;
948 		}
949 	}
950 	for (i = 0; i < RX_BUF_NUM; i++) {
951 		if (i >= lp->fbl_count) {
952 			lp->fbl_ptr->bd[i].BuffData = 0;
953 			lp->fbl_ptr->bd[i].BDCtl = 0;
954 			continue;
955 		}
956 		lp->fbl_ptr->bd[i].BuffData =
957 			cpu_to_le32(lp->rx_skbs[i].skb_dma);
958 		/* BDID is index of FrFD.bd[] */
959 		lp->fbl_ptr->bd[i].BDCtl =
960 			cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) |
961 				    RX_BUF_SIZE);
962 	}
963 
964 	printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n",
965 	       dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr);
966 	return 0;
967 }
968 
969 static void
970 tc35815_clear_queues(struct net_device *dev)
971 {
972 	struct tc35815_local *lp = netdev_priv(dev);
973 	int i;
974 
975 	for (i = 0; i < TX_FD_NUM; i++) {
976 		u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
977 		struct sk_buff *skb =
978 			fdsystem != 0xffffffff ?
979 			lp->tx_skbs[fdsystem].skb : NULL;
980 #ifdef DEBUG
981 		if (lp->tx_skbs[i].skb != skb) {
982 			printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
983 			panic_queues(dev);
984 		}
985 #else
986 		BUG_ON(lp->tx_skbs[i].skb != skb);
987 #endif
988 		if (skb) {
989 			pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
990 			lp->tx_skbs[i].skb = NULL;
991 			lp->tx_skbs[i].skb_dma = 0;
992 			dev_kfree_skb_any(skb);
993 		}
994 		lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
995 	}
996 
997 	tc35815_init_queues(dev);
998 }
999 
1000 static void
1001 tc35815_free_queues(struct net_device *dev)
1002 {
1003 	struct tc35815_local *lp = netdev_priv(dev);
1004 	int i;
1005 
1006 	if (lp->tfd_base) {
1007 		for (i = 0; i < TX_FD_NUM; i++) {
1008 			u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1009 			struct sk_buff *skb =
1010 				fdsystem != 0xffffffff ?
1011 				lp->tx_skbs[fdsystem].skb : NULL;
1012 #ifdef DEBUG
1013 			if (lp->tx_skbs[i].skb != skb) {
1014 				printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1015 				panic_queues(dev);
1016 			}
1017 #else
1018 			BUG_ON(lp->tx_skbs[i].skb != skb);
1019 #endif
1020 			if (skb) {
1021 				pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1022 				dev_kfree_skb(skb);
1023 				lp->tx_skbs[i].skb = NULL;
1024 				lp->tx_skbs[i].skb_dma = 0;
1025 			}
1026 			lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1027 		}
1028 	}
1029 
1030 	lp->rfd_base = NULL;
1031 	lp->rfd_limit = NULL;
1032 	lp->rfd_cur = NULL;
1033 	lp->fbl_ptr = NULL;
1034 
1035 	for (i = 0; i < RX_BUF_NUM; i++) {
1036 		if (lp->rx_skbs[i].skb) {
1037 			free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb,
1038 				       lp->rx_skbs[i].skb_dma);
1039 			lp->rx_skbs[i].skb = NULL;
1040 		}
1041 	}
1042 	if (lp->fd_buf) {
1043 		pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM,
1044 				    lp->fd_buf, lp->fd_buf_dma);
1045 		lp->fd_buf = NULL;
1046 	}
1047 }
1048 
1049 static void
1050 dump_txfd(struct TxFD *fd)
1051 {
1052 	printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
1053 	       le32_to_cpu(fd->fd.FDNext),
1054 	       le32_to_cpu(fd->fd.FDSystem),
1055 	       le32_to_cpu(fd->fd.FDStat),
1056 	       le32_to_cpu(fd->fd.FDCtl));
1057 	printk("BD: ");
1058 	printk(" %08x %08x",
1059 	       le32_to_cpu(fd->bd.BuffData),
1060 	       le32_to_cpu(fd->bd.BDCtl));
1061 	printk("\n");
1062 }
1063 
1064 static int
1065 dump_rxfd(struct RxFD *fd)
1066 {
1067 	int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1068 	if (bd_count > 8)
1069 		bd_count = 8;
1070 	printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
1071 	       le32_to_cpu(fd->fd.FDNext),
1072 	       le32_to_cpu(fd->fd.FDSystem),
1073 	       le32_to_cpu(fd->fd.FDStat),
1074 	       le32_to_cpu(fd->fd.FDCtl));
1075 	if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
1076 		return 0;
1077 	printk("BD: ");
1078 	for (i = 0; i < bd_count; i++)
1079 		printk(" %08x %08x",
1080 		       le32_to_cpu(fd->bd[i].BuffData),
1081 		       le32_to_cpu(fd->bd[i].BDCtl));
1082 	printk("\n");
1083 	return bd_count;
1084 }
1085 
1086 #ifdef DEBUG
1087 static void
1088 dump_frfd(struct FrFD *fd)
1089 {
1090 	int i;
1091 	printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
1092 	       le32_to_cpu(fd->fd.FDNext),
1093 	       le32_to_cpu(fd->fd.FDSystem),
1094 	       le32_to_cpu(fd->fd.FDStat),
1095 	       le32_to_cpu(fd->fd.FDCtl));
1096 	printk("BD: ");
1097 	for (i = 0; i < RX_BUF_NUM; i++)
1098 		printk(" %08x %08x",
1099 		       le32_to_cpu(fd->bd[i].BuffData),
1100 		       le32_to_cpu(fd->bd[i].BDCtl));
1101 	printk("\n");
1102 }
1103 
1104 static void
1105 panic_queues(struct net_device *dev)
1106 {
1107 	struct tc35815_local *lp = netdev_priv(dev);
1108 	int i;
1109 
1110 	printk("TxFD base %p, start %u, end %u\n",
1111 	       lp->tfd_base, lp->tfd_start, lp->tfd_end);
1112 	printk("RxFD base %p limit %p cur %p\n",
1113 	       lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
1114 	printk("FrFD %p\n", lp->fbl_ptr);
1115 	for (i = 0; i < TX_FD_NUM; i++)
1116 		dump_txfd(&lp->tfd_base[i]);
1117 	for (i = 0; i < RX_FD_NUM; i++) {
1118 		int bd_count = dump_rxfd(&lp->rfd_base[i]);
1119 		i += (bd_count + 1) / 2;	/* skip BDs */
1120 	}
1121 	dump_frfd(lp->fbl_ptr);
1122 	panic("%s: Illegal queue state.", dev->name);
1123 }
1124 #endif
1125 
1126 static void print_eth(const u8 *add)
1127 {
1128 	printk(KERN_DEBUG "print_eth(%p)\n", add);
1129 	printk(KERN_DEBUG " %pM => %pM : %02x%02x\n",
1130 		add + 6, add, add[12], add[13]);
1131 }
1132 
1133 static int tc35815_tx_full(struct net_device *dev)
1134 {
1135 	struct tc35815_local *lp = netdev_priv(dev);
1136 	return (lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end;
1137 }
1138 
1139 static void tc35815_restart(struct net_device *dev)
1140 {
1141 	struct tc35815_local *lp = netdev_priv(dev);
1142 	int ret;
1143 
1144 	if (dev->phydev) {
1145 		ret = phy_init_hw(dev->phydev);
1146 		if (ret)
1147 			printk(KERN_ERR "%s: PHY init failed.\n", dev->name);
1148 	}
1149 
1150 	spin_lock_bh(&lp->rx_lock);
1151 	spin_lock_irq(&lp->lock);
1152 	tc35815_chip_reset(dev);
1153 	tc35815_clear_queues(dev);
1154 	tc35815_chip_init(dev);
1155 	/* Reconfigure CAM again since tc35815_chip_init() initialize it. */
1156 	tc35815_set_multicast_list(dev);
1157 	spin_unlock_irq(&lp->lock);
1158 	spin_unlock_bh(&lp->rx_lock);
1159 
1160 	netif_wake_queue(dev);
1161 }
1162 
1163 static void tc35815_restart_work(struct work_struct *work)
1164 {
1165 	struct tc35815_local *lp =
1166 		container_of(work, struct tc35815_local, restart_work);
1167 	struct net_device *dev = lp->dev;
1168 
1169 	tc35815_restart(dev);
1170 }
1171 
1172 static void tc35815_schedule_restart(struct net_device *dev)
1173 {
1174 	struct tc35815_local *lp = netdev_priv(dev);
1175 	struct tc35815_regs __iomem *tr =
1176 		(struct tc35815_regs __iomem *)dev->base_addr;
1177 	unsigned long flags;
1178 
1179 	/* disable interrupts */
1180 	spin_lock_irqsave(&lp->lock, flags);
1181 	tc_writel(0, &tr->Int_En);
1182 	tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
1183 	schedule_work(&lp->restart_work);
1184 	spin_unlock_irqrestore(&lp->lock, flags);
1185 }
1186 
1187 static void tc35815_tx_timeout(struct net_device *dev)
1188 {
1189 	struct tc35815_regs __iomem *tr =
1190 		(struct tc35815_regs __iomem *)dev->base_addr;
1191 
1192 	printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
1193 	       dev->name, tc_readl(&tr->Tx_Stat));
1194 
1195 	/* Try to restart the adaptor. */
1196 	tc35815_schedule_restart(dev);
1197 	dev->stats.tx_errors++;
1198 }
1199 
1200 /*
1201  * Open/initialize the controller. This is called (in the current kernel)
1202  * sometime after booting when the 'ifconfig' program is run.
1203  *
1204  * This routine should set everything up anew at each open, even
1205  * registers that "should" only need to be set once at boot, so that
1206  * there is non-reboot way to recover if something goes wrong.
1207  */
1208 static int
1209 tc35815_open(struct net_device *dev)
1210 {
1211 	struct tc35815_local *lp = netdev_priv(dev);
1212 
1213 	/*
1214 	 * This is used if the interrupt line can turned off (shared).
1215 	 * See 3c503.c for an example of selecting the IRQ at config-time.
1216 	 */
1217 	if (request_irq(dev->irq, tc35815_interrupt, IRQF_SHARED,
1218 			dev->name, dev))
1219 		return -EAGAIN;
1220 
1221 	tc35815_chip_reset(dev);
1222 
1223 	if (tc35815_init_queues(dev) != 0) {
1224 		free_irq(dev->irq, dev);
1225 		return -EAGAIN;
1226 	}
1227 
1228 	napi_enable(&lp->napi);
1229 
1230 	/* Reset the hardware here. Don't forget to set the station address. */
1231 	spin_lock_irq(&lp->lock);
1232 	tc35815_chip_init(dev);
1233 	spin_unlock_irq(&lp->lock);
1234 
1235 	netif_carrier_off(dev);
1236 	/* schedule a link state check */
1237 	phy_start(dev->phydev);
1238 
1239 	/* We are now ready to accept transmit requeusts from
1240 	 * the queueing layer of the networking.
1241 	 */
1242 	netif_start_queue(dev);
1243 
1244 	return 0;
1245 }
1246 
1247 /* This will only be invoked if your driver is _not_ in XOFF state.
1248  * What this means is that you need not check it, and that this
1249  * invariant will hold if you make sure that the netif_*_queue()
1250  * calls are done at the proper times.
1251  */
1252 static netdev_tx_t
1253 tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
1254 {
1255 	struct tc35815_local *lp = netdev_priv(dev);
1256 	struct TxFD *txfd;
1257 	unsigned long flags;
1258 
1259 	/* If some error occurs while trying to transmit this
1260 	 * packet, you should return '1' from this function.
1261 	 * In such a case you _may not_ do anything to the
1262 	 * SKB, it is still owned by the network queueing
1263 	 * layer when an error is returned.  This means you
1264 	 * may not modify any SKB fields, you may not free
1265 	 * the SKB, etc.
1266 	 */
1267 
1268 	/* This is the most common case for modern hardware.
1269 	 * The spinlock protects this code from the TX complete
1270 	 * hardware interrupt handler.  Queue flow control is
1271 	 * thus managed under this lock as well.
1272 	 */
1273 	spin_lock_irqsave(&lp->lock, flags);
1274 
1275 	/* failsafe... (handle txdone now if half of FDs are used) */
1276 	if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM >
1277 	    TX_FD_NUM / 2)
1278 		tc35815_txdone(dev);
1279 
1280 	if (netif_msg_pktdata(lp))
1281 		print_eth(skb->data);
1282 #ifdef DEBUG
1283 	if (lp->tx_skbs[lp->tfd_start].skb) {
1284 		printk("%s: tx_skbs conflict.\n", dev->name);
1285 		panic_queues(dev);
1286 	}
1287 #else
1288 	BUG_ON(lp->tx_skbs[lp->tfd_start].skb);
1289 #endif
1290 	lp->tx_skbs[lp->tfd_start].skb = skb;
1291 	lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1292 
1293 	/*add to ring */
1294 	txfd = &lp->tfd_base[lp->tfd_start];
1295 	txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma);
1296 	txfd->bd.BDCtl = cpu_to_le32(skb->len);
1297 	txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start);
1298 	txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
1299 
1300 	if (lp->tfd_start == lp->tfd_end) {
1301 		struct tc35815_regs __iomem *tr =
1302 			(struct tc35815_regs __iomem *)dev->base_addr;
1303 		/* Start DMA Transmitter. */
1304 		txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1305 		txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1306 		if (netif_msg_tx_queued(lp)) {
1307 			printk("%s: starting TxFD.\n", dev->name);
1308 			dump_txfd(txfd);
1309 		}
1310 		tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1311 	} else {
1312 		txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
1313 		if (netif_msg_tx_queued(lp)) {
1314 			printk("%s: queueing TxFD.\n", dev->name);
1315 			dump_txfd(txfd);
1316 		}
1317 	}
1318 	lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
1319 
1320 	/* If we just used up the very last entry in the
1321 	 * TX ring on this device, tell the queueing
1322 	 * layer to send no more.
1323 	 */
1324 	if (tc35815_tx_full(dev)) {
1325 		if (netif_msg_tx_queued(lp))
1326 			printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
1327 		netif_stop_queue(dev);
1328 	}
1329 
1330 	/* When the TX completion hw interrupt arrives, this
1331 	 * is when the transmit statistics are updated.
1332 	 */
1333 
1334 	spin_unlock_irqrestore(&lp->lock, flags);
1335 	return NETDEV_TX_OK;
1336 }
1337 
1338 #define FATAL_ERROR_INT \
1339 	(Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
1340 static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status)
1341 {
1342 	static int count;
1343 	printk(KERN_WARNING "%s: Fatal Error Interrupt (%#x):",
1344 	       dev->name, status);
1345 	if (status & Int_IntPCI)
1346 		printk(" IntPCI");
1347 	if (status & Int_DmParErr)
1348 		printk(" DmParErr");
1349 	if (status & Int_IntNRAbt)
1350 		printk(" IntNRAbt");
1351 	printk("\n");
1352 	if (count++ > 100)
1353 		panic("%s: Too many fatal errors.", dev->name);
1354 	printk(KERN_WARNING "%s: Resetting ...\n", dev->name);
1355 	/* Try to restart the adaptor. */
1356 	tc35815_schedule_restart(dev);
1357 }
1358 
1359 static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit)
1360 {
1361 	struct tc35815_local *lp = netdev_priv(dev);
1362 	int ret = -1;
1363 
1364 	/* Fatal errors... */
1365 	if (status & FATAL_ERROR_INT) {
1366 		tc35815_fatal_error_interrupt(dev, status);
1367 		return 0;
1368 	}
1369 	/* recoverable errors */
1370 	if (status & Int_IntFDAEx) {
1371 		if (netif_msg_rx_err(lp))
1372 			dev_warn(&dev->dev,
1373 				 "Free Descriptor Area Exhausted (%#x).\n",
1374 				 status);
1375 		dev->stats.rx_dropped++;
1376 		ret = 0;
1377 	}
1378 	if (status & Int_IntBLEx) {
1379 		if (netif_msg_rx_err(lp))
1380 			dev_warn(&dev->dev,
1381 				 "Buffer List Exhausted (%#x).\n",
1382 				 status);
1383 		dev->stats.rx_dropped++;
1384 		ret = 0;
1385 	}
1386 	if (status & Int_IntExBD) {
1387 		if (netif_msg_rx_err(lp))
1388 			dev_warn(&dev->dev,
1389 				 "Excessive Buffer Descriptors (%#x).\n",
1390 				 status);
1391 		dev->stats.rx_length_errors++;
1392 		ret = 0;
1393 	}
1394 
1395 	/* normal notification */
1396 	if (status & Int_IntMacRx) {
1397 		/* Got a packet(s). */
1398 		ret = tc35815_rx(dev, limit);
1399 		lp->lstats.rx_ints++;
1400 	}
1401 	if (status & Int_IntMacTx) {
1402 		/* Transmit complete. */
1403 		lp->lstats.tx_ints++;
1404 		spin_lock_irq(&lp->lock);
1405 		tc35815_txdone(dev);
1406 		spin_unlock_irq(&lp->lock);
1407 		if (ret < 0)
1408 			ret = 0;
1409 	}
1410 	return ret;
1411 }
1412 
1413 /*
1414  * The typical workload of the driver:
1415  * Handle the network interface interrupts.
1416  */
1417 static irqreturn_t tc35815_interrupt(int irq, void *dev_id)
1418 {
1419 	struct net_device *dev = dev_id;
1420 	struct tc35815_local *lp = netdev_priv(dev);
1421 	struct tc35815_regs __iomem *tr =
1422 		(struct tc35815_regs __iomem *)dev->base_addr;
1423 	u32 dmactl = tc_readl(&tr->DMA_Ctl);
1424 
1425 	if (!(dmactl & DMA_IntMask)) {
1426 		/* disable interrupts */
1427 		tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
1428 		if (napi_schedule_prep(&lp->napi))
1429 			__napi_schedule(&lp->napi);
1430 		else {
1431 			printk(KERN_ERR "%s: interrupt taken in poll\n",
1432 			       dev->name);
1433 			BUG();
1434 		}
1435 		(void)tc_readl(&tr->Int_Src);	/* flush */
1436 		return IRQ_HANDLED;
1437 	}
1438 	return IRQ_NONE;
1439 }
1440 
1441 #ifdef CONFIG_NET_POLL_CONTROLLER
1442 static void tc35815_poll_controller(struct net_device *dev)
1443 {
1444 	disable_irq(dev->irq);
1445 	tc35815_interrupt(dev->irq, dev);
1446 	enable_irq(dev->irq);
1447 }
1448 #endif
1449 
1450 /* We have a good packet(s), get it/them out of the buffers. */
1451 static int
1452 tc35815_rx(struct net_device *dev, int limit)
1453 {
1454 	struct tc35815_local *lp = netdev_priv(dev);
1455 	unsigned int fdctl;
1456 	int i;
1457 	int received = 0;
1458 
1459 	while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
1460 		int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
1461 		int pkt_len = fdctl & FD_FDLength_MASK;
1462 		int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1463 #ifdef DEBUG
1464 		struct RxFD *next_rfd;
1465 #endif
1466 #if (RX_CTL_CMD & Rx_StripCRC) == 0
1467 		pkt_len -= ETH_FCS_LEN;
1468 #endif
1469 
1470 		if (netif_msg_rx_status(lp))
1471 			dump_rxfd(lp->rfd_cur);
1472 		if (status & Rx_Good) {
1473 			struct sk_buff *skb;
1474 			unsigned char *data;
1475 			int cur_bd;
1476 
1477 			if (--limit < 0)
1478 				break;
1479 			BUG_ON(bd_count > 1);
1480 			cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl)
1481 				  & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1482 #ifdef DEBUG
1483 			if (cur_bd >= RX_BUF_NUM) {
1484 				printk("%s: invalid BDID.\n", dev->name);
1485 				panic_queues(dev);
1486 			}
1487 			BUG_ON(lp->rx_skbs[cur_bd].skb_dma !=
1488 			       (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3));
1489 			if (!lp->rx_skbs[cur_bd].skb) {
1490 				printk("%s: NULL skb.\n", dev->name);
1491 				panic_queues(dev);
1492 			}
1493 #else
1494 			BUG_ON(cur_bd >= RX_BUF_NUM);
1495 #endif
1496 			skb = lp->rx_skbs[cur_bd].skb;
1497 			prefetch(skb->data);
1498 			lp->rx_skbs[cur_bd].skb = NULL;
1499 			pci_unmap_single(lp->pci_dev,
1500 					 lp->rx_skbs[cur_bd].skb_dma,
1501 					 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1502 			if (!HAVE_DMA_RXALIGN(lp) && NET_IP_ALIGN)
1503 				memmove(skb->data, skb->data - NET_IP_ALIGN,
1504 					pkt_len);
1505 			data = skb_put(skb, pkt_len);
1506 			if (netif_msg_pktdata(lp))
1507 				print_eth(data);
1508 			skb->protocol = eth_type_trans(skb, dev);
1509 			netif_receive_skb(skb);
1510 			received++;
1511 			dev->stats.rx_packets++;
1512 			dev->stats.rx_bytes += pkt_len;
1513 		} else {
1514 			dev->stats.rx_errors++;
1515 			if (netif_msg_rx_err(lp))
1516 				dev_info(&dev->dev, "Rx error (status %x)\n",
1517 					 status & Rx_Stat_Mask);
1518 			/* WORKAROUND: LongErr and CRCErr means Overflow. */
1519 			if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
1520 				status &= ~(Rx_LongErr|Rx_CRCErr);
1521 				status |= Rx_Over;
1522 			}
1523 			if (status & Rx_LongErr)
1524 				dev->stats.rx_length_errors++;
1525 			if (status & Rx_Over)
1526 				dev->stats.rx_fifo_errors++;
1527 			if (status & Rx_CRCErr)
1528 				dev->stats.rx_crc_errors++;
1529 			if (status & Rx_Align)
1530 				dev->stats.rx_frame_errors++;
1531 		}
1532 
1533 		if (bd_count > 0) {
1534 			/* put Free Buffer back to controller */
1535 			int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
1536 			unsigned char id =
1537 				(bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1538 #ifdef DEBUG
1539 			if (id >= RX_BUF_NUM) {
1540 				printk("%s: invalid BDID.\n", dev->name);
1541 				panic_queues(dev);
1542 			}
1543 #else
1544 			BUG_ON(id >= RX_BUF_NUM);
1545 #endif
1546 			/* free old buffers */
1547 			lp->fbl_count--;
1548 			while (lp->fbl_count < RX_BUF_NUM)
1549 			{
1550 				unsigned char curid =
1551 					(id + 1 + lp->fbl_count) % RX_BUF_NUM;
1552 				struct BDesc *bd = &lp->fbl_ptr->bd[curid];
1553 #ifdef DEBUG
1554 				bdctl = le32_to_cpu(bd->BDCtl);
1555 				if (bdctl & BD_CownsBD) {
1556 					printk("%s: Freeing invalid BD.\n",
1557 					       dev->name);
1558 					panic_queues(dev);
1559 				}
1560 #endif
1561 				/* pass BD to controller */
1562 				if (!lp->rx_skbs[curid].skb) {
1563 					lp->rx_skbs[curid].skb =
1564 						alloc_rxbuf_skb(dev,
1565 								lp->pci_dev,
1566 								&lp->rx_skbs[curid].skb_dma);
1567 					if (!lp->rx_skbs[curid].skb)
1568 						break; /* try on next reception */
1569 					bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma);
1570 				}
1571 				/* Note: BDLength was modified by chip. */
1572 				bd->BDCtl = cpu_to_le32(BD_CownsBD |
1573 							(curid << BD_RxBDID_SHIFT) |
1574 							RX_BUF_SIZE);
1575 				lp->fbl_count++;
1576 			}
1577 		}
1578 
1579 		/* put RxFD back to controller */
1580 #ifdef DEBUG
1581 		next_rfd = fd_bus_to_virt(lp,
1582 					  le32_to_cpu(lp->rfd_cur->fd.FDNext));
1583 		if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
1584 			printk("%s: RxFD FDNext invalid.\n", dev->name);
1585 			panic_queues(dev);
1586 		}
1587 #endif
1588 		for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
1589 			/* pass FD to controller */
1590 #ifdef DEBUG
1591 			lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead);
1592 #else
1593 			lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL);
1594 #endif
1595 			lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
1596 			lp->rfd_cur++;
1597 		}
1598 		if (lp->rfd_cur > lp->rfd_limit)
1599 			lp->rfd_cur = lp->rfd_base;
1600 #ifdef DEBUG
1601 		if (lp->rfd_cur != next_rfd)
1602 			printk("rfd_cur = %p, next_rfd %p\n",
1603 			       lp->rfd_cur, next_rfd);
1604 #endif
1605 	}
1606 
1607 	return received;
1608 }
1609 
1610 static int tc35815_poll(struct napi_struct *napi, int budget)
1611 {
1612 	struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi);
1613 	struct net_device *dev = lp->dev;
1614 	struct tc35815_regs __iomem *tr =
1615 		(struct tc35815_regs __iomem *)dev->base_addr;
1616 	int received = 0, handled;
1617 	u32 status;
1618 
1619 	if (budget <= 0)
1620 		return received;
1621 
1622 	spin_lock(&lp->rx_lock);
1623 	status = tc_readl(&tr->Int_Src);
1624 	do {
1625 		/* BLEx, FDAEx will be cleared later */
1626 		tc_writel(status & ~(Int_BLEx | Int_FDAEx),
1627 			  &tr->Int_Src);	/* write to clear */
1628 
1629 		handled = tc35815_do_interrupt(dev, status, budget - received);
1630 		if (status & (Int_BLEx | Int_FDAEx))
1631 			tc_writel(status & (Int_BLEx | Int_FDAEx),
1632 				  &tr->Int_Src);
1633 		if (handled >= 0) {
1634 			received += handled;
1635 			if (received >= budget)
1636 				break;
1637 		}
1638 		status = tc_readl(&tr->Int_Src);
1639 	} while (status);
1640 	spin_unlock(&lp->rx_lock);
1641 
1642 	if (received < budget) {
1643 		napi_complete_done(napi, received);
1644 		/* enable interrupts */
1645 		tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
1646 	}
1647 	return received;
1648 }
1649 
1650 #define TX_STA_ERR	(Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1651 
1652 static void
1653 tc35815_check_tx_stat(struct net_device *dev, int status)
1654 {
1655 	struct tc35815_local *lp = netdev_priv(dev);
1656 	const char *msg = NULL;
1657 
1658 	/* count collisions */
1659 	if (status & Tx_ExColl)
1660 		dev->stats.collisions += 16;
1661 	if (status & Tx_TxColl_MASK)
1662 		dev->stats.collisions += status & Tx_TxColl_MASK;
1663 
1664 	/* TX4939 does not have NCarr */
1665 	if (lp->chiptype == TC35815_TX4939)
1666 		status &= ~Tx_NCarr;
1667 	/* WORKAROUND: ignore LostCrS in full duplex operation */
1668 	if (!lp->link || lp->duplex == DUPLEX_FULL)
1669 		status &= ~Tx_NCarr;
1670 
1671 	if (!(status & TX_STA_ERR)) {
1672 		/* no error. */
1673 		dev->stats.tx_packets++;
1674 		return;
1675 	}
1676 
1677 	dev->stats.tx_errors++;
1678 	if (status & Tx_ExColl) {
1679 		dev->stats.tx_aborted_errors++;
1680 		msg = "Excessive Collision.";
1681 	}
1682 	if (status & Tx_Under) {
1683 		dev->stats.tx_fifo_errors++;
1684 		msg = "Tx FIFO Underrun.";
1685 		if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) {
1686 			lp->lstats.tx_underrun++;
1687 			if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) {
1688 				struct tc35815_regs __iomem *tr =
1689 					(struct tc35815_regs __iomem *)dev->base_addr;
1690 				tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh);
1691 				msg = "Tx FIFO Underrun.Change Tx threshold to max.";
1692 			}
1693 		}
1694 	}
1695 	if (status & Tx_Defer) {
1696 		dev->stats.tx_fifo_errors++;
1697 		msg = "Excessive Deferral.";
1698 	}
1699 	if (status & Tx_NCarr) {
1700 		dev->stats.tx_carrier_errors++;
1701 		msg = "Lost Carrier Sense.";
1702 	}
1703 	if (status & Tx_LateColl) {
1704 		dev->stats.tx_aborted_errors++;
1705 		msg = "Late Collision.";
1706 	}
1707 	if (status & Tx_TxPar) {
1708 		dev->stats.tx_fifo_errors++;
1709 		msg = "Transmit Parity Error.";
1710 	}
1711 	if (status & Tx_SQErr) {
1712 		dev->stats.tx_heartbeat_errors++;
1713 		msg = "Signal Quality Error.";
1714 	}
1715 	if (msg && netif_msg_tx_err(lp))
1716 		printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status);
1717 }
1718 
1719 /* This handles TX complete events posted by the device
1720  * via interrupts.
1721  */
1722 static void
1723 tc35815_txdone(struct net_device *dev)
1724 {
1725 	struct tc35815_local *lp = netdev_priv(dev);
1726 	struct TxFD *txfd;
1727 	unsigned int fdctl;
1728 
1729 	txfd = &lp->tfd_base[lp->tfd_end];
1730 	while (lp->tfd_start != lp->tfd_end &&
1731 	       !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) {
1732 		int status = le32_to_cpu(txfd->fd.FDStat);
1733 		struct sk_buff *skb;
1734 		unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext);
1735 		u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem);
1736 
1737 		if (netif_msg_tx_done(lp)) {
1738 			printk("%s: complete TxFD.\n", dev->name);
1739 			dump_txfd(txfd);
1740 		}
1741 		tc35815_check_tx_stat(dev, status);
1742 
1743 		skb = fdsystem != 0xffffffff ?
1744 			lp->tx_skbs[fdsystem].skb : NULL;
1745 #ifdef DEBUG
1746 		if (lp->tx_skbs[lp->tfd_end].skb != skb) {
1747 			printk("%s: tx_skbs mismatch.\n", dev->name);
1748 			panic_queues(dev);
1749 		}
1750 #else
1751 		BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb);
1752 #endif
1753 		if (skb) {
1754 			dev->stats.tx_bytes += skb->len;
1755 			pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE);
1756 			lp->tx_skbs[lp->tfd_end].skb = NULL;
1757 			lp->tx_skbs[lp->tfd_end].skb_dma = 0;
1758 			dev_kfree_skb_any(skb);
1759 		}
1760 		txfd->fd.FDSystem = cpu_to_le32(0xffffffff);
1761 
1762 		lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM;
1763 		txfd = &lp->tfd_base[lp->tfd_end];
1764 #ifdef DEBUG
1765 		if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) {
1766 			printk("%s: TxFD FDNext invalid.\n", dev->name);
1767 			panic_queues(dev);
1768 		}
1769 #endif
1770 		if (fdnext & FD_Next_EOL) {
1771 			/* DMA Transmitter has been stopping... */
1772 			if (lp->tfd_end != lp->tfd_start) {
1773 				struct tc35815_regs __iomem *tr =
1774 					(struct tc35815_regs __iomem *)dev->base_addr;
1775 				int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
1776 				struct TxFD *txhead = &lp->tfd_base[head];
1777 				int qlen = (lp->tfd_start + TX_FD_NUM
1778 					    - lp->tfd_end) % TX_FD_NUM;
1779 
1780 #ifdef DEBUG
1781 				if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) {
1782 					printk("%s: TxFD FDCtl invalid.\n", dev->name);
1783 					panic_queues(dev);
1784 				}
1785 #endif
1786 				/* log max queue length */
1787 				if (lp->lstats.max_tx_qlen < qlen)
1788 					lp->lstats.max_tx_qlen = qlen;
1789 
1790 
1791 				/* start DMA Transmitter again */
1792 				txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1793 				txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1794 				if (netif_msg_tx_queued(lp)) {
1795 					printk("%s: start TxFD on queue.\n",
1796 					       dev->name);
1797 					dump_txfd(txfd);
1798 				}
1799 				tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1800 			}
1801 			break;
1802 		}
1803 	}
1804 
1805 	/* If we had stopped the queue due to a "tx full"
1806 	 * condition, and space has now been made available,
1807 	 * wake up the queue.
1808 	 */
1809 	if (netif_queue_stopped(dev) && !tc35815_tx_full(dev))
1810 		netif_wake_queue(dev);
1811 }
1812 
1813 /* The inverse routine to tc35815_open(). */
1814 static int
1815 tc35815_close(struct net_device *dev)
1816 {
1817 	struct tc35815_local *lp = netdev_priv(dev);
1818 
1819 	netif_stop_queue(dev);
1820 	napi_disable(&lp->napi);
1821 	if (dev->phydev)
1822 		phy_stop(dev->phydev);
1823 	cancel_work_sync(&lp->restart_work);
1824 
1825 	/* Flush the Tx and disable Rx here. */
1826 	tc35815_chip_reset(dev);
1827 	free_irq(dev->irq, dev);
1828 
1829 	tc35815_free_queues(dev);
1830 
1831 	return 0;
1832 
1833 }
1834 
1835 /*
1836  * Get the current statistics.
1837  * This may be called with the card open or closed.
1838  */
1839 static struct net_device_stats *tc35815_get_stats(struct net_device *dev)
1840 {
1841 	struct tc35815_regs __iomem *tr =
1842 		(struct tc35815_regs __iomem *)dev->base_addr;
1843 	if (netif_running(dev))
1844 		/* Update the statistics from the device registers. */
1845 		dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt);
1846 
1847 	return &dev->stats;
1848 }
1849 
1850 static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr)
1851 {
1852 	struct tc35815_local *lp = netdev_priv(dev);
1853 	struct tc35815_regs __iomem *tr =
1854 		(struct tc35815_regs __iomem *)dev->base_addr;
1855 	int cam_index = index * 6;
1856 	u32 cam_data;
1857 	u32 saved_addr;
1858 
1859 	saved_addr = tc_readl(&tr->CAM_Adr);
1860 
1861 	if (netif_msg_hw(lp))
1862 		printk(KERN_DEBUG "%s: CAM %d: %pM\n",
1863 			dev->name, index, addr);
1864 	if (index & 1) {
1865 		/* read modify write */
1866 		tc_writel(cam_index - 2, &tr->CAM_Adr);
1867 		cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
1868 		cam_data |= addr[0] << 8 | addr[1];
1869 		tc_writel(cam_data, &tr->CAM_Data);
1870 		/* write whole word */
1871 		tc_writel(cam_index + 2, &tr->CAM_Adr);
1872 		cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
1873 		tc_writel(cam_data, &tr->CAM_Data);
1874 	} else {
1875 		/* write whole word */
1876 		tc_writel(cam_index, &tr->CAM_Adr);
1877 		cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1878 		tc_writel(cam_data, &tr->CAM_Data);
1879 		/* read modify write */
1880 		tc_writel(cam_index + 4, &tr->CAM_Adr);
1881 		cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
1882 		cam_data |= addr[4] << 24 | (addr[5] << 16);
1883 		tc_writel(cam_data, &tr->CAM_Data);
1884 	}
1885 
1886 	tc_writel(saved_addr, &tr->CAM_Adr);
1887 }
1888 
1889 
1890 /*
1891  * Set or clear the multicast filter for this adaptor.
1892  * num_addrs == -1	Promiscuous mode, receive all packets
1893  * num_addrs == 0	Normal mode, clear multicast list
1894  * num_addrs > 0	Multicast mode, receive normal and MC packets,
1895  *			and do best-effort filtering.
1896  */
1897 static void
1898 tc35815_set_multicast_list(struct net_device *dev)
1899 {
1900 	struct tc35815_regs __iomem *tr =
1901 		(struct tc35815_regs __iomem *)dev->base_addr;
1902 
1903 	if (dev->flags & IFF_PROMISC) {
1904 		/* With some (all?) 100MHalf HUB, controller will hang
1905 		 * if we enabled promiscuous mode before linkup... */
1906 		struct tc35815_local *lp = netdev_priv(dev);
1907 
1908 		if (!lp->link)
1909 			return;
1910 		/* Enable promiscuous mode */
1911 		tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
1912 	} else if ((dev->flags & IFF_ALLMULTI) ||
1913 		  netdev_mc_count(dev) > CAM_ENTRY_MAX - 3) {
1914 		/* CAM 0, 1, 20 are reserved. */
1915 		/* Disable promiscuous mode, use normal mode. */
1916 		tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
1917 	} else if (!netdev_mc_empty(dev)) {
1918 		struct netdev_hw_addr *ha;
1919 		int i;
1920 		int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
1921 
1922 		tc_writel(0, &tr->CAM_Ctl);
1923 		/* Walk the address list, and load the filter */
1924 		i = 0;
1925 		netdev_for_each_mc_addr(ha, dev) {
1926 			/* entry 0,1 is reserved. */
1927 			tc35815_set_cam_entry(dev, i + 2, ha->addr);
1928 			ena_bits |= CAM_Ena_Bit(i + 2);
1929 			i++;
1930 		}
1931 		tc_writel(ena_bits, &tr->CAM_Ena);
1932 		tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1933 	} else {
1934 		tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
1935 		tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1936 	}
1937 }
1938 
1939 static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1940 {
1941 	struct tc35815_local *lp = netdev_priv(dev);
1942 
1943 	strlcpy(info->driver, MODNAME, sizeof(info->driver));
1944 	strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1945 	strlcpy(info->bus_info, pci_name(lp->pci_dev), sizeof(info->bus_info));
1946 }
1947 
1948 static u32 tc35815_get_msglevel(struct net_device *dev)
1949 {
1950 	struct tc35815_local *lp = netdev_priv(dev);
1951 	return lp->msg_enable;
1952 }
1953 
1954 static void tc35815_set_msglevel(struct net_device *dev, u32 datum)
1955 {
1956 	struct tc35815_local *lp = netdev_priv(dev);
1957 	lp->msg_enable = datum;
1958 }
1959 
1960 static int tc35815_get_sset_count(struct net_device *dev, int sset)
1961 {
1962 	struct tc35815_local *lp = netdev_priv(dev);
1963 
1964 	switch (sset) {
1965 	case ETH_SS_STATS:
1966 		return sizeof(lp->lstats) / sizeof(int);
1967 	default:
1968 		return -EOPNOTSUPP;
1969 	}
1970 }
1971 
1972 static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
1973 {
1974 	struct tc35815_local *lp = netdev_priv(dev);
1975 	data[0] = lp->lstats.max_tx_qlen;
1976 	data[1] = lp->lstats.tx_ints;
1977 	data[2] = lp->lstats.rx_ints;
1978 	data[3] = lp->lstats.tx_underrun;
1979 }
1980 
1981 static struct {
1982 	const char str[ETH_GSTRING_LEN];
1983 } ethtool_stats_keys[] = {
1984 	{ "max_tx_qlen" },
1985 	{ "tx_ints" },
1986 	{ "rx_ints" },
1987 	{ "tx_underrun" },
1988 };
1989 
1990 static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1991 {
1992 	memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
1993 }
1994 
1995 static const struct ethtool_ops tc35815_ethtool_ops = {
1996 	.get_drvinfo		= tc35815_get_drvinfo,
1997 	.get_link		= ethtool_op_get_link,
1998 	.get_msglevel		= tc35815_get_msglevel,
1999 	.set_msglevel		= tc35815_set_msglevel,
2000 	.get_strings		= tc35815_get_strings,
2001 	.get_sset_count		= tc35815_get_sset_count,
2002 	.get_ethtool_stats	= tc35815_get_ethtool_stats,
2003 	.get_link_ksettings = phy_ethtool_get_link_ksettings,
2004 	.set_link_ksettings = phy_ethtool_set_link_ksettings,
2005 };
2006 
2007 static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2008 {
2009 	if (!netif_running(dev))
2010 		return -EINVAL;
2011 	if (!dev->phydev)
2012 		return -ENODEV;
2013 	return phy_mii_ioctl(dev->phydev, rq, cmd);
2014 }
2015 
2016 static void tc35815_chip_reset(struct net_device *dev)
2017 {
2018 	struct tc35815_regs __iomem *tr =
2019 		(struct tc35815_regs __iomem *)dev->base_addr;
2020 	int i;
2021 	/* reset the controller */
2022 	tc_writel(MAC_Reset, &tr->MAC_Ctl);
2023 	udelay(4); /* 3200ns */
2024 	i = 0;
2025 	while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) {
2026 		if (i++ > 100) {
2027 			printk(KERN_ERR "%s: MAC reset failed.\n", dev->name);
2028 			break;
2029 		}
2030 		mdelay(1);
2031 	}
2032 	tc_writel(0, &tr->MAC_Ctl);
2033 
2034 	/* initialize registers to default value */
2035 	tc_writel(0, &tr->DMA_Ctl);
2036 	tc_writel(0, &tr->TxThrsh);
2037 	tc_writel(0, &tr->TxPollCtr);
2038 	tc_writel(0, &tr->RxFragSize);
2039 	tc_writel(0, &tr->Int_En);
2040 	tc_writel(0, &tr->FDA_Bas);
2041 	tc_writel(0, &tr->FDA_Lim);
2042 	tc_writel(0xffffffff, &tr->Int_Src);	/* Write 1 to clear */
2043 	tc_writel(0, &tr->CAM_Ctl);
2044 	tc_writel(0, &tr->Tx_Ctl);
2045 	tc_writel(0, &tr->Rx_Ctl);
2046 	tc_writel(0, &tr->CAM_Ena);
2047 	(void)tc_readl(&tr->Miss_Cnt);	/* Read to clear */
2048 
2049 	/* initialize internal SRAM */
2050 	tc_writel(DMA_TestMode, &tr->DMA_Ctl);
2051 	for (i = 0; i < 0x1000; i += 4) {
2052 		tc_writel(i, &tr->CAM_Adr);
2053 		tc_writel(0, &tr->CAM_Data);
2054 	}
2055 	tc_writel(0, &tr->DMA_Ctl);
2056 }
2057 
2058 static void tc35815_chip_init(struct net_device *dev)
2059 {
2060 	struct tc35815_local *lp = netdev_priv(dev);
2061 	struct tc35815_regs __iomem *tr =
2062 		(struct tc35815_regs __iomem *)dev->base_addr;
2063 	unsigned long txctl = TX_CTL_CMD;
2064 
2065 	/* load station address to CAM */
2066 	tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr);
2067 
2068 	/* Enable CAM (broadcast and unicast) */
2069 	tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2070 	tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2071 
2072 	/* Use DMA_RxAlign_2 to make IP header 4-byte aligned. */
2073 	if (HAVE_DMA_RXALIGN(lp))
2074 		tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl);
2075 	else
2076 		tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
2077 	tc_writel(0, &tr->TxPollCtr);	/* Batch mode */
2078 	tc_writel(TX_THRESHOLD, &tr->TxThrsh);
2079 	tc_writel(INT_EN_CMD, &tr->Int_En);
2080 
2081 	/* set queues */
2082 	tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas);
2083 	tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
2084 		  &tr->FDA_Lim);
2085 	/*
2086 	 * Activation method:
2087 	 * First, enable the MAC Transmitter and the DMA Receive circuits.
2088 	 * Then enable the DMA Transmitter and the MAC Receive circuits.
2089 	 */
2090 	tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr);	/* start DMA receiver */
2091 	tc_writel(RX_CTL_CMD, &tr->Rx_Ctl);	/* start MAC receiver */
2092 
2093 	/* start MAC transmitter */
2094 	/* TX4939 does not have EnLCarr */
2095 	if (lp->chiptype == TC35815_TX4939)
2096 		txctl &= ~Tx_EnLCarr;
2097 	/* WORKAROUND: ignore LostCrS in full duplex operation */
2098 	if (!dev->phydev || !lp->link || lp->duplex == DUPLEX_FULL)
2099 		txctl &= ~Tx_EnLCarr;
2100 	tc_writel(txctl, &tr->Tx_Ctl);
2101 }
2102 
2103 #ifdef CONFIG_PM
2104 static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state)
2105 {
2106 	struct net_device *dev = pci_get_drvdata(pdev);
2107 	struct tc35815_local *lp = netdev_priv(dev);
2108 	unsigned long flags;
2109 
2110 	pci_save_state(pdev);
2111 	if (!netif_running(dev))
2112 		return 0;
2113 	netif_device_detach(dev);
2114 	if (dev->phydev)
2115 		phy_stop(dev->phydev);
2116 	spin_lock_irqsave(&lp->lock, flags);
2117 	tc35815_chip_reset(dev);
2118 	spin_unlock_irqrestore(&lp->lock, flags);
2119 	pci_set_power_state(pdev, PCI_D3hot);
2120 	return 0;
2121 }
2122 
2123 static int tc35815_resume(struct pci_dev *pdev)
2124 {
2125 	struct net_device *dev = pci_get_drvdata(pdev);
2126 
2127 	pci_restore_state(pdev);
2128 	if (!netif_running(dev))
2129 		return 0;
2130 	pci_set_power_state(pdev, PCI_D0);
2131 	tc35815_restart(dev);
2132 	netif_carrier_off(dev);
2133 	if (dev->phydev)
2134 		phy_start(dev->phydev);
2135 	netif_device_attach(dev);
2136 	return 0;
2137 }
2138 #endif /* CONFIG_PM */
2139 
2140 static struct pci_driver tc35815_pci_driver = {
2141 	.name		= MODNAME,
2142 	.id_table	= tc35815_pci_tbl,
2143 	.probe		= tc35815_init_one,
2144 	.remove		= tc35815_remove_one,
2145 #ifdef CONFIG_PM
2146 	.suspend	= tc35815_suspend,
2147 	.resume		= tc35815_resume,
2148 #endif
2149 };
2150 
2151 module_param_named(speed, options.speed, int, 0);
2152 MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps");
2153 module_param_named(duplex, options.duplex, int, 0);
2154 MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full");
2155 
2156 module_pci_driver(tc35815_pci_driver);
2157 MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver");
2158 MODULE_LICENSE("GPL");
2159