1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Network device driver for Cell Processor-Based Blade and Celleb platform 4 * 5 * (C) Copyright IBM Corp. 2005 6 * (C) Copyright 2006 TOSHIBA CORPORATION 7 * 8 * Authors : Utz Bacher <utz.bacher@de.ibm.com> 9 * Jens Osterkamp <Jens.Osterkamp@de.ibm.com> 10 */ 11 12 #ifndef _SPIDER_NET_H 13 #define _SPIDER_NET_H 14 15 #define VERSION "2.0 B" 16 17 #include <linux/sungem_phy.h> 18 19 int spider_net_stop(struct net_device *netdev); 20 int spider_net_open(struct net_device *netdev); 21 22 extern const struct ethtool_ops spider_net_ethtool_ops; 23 24 extern char spider_net_driver_name[]; 25 26 #define SPIDER_NET_MAX_FRAME 2312 27 #define SPIDER_NET_MAX_MTU 2294 28 #define SPIDER_NET_MIN_MTU 64 29 30 #define SPIDER_NET_RXBUF_ALIGN 128 31 32 #define SPIDER_NET_RX_DESCRIPTORS_DEFAULT 256 33 #define SPIDER_NET_RX_DESCRIPTORS_MIN 16 34 #define SPIDER_NET_RX_DESCRIPTORS_MAX 512 35 36 #define SPIDER_NET_TX_DESCRIPTORS_DEFAULT 256 37 #define SPIDER_NET_TX_DESCRIPTORS_MIN 16 38 #define SPIDER_NET_TX_DESCRIPTORS_MAX 512 39 40 #define SPIDER_NET_TX_TIMER (HZ/5) 41 #define SPIDER_NET_ANEG_TIMER (HZ) 42 #define SPIDER_NET_ANEG_TIMEOUT 5 43 44 #define SPIDER_NET_RX_CSUM_DEFAULT 1 45 46 #define SPIDER_NET_WATCHDOG_TIMEOUT 50*HZ 47 #define SPIDER_NET_NAPI_WEIGHT 64 48 49 #define SPIDER_NET_FIRMWARE_SEQS 6 50 #define SPIDER_NET_FIRMWARE_SEQWORDS 1024 51 #define SPIDER_NET_FIRMWARE_LEN (SPIDER_NET_FIRMWARE_SEQS * \ 52 SPIDER_NET_FIRMWARE_SEQWORDS * \ 53 sizeof(u32)) 54 #define SPIDER_NET_FIRMWARE_NAME "spider_fw.bin" 55 56 /** spider_net SMMIO registers */ 57 #define SPIDER_NET_GHIINT0STS 0x00000000 58 #define SPIDER_NET_GHIINT1STS 0x00000004 59 #define SPIDER_NET_GHIINT2STS 0x00000008 60 #define SPIDER_NET_GHIINT0MSK 0x00000010 61 #define SPIDER_NET_GHIINT1MSK 0x00000014 62 #define SPIDER_NET_GHIINT2MSK 0x00000018 63 64 #define SPIDER_NET_GRESUMINTNUM 0x00000020 65 #define SPIDER_NET_GREINTNUM 0x00000024 66 67 #define SPIDER_NET_GFFRMNUM 0x00000028 68 #define SPIDER_NET_GFAFRMNUM 0x0000002c 69 #define SPIDER_NET_GFBFRMNUM 0x00000030 70 #define SPIDER_NET_GFCFRMNUM 0x00000034 71 #define SPIDER_NET_GFDFRMNUM 0x00000038 72 73 /* clear them (don't use it) */ 74 #define SPIDER_NET_GFREECNNUM 0x0000003c 75 #define SPIDER_NET_GONETIMENUM 0x00000040 76 77 #define SPIDER_NET_GTOUTFRMNUM 0x00000044 78 79 #define SPIDER_NET_GTXMDSET 0x00000050 80 #define SPIDER_NET_GPCCTRL 0x00000054 81 #define SPIDER_NET_GRXMDSET 0x00000058 82 #define SPIDER_NET_GIPSECINIT 0x0000005c 83 #define SPIDER_NET_GFTRESTRT 0x00000060 84 #define SPIDER_NET_GRXDMAEN 0x00000064 85 #define SPIDER_NET_GMRWOLCTRL 0x00000068 86 #define SPIDER_NET_GPCWOPCMD 0x0000006c 87 #define SPIDER_NET_GPCROPCMD 0x00000070 88 #define SPIDER_NET_GTTFRMCNT 0x00000078 89 #define SPIDER_NET_GTESTMD 0x0000007c 90 91 #define SPIDER_NET_GSINIT 0x00000080 92 #define SPIDER_NET_GSnPRGADR 0x00000084 93 #define SPIDER_NET_GSnPRGDAT 0x00000088 94 95 #define SPIDER_NET_GMACOPEMD 0x00000100 96 #define SPIDER_NET_GMACLENLMT 0x00000108 97 #define SPIDER_NET_GMACST 0x00000110 98 #define SPIDER_NET_GMACINTEN 0x00000118 99 #define SPIDER_NET_GMACPHYCTRL 0x00000120 100 101 #define SPIDER_NET_GMACAPAUSE 0x00000154 102 #define SPIDER_NET_GMACTXPAUSE 0x00000164 103 104 #define SPIDER_NET_GMACMODE 0x000001b0 105 #define SPIDER_NET_GMACBSTLMT 0x000001b4 106 107 #define SPIDER_NET_GMACUNIMACU 0x000001c0 108 #define SPIDER_NET_GMACUNIMACL 0x000001c8 109 110 #define SPIDER_NET_GMRMHFILnR 0x00000400 111 #define SPIDER_NET_MULTICAST_HASHES 256 112 113 #define SPIDER_NET_GMRUAFILnR 0x00000500 114 #define SPIDER_NET_GMRUA0FIL15R 0x00000578 115 116 #define SPIDER_NET_GTTQMSK 0x00000934 117 118 /* RX DMA controller registers, all 0x00000a.. are for DMA controller A, 119 * 0x00000b.. for DMA controller B, etc. */ 120 #define SPIDER_NET_GDADCHA 0x00000a00 121 #define SPIDER_NET_GDADMACCNTR 0x00000a04 122 #define SPIDER_NET_GDACTDPA 0x00000a08 123 #define SPIDER_NET_GDACTDCNT 0x00000a0c 124 #define SPIDER_NET_GDACDBADDR 0x00000a20 125 #define SPIDER_NET_GDACDBSIZE 0x00000a24 126 #define SPIDER_NET_GDACNEXTDA 0x00000a28 127 #define SPIDER_NET_GDACCOMST 0x00000a2c 128 #define SPIDER_NET_GDAWBCOMST 0x00000a30 129 #define SPIDER_NET_GDAWBRSIZE 0x00000a34 130 #define SPIDER_NET_GDAWBVSIZE 0x00000a38 131 #define SPIDER_NET_GDAWBTRST 0x00000a3c 132 #define SPIDER_NET_GDAWBTRERR 0x00000a40 133 134 /* TX DMA controller registers */ 135 #define SPIDER_NET_GDTDCHA 0x00000e00 136 #define SPIDER_NET_GDTDMACCNTR 0x00000e04 137 #define SPIDER_NET_GDTCDPA 0x00000e08 138 #define SPIDER_NET_GDTDMASEL 0x00000e14 139 140 #define SPIDER_NET_ECMODE 0x00000f00 141 /* clock and reset control register */ 142 #define SPIDER_NET_CKRCTRL 0x00000ff0 143 144 /** SCONFIG registers */ 145 #define SPIDER_NET_SCONFIG_IOACTE 0x00002810 146 147 /** interrupt mask registers */ 148 #define SPIDER_NET_INT0_MASK_VALUE 0x3f7fe2c7 149 #define SPIDER_NET_INT1_MASK_VALUE 0x0000fff2 150 #define SPIDER_NET_INT2_MASK_VALUE 0x000003f1 151 152 /* we rely on flagged descriptor interrupts */ 153 #define SPIDER_NET_FRAMENUM_VALUE 0x00000000 154 /* set this first, then the FRAMENUM_VALUE */ 155 #define SPIDER_NET_GFXFRAMES_VALUE 0x00000000 156 157 #define SPIDER_NET_STOP_SEQ_VALUE 0x00000000 158 #define SPIDER_NET_RUN_SEQ_VALUE 0x0000007e 159 160 #define SPIDER_NET_PHY_CTRL_VALUE 0x00040040 161 /* #define SPIDER_NET_PHY_CTRL_VALUE 0x01070080*/ 162 #define SPIDER_NET_RXMODE_VALUE 0x00000011 163 /* auto retransmission in case of MAC aborts */ 164 #define SPIDER_NET_TXMODE_VALUE 0x00010000 165 #define SPIDER_NET_RESTART_VALUE 0x00000000 166 #define SPIDER_NET_WOL_VALUE 0x00001111 167 #if 0 168 #define SPIDER_NET_WOL_VALUE 0x00000000 169 #endif 170 #define SPIDER_NET_IPSECINIT_VALUE 0x6f716f71 171 172 /* pause frames: automatic, no upper retransmission count */ 173 /* outside loopback mode: ETOMOD signal dont matter, not connected */ 174 /* ETOMOD signal is brought to PHY reset. bit 2 must be 1 in Celleb */ 175 #define SPIDER_NET_OPMODE_VALUE 0x00000067 176 /*#define SPIDER_NET_OPMODE_VALUE 0x001b0062*/ 177 #define SPIDER_NET_LENLMT_VALUE 0x00000908 178 179 #define SPIDER_NET_MACAPAUSE_VALUE 0x00000800 /* about 1 ms */ 180 #define SPIDER_NET_TXPAUSE_VALUE 0x00000000 181 182 #define SPIDER_NET_MACMODE_VALUE 0x00000001 183 #define SPIDER_NET_BURSTLMT_VALUE 0x00000200 /* about 16 us */ 184 185 /* DMAC control register GDMACCNTR 186 * 187 * 1(0) enable r/tx dma 188 * 0000000 fixed to 0 189 * 190 * 000000 fixed to 0 191 * 0(1) en/disable descr writeback on force end 192 * 0(1) force end 193 * 194 * 000000 fixed to 0 195 * 00 burst alignment: 128 bytes 196 * 11 burst alignment: 1024 bytes 197 * 198 * 00000 fixed to 0 199 * 0 descr writeback size 32 bytes 200 * 0(1) descr chain end interrupt enable 201 * 0(1) descr status writeback enable */ 202 203 /* to set RX_DMA_EN */ 204 #define SPIDER_NET_DMA_RX_VALUE 0x80000000 205 #define SPIDER_NET_DMA_RX_FEND_VALUE 0x00030003 206 /* to set TX_DMA_EN */ 207 #define SPIDER_NET_TX_DMA_EN 0x80000000 208 #define SPIDER_NET_GDTBSTA 0x00000300 209 #define SPIDER_NET_GDTDCEIDIS 0x00000002 210 #define SPIDER_NET_DMA_TX_VALUE SPIDER_NET_TX_DMA_EN | \ 211 SPIDER_NET_GDTDCEIDIS | \ 212 SPIDER_NET_GDTBSTA 213 214 #define SPIDER_NET_DMA_TX_FEND_VALUE 0x00030003 215 216 /* SPIDER_NET_UA_DESCR_VALUE is OR'ed with the unicast address */ 217 #define SPIDER_NET_UA_DESCR_VALUE 0x00080000 218 #define SPIDER_NET_PROMISC_VALUE 0x00080000 219 #define SPIDER_NET_NONPROMISC_VALUE 0x00000000 220 221 #define SPIDER_NET_DMASEL_VALUE 0x00000001 222 223 #define SPIDER_NET_ECMODE_VALUE 0x00000000 224 225 #define SPIDER_NET_CKRCTRL_RUN_VALUE 0x1fff010f 226 #define SPIDER_NET_CKRCTRL_STOP_VALUE 0x0000010f 227 228 #define SPIDER_NET_SBIMSTATE_VALUE 0x00000000 229 #define SPIDER_NET_SBTMSTATE_VALUE 0x00000000 230 231 /* SPIDER_NET_GHIINT0STS bits, in reverse order so that they can be used 232 * with 1 << SPIDER_NET_... */ 233 enum spider_net_int0_status { 234 SPIDER_NET_GPHYINT = 0, 235 SPIDER_NET_GMAC2INT, 236 SPIDER_NET_GMAC1INT, 237 SPIDER_NET_GIPSINT, 238 SPIDER_NET_GFIFOINT, 239 SPIDER_NET_GDMACINT, 240 SPIDER_NET_GSYSINT, 241 SPIDER_NET_GPWOPCMPINT, 242 SPIDER_NET_GPROPCMPINT, 243 SPIDER_NET_GPWFFINT, 244 SPIDER_NET_GRMDADRINT, 245 SPIDER_NET_GRMARPINT, 246 SPIDER_NET_GRMMPINT, 247 SPIDER_NET_GDTDEN0INT, 248 SPIDER_NET_GDDDEN0INT, 249 SPIDER_NET_GDCDEN0INT, 250 SPIDER_NET_GDBDEN0INT, 251 SPIDER_NET_GDADEN0INT, 252 SPIDER_NET_GDTFDCINT, 253 SPIDER_NET_GDDFDCINT, 254 SPIDER_NET_GDCFDCINT, 255 SPIDER_NET_GDBFDCINT, 256 SPIDER_NET_GDAFDCINT, 257 SPIDER_NET_GTTEDINT, 258 SPIDER_NET_GDTDCEINT, 259 SPIDER_NET_GRFDNMINT, 260 SPIDER_NET_GRFCNMINT, 261 SPIDER_NET_GRFBNMINT, 262 SPIDER_NET_GRFANMINT, 263 SPIDER_NET_GRFNMINT, 264 SPIDER_NET_G1TMCNTINT, 265 SPIDER_NET_GFREECNTINT 266 }; 267 /* GHIINT1STS bits */ 268 enum spider_net_int1_status { 269 SPIDER_NET_GTMFLLINT = 0, 270 SPIDER_NET_GRMFLLINT, 271 SPIDER_NET_GTMSHTINT, 272 SPIDER_NET_GDTINVDINT, 273 SPIDER_NET_GRFDFLLINT, 274 SPIDER_NET_GDDDCEINT, 275 SPIDER_NET_GDDINVDINT, 276 SPIDER_NET_GRFCFLLINT, 277 SPIDER_NET_GDCDCEINT, 278 SPIDER_NET_GDCINVDINT, 279 SPIDER_NET_GRFBFLLINT, 280 SPIDER_NET_GDBDCEINT, 281 SPIDER_NET_GDBINVDINT, 282 SPIDER_NET_GRFAFLLINT, 283 SPIDER_NET_GDADCEINT, 284 SPIDER_NET_GDAINVDINT, 285 SPIDER_NET_GDTRSERINT, 286 SPIDER_NET_GDDRSERINT, 287 SPIDER_NET_GDCRSERINT, 288 SPIDER_NET_GDBRSERINT, 289 SPIDER_NET_GDARSERINT, 290 SPIDER_NET_GDSERINT, 291 SPIDER_NET_GDTPTERINT, 292 SPIDER_NET_GDDPTERINT, 293 SPIDER_NET_GDCPTERINT, 294 SPIDER_NET_GDBPTERINT, 295 SPIDER_NET_GDAPTERINT 296 }; 297 /* GHIINT2STS bits */ 298 enum spider_net_int2_status { 299 SPIDER_NET_GPROPERINT = 0, 300 SPIDER_NET_GMCTCRSNGINT, 301 SPIDER_NET_GMCTLCOLINT, 302 SPIDER_NET_GMCTTMOTINT, 303 SPIDER_NET_GMCRCAERINT, 304 SPIDER_NET_GMCRCALERINT, 305 SPIDER_NET_GMCRALNERINT, 306 SPIDER_NET_GMCROVRINT, 307 SPIDER_NET_GMCRRNTINT, 308 SPIDER_NET_GMCRRXERINT, 309 SPIDER_NET_GTITCSERINT, 310 SPIDER_NET_GTIFMTERINT, 311 SPIDER_NET_GTIPKTRVKINT, 312 SPIDER_NET_GTISPINGINT, 313 SPIDER_NET_GTISADNGINT, 314 SPIDER_NET_GTISPDNGINT, 315 SPIDER_NET_GRIFMTERINT, 316 SPIDER_NET_GRIPKTRVKINT, 317 SPIDER_NET_GRISPINGINT, 318 SPIDER_NET_GRISADNGINT, 319 SPIDER_NET_GRISPDNGINT 320 }; 321 322 #define SPIDER_NET_TXINT (1 << SPIDER_NET_GDTFDCINT) 323 324 /* We rely on flagged descriptor interrupts */ 325 #define SPIDER_NET_RXINT ( (1 << SPIDER_NET_GDAFDCINT) ) 326 327 #define SPIDER_NET_LINKINT ( 1 << SPIDER_NET_GMAC2INT ) 328 329 #define SPIDER_NET_ERRINT ( 0xffffffff & \ 330 (~SPIDER_NET_TXINT) & \ 331 (~SPIDER_NET_RXINT) & \ 332 (~SPIDER_NET_LINKINT) ) 333 334 #define SPIDER_NET_GPREXEC 0x80000000 335 #define SPIDER_NET_GPRDAT_MASK 0x0000ffff 336 337 #define SPIDER_NET_DMAC_NOINTR_COMPLETE 0x00800000 338 #define SPIDER_NET_DMAC_TXFRMTL 0x00040000 339 #define SPIDER_NET_DMAC_TCP 0x00020000 340 #define SPIDER_NET_DMAC_UDP 0x00030000 341 #define SPIDER_NET_TXDCEST 0x08000000 342 343 #define SPIDER_NET_DESCR_RXFDIS 0x00000001 344 #define SPIDER_NET_DESCR_RXDCEIS 0x00000002 345 #define SPIDER_NET_DESCR_RXDEN0IS 0x00000004 346 #define SPIDER_NET_DESCR_RXINVDIS 0x00000008 347 #define SPIDER_NET_DESCR_RXRERRIS 0x00000010 348 #define SPIDER_NET_DESCR_RXFDCIMS 0x00000100 349 #define SPIDER_NET_DESCR_RXDCEIMS 0x00000200 350 #define SPIDER_NET_DESCR_RXDEN0IMS 0x00000400 351 #define SPIDER_NET_DESCR_RXINVDIMS 0x00000800 352 #define SPIDER_NET_DESCR_RXRERRMIS 0x00001000 353 #define SPIDER_NET_DESCR_UNUSED 0x077fe0e0 354 355 #define SPIDER_NET_DESCR_IND_PROC_MASK 0xF0000000 356 #define SPIDER_NET_DESCR_COMPLETE 0x00000000 /* used in rx and tx */ 357 #define SPIDER_NET_DESCR_RESPONSE_ERROR 0x10000000 /* used in rx and tx */ 358 #define SPIDER_NET_DESCR_PROTECTION_ERROR 0x20000000 /* used in rx and tx */ 359 #define SPIDER_NET_DESCR_FRAME_END 0x40000000 /* used in rx */ 360 #define SPIDER_NET_DESCR_FORCE_END 0x50000000 /* used in rx and tx */ 361 #define SPIDER_NET_DESCR_CARDOWNED 0xA0000000 /* used in rx and tx */ 362 #define SPIDER_NET_DESCR_NOT_IN_USE 0xF0000000 363 #define SPIDER_NET_DESCR_TXDESFLG 0x00800000 364 365 #define SPIDER_NET_DESCR_BAD_STATUS (SPIDER_NET_DESCR_RXDEN0IS | \ 366 SPIDER_NET_DESCR_RXRERRIS | \ 367 SPIDER_NET_DESCR_RXDEN0IMS | \ 368 SPIDER_NET_DESCR_RXINVDIMS | \ 369 SPIDER_NET_DESCR_RXRERRMIS | \ 370 SPIDER_NET_DESCR_UNUSED) 371 372 /* Descriptor, as defined by the hardware */ 373 struct spider_net_hw_descr { 374 u32 buf_addr; 375 u32 buf_size; 376 u32 next_descr_addr; 377 u32 dmac_cmd_status; 378 u32 result_size; 379 u32 valid_size; /* all zeroes for tx */ 380 u32 data_status; 381 u32 data_error; /* all zeroes for tx */ 382 } __attribute__((aligned(32))); 383 384 struct spider_net_descr { 385 struct spider_net_hw_descr *hwdescr; 386 struct sk_buff *skb; 387 u32 bus_addr; 388 struct spider_net_descr *next; 389 struct spider_net_descr *prev; 390 }; 391 392 struct spider_net_descr_chain { 393 spinlock_t lock; 394 struct spider_net_descr *head; 395 struct spider_net_descr *tail; 396 struct spider_net_descr *ring; 397 int num_desc; 398 struct spider_net_hw_descr *hwring; 399 dma_addr_t dma_addr; 400 }; 401 402 /* descriptor data_status bits */ 403 #define SPIDER_NET_RX_IPCHK 29 404 #define SPIDER_NET_RX_TCPCHK 28 405 #define SPIDER_NET_VLAN_PACKET 21 406 #define SPIDER_NET_DATA_STATUS_CKSUM_MASK ( (1 << SPIDER_NET_RX_IPCHK) | \ 407 (1 << SPIDER_NET_RX_TCPCHK) ) 408 409 /* descriptor data_error bits */ 410 #define SPIDER_NET_RX_IPCHKERR 27 411 #define SPIDER_NET_RX_RXTCPCHKERR 28 412 413 #define SPIDER_NET_DATA_ERR_CKSUM_MASK (1 << SPIDER_NET_RX_IPCHKERR) 414 415 /* the cases we don't pass the packet to the stack. 416 * 701b8000 would be correct, but every packets gets that flag */ 417 #define SPIDER_NET_DESTROY_RX_FLAGS 0x700b8000 418 419 #define SPIDER_NET_DEFAULT_MSG ( NETIF_MSG_DRV | \ 420 NETIF_MSG_PROBE | \ 421 NETIF_MSG_LINK | \ 422 NETIF_MSG_TIMER | \ 423 NETIF_MSG_IFDOWN | \ 424 NETIF_MSG_IFUP | \ 425 NETIF_MSG_RX_ERR | \ 426 NETIF_MSG_TX_ERR | \ 427 NETIF_MSG_TX_QUEUED | \ 428 NETIF_MSG_INTR | \ 429 NETIF_MSG_TX_DONE | \ 430 NETIF_MSG_RX_STATUS | \ 431 NETIF_MSG_PKTDATA | \ 432 NETIF_MSG_HW | \ 433 NETIF_MSG_WOL ) 434 435 struct spider_net_extra_stats { 436 unsigned long rx_desc_error; 437 unsigned long tx_timeouts; 438 unsigned long alloc_rx_skb_error; 439 unsigned long rx_iommu_map_error; 440 unsigned long tx_iommu_map_error; 441 unsigned long rx_desc_unk_state; 442 }; 443 444 struct spider_net_card { 445 struct net_device *netdev; 446 struct pci_dev *pdev; 447 struct mii_phy phy; 448 449 struct napi_struct napi; 450 451 int medium; 452 453 void __iomem *regs; 454 455 struct spider_net_descr_chain tx_chain; 456 struct spider_net_descr_chain rx_chain; 457 struct spider_net_descr *low_watermark; 458 459 int aneg_count; 460 struct timer_list aneg_timer; 461 struct timer_list tx_timer; 462 struct work_struct tx_timeout_task; 463 atomic_t tx_timeout_task_counter; 464 wait_queue_head_t waitq; 465 int num_rx_ints; 466 int ignore_rx_ramfull; 467 468 /* for ethtool */ 469 int msg_enable; 470 struct spider_net_extra_stats spider_stats; 471 472 /* Must be last item in struct */ 473 struct spider_net_descr darray[0]; 474 }; 475 476 #endif 477