1de6cc651SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
28df158acSJeff Kirsher /*
38df158acSJeff Kirsher * PS3 Platfom gelic network driver.
48df158acSJeff Kirsher *
58df158acSJeff Kirsher * Copyright (C) 2007 Sony Computer Entertainment Inc.
68df158acSJeff Kirsher * Copyright 2006, 2007 Sony Corporation.
78df158acSJeff Kirsher *
88df158acSJeff Kirsher * This file is based on: spider_net.h
98df158acSJeff Kirsher *
108df158acSJeff Kirsher * (C) Copyright IBM Corp. 2005
118df158acSJeff Kirsher *
128df158acSJeff Kirsher * Authors : Utz Bacher <utz.bacher@de.ibm.com>
138df158acSJeff Kirsher * Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
148df158acSJeff Kirsher */
158df158acSJeff Kirsher #ifndef _GELIC_NET_H
168df158acSJeff Kirsher #define _GELIC_NET_H
178df158acSJeff Kirsher
188df158acSJeff Kirsher /* descriptors */
198df158acSJeff Kirsher #define GELIC_NET_RX_DESCRIPTORS 128 /* num of descriptors */
208df158acSJeff Kirsher #define GELIC_NET_TX_DESCRIPTORS 128 /* num of descriptors */
218df158acSJeff Kirsher
22*19b3bb51SGeoff Levand #define GELIC_NET_MAX_FRAME 2312
23*19b3bb51SGeoff Levand #define GELIC_NET_MAX_MTU 2294
24*19b3bb51SGeoff Levand #define GELIC_NET_MIN_MTU 64
258df158acSJeff Kirsher #define GELIC_NET_RXBUF_ALIGN 128
268df158acSJeff Kirsher #define GELIC_CARD_RX_CSUM_DEFAULT 1 /* hw chksum */
278df158acSJeff Kirsher #define GELIC_NET_WATCHDOG_TIMEOUT 5*HZ
288df158acSJeff Kirsher #define GELIC_NET_BROADCAST_ADDR 0xffffffffffffL
298df158acSJeff Kirsher
308df158acSJeff Kirsher #define GELIC_NET_MC_COUNT_MAX 32 /* multicast address list */
318df158acSJeff Kirsher
328df158acSJeff Kirsher /* virtual interrupt status register bits */
338df158acSJeff Kirsher /* INT1 */
348df158acSJeff Kirsher #define GELIC_CARD_TX_RAM_FULL_ERR 0x0000000000000001L
358df158acSJeff Kirsher #define GELIC_CARD_RX_RAM_FULL_ERR 0x0000000000000002L
368df158acSJeff Kirsher #define GELIC_CARD_TX_SHORT_FRAME_ERR 0x0000000000000004L
378df158acSJeff Kirsher #define GELIC_CARD_TX_INVALID_DESCR_ERR 0x0000000000000008L
388df158acSJeff Kirsher #define GELIC_CARD_RX_FIFO_FULL_ERR 0x0000000000002000L
398df158acSJeff Kirsher #define GELIC_CARD_RX_DESCR_CHAIN_END 0x0000000000004000L
408df158acSJeff Kirsher #define GELIC_CARD_RX_INVALID_DESCR_ERR 0x0000000000008000L
418df158acSJeff Kirsher #define GELIC_CARD_TX_RESPONCE_ERR 0x0000000000010000L
428df158acSJeff Kirsher #define GELIC_CARD_RX_RESPONCE_ERR 0x0000000000100000L
438df158acSJeff Kirsher #define GELIC_CARD_TX_PROTECTION_ERR 0x0000000000400000L
448df158acSJeff Kirsher #define GELIC_CARD_RX_PROTECTION_ERR 0x0000000004000000L
458df158acSJeff Kirsher #define GELIC_CARD_TX_TCP_UDP_CHECKSUM_ERR 0x0000000008000000L
468df158acSJeff Kirsher #define GELIC_CARD_PORT_STATUS_CHANGED 0x0000000020000000L
478df158acSJeff Kirsher #define GELIC_CARD_WLAN_EVENT_RECEIVED 0x0000000040000000L
488df158acSJeff Kirsher #define GELIC_CARD_WLAN_COMMAND_COMPLETED 0x0000000080000000L
498df158acSJeff Kirsher /* INT 0 */
508df158acSJeff Kirsher #define GELIC_CARD_TX_FLAGGED_DESCR 0x0004000000000000L
518df158acSJeff Kirsher #define GELIC_CARD_RX_FLAGGED_DESCR 0x0040000000000000L
528df158acSJeff Kirsher #define GELIC_CARD_TX_TRANSFER_END 0x0080000000000000L
538df158acSJeff Kirsher #define GELIC_CARD_TX_DESCR_CHAIN_END 0x0100000000000000L
548df158acSJeff Kirsher #define GELIC_CARD_NUMBER_OF_RX_FRAME 0x1000000000000000L
558df158acSJeff Kirsher #define GELIC_CARD_ONE_TIME_COUNT_TIMER 0x4000000000000000L
568df158acSJeff Kirsher #define GELIC_CARD_FREE_RUN_COUNT_TIMER 0x8000000000000000L
578df158acSJeff Kirsher
588df158acSJeff Kirsher /* initial interrupt mask */
598df158acSJeff Kirsher #define GELIC_CARD_TXINT GELIC_CARD_TX_DESCR_CHAIN_END
608df158acSJeff Kirsher
618df158acSJeff Kirsher #define GELIC_CARD_RXINT (GELIC_CARD_RX_DESCR_CHAIN_END | \
628df158acSJeff Kirsher GELIC_CARD_NUMBER_OF_RX_FRAME)
638df158acSJeff Kirsher
648df158acSJeff Kirsher /* RX descriptor data_status bits */
658df158acSJeff Kirsher enum gelic_descr_rx_status {
668df158acSJeff Kirsher GELIC_DESCR_RXDMADU = 0x80000000, /* destination MAC addr unknown */
678df158acSJeff Kirsher GELIC_DESCR_RXLSTFBF = 0x40000000, /* last frame buffer */
688df158acSJeff Kirsher GELIC_DESCR_RXIPCHK = 0x20000000, /* IP checksum performed */
698df158acSJeff Kirsher GELIC_DESCR_RXTCPCHK = 0x10000000, /* TCP/UDP checksup performed */
708df158acSJeff Kirsher GELIC_DESCR_RXWTPKT = 0x00C00000, /*
718df158acSJeff Kirsher * wakeup trigger packet
728df158acSJeff Kirsher * 01: Magic Packet (TM)
738df158acSJeff Kirsher * 10: ARP packet
748df158acSJeff Kirsher * 11: Multicast MAC addr
758df158acSJeff Kirsher */
768df158acSJeff Kirsher GELIC_DESCR_RXVLNPKT = 0x00200000, /* VLAN packet */
778df158acSJeff Kirsher /* bit 20..16 reserved */
788df158acSJeff Kirsher GELIC_DESCR_RXRRECNUM = 0x0000ff00, /* reception receipt number */
798df158acSJeff Kirsher /* bit 7..0 reserved */
808df158acSJeff Kirsher };
818df158acSJeff Kirsher
828df158acSJeff Kirsher #define GELIC_DESCR_DATA_STATUS_CHK_MASK \
838df158acSJeff Kirsher (GELIC_DESCR_RXIPCHK | GELIC_DESCR_RXTCPCHK)
848df158acSJeff Kirsher
858df158acSJeff Kirsher /* TX descriptor data_status bits */
868df158acSJeff Kirsher enum gelic_descr_tx_status {
878df158acSJeff Kirsher GELIC_DESCR_TX_TAIL = 0x00000001, /* gelic treated this
888df158acSJeff Kirsher * descriptor was end of
898df158acSJeff Kirsher * a tx frame
908df158acSJeff Kirsher */
918df158acSJeff Kirsher };
928df158acSJeff Kirsher
938df158acSJeff Kirsher /* RX descriptor data error bits */
948df158acSJeff Kirsher enum gelic_descr_rx_error {
958df158acSJeff Kirsher /* bit 31 reserved */
968df158acSJeff Kirsher GELIC_DESCR_RXALNERR = 0x40000000, /* alignement error 10/100M */
978df158acSJeff Kirsher GELIC_DESCR_RXOVERERR = 0x20000000, /* oversize error */
988df158acSJeff Kirsher GELIC_DESCR_RXRNTERR = 0x10000000, /* Runt error */
998df158acSJeff Kirsher GELIC_DESCR_RXIPCHKERR = 0x08000000, /* IP checksum error */
1008df158acSJeff Kirsher GELIC_DESCR_RXTCPCHKERR = 0x04000000, /* TCP/UDP checksum error */
1018df158acSJeff Kirsher GELIC_DESCR_RXDRPPKT = 0x00100000, /* drop packet */
1028df158acSJeff Kirsher GELIC_DESCR_RXIPFMTERR = 0x00080000, /* IP packet format error */
1038df158acSJeff Kirsher /* bit 18 reserved */
1048df158acSJeff Kirsher GELIC_DESCR_RXDATAERR = 0x00020000, /* IP packet format error */
1058df158acSJeff Kirsher GELIC_DESCR_RXCALERR = 0x00010000, /* cariier extension length
1068df158acSJeff Kirsher * error */
1078df158acSJeff Kirsher GELIC_DESCR_RXCREXERR = 0x00008000, /* carrier extension error */
1088df158acSJeff Kirsher GELIC_DESCR_RXMLTCST = 0x00004000, /* multicast address frame */
1098df158acSJeff Kirsher /* bit 13..0 reserved */
1108df158acSJeff Kirsher };
1118df158acSJeff Kirsher #define GELIC_DESCR_DATA_ERROR_CHK_MASK \
1128df158acSJeff Kirsher (GELIC_DESCR_RXIPCHKERR | GELIC_DESCR_RXTCPCHKERR)
1138df158acSJeff Kirsher
1148df158acSJeff Kirsher /* DMA command and status (RX and TX)*/
1158df158acSJeff Kirsher enum gelic_descr_dma_status {
1168df158acSJeff Kirsher GELIC_DESCR_DMA_COMPLETE = 0x00000000, /* used in tx */
1178df158acSJeff Kirsher GELIC_DESCR_DMA_BUFFER_FULL = 0x00000000, /* used in rx */
1188df158acSJeff Kirsher GELIC_DESCR_DMA_RESPONSE_ERROR = 0x10000000, /* used in rx, tx */
1198df158acSJeff Kirsher GELIC_DESCR_DMA_PROTECTION_ERROR = 0x20000000, /* used in rx, tx */
1208df158acSJeff Kirsher GELIC_DESCR_DMA_FRAME_END = 0x40000000, /* used in rx */
1218df158acSJeff Kirsher GELIC_DESCR_DMA_FORCE_END = 0x50000000, /* used in rx, tx */
1228df158acSJeff Kirsher GELIC_DESCR_DMA_CARDOWNED = 0xa0000000, /* used in rx, tx */
1238df158acSJeff Kirsher GELIC_DESCR_DMA_NOT_IN_USE = 0xb0000000, /* any other value */
1248df158acSJeff Kirsher };
1258df158acSJeff Kirsher
1268df158acSJeff Kirsher #define GELIC_DESCR_DMA_STAT_MASK (0xf0000000)
1278df158acSJeff Kirsher
1288df158acSJeff Kirsher /* tx descriptor command and status */
1298df158acSJeff Kirsher enum gelic_descr_tx_dma_status {
1308df158acSJeff Kirsher /* [19] */
1318df158acSJeff Kirsher GELIC_DESCR_TX_DMA_IKE = 0x00080000, /* IPSEC off */
1328df158acSJeff Kirsher /* [18] */
1338df158acSJeff Kirsher GELIC_DESCR_TX_DMA_FRAME_TAIL = 0x00040000, /* last descriptor of
1348df158acSJeff Kirsher * the packet
1358df158acSJeff Kirsher */
1368df158acSJeff Kirsher /* [17..16] */
1378df158acSJeff Kirsher GELIC_DESCR_TX_DMA_TCP_CHKSUM = 0x00020000, /* TCP packet */
1388df158acSJeff Kirsher GELIC_DESCR_TX_DMA_UDP_CHKSUM = 0x00030000, /* UDP packet */
1398df158acSJeff Kirsher GELIC_DESCR_TX_DMA_NO_CHKSUM = 0x00000000, /* no checksum */
1408df158acSJeff Kirsher
1418df158acSJeff Kirsher /* [1] */
1428df158acSJeff Kirsher GELIC_DESCR_TX_DMA_CHAIN_END = 0x00000002, /* DMA terminated
1438df158acSJeff Kirsher * due to chain end
1448df158acSJeff Kirsher */
1458df158acSJeff Kirsher };
1468df158acSJeff Kirsher
1478df158acSJeff Kirsher #define GELIC_DESCR_DMA_CMD_NO_CHKSUM \
1488df158acSJeff Kirsher (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
1498df158acSJeff Kirsher GELIC_DESCR_TX_DMA_NO_CHKSUM)
1508df158acSJeff Kirsher
1518df158acSJeff Kirsher #define GELIC_DESCR_DMA_CMD_TCP_CHKSUM \
1528df158acSJeff Kirsher (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
1538df158acSJeff Kirsher GELIC_DESCR_TX_DMA_TCP_CHKSUM)
1548df158acSJeff Kirsher
1558df158acSJeff Kirsher #define GELIC_DESCR_DMA_CMD_UDP_CHKSUM \
1568df158acSJeff Kirsher (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
1578df158acSJeff Kirsher GELIC_DESCR_TX_DMA_UDP_CHKSUM)
1588df158acSJeff Kirsher
1598df158acSJeff Kirsher enum gelic_descr_rx_dma_status {
1608df158acSJeff Kirsher /* [ 1 ] */
1618df158acSJeff Kirsher GELIC_DESCR_RX_DMA_CHAIN_END = 0x00000002, /* DMA terminated
1628df158acSJeff Kirsher * due to chain end
1638df158acSJeff Kirsher */
1648df158acSJeff Kirsher };
1658df158acSJeff Kirsher
1668df158acSJeff Kirsher /* for lv1_net_control */
1678df158acSJeff Kirsher enum gelic_lv1_net_control_code {
1688df158acSJeff Kirsher GELIC_LV1_GET_MAC_ADDRESS = 1,
1698df158acSJeff Kirsher GELIC_LV1_GET_ETH_PORT_STATUS = 2,
1708df158acSJeff Kirsher GELIC_LV1_SET_NEGOTIATION_MODE = 3,
1718df158acSJeff Kirsher GELIC_LV1_GET_VLAN_ID = 4,
1728df158acSJeff Kirsher GELIC_LV1_SET_WOL = 5,
1738df158acSJeff Kirsher GELIC_LV1_GET_CHANNEL = 6,
1748df158acSJeff Kirsher GELIC_LV1_POST_WLAN_CMD = 9,
1758df158acSJeff Kirsher GELIC_LV1_GET_WLAN_CMD_RESULT = 10,
1768df158acSJeff Kirsher GELIC_LV1_GET_WLAN_EVENT = 11,
1778df158acSJeff Kirsher };
1788df158acSJeff Kirsher
1798df158acSJeff Kirsher /* for GELIC_LV1_SET_WOL */
1808df158acSJeff Kirsher enum gelic_lv1_wol_command {
1818df158acSJeff Kirsher GELIC_LV1_WOL_MAGIC_PACKET = 1,
1828df158acSJeff Kirsher GELIC_LV1_WOL_ADD_MATCH_ADDR = 6,
1838df158acSJeff Kirsher GELIC_LV1_WOL_DELETE_MATCH_ADDR = 7,
1848df158acSJeff Kirsher };
1858df158acSJeff Kirsher
1868df158acSJeff Kirsher /* for GELIC_LV1_WOL_MAGIC_PACKET */
1878df158acSJeff Kirsher enum gelic_lv1_wol_mp_arg {
1888df158acSJeff Kirsher GELIC_LV1_WOL_MP_DISABLE = 0,
1898df158acSJeff Kirsher GELIC_LV1_WOL_MP_ENABLE = 1,
1908df158acSJeff Kirsher };
1918df158acSJeff Kirsher
1928df158acSJeff Kirsher /* for GELIC_LV1_WOL_{ADD,DELETE}_MATCH_ADDR */
1938df158acSJeff Kirsher enum gelic_lv1_wol_match_arg {
1948df158acSJeff Kirsher GELIC_LV1_WOL_MATCH_INDIVIDUAL = 0,
1958df158acSJeff Kirsher GELIC_LV1_WOL_MATCH_ALL = 1,
1968df158acSJeff Kirsher };
1978df158acSJeff Kirsher
1988df158acSJeff Kirsher /* status returened from GET_ETH_PORT_STATUS */
1998df158acSJeff Kirsher enum gelic_lv1_ether_port_status {
2008df158acSJeff Kirsher GELIC_LV1_ETHER_LINK_UP = 0x0000000000000001L,
2018df158acSJeff Kirsher GELIC_LV1_ETHER_FULL_DUPLEX = 0x0000000000000002L,
2028df158acSJeff Kirsher GELIC_LV1_ETHER_AUTO_NEG = 0x0000000000000004L,
2038df158acSJeff Kirsher
2048df158acSJeff Kirsher GELIC_LV1_ETHER_SPEED_10 = 0x0000000000000010L,
2058df158acSJeff Kirsher GELIC_LV1_ETHER_SPEED_100 = 0x0000000000000020L,
2068df158acSJeff Kirsher GELIC_LV1_ETHER_SPEED_1000 = 0x0000000000000040L,
2078df158acSJeff Kirsher GELIC_LV1_ETHER_SPEED_MASK = 0x0000000000000070L,
2088df158acSJeff Kirsher };
2098df158acSJeff Kirsher
2108df158acSJeff Kirsher enum gelic_lv1_vlan_index {
2118df158acSJeff Kirsher /* for outgoing packets */
2128df158acSJeff Kirsher GELIC_LV1_VLAN_TX_ETHERNET_0 = 0x0000000000000002L,
2138df158acSJeff Kirsher GELIC_LV1_VLAN_TX_WIRELESS = 0x0000000000000003L,
2148df158acSJeff Kirsher
2158df158acSJeff Kirsher /* for incoming packets */
2168df158acSJeff Kirsher GELIC_LV1_VLAN_RX_ETHERNET_0 = 0x0000000000000012L,
2178df158acSJeff Kirsher GELIC_LV1_VLAN_RX_WIRELESS = 0x0000000000000013L,
2188df158acSJeff Kirsher };
2198df158acSJeff Kirsher
2208df158acSJeff Kirsher enum gelic_lv1_phy {
2218df158acSJeff Kirsher GELIC_LV1_PHY_ETHERNET_0 = 0x0000000000000002L,
2228df158acSJeff Kirsher };
2238df158acSJeff Kirsher
2248df158acSJeff Kirsher /* size of hardware part of gelic descriptor */
2258df158acSJeff Kirsher #define GELIC_DESCR_SIZE (32)
2268df158acSJeff Kirsher
2278df158acSJeff Kirsher enum gelic_port_type {
2288df158acSJeff Kirsher GELIC_PORT_ETHERNET_0 = 0,
2298df158acSJeff Kirsher GELIC_PORT_WIRELESS = 1,
2308df158acSJeff Kirsher GELIC_PORT_MAX
2318df158acSJeff Kirsher };
2328df158acSJeff Kirsher
2338df158acSJeff Kirsher struct gelic_descr {
2348df158acSJeff Kirsher /* as defined by the hardware */
2358df158acSJeff Kirsher __be32 buf_addr;
2368df158acSJeff Kirsher __be32 buf_size;
2378df158acSJeff Kirsher __be32 next_descr_addr;
2388df158acSJeff Kirsher __be32 dmac_cmd_status;
2398df158acSJeff Kirsher __be32 result_size;
2408df158acSJeff Kirsher __be32 valid_size; /* all zeroes for tx */
2418df158acSJeff Kirsher __be32 data_status;
2428df158acSJeff Kirsher __be32 data_error; /* all zeroes for tx */
2438df158acSJeff Kirsher
2448df158acSJeff Kirsher /* used in the driver */
2458df158acSJeff Kirsher struct sk_buff *skb;
2468df158acSJeff Kirsher dma_addr_t bus_addr;
2478df158acSJeff Kirsher struct gelic_descr *next;
2488df158acSJeff Kirsher struct gelic_descr *prev;
2498df158acSJeff Kirsher } __attribute__((aligned(32)));
2508df158acSJeff Kirsher
2518df158acSJeff Kirsher struct gelic_descr_chain {
2528df158acSJeff Kirsher /* we walk from tail to head */
2538df158acSJeff Kirsher struct gelic_descr *head;
2548df158acSJeff Kirsher struct gelic_descr *tail;
2558df158acSJeff Kirsher };
2568df158acSJeff Kirsher
2578df158acSJeff Kirsher struct gelic_vlan_id {
2588df158acSJeff Kirsher u16 tx;
2598df158acSJeff Kirsher u16 rx;
2608df158acSJeff Kirsher };
2618df158acSJeff Kirsher
2628df158acSJeff Kirsher struct gelic_card {
2638df158acSJeff Kirsher struct napi_struct napi;
2648df158acSJeff Kirsher struct net_device *netdev[GELIC_PORT_MAX];
2658df158acSJeff Kirsher /*
2668df158acSJeff Kirsher * hypervisor requires irq_status should be
2678df158acSJeff Kirsher * 8 bytes aligned, but u64 member is
2688df158acSJeff Kirsher * always disposed in that manner
2698df158acSJeff Kirsher */
2708df158acSJeff Kirsher u64 irq_status;
2718df158acSJeff Kirsher u64 irq_mask;
2728df158acSJeff Kirsher
2738df158acSJeff Kirsher struct ps3_system_bus_device *dev;
2748df158acSJeff Kirsher struct gelic_vlan_id vlan[GELIC_PORT_MAX];
2758df158acSJeff Kirsher int vlan_required;
2768df158acSJeff Kirsher
2778df158acSJeff Kirsher struct gelic_descr_chain tx_chain;
2788df158acSJeff Kirsher struct gelic_descr_chain rx_chain;
2798df158acSJeff Kirsher /*
2808df158acSJeff Kirsher * tx_lock guards tx descriptor list and
2818df158acSJeff Kirsher * tx_dma_progress.
2828df158acSJeff Kirsher */
2838df158acSJeff Kirsher spinlock_t tx_lock;
2848df158acSJeff Kirsher int tx_dma_progress;
2858df158acSJeff Kirsher
2868df158acSJeff Kirsher struct work_struct tx_timeout_task;
2878df158acSJeff Kirsher atomic_t tx_timeout_task_counter;
2888df158acSJeff Kirsher wait_queue_head_t waitq;
2898df158acSJeff Kirsher
2908df158acSJeff Kirsher /* only first user should up the card */
2918df158acSJeff Kirsher struct mutex updown_lock;
2928df158acSJeff Kirsher atomic_t users;
2938df158acSJeff Kirsher
2948df158acSJeff Kirsher u64 ether_port_status;
2958df158acSJeff Kirsher int link_mode;
2968df158acSJeff Kirsher
2978df158acSJeff Kirsher /* original address returned by kzalloc */
2988df158acSJeff Kirsher void *unalign;
2998df158acSJeff Kirsher
3008df158acSJeff Kirsher /*
3018df158acSJeff Kirsher * each netdevice has copy of irq
3028df158acSJeff Kirsher */
3038df158acSJeff Kirsher unsigned int irq;
3048df158acSJeff Kirsher struct gelic_descr *tx_top, *rx_top;
305b594850eSGeert Uytterhoeven struct gelic_descr descr[]; /* must be the last */
3068df158acSJeff Kirsher };
3078df158acSJeff Kirsher
3088df158acSJeff Kirsher struct gelic_port {
3098df158acSJeff Kirsher struct gelic_card *card;
3108df158acSJeff Kirsher struct net_device *netdev;
3118df158acSJeff Kirsher enum gelic_port_type type;
312f49b2759SGustavo A. R. Silva long priv[]; /* long for alignment */
3138df158acSJeff Kirsher };
3148df158acSJeff Kirsher
port_to_card(struct gelic_port * p)3158df158acSJeff Kirsher static inline struct gelic_card *port_to_card(struct gelic_port *p)
3168df158acSJeff Kirsher {
3178df158acSJeff Kirsher return p->card;
3188df158acSJeff Kirsher }
port_to_netdev(struct gelic_port * p)3198df158acSJeff Kirsher static inline struct net_device *port_to_netdev(struct gelic_port *p)
3208df158acSJeff Kirsher {
3218df158acSJeff Kirsher return p->netdev;
3228df158acSJeff Kirsher }
netdev_card(struct net_device * d)3238df158acSJeff Kirsher static inline struct gelic_card *netdev_card(struct net_device *d)
3248df158acSJeff Kirsher {
3258df158acSJeff Kirsher return ((struct gelic_port *)netdev_priv(d))->card;
3268df158acSJeff Kirsher }
netdev_port(struct net_device * d)3278df158acSJeff Kirsher static inline struct gelic_port *netdev_port(struct net_device *d)
3288df158acSJeff Kirsher {
3298df158acSJeff Kirsher return (struct gelic_port *)netdev_priv(d);
3308df158acSJeff Kirsher }
ctodev(struct gelic_card * card)3318df158acSJeff Kirsher static inline struct device *ctodev(struct gelic_card *card)
3328df158acSJeff Kirsher {
3338df158acSJeff Kirsher return &card->dev->core;
3348df158acSJeff Kirsher }
bus_id(struct gelic_card * card)3358df158acSJeff Kirsher static inline u64 bus_id(struct gelic_card *card)
3368df158acSJeff Kirsher {
3378df158acSJeff Kirsher return card->dev->bus_id;
3388df158acSJeff Kirsher }
dev_id(struct gelic_card * card)3398df158acSJeff Kirsher static inline u64 dev_id(struct gelic_card *card)
3408df158acSJeff Kirsher {
3418df158acSJeff Kirsher return card->dev->dev_id;
3428df158acSJeff Kirsher }
3438df158acSJeff Kirsher
port_priv(struct gelic_port * port)3448df158acSJeff Kirsher static inline void *port_priv(struct gelic_port *port)
3458df158acSJeff Kirsher {
3468df158acSJeff Kirsher return port->priv;
3478df158acSJeff Kirsher }
3488df158acSJeff Kirsher
3491197ab29SLinus Torvalds #ifdef CONFIG_PPC_EARLY_DEBUG_PS3GELIC
3503e0dd1f4SJoe Perches void udbg_shutdown_ps3gelic(void);
3511197ab29SLinus Torvalds #else
udbg_shutdown_ps3gelic(void)3521197ab29SLinus Torvalds static inline void udbg_shutdown_ps3gelic(void) {}
3531197ab29SLinus Torvalds #endif
3541197ab29SLinus Torvalds
3553e0dd1f4SJoe Perches int gelic_card_set_irq_mask(struct gelic_card *card, u64 mask);
3568df158acSJeff Kirsher /* shared netdev ops */
3573e0dd1f4SJoe Perches void gelic_card_up(struct gelic_card *card);
3583e0dd1f4SJoe Perches void gelic_card_down(struct gelic_card *card);
3593e0dd1f4SJoe Perches int gelic_net_open(struct net_device *netdev);
3603e0dd1f4SJoe Perches int gelic_net_stop(struct net_device *netdev);
361bacade82SYueHaibing netdev_tx_t gelic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
3623e0dd1f4SJoe Perches void gelic_net_set_multi(struct net_device *netdev);
3630290bd29SMichael S. Tsirkin void gelic_net_tx_timeout(struct net_device *netdev, unsigned int txqueue);
3643e0dd1f4SJoe Perches int gelic_net_setup_netdev(struct net_device *netdev, struct gelic_card *card);
3658df158acSJeff Kirsher
3668df158acSJeff Kirsher /* shared ethtool ops */
3673e0dd1f4SJoe Perches void gelic_net_get_drvinfo(struct net_device *netdev,
3688df158acSJeff Kirsher struct ethtool_drvinfo *info);
3693e0dd1f4SJoe Perches void gelic_net_poll_controller(struct net_device *netdev);
3708df158acSJeff Kirsher
3718df158acSJeff Kirsher #endif /* _GELIC_NET_H */
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