1 /* 2 * Keystone GBE and XGBE subsystem code 3 * 4 * Copyright (C) 2014 Texas Instruments Incorporated 5 * Authors: Sandeep Nair <sandeep_n@ti.com> 6 * Sandeep Paulraj <s-paulraj@ti.com> 7 * Cyril Chemparathy <cyril@ti.com> 8 * Santosh Shilimkar <santosh.shilimkar@ti.com> 9 * Wingman Kwok <w-kwok2@ti.com> 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation version 2. 14 * 15 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 16 * kind, whether express or implied; without even the implied warranty 17 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 */ 20 21 #include <linux/io.h> 22 #include <linux/module.h> 23 #include <linux/of_mdio.h> 24 #include <linux/of_address.h> 25 #include <linux/if_vlan.h> 26 #include <linux/ptp_classify.h> 27 #include <linux/net_tstamp.h> 28 #include <linux/ethtool.h> 29 30 #include "cpsw_ale.h" 31 #include "netcp.h" 32 #include "cpts.h" 33 34 #define NETCP_DRIVER_NAME "TI KeyStone Ethernet Driver" 35 #define NETCP_DRIVER_VERSION "v1.0" 36 37 #define GBE_IDENT(reg) ((reg >> 16) & 0xffff) 38 #define GBE_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 39 #define GBE_MINOR_VERSION(reg) (reg & 0xff) 40 #define GBE_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 41 42 /* 1G Ethernet SS defines */ 43 #define GBE_MODULE_NAME "netcp-gbe" 44 #define GBE_SS_VERSION_14 0x4ed21104 45 46 #define GBE_SS_REG_INDEX 0 47 #define GBE_SGMII34_REG_INDEX 1 48 #define GBE_SM_REG_INDEX 2 49 /* offset relative to base of GBE_SS_REG_INDEX */ 50 #define GBE13_SGMII_MODULE_OFFSET 0x100 51 /* offset relative to base of GBE_SM_REG_INDEX */ 52 #define GBE13_HOST_PORT_OFFSET 0x34 53 #define GBE13_SLAVE_PORT_OFFSET 0x60 54 #define GBE13_EMAC_OFFSET 0x100 55 #define GBE13_SLAVE_PORT2_OFFSET 0x200 56 #define GBE13_HW_STATS_OFFSET 0x300 57 #define GBE13_CPTS_OFFSET 0x500 58 #define GBE13_ALE_OFFSET 0x600 59 #define GBE13_HOST_PORT_NUM 0 60 #define GBE13_NUM_ALE_ENTRIES 1024 61 62 /* 1G Ethernet NU SS defines */ 63 #define GBENU_MODULE_NAME "netcp-gbenu" 64 #define GBE_SS_ID_NU 0x4ee6 65 #define GBE_SS_ID_2U 0x4ee8 66 67 #define IS_SS_ID_MU(d) \ 68 ((GBE_IDENT((d)->ss_version) == GBE_SS_ID_NU) || \ 69 (GBE_IDENT((d)->ss_version) == GBE_SS_ID_2U)) 70 71 #define IS_SS_ID_NU(d) \ 72 (GBE_IDENT((d)->ss_version) == GBE_SS_ID_NU) 73 74 #define GBENU_SS_REG_INDEX 0 75 #define GBENU_SM_REG_INDEX 1 76 #define GBENU_SGMII_MODULE_OFFSET 0x100 77 #define GBENU_HOST_PORT_OFFSET 0x1000 78 #define GBENU_SLAVE_PORT_OFFSET 0x2000 79 #define GBENU_EMAC_OFFSET 0x2330 80 #define GBENU_HW_STATS_OFFSET 0x1a000 81 #define GBENU_CPTS_OFFSET 0x1d000 82 #define GBENU_ALE_OFFSET 0x1e000 83 #define GBENU_HOST_PORT_NUM 0 84 #define GBENU_NUM_ALE_ENTRIES 1024 85 #define GBENU_SGMII_MODULE_SIZE 0x100 86 87 /* 10G Ethernet SS defines */ 88 #define XGBE_MODULE_NAME "netcp-xgbe" 89 #define XGBE_SS_VERSION_10 0x4ee42100 90 91 #define XGBE_SS_REG_INDEX 0 92 #define XGBE_SM_REG_INDEX 1 93 #define XGBE_SERDES_REG_INDEX 2 94 95 /* offset relative to base of XGBE_SS_REG_INDEX */ 96 #define XGBE10_SGMII_MODULE_OFFSET 0x100 97 /* offset relative to base of XGBE_SM_REG_INDEX */ 98 #define XGBE10_HOST_PORT_OFFSET 0x34 99 #define XGBE10_SLAVE_PORT_OFFSET 0x64 100 #define XGBE10_EMAC_OFFSET 0x400 101 #define XGBE10_CPTS_OFFSET 0x600 102 #define XGBE10_ALE_OFFSET 0x700 103 #define XGBE10_HW_STATS_OFFSET 0x800 104 #define XGBE10_HOST_PORT_NUM 0 105 #define XGBE10_NUM_ALE_ENTRIES 1024 106 107 #define GBE_TIMER_INTERVAL (HZ / 2) 108 109 /* Soft reset register values */ 110 #define SOFT_RESET_MASK BIT(0) 111 #define SOFT_RESET BIT(0) 112 #define DEVICE_EMACSL_RESET_POLL_COUNT 100 113 #define GMACSL_RET_WARN_RESET_INCOMPLETE -2 114 115 #define MACSL_RX_ENABLE_CSF BIT(23) 116 #define MACSL_ENABLE_EXT_CTL BIT(18) 117 #define MACSL_XGMII_ENABLE BIT(13) 118 #define MACSL_XGIG_MODE BIT(8) 119 #define MACSL_GIG_MODE BIT(7) 120 #define MACSL_GMII_ENABLE BIT(5) 121 #define MACSL_FULLDUPLEX BIT(0) 122 123 #define GBE_CTL_P0_ENABLE BIT(2) 124 #define GBE13_REG_VAL_STAT_ENABLE_ALL 0xff 125 #define XGBE_REG_VAL_STAT_ENABLE_ALL 0xf 126 #define GBE_STATS_CD_SEL BIT(28) 127 128 #define GBE_PORT_MASK(x) (BIT(x) - 1) 129 #define GBE_MASK_NO_PORTS 0 130 131 #define GBE_DEF_1G_MAC_CONTROL \ 132 (MACSL_GIG_MODE | MACSL_GMII_ENABLE | \ 133 MACSL_ENABLE_EXT_CTL | MACSL_RX_ENABLE_CSF) 134 135 #define GBE_DEF_10G_MAC_CONTROL \ 136 (MACSL_XGIG_MODE | MACSL_XGMII_ENABLE | \ 137 MACSL_ENABLE_EXT_CTL | MACSL_RX_ENABLE_CSF) 138 139 #define GBE_STATSA_MODULE 0 140 #define GBE_STATSB_MODULE 1 141 #define GBE_STATSC_MODULE 2 142 #define GBE_STATSD_MODULE 3 143 144 #define GBENU_STATS0_MODULE 0 145 #define GBENU_STATS1_MODULE 1 146 #define GBENU_STATS2_MODULE 2 147 #define GBENU_STATS3_MODULE 3 148 #define GBENU_STATS4_MODULE 4 149 #define GBENU_STATS5_MODULE 5 150 #define GBENU_STATS6_MODULE 6 151 #define GBENU_STATS7_MODULE 7 152 #define GBENU_STATS8_MODULE 8 153 154 #define XGBE_STATS0_MODULE 0 155 #define XGBE_STATS1_MODULE 1 156 #define XGBE_STATS2_MODULE 2 157 158 /* s: 0-based slave_port */ 159 #define SGMII_BASE(d, s) \ 160 (((s) < 2) ? (d)->sgmii_port_regs : (d)->sgmii_port34_regs) 161 162 #define GBE_TX_QUEUE 648 163 #define GBE_TXHOOK_ORDER 0 164 #define GBE_RXHOOK_ORDER 0 165 #define GBE_DEFAULT_ALE_AGEOUT 30 166 #define SLAVE_LINK_IS_XGMII(s) ((s)->link_interface >= XGMII_LINK_MAC_PHY) 167 #define NETCP_LINK_STATE_INVALID -1 168 169 #define GBE_SET_REG_OFS(p, rb, rn) p->rb##_ofs.rn = \ 170 offsetof(struct gbe##_##rb, rn) 171 #define GBENU_SET_REG_OFS(p, rb, rn) p->rb##_ofs.rn = \ 172 offsetof(struct gbenu##_##rb, rn) 173 #define XGBE_SET_REG_OFS(p, rb, rn) p->rb##_ofs.rn = \ 174 offsetof(struct xgbe##_##rb, rn) 175 #define GBE_REG_ADDR(p, rb, rn) (p->rb + p->rb##_ofs.rn) 176 177 #define HOST_TX_PRI_MAP_DEFAULT 0x00000000 178 179 #if IS_ENABLED(CONFIG_TI_CPTS) 180 /* Px_TS_CTL register fields */ 181 #define TS_RX_ANX_F_EN BIT(0) 182 #define TS_RX_VLAN_LT1_EN BIT(1) 183 #define TS_RX_VLAN_LT2_EN BIT(2) 184 #define TS_RX_ANX_D_EN BIT(3) 185 #define TS_TX_ANX_F_EN BIT(4) 186 #define TS_TX_VLAN_LT1_EN BIT(5) 187 #define TS_TX_VLAN_LT2_EN BIT(6) 188 #define TS_TX_ANX_D_EN BIT(7) 189 #define TS_LT2_EN BIT(8) 190 #define TS_RX_ANX_E_EN BIT(9) 191 #define TS_TX_ANX_E_EN BIT(10) 192 #define TS_MSG_TYPE_EN_SHIFT 16 193 #define TS_MSG_TYPE_EN_MASK 0xffff 194 195 /* Px_TS_SEQ_LTYPE register fields */ 196 #define TS_SEQ_ID_OFS_SHIFT 16 197 #define TS_SEQ_ID_OFS_MASK 0x3f 198 199 /* Px_TS_CTL_LTYPE2 register fields */ 200 #define TS_107 BIT(16) 201 #define TS_129 BIT(17) 202 #define TS_130 BIT(18) 203 #define TS_131 BIT(19) 204 #define TS_132 BIT(20) 205 #define TS_319 BIT(21) 206 #define TS_320 BIT(22) 207 #define TS_TTL_NONZERO BIT(23) 208 #define TS_UNI_EN BIT(24) 209 #define TS_UNI_EN_SHIFT 24 210 211 #define TS_TX_ANX_ALL_EN \ 212 (TS_TX_ANX_D_EN | TS_TX_ANX_E_EN | TS_TX_ANX_F_EN) 213 214 #define TS_RX_ANX_ALL_EN \ 215 (TS_RX_ANX_D_EN | TS_RX_ANX_E_EN | TS_RX_ANX_F_EN) 216 217 #define TS_CTL_DST_PORT TS_319 218 #define TS_CTL_DST_PORT_SHIFT 21 219 220 #define TS_CTL_MADDR_ALL \ 221 (TS_107 | TS_129 | TS_130 | TS_131 | TS_132) 222 223 #define TS_CTL_MADDR_SHIFT 16 224 225 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 226 #define EVENT_MSG_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 227 #endif /* CONFIG_TI_CPTS */ 228 229 struct xgbe_ss_regs { 230 u32 id_ver; 231 u32 synce_count; 232 u32 synce_mux; 233 u32 control; 234 }; 235 236 struct xgbe_switch_regs { 237 u32 id_ver; 238 u32 control; 239 u32 emcontrol; 240 u32 stat_port_en; 241 u32 ptype; 242 u32 soft_idle; 243 u32 thru_rate; 244 u32 gap_thresh; 245 u32 tx_start_wds; 246 u32 flow_control; 247 u32 cppi_thresh; 248 }; 249 250 struct xgbe_port_regs { 251 u32 blk_cnt; 252 u32 port_vlan; 253 u32 tx_pri_map; 254 u32 sa_lo; 255 u32 sa_hi; 256 u32 ts_ctl; 257 u32 ts_seq_ltype; 258 u32 ts_vlan; 259 u32 ts_ctl_ltype2; 260 u32 ts_ctl2; 261 u32 control; 262 }; 263 264 struct xgbe_host_port_regs { 265 u32 blk_cnt; 266 u32 port_vlan; 267 u32 tx_pri_map; 268 u32 src_id; 269 u32 rx_pri_map; 270 u32 rx_maxlen; 271 }; 272 273 struct xgbe_emac_regs { 274 u32 id_ver; 275 u32 mac_control; 276 u32 mac_status; 277 u32 soft_reset; 278 u32 rx_maxlen; 279 u32 __reserved_0; 280 u32 rx_pause; 281 u32 tx_pause; 282 u32 em_control; 283 u32 __reserved_1; 284 u32 tx_gap; 285 u32 rsvd[4]; 286 }; 287 288 struct xgbe_host_hw_stats { 289 u32 rx_good_frames; 290 u32 rx_broadcast_frames; 291 u32 rx_multicast_frames; 292 u32 __rsvd_0[3]; 293 u32 rx_oversized_frames; 294 u32 __rsvd_1; 295 u32 rx_undersized_frames; 296 u32 __rsvd_2; 297 u32 overrun_type4; 298 u32 overrun_type5; 299 u32 rx_bytes; 300 u32 tx_good_frames; 301 u32 tx_broadcast_frames; 302 u32 tx_multicast_frames; 303 u32 __rsvd_3[9]; 304 u32 tx_bytes; 305 u32 tx_64byte_frames; 306 u32 tx_65_to_127byte_frames; 307 u32 tx_128_to_255byte_frames; 308 u32 tx_256_to_511byte_frames; 309 u32 tx_512_to_1023byte_frames; 310 u32 tx_1024byte_frames; 311 u32 net_bytes; 312 u32 rx_sof_overruns; 313 u32 rx_mof_overruns; 314 u32 rx_dma_overruns; 315 }; 316 317 struct xgbe_hw_stats { 318 u32 rx_good_frames; 319 u32 rx_broadcast_frames; 320 u32 rx_multicast_frames; 321 u32 rx_pause_frames; 322 u32 rx_crc_errors; 323 u32 rx_align_code_errors; 324 u32 rx_oversized_frames; 325 u32 rx_jabber_frames; 326 u32 rx_undersized_frames; 327 u32 rx_fragments; 328 u32 overrun_type4; 329 u32 overrun_type5; 330 u32 rx_bytes; 331 u32 tx_good_frames; 332 u32 tx_broadcast_frames; 333 u32 tx_multicast_frames; 334 u32 tx_pause_frames; 335 u32 tx_deferred_frames; 336 u32 tx_collision_frames; 337 u32 tx_single_coll_frames; 338 u32 tx_mult_coll_frames; 339 u32 tx_excessive_collisions; 340 u32 tx_late_collisions; 341 u32 tx_underrun; 342 u32 tx_carrier_sense_errors; 343 u32 tx_bytes; 344 u32 tx_64byte_frames; 345 u32 tx_65_to_127byte_frames; 346 u32 tx_128_to_255byte_frames; 347 u32 tx_256_to_511byte_frames; 348 u32 tx_512_to_1023byte_frames; 349 u32 tx_1024byte_frames; 350 u32 net_bytes; 351 u32 rx_sof_overruns; 352 u32 rx_mof_overruns; 353 u32 rx_dma_overruns; 354 }; 355 356 struct gbenu_ss_regs { 357 u32 id_ver; 358 u32 synce_count; /* NU */ 359 u32 synce_mux; /* NU */ 360 u32 control; /* 2U */ 361 u32 __rsvd_0[2]; /* 2U */ 362 u32 rgmii_status; /* 2U */ 363 u32 ss_status; /* 2U */ 364 }; 365 366 struct gbenu_switch_regs { 367 u32 id_ver; 368 u32 control; 369 u32 __rsvd_0[2]; 370 u32 emcontrol; 371 u32 stat_port_en; 372 u32 ptype; /* NU */ 373 u32 soft_idle; 374 u32 thru_rate; /* NU */ 375 u32 gap_thresh; /* NU */ 376 u32 tx_start_wds; /* NU */ 377 u32 eee_prescale; /* 2U */ 378 u32 tx_g_oflow_thresh_set; /* NU */ 379 u32 tx_g_oflow_thresh_clr; /* NU */ 380 u32 tx_g_buf_thresh_set_l; /* NU */ 381 u32 tx_g_buf_thresh_set_h; /* NU */ 382 u32 tx_g_buf_thresh_clr_l; /* NU */ 383 u32 tx_g_buf_thresh_clr_h; /* NU */ 384 }; 385 386 struct gbenu_port_regs { 387 u32 __rsvd_0; 388 u32 control; 389 u32 max_blks; /* 2U */ 390 u32 mem_align1; 391 u32 blk_cnt; 392 u32 port_vlan; 393 u32 tx_pri_map; /* NU */ 394 u32 pri_ctl; /* 2U */ 395 u32 rx_pri_map; 396 u32 rx_maxlen; 397 u32 tx_blks_pri; /* NU */ 398 u32 __rsvd_1; 399 u32 idle2lpi; /* 2U */ 400 u32 lpi2idle; /* 2U */ 401 u32 eee_status; /* 2U */ 402 u32 __rsvd_2; 403 u32 __rsvd_3[176]; /* NU: more to add */ 404 u32 __rsvd_4[2]; 405 u32 sa_lo; 406 u32 sa_hi; 407 u32 ts_ctl; 408 u32 ts_seq_ltype; 409 u32 ts_vlan; 410 u32 ts_ctl_ltype2; 411 u32 ts_ctl2; 412 }; 413 414 struct gbenu_host_port_regs { 415 u32 __rsvd_0; 416 u32 control; 417 u32 flow_id_offset; /* 2U */ 418 u32 __rsvd_1; 419 u32 blk_cnt; 420 u32 port_vlan; 421 u32 tx_pri_map; /* NU */ 422 u32 pri_ctl; 423 u32 rx_pri_map; 424 u32 rx_maxlen; 425 u32 tx_blks_pri; /* NU */ 426 u32 __rsvd_2; 427 u32 idle2lpi; /* 2U */ 428 u32 lpi2wake; /* 2U */ 429 u32 eee_status; /* 2U */ 430 u32 __rsvd_3; 431 u32 __rsvd_4[184]; /* NU */ 432 u32 host_blks_pri; /* NU */ 433 }; 434 435 struct gbenu_emac_regs { 436 u32 mac_control; 437 u32 mac_status; 438 u32 soft_reset; 439 u32 boff_test; 440 u32 rx_pause; 441 u32 __rsvd_0[11]; /* NU */ 442 u32 tx_pause; 443 u32 __rsvd_1[11]; /* NU */ 444 u32 em_control; 445 u32 tx_gap; 446 }; 447 448 /* Some hw stat regs are applicable to slave port only. 449 * This is handled by gbenu_et_stats struct. Also some 450 * are for SS version NU and some are for 2U. 451 */ 452 struct gbenu_hw_stats { 453 u32 rx_good_frames; 454 u32 rx_broadcast_frames; 455 u32 rx_multicast_frames; 456 u32 rx_pause_frames; /* slave */ 457 u32 rx_crc_errors; 458 u32 rx_align_code_errors; /* slave */ 459 u32 rx_oversized_frames; 460 u32 rx_jabber_frames; /* slave */ 461 u32 rx_undersized_frames; 462 u32 rx_fragments; /* slave */ 463 u32 ale_drop; 464 u32 ale_overrun_drop; 465 u32 rx_bytes; 466 u32 tx_good_frames; 467 u32 tx_broadcast_frames; 468 u32 tx_multicast_frames; 469 u32 tx_pause_frames; /* slave */ 470 u32 tx_deferred_frames; /* slave */ 471 u32 tx_collision_frames; /* slave */ 472 u32 tx_single_coll_frames; /* slave */ 473 u32 tx_mult_coll_frames; /* slave */ 474 u32 tx_excessive_collisions; /* slave */ 475 u32 tx_late_collisions; /* slave */ 476 u32 rx_ipg_error; /* slave 10G only */ 477 u32 tx_carrier_sense_errors; /* slave */ 478 u32 tx_bytes; 479 u32 tx_64B_frames; 480 u32 tx_65_to_127B_frames; 481 u32 tx_128_to_255B_frames; 482 u32 tx_256_to_511B_frames; 483 u32 tx_512_to_1023B_frames; 484 u32 tx_1024B_frames; 485 u32 net_bytes; 486 u32 rx_bottom_fifo_drop; 487 u32 rx_port_mask_drop; 488 u32 rx_top_fifo_drop; 489 u32 ale_rate_limit_drop; 490 u32 ale_vid_ingress_drop; 491 u32 ale_da_eq_sa_drop; 492 u32 __rsvd_0[3]; 493 u32 ale_unknown_ucast; 494 u32 ale_unknown_ucast_bytes; 495 u32 ale_unknown_mcast; 496 u32 ale_unknown_mcast_bytes; 497 u32 ale_unknown_bcast; 498 u32 ale_unknown_bcast_bytes; 499 u32 ale_pol_match; 500 u32 ale_pol_match_red; /* NU */ 501 u32 ale_pol_match_yellow; /* NU */ 502 u32 __rsvd_1[44]; 503 u32 tx_mem_protect_err; 504 /* following NU only */ 505 u32 tx_pri0; 506 u32 tx_pri1; 507 u32 tx_pri2; 508 u32 tx_pri3; 509 u32 tx_pri4; 510 u32 tx_pri5; 511 u32 tx_pri6; 512 u32 tx_pri7; 513 u32 tx_pri0_bcnt; 514 u32 tx_pri1_bcnt; 515 u32 tx_pri2_bcnt; 516 u32 tx_pri3_bcnt; 517 u32 tx_pri4_bcnt; 518 u32 tx_pri5_bcnt; 519 u32 tx_pri6_bcnt; 520 u32 tx_pri7_bcnt; 521 u32 tx_pri0_drop; 522 u32 tx_pri1_drop; 523 u32 tx_pri2_drop; 524 u32 tx_pri3_drop; 525 u32 tx_pri4_drop; 526 u32 tx_pri5_drop; 527 u32 tx_pri6_drop; 528 u32 tx_pri7_drop; 529 u32 tx_pri0_drop_bcnt; 530 u32 tx_pri1_drop_bcnt; 531 u32 tx_pri2_drop_bcnt; 532 u32 tx_pri3_drop_bcnt; 533 u32 tx_pri4_drop_bcnt; 534 u32 tx_pri5_drop_bcnt; 535 u32 tx_pri6_drop_bcnt; 536 u32 tx_pri7_drop_bcnt; 537 }; 538 539 #define GBENU_HW_STATS_REG_MAP_SZ 0x200 540 541 struct gbe_ss_regs { 542 u32 id_ver; 543 u32 synce_count; 544 u32 synce_mux; 545 }; 546 547 struct gbe_ss_regs_ofs { 548 u16 id_ver; 549 u16 control; 550 }; 551 552 struct gbe_switch_regs { 553 u32 id_ver; 554 u32 control; 555 u32 soft_reset; 556 u32 stat_port_en; 557 u32 ptype; 558 u32 soft_idle; 559 u32 thru_rate; 560 u32 gap_thresh; 561 u32 tx_start_wds; 562 u32 flow_control; 563 }; 564 565 struct gbe_switch_regs_ofs { 566 u16 id_ver; 567 u16 control; 568 u16 soft_reset; 569 u16 emcontrol; 570 u16 stat_port_en; 571 u16 ptype; 572 u16 flow_control; 573 }; 574 575 struct gbe_port_regs { 576 u32 max_blks; 577 u32 blk_cnt; 578 u32 port_vlan; 579 u32 tx_pri_map; 580 u32 sa_lo; 581 u32 sa_hi; 582 u32 ts_ctl; 583 u32 ts_seq_ltype; 584 u32 ts_vlan; 585 u32 ts_ctl_ltype2; 586 u32 ts_ctl2; 587 }; 588 589 struct gbe_port_regs_ofs { 590 u16 port_vlan; 591 u16 tx_pri_map; 592 u16 sa_lo; 593 u16 sa_hi; 594 u16 ts_ctl; 595 u16 ts_seq_ltype; 596 u16 ts_vlan; 597 u16 ts_ctl_ltype2; 598 u16 ts_ctl2; 599 u16 rx_maxlen; /* 2U, NU */ 600 }; 601 602 struct gbe_host_port_regs { 603 u32 src_id; 604 u32 port_vlan; 605 u32 rx_pri_map; 606 u32 rx_maxlen; 607 }; 608 609 struct gbe_host_port_regs_ofs { 610 u16 port_vlan; 611 u16 tx_pri_map; 612 u16 rx_maxlen; 613 }; 614 615 struct gbe_emac_regs { 616 u32 id_ver; 617 u32 mac_control; 618 u32 mac_status; 619 u32 soft_reset; 620 u32 rx_maxlen; 621 u32 __reserved_0; 622 u32 rx_pause; 623 u32 tx_pause; 624 u32 __reserved_1; 625 u32 rx_pri_map; 626 u32 rsvd[6]; 627 }; 628 629 struct gbe_emac_regs_ofs { 630 u16 mac_control; 631 u16 soft_reset; 632 u16 rx_maxlen; 633 }; 634 635 struct gbe_hw_stats { 636 u32 rx_good_frames; 637 u32 rx_broadcast_frames; 638 u32 rx_multicast_frames; 639 u32 rx_pause_frames; 640 u32 rx_crc_errors; 641 u32 rx_align_code_errors; 642 u32 rx_oversized_frames; 643 u32 rx_jabber_frames; 644 u32 rx_undersized_frames; 645 u32 rx_fragments; 646 u32 __pad_0[2]; 647 u32 rx_bytes; 648 u32 tx_good_frames; 649 u32 tx_broadcast_frames; 650 u32 tx_multicast_frames; 651 u32 tx_pause_frames; 652 u32 tx_deferred_frames; 653 u32 tx_collision_frames; 654 u32 tx_single_coll_frames; 655 u32 tx_mult_coll_frames; 656 u32 tx_excessive_collisions; 657 u32 tx_late_collisions; 658 u32 tx_underrun; 659 u32 tx_carrier_sense_errors; 660 u32 tx_bytes; 661 u32 tx_64byte_frames; 662 u32 tx_65_to_127byte_frames; 663 u32 tx_128_to_255byte_frames; 664 u32 tx_256_to_511byte_frames; 665 u32 tx_512_to_1023byte_frames; 666 u32 tx_1024byte_frames; 667 u32 net_bytes; 668 u32 rx_sof_overruns; 669 u32 rx_mof_overruns; 670 u32 rx_dma_overruns; 671 }; 672 673 #define GBE_MAX_HW_STAT_MODS 9 674 #define GBE_HW_STATS_REG_MAP_SZ 0x100 675 676 struct ts_ctl { 677 int uni; 678 u8 dst_port_map; 679 u8 maddr_map; 680 u8 ts_mcast_type; 681 }; 682 683 struct gbe_slave { 684 void __iomem *port_regs; 685 void __iomem *emac_regs; 686 struct gbe_port_regs_ofs port_regs_ofs; 687 struct gbe_emac_regs_ofs emac_regs_ofs; 688 int slave_num; /* 0 based logical number */ 689 int port_num; /* actual port number */ 690 atomic_t link_state; 691 bool open; 692 struct phy_device *phy; 693 u32 link_interface; 694 u32 mac_control; 695 u8 phy_port_t; 696 struct device_node *phy_node; 697 struct ts_ctl ts_ctl; 698 struct list_head slave_list; 699 }; 700 701 struct gbe_priv { 702 struct device *dev; 703 struct netcp_device *netcp_device; 704 struct timer_list timer; 705 u32 num_slaves; 706 u32 ale_entries; 707 u32 ale_ports; 708 bool enable_ale; 709 u8 max_num_slaves; 710 u8 max_num_ports; /* max_num_slaves + 1 */ 711 u8 num_stats_mods; 712 struct netcp_tx_pipe tx_pipe; 713 714 int host_port; 715 u32 rx_packet_max; 716 u32 ss_version; 717 u32 stats_en_mask; 718 719 void __iomem *ss_regs; 720 void __iomem *switch_regs; 721 void __iomem *host_port_regs; 722 void __iomem *ale_reg; 723 void __iomem *cpts_reg; 724 void __iomem *sgmii_port_regs; 725 void __iomem *sgmii_port34_regs; 726 void __iomem *xgbe_serdes_regs; 727 void __iomem *hw_stats_regs[GBE_MAX_HW_STAT_MODS]; 728 729 struct gbe_ss_regs_ofs ss_regs_ofs; 730 struct gbe_switch_regs_ofs switch_regs_ofs; 731 struct gbe_host_port_regs_ofs host_port_regs_ofs; 732 733 struct cpsw_ale *ale; 734 unsigned int tx_queue_id; 735 const char *dma_chan_name; 736 737 struct list_head gbe_intf_head; 738 struct list_head secondary_slaves; 739 struct net_device *dummy_ndev; 740 741 u64 *hw_stats; 742 u32 *hw_stats_prev; 743 const struct netcp_ethtool_stat *et_stats; 744 int num_et_stats; 745 /* Lock for updating the hwstats */ 746 spinlock_t hw_stats_lock; 747 748 int cpts_registered; 749 struct cpts *cpts; 750 }; 751 752 struct gbe_intf { 753 struct net_device *ndev; 754 struct device *dev; 755 struct gbe_priv *gbe_dev; 756 struct netcp_tx_pipe tx_pipe; 757 struct gbe_slave *slave; 758 struct list_head gbe_intf_list; 759 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 760 }; 761 762 static struct netcp_module gbe_module; 763 static struct netcp_module xgbe_module; 764 765 /* Statistic management */ 766 struct netcp_ethtool_stat { 767 char desc[ETH_GSTRING_LEN]; 768 int type; 769 u32 size; 770 int offset; 771 }; 772 773 #define GBE_STATSA_INFO(field) \ 774 { \ 775 "GBE_A:"#field, GBE_STATSA_MODULE, \ 776 FIELD_SIZEOF(struct gbe_hw_stats, field), \ 777 offsetof(struct gbe_hw_stats, field) \ 778 } 779 780 #define GBE_STATSB_INFO(field) \ 781 { \ 782 "GBE_B:"#field, GBE_STATSB_MODULE, \ 783 FIELD_SIZEOF(struct gbe_hw_stats, field), \ 784 offsetof(struct gbe_hw_stats, field) \ 785 } 786 787 #define GBE_STATSC_INFO(field) \ 788 { \ 789 "GBE_C:"#field, GBE_STATSC_MODULE, \ 790 FIELD_SIZEOF(struct gbe_hw_stats, field), \ 791 offsetof(struct gbe_hw_stats, field) \ 792 } 793 794 #define GBE_STATSD_INFO(field) \ 795 { \ 796 "GBE_D:"#field, GBE_STATSD_MODULE, \ 797 FIELD_SIZEOF(struct gbe_hw_stats, field), \ 798 offsetof(struct gbe_hw_stats, field) \ 799 } 800 801 static const struct netcp_ethtool_stat gbe13_et_stats[] = { 802 /* GBE module A */ 803 GBE_STATSA_INFO(rx_good_frames), 804 GBE_STATSA_INFO(rx_broadcast_frames), 805 GBE_STATSA_INFO(rx_multicast_frames), 806 GBE_STATSA_INFO(rx_pause_frames), 807 GBE_STATSA_INFO(rx_crc_errors), 808 GBE_STATSA_INFO(rx_align_code_errors), 809 GBE_STATSA_INFO(rx_oversized_frames), 810 GBE_STATSA_INFO(rx_jabber_frames), 811 GBE_STATSA_INFO(rx_undersized_frames), 812 GBE_STATSA_INFO(rx_fragments), 813 GBE_STATSA_INFO(rx_bytes), 814 GBE_STATSA_INFO(tx_good_frames), 815 GBE_STATSA_INFO(tx_broadcast_frames), 816 GBE_STATSA_INFO(tx_multicast_frames), 817 GBE_STATSA_INFO(tx_pause_frames), 818 GBE_STATSA_INFO(tx_deferred_frames), 819 GBE_STATSA_INFO(tx_collision_frames), 820 GBE_STATSA_INFO(tx_single_coll_frames), 821 GBE_STATSA_INFO(tx_mult_coll_frames), 822 GBE_STATSA_INFO(tx_excessive_collisions), 823 GBE_STATSA_INFO(tx_late_collisions), 824 GBE_STATSA_INFO(tx_underrun), 825 GBE_STATSA_INFO(tx_carrier_sense_errors), 826 GBE_STATSA_INFO(tx_bytes), 827 GBE_STATSA_INFO(tx_64byte_frames), 828 GBE_STATSA_INFO(tx_65_to_127byte_frames), 829 GBE_STATSA_INFO(tx_128_to_255byte_frames), 830 GBE_STATSA_INFO(tx_256_to_511byte_frames), 831 GBE_STATSA_INFO(tx_512_to_1023byte_frames), 832 GBE_STATSA_INFO(tx_1024byte_frames), 833 GBE_STATSA_INFO(net_bytes), 834 GBE_STATSA_INFO(rx_sof_overruns), 835 GBE_STATSA_INFO(rx_mof_overruns), 836 GBE_STATSA_INFO(rx_dma_overruns), 837 /* GBE module B */ 838 GBE_STATSB_INFO(rx_good_frames), 839 GBE_STATSB_INFO(rx_broadcast_frames), 840 GBE_STATSB_INFO(rx_multicast_frames), 841 GBE_STATSB_INFO(rx_pause_frames), 842 GBE_STATSB_INFO(rx_crc_errors), 843 GBE_STATSB_INFO(rx_align_code_errors), 844 GBE_STATSB_INFO(rx_oversized_frames), 845 GBE_STATSB_INFO(rx_jabber_frames), 846 GBE_STATSB_INFO(rx_undersized_frames), 847 GBE_STATSB_INFO(rx_fragments), 848 GBE_STATSB_INFO(rx_bytes), 849 GBE_STATSB_INFO(tx_good_frames), 850 GBE_STATSB_INFO(tx_broadcast_frames), 851 GBE_STATSB_INFO(tx_multicast_frames), 852 GBE_STATSB_INFO(tx_pause_frames), 853 GBE_STATSB_INFO(tx_deferred_frames), 854 GBE_STATSB_INFO(tx_collision_frames), 855 GBE_STATSB_INFO(tx_single_coll_frames), 856 GBE_STATSB_INFO(tx_mult_coll_frames), 857 GBE_STATSB_INFO(tx_excessive_collisions), 858 GBE_STATSB_INFO(tx_late_collisions), 859 GBE_STATSB_INFO(tx_underrun), 860 GBE_STATSB_INFO(tx_carrier_sense_errors), 861 GBE_STATSB_INFO(tx_bytes), 862 GBE_STATSB_INFO(tx_64byte_frames), 863 GBE_STATSB_INFO(tx_65_to_127byte_frames), 864 GBE_STATSB_INFO(tx_128_to_255byte_frames), 865 GBE_STATSB_INFO(tx_256_to_511byte_frames), 866 GBE_STATSB_INFO(tx_512_to_1023byte_frames), 867 GBE_STATSB_INFO(tx_1024byte_frames), 868 GBE_STATSB_INFO(net_bytes), 869 GBE_STATSB_INFO(rx_sof_overruns), 870 GBE_STATSB_INFO(rx_mof_overruns), 871 GBE_STATSB_INFO(rx_dma_overruns), 872 /* GBE module C */ 873 GBE_STATSC_INFO(rx_good_frames), 874 GBE_STATSC_INFO(rx_broadcast_frames), 875 GBE_STATSC_INFO(rx_multicast_frames), 876 GBE_STATSC_INFO(rx_pause_frames), 877 GBE_STATSC_INFO(rx_crc_errors), 878 GBE_STATSC_INFO(rx_align_code_errors), 879 GBE_STATSC_INFO(rx_oversized_frames), 880 GBE_STATSC_INFO(rx_jabber_frames), 881 GBE_STATSC_INFO(rx_undersized_frames), 882 GBE_STATSC_INFO(rx_fragments), 883 GBE_STATSC_INFO(rx_bytes), 884 GBE_STATSC_INFO(tx_good_frames), 885 GBE_STATSC_INFO(tx_broadcast_frames), 886 GBE_STATSC_INFO(tx_multicast_frames), 887 GBE_STATSC_INFO(tx_pause_frames), 888 GBE_STATSC_INFO(tx_deferred_frames), 889 GBE_STATSC_INFO(tx_collision_frames), 890 GBE_STATSC_INFO(tx_single_coll_frames), 891 GBE_STATSC_INFO(tx_mult_coll_frames), 892 GBE_STATSC_INFO(tx_excessive_collisions), 893 GBE_STATSC_INFO(tx_late_collisions), 894 GBE_STATSC_INFO(tx_underrun), 895 GBE_STATSC_INFO(tx_carrier_sense_errors), 896 GBE_STATSC_INFO(tx_bytes), 897 GBE_STATSC_INFO(tx_64byte_frames), 898 GBE_STATSC_INFO(tx_65_to_127byte_frames), 899 GBE_STATSC_INFO(tx_128_to_255byte_frames), 900 GBE_STATSC_INFO(tx_256_to_511byte_frames), 901 GBE_STATSC_INFO(tx_512_to_1023byte_frames), 902 GBE_STATSC_INFO(tx_1024byte_frames), 903 GBE_STATSC_INFO(net_bytes), 904 GBE_STATSC_INFO(rx_sof_overruns), 905 GBE_STATSC_INFO(rx_mof_overruns), 906 GBE_STATSC_INFO(rx_dma_overruns), 907 /* GBE module D */ 908 GBE_STATSD_INFO(rx_good_frames), 909 GBE_STATSD_INFO(rx_broadcast_frames), 910 GBE_STATSD_INFO(rx_multicast_frames), 911 GBE_STATSD_INFO(rx_pause_frames), 912 GBE_STATSD_INFO(rx_crc_errors), 913 GBE_STATSD_INFO(rx_align_code_errors), 914 GBE_STATSD_INFO(rx_oversized_frames), 915 GBE_STATSD_INFO(rx_jabber_frames), 916 GBE_STATSD_INFO(rx_undersized_frames), 917 GBE_STATSD_INFO(rx_fragments), 918 GBE_STATSD_INFO(rx_bytes), 919 GBE_STATSD_INFO(tx_good_frames), 920 GBE_STATSD_INFO(tx_broadcast_frames), 921 GBE_STATSD_INFO(tx_multicast_frames), 922 GBE_STATSD_INFO(tx_pause_frames), 923 GBE_STATSD_INFO(tx_deferred_frames), 924 GBE_STATSD_INFO(tx_collision_frames), 925 GBE_STATSD_INFO(tx_single_coll_frames), 926 GBE_STATSD_INFO(tx_mult_coll_frames), 927 GBE_STATSD_INFO(tx_excessive_collisions), 928 GBE_STATSD_INFO(tx_late_collisions), 929 GBE_STATSD_INFO(tx_underrun), 930 GBE_STATSD_INFO(tx_carrier_sense_errors), 931 GBE_STATSD_INFO(tx_bytes), 932 GBE_STATSD_INFO(tx_64byte_frames), 933 GBE_STATSD_INFO(tx_65_to_127byte_frames), 934 GBE_STATSD_INFO(tx_128_to_255byte_frames), 935 GBE_STATSD_INFO(tx_256_to_511byte_frames), 936 GBE_STATSD_INFO(tx_512_to_1023byte_frames), 937 GBE_STATSD_INFO(tx_1024byte_frames), 938 GBE_STATSD_INFO(net_bytes), 939 GBE_STATSD_INFO(rx_sof_overruns), 940 GBE_STATSD_INFO(rx_mof_overruns), 941 GBE_STATSD_INFO(rx_dma_overruns), 942 }; 943 944 /* This is the size of entries in GBENU_STATS_HOST */ 945 #define GBENU_ET_STATS_HOST_SIZE 52 946 947 #define GBENU_STATS_HOST(field) \ 948 { \ 949 "GBE_HOST:"#field, GBENU_STATS0_MODULE, \ 950 FIELD_SIZEOF(struct gbenu_hw_stats, field), \ 951 offsetof(struct gbenu_hw_stats, field) \ 952 } 953 954 /* This is the size of entries in GBENU_STATS_PORT */ 955 #define GBENU_ET_STATS_PORT_SIZE 65 956 957 #define GBENU_STATS_P1(field) \ 958 { \ 959 "GBE_P1:"#field, GBENU_STATS1_MODULE, \ 960 FIELD_SIZEOF(struct gbenu_hw_stats, field), \ 961 offsetof(struct gbenu_hw_stats, field) \ 962 } 963 964 #define GBENU_STATS_P2(field) \ 965 { \ 966 "GBE_P2:"#field, GBENU_STATS2_MODULE, \ 967 FIELD_SIZEOF(struct gbenu_hw_stats, field), \ 968 offsetof(struct gbenu_hw_stats, field) \ 969 } 970 971 #define GBENU_STATS_P3(field) \ 972 { \ 973 "GBE_P3:"#field, GBENU_STATS3_MODULE, \ 974 FIELD_SIZEOF(struct gbenu_hw_stats, field), \ 975 offsetof(struct gbenu_hw_stats, field) \ 976 } 977 978 #define GBENU_STATS_P4(field) \ 979 { \ 980 "GBE_P4:"#field, GBENU_STATS4_MODULE, \ 981 FIELD_SIZEOF(struct gbenu_hw_stats, field), \ 982 offsetof(struct gbenu_hw_stats, field) \ 983 } 984 985 #define GBENU_STATS_P5(field) \ 986 { \ 987 "GBE_P5:"#field, GBENU_STATS5_MODULE, \ 988 FIELD_SIZEOF(struct gbenu_hw_stats, field), \ 989 offsetof(struct gbenu_hw_stats, field) \ 990 } 991 992 #define GBENU_STATS_P6(field) \ 993 { \ 994 "GBE_P6:"#field, GBENU_STATS6_MODULE, \ 995 FIELD_SIZEOF(struct gbenu_hw_stats, field), \ 996 offsetof(struct gbenu_hw_stats, field) \ 997 } 998 999 #define GBENU_STATS_P7(field) \ 1000 { \ 1001 "GBE_P7:"#field, GBENU_STATS7_MODULE, \ 1002 FIELD_SIZEOF(struct gbenu_hw_stats, field), \ 1003 offsetof(struct gbenu_hw_stats, field) \ 1004 } 1005 1006 #define GBENU_STATS_P8(field) \ 1007 { \ 1008 "GBE_P8:"#field, GBENU_STATS8_MODULE, \ 1009 FIELD_SIZEOF(struct gbenu_hw_stats, field), \ 1010 offsetof(struct gbenu_hw_stats, field) \ 1011 } 1012 1013 static const struct netcp_ethtool_stat gbenu_et_stats[] = { 1014 /* GBENU Host Module */ 1015 GBENU_STATS_HOST(rx_good_frames), 1016 GBENU_STATS_HOST(rx_broadcast_frames), 1017 GBENU_STATS_HOST(rx_multicast_frames), 1018 GBENU_STATS_HOST(rx_crc_errors), 1019 GBENU_STATS_HOST(rx_oversized_frames), 1020 GBENU_STATS_HOST(rx_undersized_frames), 1021 GBENU_STATS_HOST(ale_drop), 1022 GBENU_STATS_HOST(ale_overrun_drop), 1023 GBENU_STATS_HOST(rx_bytes), 1024 GBENU_STATS_HOST(tx_good_frames), 1025 GBENU_STATS_HOST(tx_broadcast_frames), 1026 GBENU_STATS_HOST(tx_multicast_frames), 1027 GBENU_STATS_HOST(tx_bytes), 1028 GBENU_STATS_HOST(tx_64B_frames), 1029 GBENU_STATS_HOST(tx_65_to_127B_frames), 1030 GBENU_STATS_HOST(tx_128_to_255B_frames), 1031 GBENU_STATS_HOST(tx_256_to_511B_frames), 1032 GBENU_STATS_HOST(tx_512_to_1023B_frames), 1033 GBENU_STATS_HOST(tx_1024B_frames), 1034 GBENU_STATS_HOST(net_bytes), 1035 GBENU_STATS_HOST(rx_bottom_fifo_drop), 1036 GBENU_STATS_HOST(rx_port_mask_drop), 1037 GBENU_STATS_HOST(rx_top_fifo_drop), 1038 GBENU_STATS_HOST(ale_rate_limit_drop), 1039 GBENU_STATS_HOST(ale_vid_ingress_drop), 1040 GBENU_STATS_HOST(ale_da_eq_sa_drop), 1041 GBENU_STATS_HOST(ale_unknown_ucast), 1042 GBENU_STATS_HOST(ale_unknown_ucast_bytes), 1043 GBENU_STATS_HOST(ale_unknown_mcast), 1044 GBENU_STATS_HOST(ale_unknown_mcast_bytes), 1045 GBENU_STATS_HOST(ale_unknown_bcast), 1046 GBENU_STATS_HOST(ale_unknown_bcast_bytes), 1047 GBENU_STATS_HOST(ale_pol_match), 1048 GBENU_STATS_HOST(ale_pol_match_red), 1049 GBENU_STATS_HOST(ale_pol_match_yellow), 1050 GBENU_STATS_HOST(tx_mem_protect_err), 1051 GBENU_STATS_HOST(tx_pri0_drop), 1052 GBENU_STATS_HOST(tx_pri1_drop), 1053 GBENU_STATS_HOST(tx_pri2_drop), 1054 GBENU_STATS_HOST(tx_pri3_drop), 1055 GBENU_STATS_HOST(tx_pri4_drop), 1056 GBENU_STATS_HOST(tx_pri5_drop), 1057 GBENU_STATS_HOST(tx_pri6_drop), 1058 GBENU_STATS_HOST(tx_pri7_drop), 1059 GBENU_STATS_HOST(tx_pri0_drop_bcnt), 1060 GBENU_STATS_HOST(tx_pri1_drop_bcnt), 1061 GBENU_STATS_HOST(tx_pri2_drop_bcnt), 1062 GBENU_STATS_HOST(tx_pri3_drop_bcnt), 1063 GBENU_STATS_HOST(tx_pri4_drop_bcnt), 1064 GBENU_STATS_HOST(tx_pri5_drop_bcnt), 1065 GBENU_STATS_HOST(tx_pri6_drop_bcnt), 1066 GBENU_STATS_HOST(tx_pri7_drop_bcnt), 1067 /* GBENU Module 1 */ 1068 GBENU_STATS_P1(rx_good_frames), 1069 GBENU_STATS_P1(rx_broadcast_frames), 1070 GBENU_STATS_P1(rx_multicast_frames), 1071 GBENU_STATS_P1(rx_pause_frames), 1072 GBENU_STATS_P1(rx_crc_errors), 1073 GBENU_STATS_P1(rx_align_code_errors), 1074 GBENU_STATS_P1(rx_oversized_frames), 1075 GBENU_STATS_P1(rx_jabber_frames), 1076 GBENU_STATS_P1(rx_undersized_frames), 1077 GBENU_STATS_P1(rx_fragments), 1078 GBENU_STATS_P1(ale_drop), 1079 GBENU_STATS_P1(ale_overrun_drop), 1080 GBENU_STATS_P1(rx_bytes), 1081 GBENU_STATS_P1(tx_good_frames), 1082 GBENU_STATS_P1(tx_broadcast_frames), 1083 GBENU_STATS_P1(tx_multicast_frames), 1084 GBENU_STATS_P1(tx_pause_frames), 1085 GBENU_STATS_P1(tx_deferred_frames), 1086 GBENU_STATS_P1(tx_collision_frames), 1087 GBENU_STATS_P1(tx_single_coll_frames), 1088 GBENU_STATS_P1(tx_mult_coll_frames), 1089 GBENU_STATS_P1(tx_excessive_collisions), 1090 GBENU_STATS_P1(tx_late_collisions), 1091 GBENU_STATS_P1(rx_ipg_error), 1092 GBENU_STATS_P1(tx_carrier_sense_errors), 1093 GBENU_STATS_P1(tx_bytes), 1094 GBENU_STATS_P1(tx_64B_frames), 1095 GBENU_STATS_P1(tx_65_to_127B_frames), 1096 GBENU_STATS_P1(tx_128_to_255B_frames), 1097 GBENU_STATS_P1(tx_256_to_511B_frames), 1098 GBENU_STATS_P1(tx_512_to_1023B_frames), 1099 GBENU_STATS_P1(tx_1024B_frames), 1100 GBENU_STATS_P1(net_bytes), 1101 GBENU_STATS_P1(rx_bottom_fifo_drop), 1102 GBENU_STATS_P1(rx_port_mask_drop), 1103 GBENU_STATS_P1(rx_top_fifo_drop), 1104 GBENU_STATS_P1(ale_rate_limit_drop), 1105 GBENU_STATS_P1(ale_vid_ingress_drop), 1106 GBENU_STATS_P1(ale_da_eq_sa_drop), 1107 GBENU_STATS_P1(ale_unknown_ucast), 1108 GBENU_STATS_P1(ale_unknown_ucast_bytes), 1109 GBENU_STATS_P1(ale_unknown_mcast), 1110 GBENU_STATS_P1(ale_unknown_mcast_bytes), 1111 GBENU_STATS_P1(ale_unknown_bcast), 1112 GBENU_STATS_P1(ale_unknown_bcast_bytes), 1113 GBENU_STATS_P1(ale_pol_match), 1114 GBENU_STATS_P1(ale_pol_match_red), 1115 GBENU_STATS_P1(ale_pol_match_yellow), 1116 GBENU_STATS_P1(tx_mem_protect_err), 1117 GBENU_STATS_P1(tx_pri0_drop), 1118 GBENU_STATS_P1(tx_pri1_drop), 1119 GBENU_STATS_P1(tx_pri2_drop), 1120 GBENU_STATS_P1(tx_pri3_drop), 1121 GBENU_STATS_P1(tx_pri4_drop), 1122 GBENU_STATS_P1(tx_pri5_drop), 1123 GBENU_STATS_P1(tx_pri6_drop), 1124 GBENU_STATS_P1(tx_pri7_drop), 1125 GBENU_STATS_P1(tx_pri0_drop_bcnt), 1126 GBENU_STATS_P1(tx_pri1_drop_bcnt), 1127 GBENU_STATS_P1(tx_pri2_drop_bcnt), 1128 GBENU_STATS_P1(tx_pri3_drop_bcnt), 1129 GBENU_STATS_P1(tx_pri4_drop_bcnt), 1130 GBENU_STATS_P1(tx_pri5_drop_bcnt), 1131 GBENU_STATS_P1(tx_pri6_drop_bcnt), 1132 GBENU_STATS_P1(tx_pri7_drop_bcnt), 1133 /* GBENU Module 2 */ 1134 GBENU_STATS_P2(rx_good_frames), 1135 GBENU_STATS_P2(rx_broadcast_frames), 1136 GBENU_STATS_P2(rx_multicast_frames), 1137 GBENU_STATS_P2(rx_pause_frames), 1138 GBENU_STATS_P2(rx_crc_errors), 1139 GBENU_STATS_P2(rx_align_code_errors), 1140 GBENU_STATS_P2(rx_oversized_frames), 1141 GBENU_STATS_P2(rx_jabber_frames), 1142 GBENU_STATS_P2(rx_undersized_frames), 1143 GBENU_STATS_P2(rx_fragments), 1144 GBENU_STATS_P2(ale_drop), 1145 GBENU_STATS_P2(ale_overrun_drop), 1146 GBENU_STATS_P2(rx_bytes), 1147 GBENU_STATS_P2(tx_good_frames), 1148 GBENU_STATS_P2(tx_broadcast_frames), 1149 GBENU_STATS_P2(tx_multicast_frames), 1150 GBENU_STATS_P2(tx_pause_frames), 1151 GBENU_STATS_P2(tx_deferred_frames), 1152 GBENU_STATS_P2(tx_collision_frames), 1153 GBENU_STATS_P2(tx_single_coll_frames), 1154 GBENU_STATS_P2(tx_mult_coll_frames), 1155 GBENU_STATS_P2(tx_excessive_collisions), 1156 GBENU_STATS_P2(tx_late_collisions), 1157 GBENU_STATS_P2(rx_ipg_error), 1158 GBENU_STATS_P2(tx_carrier_sense_errors), 1159 GBENU_STATS_P2(tx_bytes), 1160 GBENU_STATS_P2(tx_64B_frames), 1161 GBENU_STATS_P2(tx_65_to_127B_frames), 1162 GBENU_STATS_P2(tx_128_to_255B_frames), 1163 GBENU_STATS_P2(tx_256_to_511B_frames), 1164 GBENU_STATS_P2(tx_512_to_1023B_frames), 1165 GBENU_STATS_P2(tx_1024B_frames), 1166 GBENU_STATS_P2(net_bytes), 1167 GBENU_STATS_P2(rx_bottom_fifo_drop), 1168 GBENU_STATS_P2(rx_port_mask_drop), 1169 GBENU_STATS_P2(rx_top_fifo_drop), 1170 GBENU_STATS_P2(ale_rate_limit_drop), 1171 GBENU_STATS_P2(ale_vid_ingress_drop), 1172 GBENU_STATS_P2(ale_da_eq_sa_drop), 1173 GBENU_STATS_P2(ale_unknown_ucast), 1174 GBENU_STATS_P2(ale_unknown_ucast_bytes), 1175 GBENU_STATS_P2(ale_unknown_mcast), 1176 GBENU_STATS_P2(ale_unknown_mcast_bytes), 1177 GBENU_STATS_P2(ale_unknown_bcast), 1178 GBENU_STATS_P2(ale_unknown_bcast_bytes), 1179 GBENU_STATS_P2(ale_pol_match), 1180 GBENU_STATS_P2(ale_pol_match_red), 1181 GBENU_STATS_P2(ale_pol_match_yellow), 1182 GBENU_STATS_P2(tx_mem_protect_err), 1183 GBENU_STATS_P2(tx_pri0_drop), 1184 GBENU_STATS_P2(tx_pri1_drop), 1185 GBENU_STATS_P2(tx_pri2_drop), 1186 GBENU_STATS_P2(tx_pri3_drop), 1187 GBENU_STATS_P2(tx_pri4_drop), 1188 GBENU_STATS_P2(tx_pri5_drop), 1189 GBENU_STATS_P2(tx_pri6_drop), 1190 GBENU_STATS_P2(tx_pri7_drop), 1191 GBENU_STATS_P2(tx_pri0_drop_bcnt), 1192 GBENU_STATS_P2(tx_pri1_drop_bcnt), 1193 GBENU_STATS_P2(tx_pri2_drop_bcnt), 1194 GBENU_STATS_P2(tx_pri3_drop_bcnt), 1195 GBENU_STATS_P2(tx_pri4_drop_bcnt), 1196 GBENU_STATS_P2(tx_pri5_drop_bcnt), 1197 GBENU_STATS_P2(tx_pri6_drop_bcnt), 1198 GBENU_STATS_P2(tx_pri7_drop_bcnt), 1199 /* GBENU Module 3 */ 1200 GBENU_STATS_P3(rx_good_frames), 1201 GBENU_STATS_P3(rx_broadcast_frames), 1202 GBENU_STATS_P3(rx_multicast_frames), 1203 GBENU_STATS_P3(rx_pause_frames), 1204 GBENU_STATS_P3(rx_crc_errors), 1205 GBENU_STATS_P3(rx_align_code_errors), 1206 GBENU_STATS_P3(rx_oversized_frames), 1207 GBENU_STATS_P3(rx_jabber_frames), 1208 GBENU_STATS_P3(rx_undersized_frames), 1209 GBENU_STATS_P3(rx_fragments), 1210 GBENU_STATS_P3(ale_drop), 1211 GBENU_STATS_P3(ale_overrun_drop), 1212 GBENU_STATS_P3(rx_bytes), 1213 GBENU_STATS_P3(tx_good_frames), 1214 GBENU_STATS_P3(tx_broadcast_frames), 1215 GBENU_STATS_P3(tx_multicast_frames), 1216 GBENU_STATS_P3(tx_pause_frames), 1217 GBENU_STATS_P3(tx_deferred_frames), 1218 GBENU_STATS_P3(tx_collision_frames), 1219 GBENU_STATS_P3(tx_single_coll_frames), 1220 GBENU_STATS_P3(tx_mult_coll_frames), 1221 GBENU_STATS_P3(tx_excessive_collisions), 1222 GBENU_STATS_P3(tx_late_collisions), 1223 GBENU_STATS_P3(rx_ipg_error), 1224 GBENU_STATS_P3(tx_carrier_sense_errors), 1225 GBENU_STATS_P3(tx_bytes), 1226 GBENU_STATS_P3(tx_64B_frames), 1227 GBENU_STATS_P3(tx_65_to_127B_frames), 1228 GBENU_STATS_P3(tx_128_to_255B_frames), 1229 GBENU_STATS_P3(tx_256_to_511B_frames), 1230 GBENU_STATS_P3(tx_512_to_1023B_frames), 1231 GBENU_STATS_P3(tx_1024B_frames), 1232 GBENU_STATS_P3(net_bytes), 1233 GBENU_STATS_P3(rx_bottom_fifo_drop), 1234 GBENU_STATS_P3(rx_port_mask_drop), 1235 GBENU_STATS_P3(rx_top_fifo_drop), 1236 GBENU_STATS_P3(ale_rate_limit_drop), 1237 GBENU_STATS_P3(ale_vid_ingress_drop), 1238 GBENU_STATS_P3(ale_da_eq_sa_drop), 1239 GBENU_STATS_P3(ale_unknown_ucast), 1240 GBENU_STATS_P3(ale_unknown_ucast_bytes), 1241 GBENU_STATS_P3(ale_unknown_mcast), 1242 GBENU_STATS_P3(ale_unknown_mcast_bytes), 1243 GBENU_STATS_P3(ale_unknown_bcast), 1244 GBENU_STATS_P3(ale_unknown_bcast_bytes), 1245 GBENU_STATS_P3(ale_pol_match), 1246 GBENU_STATS_P3(ale_pol_match_red), 1247 GBENU_STATS_P3(ale_pol_match_yellow), 1248 GBENU_STATS_P3(tx_mem_protect_err), 1249 GBENU_STATS_P3(tx_pri0_drop), 1250 GBENU_STATS_P3(tx_pri1_drop), 1251 GBENU_STATS_P3(tx_pri2_drop), 1252 GBENU_STATS_P3(tx_pri3_drop), 1253 GBENU_STATS_P3(tx_pri4_drop), 1254 GBENU_STATS_P3(tx_pri5_drop), 1255 GBENU_STATS_P3(tx_pri6_drop), 1256 GBENU_STATS_P3(tx_pri7_drop), 1257 GBENU_STATS_P3(tx_pri0_drop_bcnt), 1258 GBENU_STATS_P3(tx_pri1_drop_bcnt), 1259 GBENU_STATS_P3(tx_pri2_drop_bcnt), 1260 GBENU_STATS_P3(tx_pri3_drop_bcnt), 1261 GBENU_STATS_P3(tx_pri4_drop_bcnt), 1262 GBENU_STATS_P3(tx_pri5_drop_bcnt), 1263 GBENU_STATS_P3(tx_pri6_drop_bcnt), 1264 GBENU_STATS_P3(tx_pri7_drop_bcnt), 1265 /* GBENU Module 4 */ 1266 GBENU_STATS_P4(rx_good_frames), 1267 GBENU_STATS_P4(rx_broadcast_frames), 1268 GBENU_STATS_P4(rx_multicast_frames), 1269 GBENU_STATS_P4(rx_pause_frames), 1270 GBENU_STATS_P4(rx_crc_errors), 1271 GBENU_STATS_P4(rx_align_code_errors), 1272 GBENU_STATS_P4(rx_oversized_frames), 1273 GBENU_STATS_P4(rx_jabber_frames), 1274 GBENU_STATS_P4(rx_undersized_frames), 1275 GBENU_STATS_P4(rx_fragments), 1276 GBENU_STATS_P4(ale_drop), 1277 GBENU_STATS_P4(ale_overrun_drop), 1278 GBENU_STATS_P4(rx_bytes), 1279 GBENU_STATS_P4(tx_good_frames), 1280 GBENU_STATS_P4(tx_broadcast_frames), 1281 GBENU_STATS_P4(tx_multicast_frames), 1282 GBENU_STATS_P4(tx_pause_frames), 1283 GBENU_STATS_P4(tx_deferred_frames), 1284 GBENU_STATS_P4(tx_collision_frames), 1285 GBENU_STATS_P4(tx_single_coll_frames), 1286 GBENU_STATS_P4(tx_mult_coll_frames), 1287 GBENU_STATS_P4(tx_excessive_collisions), 1288 GBENU_STATS_P4(tx_late_collisions), 1289 GBENU_STATS_P4(rx_ipg_error), 1290 GBENU_STATS_P4(tx_carrier_sense_errors), 1291 GBENU_STATS_P4(tx_bytes), 1292 GBENU_STATS_P4(tx_64B_frames), 1293 GBENU_STATS_P4(tx_65_to_127B_frames), 1294 GBENU_STATS_P4(tx_128_to_255B_frames), 1295 GBENU_STATS_P4(tx_256_to_511B_frames), 1296 GBENU_STATS_P4(tx_512_to_1023B_frames), 1297 GBENU_STATS_P4(tx_1024B_frames), 1298 GBENU_STATS_P4(net_bytes), 1299 GBENU_STATS_P4(rx_bottom_fifo_drop), 1300 GBENU_STATS_P4(rx_port_mask_drop), 1301 GBENU_STATS_P4(rx_top_fifo_drop), 1302 GBENU_STATS_P4(ale_rate_limit_drop), 1303 GBENU_STATS_P4(ale_vid_ingress_drop), 1304 GBENU_STATS_P4(ale_da_eq_sa_drop), 1305 GBENU_STATS_P4(ale_unknown_ucast), 1306 GBENU_STATS_P4(ale_unknown_ucast_bytes), 1307 GBENU_STATS_P4(ale_unknown_mcast), 1308 GBENU_STATS_P4(ale_unknown_mcast_bytes), 1309 GBENU_STATS_P4(ale_unknown_bcast), 1310 GBENU_STATS_P4(ale_unknown_bcast_bytes), 1311 GBENU_STATS_P4(ale_pol_match), 1312 GBENU_STATS_P4(ale_pol_match_red), 1313 GBENU_STATS_P4(ale_pol_match_yellow), 1314 GBENU_STATS_P4(tx_mem_protect_err), 1315 GBENU_STATS_P4(tx_pri0_drop), 1316 GBENU_STATS_P4(tx_pri1_drop), 1317 GBENU_STATS_P4(tx_pri2_drop), 1318 GBENU_STATS_P4(tx_pri3_drop), 1319 GBENU_STATS_P4(tx_pri4_drop), 1320 GBENU_STATS_P4(tx_pri5_drop), 1321 GBENU_STATS_P4(tx_pri6_drop), 1322 GBENU_STATS_P4(tx_pri7_drop), 1323 GBENU_STATS_P4(tx_pri0_drop_bcnt), 1324 GBENU_STATS_P4(tx_pri1_drop_bcnt), 1325 GBENU_STATS_P4(tx_pri2_drop_bcnt), 1326 GBENU_STATS_P4(tx_pri3_drop_bcnt), 1327 GBENU_STATS_P4(tx_pri4_drop_bcnt), 1328 GBENU_STATS_P4(tx_pri5_drop_bcnt), 1329 GBENU_STATS_P4(tx_pri6_drop_bcnt), 1330 GBENU_STATS_P4(tx_pri7_drop_bcnt), 1331 /* GBENU Module 5 */ 1332 GBENU_STATS_P5(rx_good_frames), 1333 GBENU_STATS_P5(rx_broadcast_frames), 1334 GBENU_STATS_P5(rx_multicast_frames), 1335 GBENU_STATS_P5(rx_pause_frames), 1336 GBENU_STATS_P5(rx_crc_errors), 1337 GBENU_STATS_P5(rx_align_code_errors), 1338 GBENU_STATS_P5(rx_oversized_frames), 1339 GBENU_STATS_P5(rx_jabber_frames), 1340 GBENU_STATS_P5(rx_undersized_frames), 1341 GBENU_STATS_P5(rx_fragments), 1342 GBENU_STATS_P5(ale_drop), 1343 GBENU_STATS_P5(ale_overrun_drop), 1344 GBENU_STATS_P5(rx_bytes), 1345 GBENU_STATS_P5(tx_good_frames), 1346 GBENU_STATS_P5(tx_broadcast_frames), 1347 GBENU_STATS_P5(tx_multicast_frames), 1348 GBENU_STATS_P5(tx_pause_frames), 1349 GBENU_STATS_P5(tx_deferred_frames), 1350 GBENU_STATS_P5(tx_collision_frames), 1351 GBENU_STATS_P5(tx_single_coll_frames), 1352 GBENU_STATS_P5(tx_mult_coll_frames), 1353 GBENU_STATS_P5(tx_excessive_collisions), 1354 GBENU_STATS_P5(tx_late_collisions), 1355 GBENU_STATS_P5(rx_ipg_error), 1356 GBENU_STATS_P5(tx_carrier_sense_errors), 1357 GBENU_STATS_P5(tx_bytes), 1358 GBENU_STATS_P5(tx_64B_frames), 1359 GBENU_STATS_P5(tx_65_to_127B_frames), 1360 GBENU_STATS_P5(tx_128_to_255B_frames), 1361 GBENU_STATS_P5(tx_256_to_511B_frames), 1362 GBENU_STATS_P5(tx_512_to_1023B_frames), 1363 GBENU_STATS_P5(tx_1024B_frames), 1364 GBENU_STATS_P5(net_bytes), 1365 GBENU_STATS_P5(rx_bottom_fifo_drop), 1366 GBENU_STATS_P5(rx_port_mask_drop), 1367 GBENU_STATS_P5(rx_top_fifo_drop), 1368 GBENU_STATS_P5(ale_rate_limit_drop), 1369 GBENU_STATS_P5(ale_vid_ingress_drop), 1370 GBENU_STATS_P5(ale_da_eq_sa_drop), 1371 GBENU_STATS_P5(ale_unknown_ucast), 1372 GBENU_STATS_P5(ale_unknown_ucast_bytes), 1373 GBENU_STATS_P5(ale_unknown_mcast), 1374 GBENU_STATS_P5(ale_unknown_mcast_bytes), 1375 GBENU_STATS_P5(ale_unknown_bcast), 1376 GBENU_STATS_P5(ale_unknown_bcast_bytes), 1377 GBENU_STATS_P5(ale_pol_match), 1378 GBENU_STATS_P5(ale_pol_match_red), 1379 GBENU_STATS_P5(ale_pol_match_yellow), 1380 GBENU_STATS_P5(tx_mem_protect_err), 1381 GBENU_STATS_P5(tx_pri0_drop), 1382 GBENU_STATS_P5(tx_pri1_drop), 1383 GBENU_STATS_P5(tx_pri2_drop), 1384 GBENU_STATS_P5(tx_pri3_drop), 1385 GBENU_STATS_P5(tx_pri4_drop), 1386 GBENU_STATS_P5(tx_pri5_drop), 1387 GBENU_STATS_P5(tx_pri6_drop), 1388 GBENU_STATS_P5(tx_pri7_drop), 1389 GBENU_STATS_P5(tx_pri0_drop_bcnt), 1390 GBENU_STATS_P5(tx_pri1_drop_bcnt), 1391 GBENU_STATS_P5(tx_pri2_drop_bcnt), 1392 GBENU_STATS_P5(tx_pri3_drop_bcnt), 1393 GBENU_STATS_P5(tx_pri4_drop_bcnt), 1394 GBENU_STATS_P5(tx_pri5_drop_bcnt), 1395 GBENU_STATS_P5(tx_pri6_drop_bcnt), 1396 GBENU_STATS_P5(tx_pri7_drop_bcnt), 1397 /* GBENU Module 6 */ 1398 GBENU_STATS_P6(rx_good_frames), 1399 GBENU_STATS_P6(rx_broadcast_frames), 1400 GBENU_STATS_P6(rx_multicast_frames), 1401 GBENU_STATS_P6(rx_pause_frames), 1402 GBENU_STATS_P6(rx_crc_errors), 1403 GBENU_STATS_P6(rx_align_code_errors), 1404 GBENU_STATS_P6(rx_oversized_frames), 1405 GBENU_STATS_P6(rx_jabber_frames), 1406 GBENU_STATS_P6(rx_undersized_frames), 1407 GBENU_STATS_P6(rx_fragments), 1408 GBENU_STATS_P6(ale_drop), 1409 GBENU_STATS_P6(ale_overrun_drop), 1410 GBENU_STATS_P6(rx_bytes), 1411 GBENU_STATS_P6(tx_good_frames), 1412 GBENU_STATS_P6(tx_broadcast_frames), 1413 GBENU_STATS_P6(tx_multicast_frames), 1414 GBENU_STATS_P6(tx_pause_frames), 1415 GBENU_STATS_P6(tx_deferred_frames), 1416 GBENU_STATS_P6(tx_collision_frames), 1417 GBENU_STATS_P6(tx_single_coll_frames), 1418 GBENU_STATS_P6(tx_mult_coll_frames), 1419 GBENU_STATS_P6(tx_excessive_collisions), 1420 GBENU_STATS_P6(tx_late_collisions), 1421 GBENU_STATS_P6(rx_ipg_error), 1422 GBENU_STATS_P6(tx_carrier_sense_errors), 1423 GBENU_STATS_P6(tx_bytes), 1424 GBENU_STATS_P6(tx_64B_frames), 1425 GBENU_STATS_P6(tx_65_to_127B_frames), 1426 GBENU_STATS_P6(tx_128_to_255B_frames), 1427 GBENU_STATS_P6(tx_256_to_511B_frames), 1428 GBENU_STATS_P6(tx_512_to_1023B_frames), 1429 GBENU_STATS_P6(tx_1024B_frames), 1430 GBENU_STATS_P6(net_bytes), 1431 GBENU_STATS_P6(rx_bottom_fifo_drop), 1432 GBENU_STATS_P6(rx_port_mask_drop), 1433 GBENU_STATS_P6(rx_top_fifo_drop), 1434 GBENU_STATS_P6(ale_rate_limit_drop), 1435 GBENU_STATS_P6(ale_vid_ingress_drop), 1436 GBENU_STATS_P6(ale_da_eq_sa_drop), 1437 GBENU_STATS_P6(ale_unknown_ucast), 1438 GBENU_STATS_P6(ale_unknown_ucast_bytes), 1439 GBENU_STATS_P6(ale_unknown_mcast), 1440 GBENU_STATS_P6(ale_unknown_mcast_bytes), 1441 GBENU_STATS_P6(ale_unknown_bcast), 1442 GBENU_STATS_P6(ale_unknown_bcast_bytes), 1443 GBENU_STATS_P6(ale_pol_match), 1444 GBENU_STATS_P6(ale_pol_match_red), 1445 GBENU_STATS_P6(ale_pol_match_yellow), 1446 GBENU_STATS_P6(tx_mem_protect_err), 1447 GBENU_STATS_P6(tx_pri0_drop), 1448 GBENU_STATS_P6(tx_pri1_drop), 1449 GBENU_STATS_P6(tx_pri2_drop), 1450 GBENU_STATS_P6(tx_pri3_drop), 1451 GBENU_STATS_P6(tx_pri4_drop), 1452 GBENU_STATS_P6(tx_pri5_drop), 1453 GBENU_STATS_P6(tx_pri6_drop), 1454 GBENU_STATS_P6(tx_pri7_drop), 1455 GBENU_STATS_P6(tx_pri0_drop_bcnt), 1456 GBENU_STATS_P6(tx_pri1_drop_bcnt), 1457 GBENU_STATS_P6(tx_pri2_drop_bcnt), 1458 GBENU_STATS_P6(tx_pri3_drop_bcnt), 1459 GBENU_STATS_P6(tx_pri4_drop_bcnt), 1460 GBENU_STATS_P6(tx_pri5_drop_bcnt), 1461 GBENU_STATS_P6(tx_pri6_drop_bcnt), 1462 GBENU_STATS_P6(tx_pri7_drop_bcnt), 1463 /* GBENU Module 7 */ 1464 GBENU_STATS_P7(rx_good_frames), 1465 GBENU_STATS_P7(rx_broadcast_frames), 1466 GBENU_STATS_P7(rx_multicast_frames), 1467 GBENU_STATS_P7(rx_pause_frames), 1468 GBENU_STATS_P7(rx_crc_errors), 1469 GBENU_STATS_P7(rx_align_code_errors), 1470 GBENU_STATS_P7(rx_oversized_frames), 1471 GBENU_STATS_P7(rx_jabber_frames), 1472 GBENU_STATS_P7(rx_undersized_frames), 1473 GBENU_STATS_P7(rx_fragments), 1474 GBENU_STATS_P7(ale_drop), 1475 GBENU_STATS_P7(ale_overrun_drop), 1476 GBENU_STATS_P7(rx_bytes), 1477 GBENU_STATS_P7(tx_good_frames), 1478 GBENU_STATS_P7(tx_broadcast_frames), 1479 GBENU_STATS_P7(tx_multicast_frames), 1480 GBENU_STATS_P7(tx_pause_frames), 1481 GBENU_STATS_P7(tx_deferred_frames), 1482 GBENU_STATS_P7(tx_collision_frames), 1483 GBENU_STATS_P7(tx_single_coll_frames), 1484 GBENU_STATS_P7(tx_mult_coll_frames), 1485 GBENU_STATS_P7(tx_excessive_collisions), 1486 GBENU_STATS_P7(tx_late_collisions), 1487 GBENU_STATS_P7(rx_ipg_error), 1488 GBENU_STATS_P7(tx_carrier_sense_errors), 1489 GBENU_STATS_P7(tx_bytes), 1490 GBENU_STATS_P7(tx_64B_frames), 1491 GBENU_STATS_P7(tx_65_to_127B_frames), 1492 GBENU_STATS_P7(tx_128_to_255B_frames), 1493 GBENU_STATS_P7(tx_256_to_511B_frames), 1494 GBENU_STATS_P7(tx_512_to_1023B_frames), 1495 GBENU_STATS_P7(tx_1024B_frames), 1496 GBENU_STATS_P7(net_bytes), 1497 GBENU_STATS_P7(rx_bottom_fifo_drop), 1498 GBENU_STATS_P7(rx_port_mask_drop), 1499 GBENU_STATS_P7(rx_top_fifo_drop), 1500 GBENU_STATS_P7(ale_rate_limit_drop), 1501 GBENU_STATS_P7(ale_vid_ingress_drop), 1502 GBENU_STATS_P7(ale_da_eq_sa_drop), 1503 GBENU_STATS_P7(ale_unknown_ucast), 1504 GBENU_STATS_P7(ale_unknown_ucast_bytes), 1505 GBENU_STATS_P7(ale_unknown_mcast), 1506 GBENU_STATS_P7(ale_unknown_mcast_bytes), 1507 GBENU_STATS_P7(ale_unknown_bcast), 1508 GBENU_STATS_P7(ale_unknown_bcast_bytes), 1509 GBENU_STATS_P7(ale_pol_match), 1510 GBENU_STATS_P7(ale_pol_match_red), 1511 GBENU_STATS_P7(ale_pol_match_yellow), 1512 GBENU_STATS_P7(tx_mem_protect_err), 1513 GBENU_STATS_P7(tx_pri0_drop), 1514 GBENU_STATS_P7(tx_pri1_drop), 1515 GBENU_STATS_P7(tx_pri2_drop), 1516 GBENU_STATS_P7(tx_pri3_drop), 1517 GBENU_STATS_P7(tx_pri4_drop), 1518 GBENU_STATS_P7(tx_pri5_drop), 1519 GBENU_STATS_P7(tx_pri6_drop), 1520 GBENU_STATS_P7(tx_pri7_drop), 1521 GBENU_STATS_P7(tx_pri0_drop_bcnt), 1522 GBENU_STATS_P7(tx_pri1_drop_bcnt), 1523 GBENU_STATS_P7(tx_pri2_drop_bcnt), 1524 GBENU_STATS_P7(tx_pri3_drop_bcnt), 1525 GBENU_STATS_P7(tx_pri4_drop_bcnt), 1526 GBENU_STATS_P7(tx_pri5_drop_bcnt), 1527 GBENU_STATS_P7(tx_pri6_drop_bcnt), 1528 GBENU_STATS_P7(tx_pri7_drop_bcnt), 1529 /* GBENU Module 8 */ 1530 GBENU_STATS_P8(rx_good_frames), 1531 GBENU_STATS_P8(rx_broadcast_frames), 1532 GBENU_STATS_P8(rx_multicast_frames), 1533 GBENU_STATS_P8(rx_pause_frames), 1534 GBENU_STATS_P8(rx_crc_errors), 1535 GBENU_STATS_P8(rx_align_code_errors), 1536 GBENU_STATS_P8(rx_oversized_frames), 1537 GBENU_STATS_P8(rx_jabber_frames), 1538 GBENU_STATS_P8(rx_undersized_frames), 1539 GBENU_STATS_P8(rx_fragments), 1540 GBENU_STATS_P8(ale_drop), 1541 GBENU_STATS_P8(ale_overrun_drop), 1542 GBENU_STATS_P8(rx_bytes), 1543 GBENU_STATS_P8(tx_good_frames), 1544 GBENU_STATS_P8(tx_broadcast_frames), 1545 GBENU_STATS_P8(tx_multicast_frames), 1546 GBENU_STATS_P8(tx_pause_frames), 1547 GBENU_STATS_P8(tx_deferred_frames), 1548 GBENU_STATS_P8(tx_collision_frames), 1549 GBENU_STATS_P8(tx_single_coll_frames), 1550 GBENU_STATS_P8(tx_mult_coll_frames), 1551 GBENU_STATS_P8(tx_excessive_collisions), 1552 GBENU_STATS_P8(tx_late_collisions), 1553 GBENU_STATS_P8(rx_ipg_error), 1554 GBENU_STATS_P8(tx_carrier_sense_errors), 1555 GBENU_STATS_P8(tx_bytes), 1556 GBENU_STATS_P8(tx_64B_frames), 1557 GBENU_STATS_P8(tx_65_to_127B_frames), 1558 GBENU_STATS_P8(tx_128_to_255B_frames), 1559 GBENU_STATS_P8(tx_256_to_511B_frames), 1560 GBENU_STATS_P8(tx_512_to_1023B_frames), 1561 GBENU_STATS_P8(tx_1024B_frames), 1562 GBENU_STATS_P8(net_bytes), 1563 GBENU_STATS_P8(rx_bottom_fifo_drop), 1564 GBENU_STATS_P8(rx_port_mask_drop), 1565 GBENU_STATS_P8(rx_top_fifo_drop), 1566 GBENU_STATS_P8(ale_rate_limit_drop), 1567 GBENU_STATS_P8(ale_vid_ingress_drop), 1568 GBENU_STATS_P8(ale_da_eq_sa_drop), 1569 GBENU_STATS_P8(ale_unknown_ucast), 1570 GBENU_STATS_P8(ale_unknown_ucast_bytes), 1571 GBENU_STATS_P8(ale_unknown_mcast), 1572 GBENU_STATS_P8(ale_unknown_mcast_bytes), 1573 GBENU_STATS_P8(ale_unknown_bcast), 1574 GBENU_STATS_P8(ale_unknown_bcast_bytes), 1575 GBENU_STATS_P8(ale_pol_match), 1576 GBENU_STATS_P8(ale_pol_match_red), 1577 GBENU_STATS_P8(ale_pol_match_yellow), 1578 GBENU_STATS_P8(tx_mem_protect_err), 1579 GBENU_STATS_P8(tx_pri0_drop), 1580 GBENU_STATS_P8(tx_pri1_drop), 1581 GBENU_STATS_P8(tx_pri2_drop), 1582 GBENU_STATS_P8(tx_pri3_drop), 1583 GBENU_STATS_P8(tx_pri4_drop), 1584 GBENU_STATS_P8(tx_pri5_drop), 1585 GBENU_STATS_P8(tx_pri6_drop), 1586 GBENU_STATS_P8(tx_pri7_drop), 1587 GBENU_STATS_P8(tx_pri0_drop_bcnt), 1588 GBENU_STATS_P8(tx_pri1_drop_bcnt), 1589 GBENU_STATS_P8(tx_pri2_drop_bcnt), 1590 GBENU_STATS_P8(tx_pri3_drop_bcnt), 1591 GBENU_STATS_P8(tx_pri4_drop_bcnt), 1592 GBENU_STATS_P8(tx_pri5_drop_bcnt), 1593 GBENU_STATS_P8(tx_pri6_drop_bcnt), 1594 GBENU_STATS_P8(tx_pri7_drop_bcnt), 1595 }; 1596 1597 #define XGBE_STATS0_INFO(field) \ 1598 { \ 1599 "GBE_0:"#field, XGBE_STATS0_MODULE, \ 1600 FIELD_SIZEOF(struct xgbe_hw_stats, field), \ 1601 offsetof(struct xgbe_hw_stats, field) \ 1602 } 1603 1604 #define XGBE_STATS1_INFO(field) \ 1605 { \ 1606 "GBE_1:"#field, XGBE_STATS1_MODULE, \ 1607 FIELD_SIZEOF(struct xgbe_hw_stats, field), \ 1608 offsetof(struct xgbe_hw_stats, field) \ 1609 } 1610 1611 #define XGBE_STATS2_INFO(field) \ 1612 { \ 1613 "GBE_2:"#field, XGBE_STATS2_MODULE, \ 1614 FIELD_SIZEOF(struct xgbe_hw_stats, field), \ 1615 offsetof(struct xgbe_hw_stats, field) \ 1616 } 1617 1618 static const struct netcp_ethtool_stat xgbe10_et_stats[] = { 1619 /* GBE module 0 */ 1620 XGBE_STATS0_INFO(rx_good_frames), 1621 XGBE_STATS0_INFO(rx_broadcast_frames), 1622 XGBE_STATS0_INFO(rx_multicast_frames), 1623 XGBE_STATS0_INFO(rx_oversized_frames), 1624 XGBE_STATS0_INFO(rx_undersized_frames), 1625 XGBE_STATS0_INFO(overrun_type4), 1626 XGBE_STATS0_INFO(overrun_type5), 1627 XGBE_STATS0_INFO(rx_bytes), 1628 XGBE_STATS0_INFO(tx_good_frames), 1629 XGBE_STATS0_INFO(tx_broadcast_frames), 1630 XGBE_STATS0_INFO(tx_multicast_frames), 1631 XGBE_STATS0_INFO(tx_bytes), 1632 XGBE_STATS0_INFO(tx_64byte_frames), 1633 XGBE_STATS0_INFO(tx_65_to_127byte_frames), 1634 XGBE_STATS0_INFO(tx_128_to_255byte_frames), 1635 XGBE_STATS0_INFO(tx_256_to_511byte_frames), 1636 XGBE_STATS0_INFO(tx_512_to_1023byte_frames), 1637 XGBE_STATS0_INFO(tx_1024byte_frames), 1638 XGBE_STATS0_INFO(net_bytes), 1639 XGBE_STATS0_INFO(rx_sof_overruns), 1640 XGBE_STATS0_INFO(rx_mof_overruns), 1641 XGBE_STATS0_INFO(rx_dma_overruns), 1642 /* XGBE module 1 */ 1643 XGBE_STATS1_INFO(rx_good_frames), 1644 XGBE_STATS1_INFO(rx_broadcast_frames), 1645 XGBE_STATS1_INFO(rx_multicast_frames), 1646 XGBE_STATS1_INFO(rx_pause_frames), 1647 XGBE_STATS1_INFO(rx_crc_errors), 1648 XGBE_STATS1_INFO(rx_align_code_errors), 1649 XGBE_STATS1_INFO(rx_oversized_frames), 1650 XGBE_STATS1_INFO(rx_jabber_frames), 1651 XGBE_STATS1_INFO(rx_undersized_frames), 1652 XGBE_STATS1_INFO(rx_fragments), 1653 XGBE_STATS1_INFO(overrun_type4), 1654 XGBE_STATS1_INFO(overrun_type5), 1655 XGBE_STATS1_INFO(rx_bytes), 1656 XGBE_STATS1_INFO(tx_good_frames), 1657 XGBE_STATS1_INFO(tx_broadcast_frames), 1658 XGBE_STATS1_INFO(tx_multicast_frames), 1659 XGBE_STATS1_INFO(tx_pause_frames), 1660 XGBE_STATS1_INFO(tx_deferred_frames), 1661 XGBE_STATS1_INFO(tx_collision_frames), 1662 XGBE_STATS1_INFO(tx_single_coll_frames), 1663 XGBE_STATS1_INFO(tx_mult_coll_frames), 1664 XGBE_STATS1_INFO(tx_excessive_collisions), 1665 XGBE_STATS1_INFO(tx_late_collisions), 1666 XGBE_STATS1_INFO(tx_underrun), 1667 XGBE_STATS1_INFO(tx_carrier_sense_errors), 1668 XGBE_STATS1_INFO(tx_bytes), 1669 XGBE_STATS1_INFO(tx_64byte_frames), 1670 XGBE_STATS1_INFO(tx_65_to_127byte_frames), 1671 XGBE_STATS1_INFO(tx_128_to_255byte_frames), 1672 XGBE_STATS1_INFO(tx_256_to_511byte_frames), 1673 XGBE_STATS1_INFO(tx_512_to_1023byte_frames), 1674 XGBE_STATS1_INFO(tx_1024byte_frames), 1675 XGBE_STATS1_INFO(net_bytes), 1676 XGBE_STATS1_INFO(rx_sof_overruns), 1677 XGBE_STATS1_INFO(rx_mof_overruns), 1678 XGBE_STATS1_INFO(rx_dma_overruns), 1679 /* XGBE module 2 */ 1680 XGBE_STATS2_INFO(rx_good_frames), 1681 XGBE_STATS2_INFO(rx_broadcast_frames), 1682 XGBE_STATS2_INFO(rx_multicast_frames), 1683 XGBE_STATS2_INFO(rx_pause_frames), 1684 XGBE_STATS2_INFO(rx_crc_errors), 1685 XGBE_STATS2_INFO(rx_align_code_errors), 1686 XGBE_STATS2_INFO(rx_oversized_frames), 1687 XGBE_STATS2_INFO(rx_jabber_frames), 1688 XGBE_STATS2_INFO(rx_undersized_frames), 1689 XGBE_STATS2_INFO(rx_fragments), 1690 XGBE_STATS2_INFO(overrun_type4), 1691 XGBE_STATS2_INFO(overrun_type5), 1692 XGBE_STATS2_INFO(rx_bytes), 1693 XGBE_STATS2_INFO(tx_good_frames), 1694 XGBE_STATS2_INFO(tx_broadcast_frames), 1695 XGBE_STATS2_INFO(tx_multicast_frames), 1696 XGBE_STATS2_INFO(tx_pause_frames), 1697 XGBE_STATS2_INFO(tx_deferred_frames), 1698 XGBE_STATS2_INFO(tx_collision_frames), 1699 XGBE_STATS2_INFO(tx_single_coll_frames), 1700 XGBE_STATS2_INFO(tx_mult_coll_frames), 1701 XGBE_STATS2_INFO(tx_excessive_collisions), 1702 XGBE_STATS2_INFO(tx_late_collisions), 1703 XGBE_STATS2_INFO(tx_underrun), 1704 XGBE_STATS2_INFO(tx_carrier_sense_errors), 1705 XGBE_STATS2_INFO(tx_bytes), 1706 XGBE_STATS2_INFO(tx_64byte_frames), 1707 XGBE_STATS2_INFO(tx_65_to_127byte_frames), 1708 XGBE_STATS2_INFO(tx_128_to_255byte_frames), 1709 XGBE_STATS2_INFO(tx_256_to_511byte_frames), 1710 XGBE_STATS2_INFO(tx_512_to_1023byte_frames), 1711 XGBE_STATS2_INFO(tx_1024byte_frames), 1712 XGBE_STATS2_INFO(net_bytes), 1713 XGBE_STATS2_INFO(rx_sof_overruns), 1714 XGBE_STATS2_INFO(rx_mof_overruns), 1715 XGBE_STATS2_INFO(rx_dma_overruns), 1716 }; 1717 1718 #define for_each_intf(i, priv) \ 1719 list_for_each_entry((i), &(priv)->gbe_intf_head, gbe_intf_list) 1720 1721 #define for_each_sec_slave(slave, priv) \ 1722 list_for_each_entry((slave), &(priv)->secondary_slaves, slave_list) 1723 1724 #define first_sec_slave(priv) \ 1725 list_first_entry(&priv->secondary_slaves, \ 1726 struct gbe_slave, slave_list) 1727 1728 static void keystone_get_drvinfo(struct net_device *ndev, 1729 struct ethtool_drvinfo *info) 1730 { 1731 strncpy(info->driver, NETCP_DRIVER_NAME, sizeof(info->driver)); 1732 strncpy(info->version, NETCP_DRIVER_VERSION, sizeof(info->version)); 1733 } 1734 1735 static u32 keystone_get_msglevel(struct net_device *ndev) 1736 { 1737 struct netcp_intf *netcp = netdev_priv(ndev); 1738 1739 return netcp->msg_enable; 1740 } 1741 1742 static void keystone_set_msglevel(struct net_device *ndev, u32 value) 1743 { 1744 struct netcp_intf *netcp = netdev_priv(ndev); 1745 1746 netcp->msg_enable = value; 1747 } 1748 1749 static struct gbe_intf *keystone_get_intf_data(struct netcp_intf *netcp) 1750 { 1751 struct gbe_intf *gbe_intf; 1752 1753 gbe_intf = netcp_module_get_intf_data(&gbe_module, netcp); 1754 if (!gbe_intf) 1755 gbe_intf = netcp_module_get_intf_data(&xgbe_module, netcp); 1756 1757 return gbe_intf; 1758 } 1759 1760 static void keystone_get_stat_strings(struct net_device *ndev, 1761 uint32_t stringset, uint8_t *data) 1762 { 1763 struct netcp_intf *netcp = netdev_priv(ndev); 1764 struct gbe_intf *gbe_intf; 1765 struct gbe_priv *gbe_dev; 1766 int i; 1767 1768 gbe_intf = keystone_get_intf_data(netcp); 1769 if (!gbe_intf) 1770 return; 1771 gbe_dev = gbe_intf->gbe_dev; 1772 1773 switch (stringset) { 1774 case ETH_SS_STATS: 1775 for (i = 0; i < gbe_dev->num_et_stats; i++) { 1776 memcpy(data, gbe_dev->et_stats[i].desc, 1777 ETH_GSTRING_LEN); 1778 data += ETH_GSTRING_LEN; 1779 } 1780 break; 1781 case ETH_SS_TEST: 1782 break; 1783 } 1784 } 1785 1786 static int keystone_get_sset_count(struct net_device *ndev, int stringset) 1787 { 1788 struct netcp_intf *netcp = netdev_priv(ndev); 1789 struct gbe_intf *gbe_intf; 1790 struct gbe_priv *gbe_dev; 1791 1792 gbe_intf = keystone_get_intf_data(netcp); 1793 if (!gbe_intf) 1794 return -EINVAL; 1795 gbe_dev = gbe_intf->gbe_dev; 1796 1797 switch (stringset) { 1798 case ETH_SS_TEST: 1799 return 0; 1800 case ETH_SS_STATS: 1801 return gbe_dev->num_et_stats; 1802 default: 1803 return -EINVAL; 1804 } 1805 } 1806 1807 static void gbe_reset_mod_stats(struct gbe_priv *gbe_dev, int stats_mod) 1808 { 1809 void __iomem *base = gbe_dev->hw_stats_regs[stats_mod]; 1810 u32 __iomem *p_stats_entry; 1811 int i; 1812 1813 for (i = 0; i < gbe_dev->num_et_stats; i++) { 1814 if (gbe_dev->et_stats[i].type == stats_mod) { 1815 p_stats_entry = base + gbe_dev->et_stats[i].offset; 1816 gbe_dev->hw_stats[i] = 0; 1817 gbe_dev->hw_stats_prev[i] = readl(p_stats_entry); 1818 } 1819 } 1820 } 1821 1822 static inline void gbe_update_hw_stats_entry(struct gbe_priv *gbe_dev, 1823 int et_stats_entry) 1824 { 1825 void __iomem *base = NULL; 1826 u32 __iomem *p_stats_entry; 1827 u32 curr, delta; 1828 1829 /* The hw_stats_regs pointers are already 1830 * properly set to point to the right base: 1831 */ 1832 base = gbe_dev->hw_stats_regs[gbe_dev->et_stats[et_stats_entry].type]; 1833 p_stats_entry = base + gbe_dev->et_stats[et_stats_entry].offset; 1834 curr = readl(p_stats_entry); 1835 delta = curr - gbe_dev->hw_stats_prev[et_stats_entry]; 1836 gbe_dev->hw_stats_prev[et_stats_entry] = curr; 1837 gbe_dev->hw_stats[et_stats_entry] += delta; 1838 } 1839 1840 static void gbe_update_stats(struct gbe_priv *gbe_dev, uint64_t *data) 1841 { 1842 int i; 1843 1844 for (i = 0; i < gbe_dev->num_et_stats; i++) { 1845 gbe_update_hw_stats_entry(gbe_dev, i); 1846 1847 if (data) 1848 data[i] = gbe_dev->hw_stats[i]; 1849 } 1850 } 1851 1852 static inline void gbe_stats_mod_visible_ver14(struct gbe_priv *gbe_dev, 1853 int stats_mod) 1854 { 1855 u32 val; 1856 1857 val = readl(GBE_REG_ADDR(gbe_dev, switch_regs, stat_port_en)); 1858 1859 switch (stats_mod) { 1860 case GBE_STATSA_MODULE: 1861 case GBE_STATSB_MODULE: 1862 val &= ~GBE_STATS_CD_SEL; 1863 break; 1864 case GBE_STATSC_MODULE: 1865 case GBE_STATSD_MODULE: 1866 val |= GBE_STATS_CD_SEL; 1867 break; 1868 default: 1869 return; 1870 } 1871 1872 /* make the stat module visible */ 1873 writel(val, GBE_REG_ADDR(gbe_dev, switch_regs, stat_port_en)); 1874 } 1875 1876 static void gbe_reset_mod_stats_ver14(struct gbe_priv *gbe_dev, int stats_mod) 1877 { 1878 gbe_stats_mod_visible_ver14(gbe_dev, stats_mod); 1879 gbe_reset_mod_stats(gbe_dev, stats_mod); 1880 } 1881 1882 static void gbe_update_stats_ver14(struct gbe_priv *gbe_dev, uint64_t *data) 1883 { 1884 u32 half_num_et_stats = (gbe_dev->num_et_stats / 2); 1885 int et_entry, j, pair; 1886 1887 for (pair = 0; pair < 2; pair++) { 1888 gbe_stats_mod_visible_ver14(gbe_dev, (pair ? 1889 GBE_STATSC_MODULE : 1890 GBE_STATSA_MODULE)); 1891 1892 for (j = 0; j < half_num_et_stats; j++) { 1893 et_entry = pair * half_num_et_stats + j; 1894 gbe_update_hw_stats_entry(gbe_dev, et_entry); 1895 1896 if (data) 1897 data[et_entry] = gbe_dev->hw_stats[et_entry]; 1898 } 1899 } 1900 } 1901 1902 static void keystone_get_ethtool_stats(struct net_device *ndev, 1903 struct ethtool_stats *stats, 1904 uint64_t *data) 1905 { 1906 struct netcp_intf *netcp = netdev_priv(ndev); 1907 struct gbe_intf *gbe_intf; 1908 struct gbe_priv *gbe_dev; 1909 1910 gbe_intf = keystone_get_intf_data(netcp); 1911 if (!gbe_intf) 1912 return; 1913 1914 gbe_dev = gbe_intf->gbe_dev; 1915 spin_lock_bh(&gbe_dev->hw_stats_lock); 1916 if (gbe_dev->ss_version == GBE_SS_VERSION_14) 1917 gbe_update_stats_ver14(gbe_dev, data); 1918 else 1919 gbe_update_stats(gbe_dev, data); 1920 spin_unlock_bh(&gbe_dev->hw_stats_lock); 1921 } 1922 1923 static int keystone_get_link_ksettings(struct net_device *ndev, 1924 struct ethtool_link_ksettings *cmd) 1925 { 1926 struct netcp_intf *netcp = netdev_priv(ndev); 1927 struct phy_device *phy = ndev->phydev; 1928 struct gbe_intf *gbe_intf; 1929 int ret; 1930 1931 if (!phy) 1932 return -EINVAL; 1933 1934 gbe_intf = keystone_get_intf_data(netcp); 1935 if (!gbe_intf) 1936 return -EINVAL; 1937 1938 if (!gbe_intf->slave) 1939 return -EINVAL; 1940 1941 ret = phy_ethtool_ksettings_get(phy, cmd); 1942 if (!ret) 1943 cmd->base.port = gbe_intf->slave->phy_port_t; 1944 1945 return ret; 1946 } 1947 1948 static int keystone_set_link_ksettings(struct net_device *ndev, 1949 const struct ethtool_link_ksettings *cmd) 1950 { 1951 struct netcp_intf *netcp = netdev_priv(ndev); 1952 struct phy_device *phy = ndev->phydev; 1953 struct gbe_intf *gbe_intf; 1954 u8 port = cmd->base.port; 1955 u32 advertising, supported; 1956 u32 features; 1957 1958 ethtool_convert_link_mode_to_legacy_u32(&advertising, 1959 cmd->link_modes.advertising); 1960 ethtool_convert_link_mode_to_legacy_u32(&supported, 1961 cmd->link_modes.supported); 1962 features = advertising & supported; 1963 1964 if (!phy) 1965 return -EINVAL; 1966 1967 gbe_intf = keystone_get_intf_data(netcp); 1968 if (!gbe_intf) 1969 return -EINVAL; 1970 1971 if (!gbe_intf->slave) 1972 return -EINVAL; 1973 1974 if (port != gbe_intf->slave->phy_port_t) { 1975 if ((port == PORT_TP) && !(features & ADVERTISED_TP)) 1976 return -EINVAL; 1977 1978 if ((port == PORT_AUI) && !(features & ADVERTISED_AUI)) 1979 return -EINVAL; 1980 1981 if ((port == PORT_BNC) && !(features & ADVERTISED_BNC)) 1982 return -EINVAL; 1983 1984 if ((port == PORT_MII) && !(features & ADVERTISED_MII)) 1985 return -EINVAL; 1986 1987 if ((port == PORT_FIBRE) && !(features & ADVERTISED_FIBRE)) 1988 return -EINVAL; 1989 } 1990 1991 gbe_intf->slave->phy_port_t = port; 1992 return phy_ethtool_ksettings_set(phy, cmd); 1993 } 1994 1995 #if IS_ENABLED(CONFIG_TI_CPTS) 1996 static int keystone_get_ts_info(struct net_device *ndev, 1997 struct ethtool_ts_info *info) 1998 { 1999 struct netcp_intf *netcp = netdev_priv(ndev); 2000 struct gbe_intf *gbe_intf; 2001 2002 gbe_intf = netcp_module_get_intf_data(&gbe_module, netcp); 2003 if (!gbe_intf || !gbe_intf->gbe_dev->cpts) 2004 return -EINVAL; 2005 2006 info->so_timestamping = 2007 SOF_TIMESTAMPING_TX_HARDWARE | 2008 SOF_TIMESTAMPING_TX_SOFTWARE | 2009 SOF_TIMESTAMPING_RX_HARDWARE | 2010 SOF_TIMESTAMPING_RX_SOFTWARE | 2011 SOF_TIMESTAMPING_SOFTWARE | 2012 SOF_TIMESTAMPING_RAW_HARDWARE; 2013 info->phc_index = gbe_intf->gbe_dev->cpts->phc_index; 2014 info->tx_types = 2015 (1 << HWTSTAMP_TX_OFF) | 2016 (1 << HWTSTAMP_TX_ON); 2017 info->rx_filters = 2018 (1 << HWTSTAMP_FILTER_NONE) | 2019 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 2020 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 2021 return 0; 2022 } 2023 #else 2024 static int keystone_get_ts_info(struct net_device *ndev, 2025 struct ethtool_ts_info *info) 2026 { 2027 info->so_timestamping = 2028 SOF_TIMESTAMPING_TX_SOFTWARE | 2029 SOF_TIMESTAMPING_RX_SOFTWARE | 2030 SOF_TIMESTAMPING_SOFTWARE; 2031 info->phc_index = -1; 2032 info->tx_types = 0; 2033 info->rx_filters = 0; 2034 return 0; 2035 } 2036 #endif /* CONFIG_TI_CPTS */ 2037 2038 static const struct ethtool_ops keystone_ethtool_ops = { 2039 .get_drvinfo = keystone_get_drvinfo, 2040 .get_link = ethtool_op_get_link, 2041 .get_msglevel = keystone_get_msglevel, 2042 .set_msglevel = keystone_set_msglevel, 2043 .get_strings = keystone_get_stat_strings, 2044 .get_sset_count = keystone_get_sset_count, 2045 .get_ethtool_stats = keystone_get_ethtool_stats, 2046 .get_link_ksettings = keystone_get_link_ksettings, 2047 .set_link_ksettings = keystone_set_link_ksettings, 2048 .get_ts_info = keystone_get_ts_info, 2049 }; 2050 2051 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 2052 ((mac)[2] << 16) | ((mac)[3] << 24)) 2053 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 2054 2055 static void gbe_set_slave_mac(struct gbe_slave *slave, 2056 struct gbe_intf *gbe_intf) 2057 { 2058 struct net_device *ndev = gbe_intf->ndev; 2059 2060 writel(mac_hi(ndev->dev_addr), GBE_REG_ADDR(slave, port_regs, sa_hi)); 2061 writel(mac_lo(ndev->dev_addr), GBE_REG_ADDR(slave, port_regs, sa_lo)); 2062 } 2063 2064 static int gbe_get_slave_port(struct gbe_priv *priv, u32 slave_num) 2065 { 2066 if (priv->host_port == 0) 2067 return slave_num + 1; 2068 2069 return slave_num; 2070 } 2071 2072 static void netcp_ethss_link_state_action(struct gbe_priv *gbe_dev, 2073 struct net_device *ndev, 2074 struct gbe_slave *slave, 2075 int up) 2076 { 2077 struct phy_device *phy = slave->phy; 2078 u32 mac_control = 0; 2079 2080 if (up) { 2081 mac_control = slave->mac_control; 2082 if (phy && (phy->speed == SPEED_1000)) { 2083 mac_control |= MACSL_GIG_MODE; 2084 mac_control &= ~MACSL_XGIG_MODE; 2085 } else if (phy && (phy->speed == SPEED_10000)) { 2086 mac_control |= MACSL_XGIG_MODE; 2087 mac_control &= ~MACSL_GIG_MODE; 2088 } 2089 2090 writel(mac_control, GBE_REG_ADDR(slave, emac_regs, 2091 mac_control)); 2092 2093 cpsw_ale_control_set(gbe_dev->ale, slave->port_num, 2094 ALE_PORT_STATE, 2095 ALE_PORT_STATE_FORWARD); 2096 2097 if (ndev && slave->open && 2098 slave->link_interface != SGMII_LINK_MAC_PHY && 2099 slave->link_interface != XGMII_LINK_MAC_PHY) 2100 netif_carrier_on(ndev); 2101 } else { 2102 writel(mac_control, GBE_REG_ADDR(slave, emac_regs, 2103 mac_control)); 2104 cpsw_ale_control_set(gbe_dev->ale, slave->port_num, 2105 ALE_PORT_STATE, 2106 ALE_PORT_STATE_DISABLE); 2107 if (ndev && 2108 slave->link_interface != SGMII_LINK_MAC_PHY && 2109 slave->link_interface != XGMII_LINK_MAC_PHY) 2110 netif_carrier_off(ndev); 2111 } 2112 2113 if (phy) 2114 phy_print_status(phy); 2115 } 2116 2117 static bool gbe_phy_link_status(struct gbe_slave *slave) 2118 { 2119 return !slave->phy || slave->phy->link; 2120 } 2121 2122 static void netcp_ethss_update_link_state(struct gbe_priv *gbe_dev, 2123 struct gbe_slave *slave, 2124 struct net_device *ndev) 2125 { 2126 int sp = slave->slave_num; 2127 int phy_link_state, sgmii_link_state = 1, link_state; 2128 2129 if (!slave->open) 2130 return; 2131 2132 if (!SLAVE_LINK_IS_XGMII(slave)) { 2133 sgmii_link_state = 2134 netcp_sgmii_get_port_link(SGMII_BASE(gbe_dev, sp), sp); 2135 } 2136 2137 phy_link_state = gbe_phy_link_status(slave); 2138 link_state = phy_link_state & sgmii_link_state; 2139 2140 if (atomic_xchg(&slave->link_state, link_state) != link_state) 2141 netcp_ethss_link_state_action(gbe_dev, ndev, slave, 2142 link_state); 2143 } 2144 2145 static void xgbe_adjust_link(struct net_device *ndev) 2146 { 2147 struct netcp_intf *netcp = netdev_priv(ndev); 2148 struct gbe_intf *gbe_intf; 2149 2150 gbe_intf = netcp_module_get_intf_data(&xgbe_module, netcp); 2151 if (!gbe_intf) 2152 return; 2153 2154 netcp_ethss_update_link_state(gbe_intf->gbe_dev, gbe_intf->slave, 2155 ndev); 2156 } 2157 2158 static void gbe_adjust_link(struct net_device *ndev) 2159 { 2160 struct netcp_intf *netcp = netdev_priv(ndev); 2161 struct gbe_intf *gbe_intf; 2162 2163 gbe_intf = netcp_module_get_intf_data(&gbe_module, netcp); 2164 if (!gbe_intf) 2165 return; 2166 2167 netcp_ethss_update_link_state(gbe_intf->gbe_dev, gbe_intf->slave, 2168 ndev); 2169 } 2170 2171 static void gbe_adjust_link_sec_slaves(struct net_device *ndev) 2172 { 2173 struct gbe_priv *gbe_dev = netdev_priv(ndev); 2174 struct gbe_slave *slave; 2175 2176 for_each_sec_slave(slave, gbe_dev) 2177 netcp_ethss_update_link_state(gbe_dev, slave, NULL); 2178 } 2179 2180 /* Reset EMAC 2181 * Soft reset is set and polled until clear, or until a timeout occurs 2182 */ 2183 static int gbe_port_reset(struct gbe_slave *slave) 2184 { 2185 u32 i, v; 2186 2187 /* Set the soft reset bit */ 2188 writel(SOFT_RESET, GBE_REG_ADDR(slave, emac_regs, soft_reset)); 2189 2190 /* Wait for the bit to clear */ 2191 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { 2192 v = readl(GBE_REG_ADDR(slave, emac_regs, soft_reset)); 2193 if ((v & SOFT_RESET_MASK) != SOFT_RESET) 2194 return 0; 2195 } 2196 2197 /* Timeout on the reset */ 2198 return GMACSL_RET_WARN_RESET_INCOMPLETE; 2199 } 2200 2201 /* Configure EMAC */ 2202 static void gbe_port_config(struct gbe_priv *gbe_dev, struct gbe_slave *slave, 2203 int max_rx_len) 2204 { 2205 void __iomem *rx_maxlen_reg; 2206 u32 xgmii_mode; 2207 2208 if (max_rx_len > NETCP_MAX_FRAME_SIZE) 2209 max_rx_len = NETCP_MAX_FRAME_SIZE; 2210 2211 /* Enable correct MII mode at SS level */ 2212 if ((gbe_dev->ss_version == XGBE_SS_VERSION_10) && 2213 (slave->link_interface >= XGMII_LINK_MAC_PHY)) { 2214 xgmii_mode = readl(GBE_REG_ADDR(gbe_dev, ss_regs, control)); 2215 xgmii_mode |= (1 << slave->slave_num); 2216 writel(xgmii_mode, GBE_REG_ADDR(gbe_dev, ss_regs, control)); 2217 } 2218 2219 if (IS_SS_ID_MU(gbe_dev)) 2220 rx_maxlen_reg = GBE_REG_ADDR(slave, port_regs, rx_maxlen); 2221 else 2222 rx_maxlen_reg = GBE_REG_ADDR(slave, emac_regs, rx_maxlen); 2223 2224 writel(max_rx_len, rx_maxlen_reg); 2225 writel(slave->mac_control, GBE_REG_ADDR(slave, emac_regs, mac_control)); 2226 } 2227 2228 static void gbe_sgmii_rtreset(struct gbe_priv *priv, 2229 struct gbe_slave *slave, bool set) 2230 { 2231 if (SLAVE_LINK_IS_XGMII(slave)) 2232 return; 2233 2234 netcp_sgmii_rtreset(SGMII_BASE(priv, slave->slave_num), 2235 slave->slave_num, set); 2236 } 2237 2238 static void gbe_slave_stop(struct gbe_intf *intf) 2239 { 2240 struct gbe_priv *gbe_dev = intf->gbe_dev; 2241 struct gbe_slave *slave = intf->slave; 2242 2243 gbe_sgmii_rtreset(gbe_dev, slave, true); 2244 gbe_port_reset(slave); 2245 /* Disable forwarding */ 2246 cpsw_ale_control_set(gbe_dev->ale, slave->port_num, 2247 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 2248 cpsw_ale_del_mcast(gbe_dev->ale, intf->ndev->broadcast, 2249 1 << slave->port_num, 0, 0); 2250 2251 if (!slave->phy) 2252 return; 2253 2254 phy_stop(slave->phy); 2255 phy_disconnect(slave->phy); 2256 slave->phy = NULL; 2257 } 2258 2259 static void gbe_sgmii_config(struct gbe_priv *priv, struct gbe_slave *slave) 2260 { 2261 if (SLAVE_LINK_IS_XGMII(slave)) 2262 return; 2263 2264 netcp_sgmii_reset(SGMII_BASE(priv, slave->slave_num), slave->slave_num); 2265 netcp_sgmii_config(SGMII_BASE(priv, slave->slave_num), slave->slave_num, 2266 slave->link_interface); 2267 } 2268 2269 static int gbe_slave_open(struct gbe_intf *gbe_intf) 2270 { 2271 struct gbe_priv *priv = gbe_intf->gbe_dev; 2272 struct gbe_slave *slave = gbe_intf->slave; 2273 phy_interface_t phy_mode; 2274 bool has_phy = false; 2275 2276 void (*hndlr)(struct net_device *) = gbe_adjust_link; 2277 2278 gbe_sgmii_config(priv, slave); 2279 gbe_port_reset(slave); 2280 gbe_sgmii_rtreset(priv, slave, false); 2281 gbe_port_config(priv, slave, priv->rx_packet_max); 2282 gbe_set_slave_mac(slave, gbe_intf); 2283 /* enable forwarding */ 2284 cpsw_ale_control_set(priv->ale, slave->port_num, 2285 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 2286 cpsw_ale_add_mcast(priv->ale, gbe_intf->ndev->broadcast, 2287 1 << slave->port_num, 0, 0, ALE_MCAST_FWD_2); 2288 2289 if (slave->link_interface == SGMII_LINK_MAC_PHY) { 2290 has_phy = true; 2291 phy_mode = PHY_INTERFACE_MODE_SGMII; 2292 slave->phy_port_t = PORT_MII; 2293 } else if (slave->link_interface == XGMII_LINK_MAC_PHY) { 2294 has_phy = true; 2295 phy_mode = PHY_INTERFACE_MODE_NA; 2296 slave->phy_port_t = PORT_FIBRE; 2297 } 2298 2299 if (has_phy) { 2300 if (priv->ss_version == XGBE_SS_VERSION_10) 2301 hndlr = xgbe_adjust_link; 2302 2303 slave->phy = of_phy_connect(gbe_intf->ndev, 2304 slave->phy_node, 2305 hndlr, 0, 2306 phy_mode); 2307 if (!slave->phy) { 2308 dev_err(priv->dev, "phy not found on slave %d\n", 2309 slave->slave_num); 2310 return -ENODEV; 2311 } 2312 dev_dbg(priv->dev, "phy found: id is: 0x%s\n", 2313 phydev_name(slave->phy)); 2314 phy_start(slave->phy); 2315 phy_read_status(slave->phy); 2316 } 2317 return 0; 2318 } 2319 2320 static void gbe_init_host_port(struct gbe_priv *priv) 2321 { 2322 int bypass_en = 1; 2323 2324 /* Host Tx Pri */ 2325 if (IS_SS_ID_NU(priv)) 2326 writel(HOST_TX_PRI_MAP_DEFAULT, 2327 GBE_REG_ADDR(priv, host_port_regs, tx_pri_map)); 2328 2329 /* Max length register */ 2330 writel(NETCP_MAX_FRAME_SIZE, GBE_REG_ADDR(priv, host_port_regs, 2331 rx_maxlen)); 2332 2333 cpsw_ale_start(priv->ale); 2334 2335 if (priv->enable_ale) 2336 bypass_en = 0; 2337 2338 cpsw_ale_control_set(priv->ale, 0, ALE_BYPASS, bypass_en); 2339 2340 cpsw_ale_control_set(priv->ale, 0, ALE_NO_PORT_VLAN, 1); 2341 2342 cpsw_ale_control_set(priv->ale, priv->host_port, 2343 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 2344 2345 cpsw_ale_control_set(priv->ale, 0, 2346 ALE_PORT_UNKNOWN_VLAN_MEMBER, 2347 GBE_PORT_MASK(priv->ale_ports)); 2348 2349 cpsw_ale_control_set(priv->ale, 0, 2350 ALE_PORT_UNKNOWN_MCAST_FLOOD, 2351 GBE_PORT_MASK(priv->ale_ports - 1)); 2352 2353 cpsw_ale_control_set(priv->ale, 0, 2354 ALE_PORT_UNKNOWN_REG_MCAST_FLOOD, 2355 GBE_PORT_MASK(priv->ale_ports)); 2356 2357 cpsw_ale_control_set(priv->ale, 0, 2358 ALE_PORT_UNTAGGED_EGRESS, 2359 GBE_PORT_MASK(priv->ale_ports)); 2360 } 2361 2362 static void gbe_add_mcast_addr(struct gbe_intf *gbe_intf, u8 *addr) 2363 { 2364 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2365 u16 vlan_id; 2366 2367 cpsw_ale_add_mcast(gbe_dev->ale, addr, 2368 GBE_PORT_MASK(gbe_dev->ale_ports), 0, 0, 2369 ALE_MCAST_FWD_2); 2370 for_each_set_bit(vlan_id, gbe_intf->active_vlans, VLAN_N_VID) { 2371 cpsw_ale_add_mcast(gbe_dev->ale, addr, 2372 GBE_PORT_MASK(gbe_dev->ale_ports), 2373 ALE_VLAN, vlan_id, ALE_MCAST_FWD_2); 2374 } 2375 } 2376 2377 static void gbe_add_ucast_addr(struct gbe_intf *gbe_intf, u8 *addr) 2378 { 2379 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2380 u16 vlan_id; 2381 2382 cpsw_ale_add_ucast(gbe_dev->ale, addr, gbe_dev->host_port, 0, 0); 2383 2384 for_each_set_bit(vlan_id, gbe_intf->active_vlans, VLAN_N_VID) 2385 cpsw_ale_add_ucast(gbe_dev->ale, addr, gbe_dev->host_port, 2386 ALE_VLAN, vlan_id); 2387 } 2388 2389 static void gbe_del_mcast_addr(struct gbe_intf *gbe_intf, u8 *addr) 2390 { 2391 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2392 u16 vlan_id; 2393 2394 cpsw_ale_del_mcast(gbe_dev->ale, addr, 0, 0, 0); 2395 2396 for_each_set_bit(vlan_id, gbe_intf->active_vlans, VLAN_N_VID) { 2397 cpsw_ale_del_mcast(gbe_dev->ale, addr, 0, ALE_VLAN, vlan_id); 2398 } 2399 } 2400 2401 static void gbe_del_ucast_addr(struct gbe_intf *gbe_intf, u8 *addr) 2402 { 2403 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2404 u16 vlan_id; 2405 2406 cpsw_ale_del_ucast(gbe_dev->ale, addr, gbe_dev->host_port, 0, 0); 2407 2408 for_each_set_bit(vlan_id, gbe_intf->active_vlans, VLAN_N_VID) { 2409 cpsw_ale_del_ucast(gbe_dev->ale, addr, gbe_dev->host_port, 2410 ALE_VLAN, vlan_id); 2411 } 2412 } 2413 2414 static int gbe_add_addr(void *intf_priv, struct netcp_addr *naddr) 2415 { 2416 struct gbe_intf *gbe_intf = intf_priv; 2417 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2418 2419 dev_dbg(gbe_dev->dev, "ethss adding address %pM, type %d\n", 2420 naddr->addr, naddr->type); 2421 2422 switch (naddr->type) { 2423 case ADDR_MCAST: 2424 case ADDR_BCAST: 2425 gbe_add_mcast_addr(gbe_intf, naddr->addr); 2426 break; 2427 case ADDR_UCAST: 2428 case ADDR_DEV: 2429 gbe_add_ucast_addr(gbe_intf, naddr->addr); 2430 break; 2431 case ADDR_ANY: 2432 /* nothing to do for promiscuous */ 2433 default: 2434 break; 2435 } 2436 2437 return 0; 2438 } 2439 2440 static int gbe_del_addr(void *intf_priv, struct netcp_addr *naddr) 2441 { 2442 struct gbe_intf *gbe_intf = intf_priv; 2443 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2444 2445 dev_dbg(gbe_dev->dev, "ethss deleting address %pM, type %d\n", 2446 naddr->addr, naddr->type); 2447 2448 switch (naddr->type) { 2449 case ADDR_MCAST: 2450 case ADDR_BCAST: 2451 gbe_del_mcast_addr(gbe_intf, naddr->addr); 2452 break; 2453 case ADDR_UCAST: 2454 case ADDR_DEV: 2455 gbe_del_ucast_addr(gbe_intf, naddr->addr); 2456 break; 2457 case ADDR_ANY: 2458 /* nothing to do for promiscuous */ 2459 default: 2460 break; 2461 } 2462 2463 return 0; 2464 } 2465 2466 static int gbe_add_vid(void *intf_priv, int vid) 2467 { 2468 struct gbe_intf *gbe_intf = intf_priv; 2469 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2470 2471 set_bit(vid, gbe_intf->active_vlans); 2472 2473 cpsw_ale_add_vlan(gbe_dev->ale, vid, 2474 GBE_PORT_MASK(gbe_dev->ale_ports), 2475 GBE_MASK_NO_PORTS, 2476 GBE_PORT_MASK(gbe_dev->ale_ports), 2477 GBE_PORT_MASK(gbe_dev->ale_ports - 1)); 2478 2479 return 0; 2480 } 2481 2482 static int gbe_del_vid(void *intf_priv, int vid) 2483 { 2484 struct gbe_intf *gbe_intf = intf_priv; 2485 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2486 2487 cpsw_ale_del_vlan(gbe_dev->ale, vid, 0); 2488 clear_bit(vid, gbe_intf->active_vlans); 2489 return 0; 2490 } 2491 2492 #if IS_ENABLED(CONFIG_TI_CPTS) 2493 #define HAS_PHY_TXTSTAMP(p) ((p)->drv && (p)->drv->txtstamp) 2494 #define HAS_PHY_RXTSTAMP(p) ((p)->drv && (p)->drv->rxtstamp) 2495 2496 static void gbe_txtstamp(void *context, struct sk_buff *skb) 2497 { 2498 struct gbe_intf *gbe_intf = context; 2499 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2500 2501 cpts_tx_timestamp(gbe_dev->cpts, skb); 2502 } 2503 2504 static bool gbe_need_txtstamp(struct gbe_intf *gbe_intf, 2505 const struct netcp_packet *p_info) 2506 { 2507 struct sk_buff *skb = p_info->skb; 2508 unsigned int class = ptp_classify_raw(skb); 2509 2510 if (class == PTP_CLASS_NONE) 2511 return false; 2512 2513 switch (class) { 2514 case PTP_CLASS_V1_IPV4: 2515 case PTP_CLASS_V1_IPV6: 2516 case PTP_CLASS_V2_IPV4: 2517 case PTP_CLASS_V2_IPV6: 2518 case PTP_CLASS_V2_L2: 2519 case (PTP_CLASS_V2_VLAN | PTP_CLASS_L2): 2520 case (PTP_CLASS_V2_VLAN | PTP_CLASS_IPV4): 2521 case (PTP_CLASS_V2_VLAN | PTP_CLASS_IPV6): 2522 return true; 2523 } 2524 2525 return false; 2526 } 2527 2528 static int gbe_txtstamp_mark_pkt(struct gbe_intf *gbe_intf, 2529 struct netcp_packet *p_info) 2530 { 2531 struct phy_device *phydev = p_info->skb->dev->phydev; 2532 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2533 2534 if (!(skb_shinfo(p_info->skb)->tx_flags & SKBTX_HW_TSTAMP) || 2535 !cpts_is_tx_enabled(gbe_dev->cpts)) 2536 return 0; 2537 2538 /* If phy has the txtstamp api, assume it will do it. 2539 * We mark it here because skb_tx_timestamp() is called 2540 * after all the txhooks are called. 2541 */ 2542 if (phydev && HAS_PHY_TXTSTAMP(phydev)) { 2543 skb_shinfo(p_info->skb)->tx_flags |= SKBTX_IN_PROGRESS; 2544 return 0; 2545 } 2546 2547 if (gbe_need_txtstamp(gbe_intf, p_info)) { 2548 p_info->txtstamp = gbe_txtstamp; 2549 p_info->ts_context = (void *)gbe_intf; 2550 skb_shinfo(p_info->skb)->tx_flags |= SKBTX_IN_PROGRESS; 2551 } 2552 2553 return 0; 2554 } 2555 2556 static int gbe_rxtstamp(struct gbe_intf *gbe_intf, struct netcp_packet *p_info) 2557 { 2558 struct phy_device *phydev = p_info->skb->dev->phydev; 2559 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2560 2561 if (p_info->rxtstamp_complete) 2562 return 0; 2563 2564 if (phydev && HAS_PHY_RXTSTAMP(phydev)) { 2565 p_info->rxtstamp_complete = true; 2566 return 0; 2567 } 2568 2569 cpts_rx_timestamp(gbe_dev->cpts, p_info->skb); 2570 p_info->rxtstamp_complete = true; 2571 2572 return 0; 2573 } 2574 2575 static int gbe_hwtstamp_get(struct gbe_intf *gbe_intf, struct ifreq *ifr) 2576 { 2577 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2578 struct cpts *cpts = gbe_dev->cpts; 2579 struct hwtstamp_config cfg; 2580 2581 if (!cpts) 2582 return -EOPNOTSUPP; 2583 2584 cfg.flags = 0; 2585 cfg.tx_type = cpts_is_tx_enabled(cpts) ? 2586 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 2587 cfg.rx_filter = (cpts_is_rx_enabled(cpts) ? 2588 cpts->rx_enable : HWTSTAMP_FILTER_NONE); 2589 2590 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 2591 } 2592 2593 static void gbe_hwtstamp(struct gbe_intf *gbe_intf) 2594 { 2595 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2596 struct gbe_slave *slave = gbe_intf->slave; 2597 u32 ts_en, seq_id, ctl; 2598 2599 if (!cpts_is_rx_enabled(gbe_dev->cpts) && 2600 !cpts_is_tx_enabled(gbe_dev->cpts)) { 2601 writel(0, GBE_REG_ADDR(slave, port_regs, ts_ctl)); 2602 return; 2603 } 2604 2605 seq_id = (30 << TS_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 2606 ts_en = EVENT_MSG_BITS << TS_MSG_TYPE_EN_SHIFT; 2607 ctl = ETH_P_1588 | TS_TTL_NONZERO | 2608 (slave->ts_ctl.dst_port_map << TS_CTL_DST_PORT_SHIFT) | 2609 (slave->ts_ctl.uni ? TS_UNI_EN : 2610 slave->ts_ctl.maddr_map << TS_CTL_MADDR_SHIFT); 2611 2612 if (cpts_is_tx_enabled(gbe_dev->cpts)) 2613 ts_en |= (TS_TX_ANX_ALL_EN | TS_TX_VLAN_LT1_EN); 2614 2615 if (cpts_is_rx_enabled(gbe_dev->cpts)) 2616 ts_en |= (TS_RX_ANX_ALL_EN | TS_RX_VLAN_LT1_EN); 2617 2618 writel(ts_en, GBE_REG_ADDR(slave, port_regs, ts_ctl)); 2619 writel(seq_id, GBE_REG_ADDR(slave, port_regs, ts_seq_ltype)); 2620 writel(ctl, GBE_REG_ADDR(slave, port_regs, ts_ctl_ltype2)); 2621 } 2622 2623 static int gbe_hwtstamp_set(struct gbe_intf *gbe_intf, struct ifreq *ifr) 2624 { 2625 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2626 struct cpts *cpts = gbe_dev->cpts; 2627 struct hwtstamp_config cfg; 2628 2629 if (!cpts) 2630 return -EOPNOTSUPP; 2631 2632 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 2633 return -EFAULT; 2634 2635 /* reserved for future extensions */ 2636 if (cfg.flags) 2637 return -EINVAL; 2638 2639 switch (cfg.tx_type) { 2640 case HWTSTAMP_TX_OFF: 2641 cpts_tx_enable(cpts, 0); 2642 break; 2643 case HWTSTAMP_TX_ON: 2644 cpts_tx_enable(cpts, 1); 2645 break; 2646 default: 2647 return -ERANGE; 2648 } 2649 2650 switch (cfg.rx_filter) { 2651 case HWTSTAMP_FILTER_NONE: 2652 cpts_rx_enable(cpts, 0); 2653 break; 2654 case HWTSTAMP_FILTER_ALL: 2655 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2656 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2657 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2658 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V1_L4_EVENT); 2659 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 2660 break; 2661 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2662 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2663 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2664 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2665 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 2666 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 2667 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2668 case HWTSTAMP_FILTER_PTP_V2_SYNC: 2669 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2670 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V2_EVENT); 2671 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 2672 break; 2673 default: 2674 return -ERANGE; 2675 } 2676 2677 gbe_hwtstamp(gbe_intf); 2678 2679 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 2680 } 2681 2682 static void gbe_register_cpts(struct gbe_priv *gbe_dev) 2683 { 2684 if (!gbe_dev->cpts) 2685 return; 2686 2687 if (gbe_dev->cpts_registered > 0) 2688 goto done; 2689 2690 if (cpts_register(gbe_dev->cpts)) { 2691 dev_err(gbe_dev->dev, "error registering cpts device\n"); 2692 return; 2693 } 2694 2695 done: 2696 ++gbe_dev->cpts_registered; 2697 } 2698 2699 static void gbe_unregister_cpts(struct gbe_priv *gbe_dev) 2700 { 2701 if (!gbe_dev->cpts || (gbe_dev->cpts_registered <= 0)) 2702 return; 2703 2704 if (--gbe_dev->cpts_registered) 2705 return; 2706 2707 cpts_unregister(gbe_dev->cpts); 2708 } 2709 #else 2710 static inline int gbe_txtstamp_mark_pkt(struct gbe_intf *gbe_intf, 2711 struct netcp_packet *p_info) 2712 { 2713 return 0; 2714 } 2715 2716 static inline int gbe_rxtstamp(struct gbe_intf *gbe_intf, 2717 struct netcp_packet *p_info) 2718 { 2719 return 0; 2720 } 2721 2722 static inline int gbe_hwtstamp(struct gbe_intf *gbe_intf, 2723 struct ifreq *ifr, int cmd) 2724 { 2725 return -EOPNOTSUPP; 2726 } 2727 2728 static inline void gbe_register_cpts(struct gbe_priv *gbe_dev) 2729 { 2730 } 2731 2732 static inline void gbe_unregister_cpts(struct gbe_priv *gbe_dev) 2733 { 2734 } 2735 2736 static inline int gbe_hwtstamp_get(struct gbe_intf *gbe_intf, struct ifreq *req) 2737 { 2738 return -EOPNOTSUPP; 2739 } 2740 2741 static inline int gbe_hwtstamp_set(struct gbe_intf *gbe_intf, struct ifreq *req) 2742 { 2743 return -EOPNOTSUPP; 2744 } 2745 #endif /* CONFIG_TI_CPTS */ 2746 2747 static int gbe_ioctl(void *intf_priv, struct ifreq *req, int cmd) 2748 { 2749 struct gbe_intf *gbe_intf = intf_priv; 2750 struct phy_device *phy = gbe_intf->slave->phy; 2751 2752 if (!phy || !phy->drv->hwtstamp) { 2753 switch (cmd) { 2754 case SIOCGHWTSTAMP: 2755 return gbe_hwtstamp_get(gbe_intf, req); 2756 case SIOCSHWTSTAMP: 2757 return gbe_hwtstamp_set(gbe_intf, req); 2758 } 2759 } 2760 2761 if (phy) 2762 return phy_mii_ioctl(phy, req, cmd); 2763 2764 return -EOPNOTSUPP; 2765 } 2766 2767 static void netcp_ethss_timer(unsigned long arg) 2768 { 2769 struct gbe_priv *gbe_dev = (struct gbe_priv *)arg; 2770 struct gbe_intf *gbe_intf; 2771 struct gbe_slave *slave; 2772 2773 /* Check & update SGMII link state of interfaces */ 2774 for_each_intf(gbe_intf, gbe_dev) { 2775 if (!gbe_intf->slave->open) 2776 continue; 2777 netcp_ethss_update_link_state(gbe_dev, gbe_intf->slave, 2778 gbe_intf->ndev); 2779 } 2780 2781 /* Check & update SGMII link state of secondary ports */ 2782 for_each_sec_slave(slave, gbe_dev) { 2783 netcp_ethss_update_link_state(gbe_dev, slave, NULL); 2784 } 2785 2786 /* A timer runs as a BH, no need to block them */ 2787 spin_lock(&gbe_dev->hw_stats_lock); 2788 2789 if (gbe_dev->ss_version == GBE_SS_VERSION_14) 2790 gbe_update_stats_ver14(gbe_dev, NULL); 2791 else 2792 gbe_update_stats(gbe_dev, NULL); 2793 2794 spin_unlock(&gbe_dev->hw_stats_lock); 2795 2796 gbe_dev->timer.expires = jiffies + GBE_TIMER_INTERVAL; 2797 add_timer(&gbe_dev->timer); 2798 } 2799 2800 static int gbe_txhook(int order, void *data, struct netcp_packet *p_info) 2801 { 2802 struct gbe_intf *gbe_intf = data; 2803 2804 p_info->tx_pipe = &gbe_intf->tx_pipe; 2805 2806 return gbe_txtstamp_mark_pkt(gbe_intf, p_info); 2807 } 2808 2809 static int gbe_rxhook(int order, void *data, struct netcp_packet *p_info) 2810 { 2811 struct gbe_intf *gbe_intf = data; 2812 2813 return gbe_rxtstamp(gbe_intf, p_info); 2814 } 2815 2816 static int gbe_open(void *intf_priv, struct net_device *ndev) 2817 { 2818 struct gbe_intf *gbe_intf = intf_priv; 2819 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2820 struct netcp_intf *netcp = netdev_priv(ndev); 2821 struct gbe_slave *slave = gbe_intf->slave; 2822 int port_num = slave->port_num; 2823 u32 reg; 2824 int ret; 2825 2826 reg = readl(GBE_REG_ADDR(gbe_dev, switch_regs, id_ver)); 2827 dev_dbg(gbe_dev->dev, "initializing gbe version %d.%d (%d) GBE identification value 0x%x\n", 2828 GBE_MAJOR_VERSION(reg), GBE_MINOR_VERSION(reg), 2829 GBE_RTL_VERSION(reg), GBE_IDENT(reg)); 2830 2831 /* For 10G and on NetCP 1.5, use directed to port */ 2832 if ((gbe_dev->ss_version == XGBE_SS_VERSION_10) || IS_SS_ID_MU(gbe_dev)) 2833 gbe_intf->tx_pipe.flags = SWITCH_TO_PORT_IN_TAGINFO; 2834 2835 if (gbe_dev->enable_ale) 2836 gbe_intf->tx_pipe.switch_to_port = 0; 2837 else 2838 gbe_intf->tx_pipe.switch_to_port = port_num; 2839 2840 dev_dbg(gbe_dev->dev, 2841 "opened TX channel %s: %p with to port %d, flags %d\n", 2842 gbe_intf->tx_pipe.dma_chan_name, 2843 gbe_intf->tx_pipe.dma_channel, 2844 gbe_intf->tx_pipe.switch_to_port, 2845 gbe_intf->tx_pipe.flags); 2846 2847 gbe_slave_stop(gbe_intf); 2848 2849 /* disable priority elevation and enable statistics on all ports */ 2850 writel(0, GBE_REG_ADDR(gbe_dev, switch_regs, ptype)); 2851 2852 /* Control register */ 2853 writel(GBE_CTL_P0_ENABLE, GBE_REG_ADDR(gbe_dev, switch_regs, control)); 2854 2855 /* All statistics enabled and STAT AB visible by default */ 2856 writel(gbe_dev->stats_en_mask, GBE_REG_ADDR(gbe_dev, switch_regs, 2857 stat_port_en)); 2858 2859 ret = gbe_slave_open(gbe_intf); 2860 if (ret) 2861 goto fail; 2862 2863 netcp_register_txhook(netcp, GBE_TXHOOK_ORDER, gbe_txhook, gbe_intf); 2864 netcp_register_rxhook(netcp, GBE_RXHOOK_ORDER, gbe_rxhook, gbe_intf); 2865 2866 slave->open = true; 2867 netcp_ethss_update_link_state(gbe_dev, slave, ndev); 2868 2869 gbe_register_cpts(gbe_dev); 2870 2871 return 0; 2872 2873 fail: 2874 gbe_slave_stop(gbe_intf); 2875 return ret; 2876 } 2877 2878 static int gbe_close(void *intf_priv, struct net_device *ndev) 2879 { 2880 struct gbe_intf *gbe_intf = intf_priv; 2881 struct netcp_intf *netcp = netdev_priv(ndev); 2882 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2883 2884 gbe_unregister_cpts(gbe_dev); 2885 2886 gbe_slave_stop(gbe_intf); 2887 2888 netcp_unregister_rxhook(netcp, GBE_RXHOOK_ORDER, gbe_rxhook, gbe_intf); 2889 netcp_unregister_txhook(netcp, GBE_TXHOOK_ORDER, gbe_txhook, gbe_intf); 2890 2891 gbe_intf->slave->open = false; 2892 atomic_set(&gbe_intf->slave->link_state, NETCP_LINK_STATE_INVALID); 2893 return 0; 2894 } 2895 2896 #if IS_ENABLED(CONFIG_TI_CPTS) 2897 static void init_slave_ts_ctl(struct gbe_slave *slave) 2898 { 2899 slave->ts_ctl.uni = 1; 2900 slave->ts_ctl.dst_port_map = 2901 (TS_CTL_DST_PORT >> TS_CTL_DST_PORT_SHIFT) & 0x3; 2902 slave->ts_ctl.maddr_map = 2903 (TS_CTL_MADDR_ALL >> TS_CTL_MADDR_SHIFT) & 0x1f; 2904 } 2905 2906 #else 2907 static void init_slave_ts_ctl(struct gbe_slave *slave) 2908 { 2909 } 2910 #endif /* CONFIG_TI_CPTS */ 2911 2912 static int init_slave(struct gbe_priv *gbe_dev, struct gbe_slave *slave, 2913 struct device_node *node) 2914 { 2915 int port_reg_num; 2916 u32 port_reg_ofs, emac_reg_ofs; 2917 u32 port_reg_blk_sz, emac_reg_blk_sz; 2918 2919 if (of_property_read_u32(node, "slave-port", &slave->slave_num)) { 2920 dev_err(gbe_dev->dev, "missing slave-port parameter\n"); 2921 return -EINVAL; 2922 } 2923 2924 if (of_property_read_u32(node, "link-interface", 2925 &slave->link_interface)) { 2926 dev_warn(gbe_dev->dev, 2927 "missing link-interface value defaulting to 1G mac-phy link\n"); 2928 slave->link_interface = SGMII_LINK_MAC_PHY; 2929 } 2930 2931 slave->open = false; 2932 slave->phy_node = of_parse_phandle(node, "phy-handle", 0); 2933 slave->port_num = gbe_get_slave_port(gbe_dev, slave->slave_num); 2934 2935 if (slave->link_interface >= XGMII_LINK_MAC_PHY) 2936 slave->mac_control = GBE_DEF_10G_MAC_CONTROL; 2937 else 2938 slave->mac_control = GBE_DEF_1G_MAC_CONTROL; 2939 2940 /* Emac regs memmap are contiguous but port regs are not */ 2941 port_reg_num = slave->slave_num; 2942 if (gbe_dev->ss_version == GBE_SS_VERSION_14) { 2943 if (slave->slave_num > 1) { 2944 port_reg_ofs = GBE13_SLAVE_PORT2_OFFSET; 2945 port_reg_num -= 2; 2946 } else { 2947 port_reg_ofs = GBE13_SLAVE_PORT_OFFSET; 2948 } 2949 emac_reg_ofs = GBE13_EMAC_OFFSET; 2950 port_reg_blk_sz = 0x30; 2951 emac_reg_blk_sz = 0x40; 2952 } else if (IS_SS_ID_MU(gbe_dev)) { 2953 port_reg_ofs = GBENU_SLAVE_PORT_OFFSET; 2954 emac_reg_ofs = GBENU_EMAC_OFFSET; 2955 port_reg_blk_sz = 0x1000; 2956 emac_reg_blk_sz = 0x1000; 2957 } else if (gbe_dev->ss_version == XGBE_SS_VERSION_10) { 2958 port_reg_ofs = XGBE10_SLAVE_PORT_OFFSET; 2959 emac_reg_ofs = XGBE10_EMAC_OFFSET; 2960 port_reg_blk_sz = 0x30; 2961 emac_reg_blk_sz = 0x40; 2962 } else { 2963 dev_err(gbe_dev->dev, "unknown ethss(0x%x)\n", 2964 gbe_dev->ss_version); 2965 return -EINVAL; 2966 } 2967 2968 slave->port_regs = gbe_dev->switch_regs + port_reg_ofs + 2969 (port_reg_blk_sz * port_reg_num); 2970 slave->emac_regs = gbe_dev->switch_regs + emac_reg_ofs + 2971 (emac_reg_blk_sz * slave->slave_num); 2972 2973 if (gbe_dev->ss_version == GBE_SS_VERSION_14) { 2974 /* Initialize slave port register offsets */ 2975 GBE_SET_REG_OFS(slave, port_regs, port_vlan); 2976 GBE_SET_REG_OFS(slave, port_regs, tx_pri_map); 2977 GBE_SET_REG_OFS(slave, port_regs, sa_lo); 2978 GBE_SET_REG_OFS(slave, port_regs, sa_hi); 2979 GBE_SET_REG_OFS(slave, port_regs, ts_ctl); 2980 GBE_SET_REG_OFS(slave, port_regs, ts_seq_ltype); 2981 GBE_SET_REG_OFS(slave, port_regs, ts_vlan); 2982 GBE_SET_REG_OFS(slave, port_regs, ts_ctl_ltype2); 2983 GBE_SET_REG_OFS(slave, port_regs, ts_ctl2); 2984 2985 /* Initialize EMAC register offsets */ 2986 GBE_SET_REG_OFS(slave, emac_regs, mac_control); 2987 GBE_SET_REG_OFS(slave, emac_regs, soft_reset); 2988 GBE_SET_REG_OFS(slave, emac_regs, rx_maxlen); 2989 2990 } else if (IS_SS_ID_MU(gbe_dev)) { 2991 /* Initialize slave port register offsets */ 2992 GBENU_SET_REG_OFS(slave, port_regs, port_vlan); 2993 GBENU_SET_REG_OFS(slave, port_regs, tx_pri_map); 2994 GBENU_SET_REG_OFS(slave, port_regs, sa_lo); 2995 GBENU_SET_REG_OFS(slave, port_regs, sa_hi); 2996 GBENU_SET_REG_OFS(slave, port_regs, ts_ctl); 2997 GBENU_SET_REG_OFS(slave, port_regs, ts_seq_ltype); 2998 GBENU_SET_REG_OFS(slave, port_regs, ts_vlan); 2999 GBENU_SET_REG_OFS(slave, port_regs, ts_ctl_ltype2); 3000 GBENU_SET_REG_OFS(slave, port_regs, ts_ctl2); 3001 GBENU_SET_REG_OFS(slave, port_regs, rx_maxlen); 3002 3003 /* Initialize EMAC register offsets */ 3004 GBENU_SET_REG_OFS(slave, emac_regs, mac_control); 3005 GBENU_SET_REG_OFS(slave, emac_regs, soft_reset); 3006 3007 } else if (gbe_dev->ss_version == XGBE_SS_VERSION_10) { 3008 /* Initialize slave port register offsets */ 3009 XGBE_SET_REG_OFS(slave, port_regs, port_vlan); 3010 XGBE_SET_REG_OFS(slave, port_regs, tx_pri_map); 3011 XGBE_SET_REG_OFS(slave, port_regs, sa_lo); 3012 XGBE_SET_REG_OFS(slave, port_regs, sa_hi); 3013 XGBE_SET_REG_OFS(slave, port_regs, ts_ctl); 3014 XGBE_SET_REG_OFS(slave, port_regs, ts_seq_ltype); 3015 XGBE_SET_REG_OFS(slave, port_regs, ts_vlan); 3016 XGBE_SET_REG_OFS(slave, port_regs, ts_ctl_ltype2); 3017 XGBE_SET_REG_OFS(slave, port_regs, ts_ctl2); 3018 3019 /* Initialize EMAC register offsets */ 3020 XGBE_SET_REG_OFS(slave, emac_regs, mac_control); 3021 XGBE_SET_REG_OFS(slave, emac_regs, soft_reset); 3022 XGBE_SET_REG_OFS(slave, emac_regs, rx_maxlen); 3023 } 3024 3025 atomic_set(&slave->link_state, NETCP_LINK_STATE_INVALID); 3026 3027 init_slave_ts_ctl(slave); 3028 return 0; 3029 } 3030 3031 static void init_secondary_ports(struct gbe_priv *gbe_dev, 3032 struct device_node *node) 3033 { 3034 struct device *dev = gbe_dev->dev; 3035 phy_interface_t phy_mode; 3036 struct gbe_priv **priv; 3037 struct device_node *port; 3038 struct gbe_slave *slave; 3039 bool mac_phy_link = false; 3040 3041 for_each_child_of_node(node, port) { 3042 slave = devm_kzalloc(dev, sizeof(*slave), GFP_KERNEL); 3043 if (!slave) { 3044 dev_err(dev, 3045 "memomry alloc failed for secondary port(%s), skipping...\n", 3046 port->name); 3047 continue; 3048 } 3049 3050 if (init_slave(gbe_dev, slave, port)) { 3051 dev_err(dev, 3052 "Failed to initialize secondary port(%s), skipping...\n", 3053 port->name); 3054 devm_kfree(dev, slave); 3055 continue; 3056 } 3057 3058 gbe_sgmii_config(gbe_dev, slave); 3059 gbe_port_reset(slave); 3060 gbe_port_config(gbe_dev, slave, gbe_dev->rx_packet_max); 3061 list_add_tail(&slave->slave_list, &gbe_dev->secondary_slaves); 3062 gbe_dev->num_slaves++; 3063 if ((slave->link_interface == SGMII_LINK_MAC_PHY) || 3064 (slave->link_interface == XGMII_LINK_MAC_PHY)) 3065 mac_phy_link = true; 3066 3067 slave->open = true; 3068 if (gbe_dev->num_slaves >= gbe_dev->max_num_slaves) { 3069 of_node_put(port); 3070 break; 3071 } 3072 } 3073 3074 /* of_phy_connect() is needed only for MAC-PHY interface */ 3075 if (!mac_phy_link) 3076 return; 3077 3078 /* Allocate dummy netdev device for attaching to phy device */ 3079 gbe_dev->dummy_ndev = alloc_netdev(sizeof(gbe_dev), "dummy", 3080 NET_NAME_UNKNOWN, ether_setup); 3081 if (!gbe_dev->dummy_ndev) { 3082 dev_err(dev, 3083 "Failed to allocate dummy netdev for secondary ports, skipping phy_connect()...\n"); 3084 return; 3085 } 3086 priv = netdev_priv(gbe_dev->dummy_ndev); 3087 *priv = gbe_dev; 3088 3089 if (slave->link_interface == SGMII_LINK_MAC_PHY) { 3090 phy_mode = PHY_INTERFACE_MODE_SGMII; 3091 slave->phy_port_t = PORT_MII; 3092 } else { 3093 phy_mode = PHY_INTERFACE_MODE_NA; 3094 slave->phy_port_t = PORT_FIBRE; 3095 } 3096 3097 for_each_sec_slave(slave, gbe_dev) { 3098 if ((slave->link_interface != SGMII_LINK_MAC_PHY) && 3099 (slave->link_interface != XGMII_LINK_MAC_PHY)) 3100 continue; 3101 slave->phy = 3102 of_phy_connect(gbe_dev->dummy_ndev, 3103 slave->phy_node, 3104 gbe_adjust_link_sec_slaves, 3105 0, phy_mode); 3106 if (!slave->phy) { 3107 dev_err(dev, "phy not found for slave %d\n", 3108 slave->slave_num); 3109 slave->phy = NULL; 3110 } else { 3111 dev_dbg(dev, "phy found: id is: 0x%s\n", 3112 phydev_name(slave->phy)); 3113 phy_start(slave->phy); 3114 phy_read_status(slave->phy); 3115 } 3116 } 3117 } 3118 3119 static void free_secondary_ports(struct gbe_priv *gbe_dev) 3120 { 3121 struct gbe_slave *slave; 3122 3123 while (!list_empty(&gbe_dev->secondary_slaves)) { 3124 slave = first_sec_slave(gbe_dev); 3125 3126 if (slave->phy) 3127 phy_disconnect(slave->phy); 3128 list_del(&slave->slave_list); 3129 } 3130 if (gbe_dev->dummy_ndev) 3131 free_netdev(gbe_dev->dummy_ndev); 3132 } 3133 3134 static int set_xgbe_ethss10_priv(struct gbe_priv *gbe_dev, 3135 struct device_node *node) 3136 { 3137 struct resource res; 3138 void __iomem *regs; 3139 int ret, i; 3140 3141 ret = of_address_to_resource(node, XGBE_SS_REG_INDEX, &res); 3142 if (ret) { 3143 dev_err(gbe_dev->dev, 3144 "Can't xlate xgbe of node(%s) ss address at %d\n", 3145 node->name, XGBE_SS_REG_INDEX); 3146 return ret; 3147 } 3148 3149 regs = devm_ioremap_resource(gbe_dev->dev, &res); 3150 if (IS_ERR(regs)) { 3151 dev_err(gbe_dev->dev, "Failed to map xgbe ss register base\n"); 3152 return PTR_ERR(regs); 3153 } 3154 gbe_dev->ss_regs = regs; 3155 3156 ret = of_address_to_resource(node, XGBE_SM_REG_INDEX, &res); 3157 if (ret) { 3158 dev_err(gbe_dev->dev, 3159 "Can't xlate xgbe of node(%s) sm address at %d\n", 3160 node->name, XGBE_SM_REG_INDEX); 3161 return ret; 3162 } 3163 3164 regs = devm_ioremap_resource(gbe_dev->dev, &res); 3165 if (IS_ERR(regs)) { 3166 dev_err(gbe_dev->dev, "Failed to map xgbe sm register base\n"); 3167 return PTR_ERR(regs); 3168 } 3169 gbe_dev->switch_regs = regs; 3170 3171 ret = of_address_to_resource(node, XGBE_SERDES_REG_INDEX, &res); 3172 if (ret) { 3173 dev_err(gbe_dev->dev, 3174 "Can't xlate xgbe serdes of node(%s) address at %d\n", 3175 node->name, XGBE_SERDES_REG_INDEX); 3176 return ret; 3177 } 3178 3179 regs = devm_ioremap_resource(gbe_dev->dev, &res); 3180 if (IS_ERR(regs)) { 3181 dev_err(gbe_dev->dev, "Failed to map xgbe serdes register base\n"); 3182 return PTR_ERR(regs); 3183 } 3184 gbe_dev->xgbe_serdes_regs = regs; 3185 3186 gbe_dev->num_stats_mods = gbe_dev->max_num_ports; 3187 gbe_dev->et_stats = xgbe10_et_stats; 3188 gbe_dev->num_et_stats = ARRAY_SIZE(xgbe10_et_stats); 3189 3190 gbe_dev->hw_stats = devm_kzalloc(gbe_dev->dev, 3191 gbe_dev->num_et_stats * sizeof(u64), 3192 GFP_KERNEL); 3193 if (!gbe_dev->hw_stats) { 3194 dev_err(gbe_dev->dev, "hw_stats memory allocation failed\n"); 3195 return -ENOMEM; 3196 } 3197 3198 gbe_dev->hw_stats_prev = 3199 devm_kzalloc(gbe_dev->dev, 3200 gbe_dev->num_et_stats * sizeof(u32), 3201 GFP_KERNEL); 3202 if (!gbe_dev->hw_stats_prev) { 3203 dev_err(gbe_dev->dev, 3204 "hw_stats_prev memory allocation failed\n"); 3205 return -ENOMEM; 3206 } 3207 3208 gbe_dev->ss_version = XGBE_SS_VERSION_10; 3209 gbe_dev->sgmii_port_regs = gbe_dev->ss_regs + 3210 XGBE10_SGMII_MODULE_OFFSET; 3211 gbe_dev->host_port_regs = gbe_dev->ss_regs + XGBE10_HOST_PORT_OFFSET; 3212 3213 for (i = 0; i < gbe_dev->max_num_ports; i++) 3214 gbe_dev->hw_stats_regs[i] = gbe_dev->switch_regs + 3215 XGBE10_HW_STATS_OFFSET + (GBE_HW_STATS_REG_MAP_SZ * i); 3216 3217 gbe_dev->ale_reg = gbe_dev->switch_regs + XGBE10_ALE_OFFSET; 3218 gbe_dev->cpts_reg = gbe_dev->switch_regs + XGBE10_CPTS_OFFSET; 3219 gbe_dev->ale_ports = gbe_dev->max_num_ports; 3220 gbe_dev->host_port = XGBE10_HOST_PORT_NUM; 3221 gbe_dev->ale_entries = XGBE10_NUM_ALE_ENTRIES; 3222 gbe_dev->stats_en_mask = (1 << (gbe_dev->max_num_ports)) - 1; 3223 3224 /* Subsystem registers */ 3225 XGBE_SET_REG_OFS(gbe_dev, ss_regs, id_ver); 3226 XGBE_SET_REG_OFS(gbe_dev, ss_regs, control); 3227 3228 /* Switch module registers */ 3229 XGBE_SET_REG_OFS(gbe_dev, switch_regs, id_ver); 3230 XGBE_SET_REG_OFS(gbe_dev, switch_regs, control); 3231 XGBE_SET_REG_OFS(gbe_dev, switch_regs, ptype); 3232 XGBE_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en); 3233 XGBE_SET_REG_OFS(gbe_dev, switch_regs, flow_control); 3234 3235 /* Host port registers */ 3236 XGBE_SET_REG_OFS(gbe_dev, host_port_regs, port_vlan); 3237 XGBE_SET_REG_OFS(gbe_dev, host_port_regs, tx_pri_map); 3238 XGBE_SET_REG_OFS(gbe_dev, host_port_regs, rx_maxlen); 3239 return 0; 3240 } 3241 3242 static int get_gbe_resource_version(struct gbe_priv *gbe_dev, 3243 struct device_node *node) 3244 { 3245 struct resource res; 3246 void __iomem *regs; 3247 int ret; 3248 3249 ret = of_address_to_resource(node, GBE_SS_REG_INDEX, &res); 3250 if (ret) { 3251 dev_err(gbe_dev->dev, 3252 "Can't translate of node(%s) of gbe ss address at %d\n", 3253 node->name, GBE_SS_REG_INDEX); 3254 return ret; 3255 } 3256 3257 regs = devm_ioremap_resource(gbe_dev->dev, &res); 3258 if (IS_ERR(regs)) { 3259 dev_err(gbe_dev->dev, "Failed to map gbe register base\n"); 3260 return PTR_ERR(regs); 3261 } 3262 gbe_dev->ss_regs = regs; 3263 gbe_dev->ss_version = readl(gbe_dev->ss_regs); 3264 return 0; 3265 } 3266 3267 static int set_gbe_ethss14_priv(struct gbe_priv *gbe_dev, 3268 struct device_node *node) 3269 { 3270 struct resource res; 3271 void __iomem *regs; 3272 int i, ret; 3273 3274 ret = of_address_to_resource(node, GBE_SGMII34_REG_INDEX, &res); 3275 if (ret) { 3276 dev_err(gbe_dev->dev, 3277 "Can't translate of gbe node(%s) address at index %d\n", 3278 node->name, GBE_SGMII34_REG_INDEX); 3279 return ret; 3280 } 3281 3282 regs = devm_ioremap_resource(gbe_dev->dev, &res); 3283 if (IS_ERR(regs)) { 3284 dev_err(gbe_dev->dev, 3285 "Failed to map gbe sgmii port34 register base\n"); 3286 return PTR_ERR(regs); 3287 } 3288 gbe_dev->sgmii_port34_regs = regs; 3289 3290 ret = of_address_to_resource(node, GBE_SM_REG_INDEX, &res); 3291 if (ret) { 3292 dev_err(gbe_dev->dev, 3293 "Can't translate of gbe node(%s) address at index %d\n", 3294 node->name, GBE_SM_REG_INDEX); 3295 return ret; 3296 } 3297 3298 regs = devm_ioremap_resource(gbe_dev->dev, &res); 3299 if (IS_ERR(regs)) { 3300 dev_err(gbe_dev->dev, 3301 "Failed to map gbe switch module register base\n"); 3302 return PTR_ERR(regs); 3303 } 3304 gbe_dev->switch_regs = regs; 3305 3306 gbe_dev->num_stats_mods = gbe_dev->max_num_slaves; 3307 gbe_dev->et_stats = gbe13_et_stats; 3308 gbe_dev->num_et_stats = ARRAY_SIZE(gbe13_et_stats); 3309 3310 gbe_dev->hw_stats = devm_kzalloc(gbe_dev->dev, 3311 gbe_dev->num_et_stats * sizeof(u64), 3312 GFP_KERNEL); 3313 if (!gbe_dev->hw_stats) { 3314 dev_err(gbe_dev->dev, "hw_stats memory allocation failed\n"); 3315 return -ENOMEM; 3316 } 3317 3318 gbe_dev->hw_stats_prev = 3319 devm_kzalloc(gbe_dev->dev, 3320 gbe_dev->num_et_stats * sizeof(u32), 3321 GFP_KERNEL); 3322 if (!gbe_dev->hw_stats_prev) { 3323 dev_err(gbe_dev->dev, 3324 "hw_stats_prev memory allocation failed\n"); 3325 return -ENOMEM; 3326 } 3327 3328 gbe_dev->sgmii_port_regs = gbe_dev->ss_regs + GBE13_SGMII_MODULE_OFFSET; 3329 gbe_dev->host_port_regs = gbe_dev->switch_regs + GBE13_HOST_PORT_OFFSET; 3330 3331 /* K2HK has only 2 hw stats modules visible at a time, so 3332 * module 0 & 2 points to one base and 3333 * module 1 & 3 points to the other base 3334 */ 3335 for (i = 0; i < gbe_dev->max_num_slaves; i++) { 3336 gbe_dev->hw_stats_regs[i] = 3337 gbe_dev->switch_regs + GBE13_HW_STATS_OFFSET + 3338 (GBE_HW_STATS_REG_MAP_SZ * (i & 0x1)); 3339 } 3340 3341 gbe_dev->cpts_reg = gbe_dev->switch_regs + GBE13_CPTS_OFFSET; 3342 gbe_dev->ale_reg = gbe_dev->switch_regs + GBE13_ALE_OFFSET; 3343 gbe_dev->ale_ports = gbe_dev->max_num_ports; 3344 gbe_dev->host_port = GBE13_HOST_PORT_NUM; 3345 gbe_dev->ale_entries = GBE13_NUM_ALE_ENTRIES; 3346 gbe_dev->stats_en_mask = GBE13_REG_VAL_STAT_ENABLE_ALL; 3347 3348 /* Subsystem registers */ 3349 GBE_SET_REG_OFS(gbe_dev, ss_regs, id_ver); 3350 3351 /* Switch module registers */ 3352 GBE_SET_REG_OFS(gbe_dev, switch_regs, id_ver); 3353 GBE_SET_REG_OFS(gbe_dev, switch_regs, control); 3354 GBE_SET_REG_OFS(gbe_dev, switch_regs, soft_reset); 3355 GBE_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en); 3356 GBE_SET_REG_OFS(gbe_dev, switch_regs, ptype); 3357 GBE_SET_REG_OFS(gbe_dev, switch_regs, flow_control); 3358 3359 /* Host port registers */ 3360 GBE_SET_REG_OFS(gbe_dev, host_port_regs, port_vlan); 3361 GBE_SET_REG_OFS(gbe_dev, host_port_regs, rx_maxlen); 3362 return 0; 3363 } 3364 3365 static int set_gbenu_ethss_priv(struct gbe_priv *gbe_dev, 3366 struct device_node *node) 3367 { 3368 struct resource res; 3369 void __iomem *regs; 3370 int i, ret; 3371 3372 gbe_dev->num_stats_mods = gbe_dev->max_num_ports; 3373 gbe_dev->et_stats = gbenu_et_stats; 3374 3375 if (IS_SS_ID_NU(gbe_dev)) 3376 gbe_dev->num_et_stats = GBENU_ET_STATS_HOST_SIZE + 3377 (gbe_dev->max_num_slaves * GBENU_ET_STATS_PORT_SIZE); 3378 else 3379 gbe_dev->num_et_stats = GBENU_ET_STATS_HOST_SIZE + 3380 GBENU_ET_STATS_PORT_SIZE; 3381 3382 gbe_dev->hw_stats = devm_kzalloc(gbe_dev->dev, 3383 gbe_dev->num_et_stats * sizeof(u64), 3384 GFP_KERNEL); 3385 if (!gbe_dev->hw_stats) { 3386 dev_err(gbe_dev->dev, "hw_stats memory allocation failed\n"); 3387 return -ENOMEM; 3388 } 3389 3390 gbe_dev->hw_stats_prev = 3391 devm_kzalloc(gbe_dev->dev, 3392 gbe_dev->num_et_stats * sizeof(u32), 3393 GFP_KERNEL); 3394 if (!gbe_dev->hw_stats_prev) { 3395 dev_err(gbe_dev->dev, 3396 "hw_stats_prev memory allocation failed\n"); 3397 return -ENOMEM; 3398 } 3399 3400 ret = of_address_to_resource(node, GBENU_SM_REG_INDEX, &res); 3401 if (ret) { 3402 dev_err(gbe_dev->dev, 3403 "Can't translate of gbenu node(%s) addr at index %d\n", 3404 node->name, GBENU_SM_REG_INDEX); 3405 return ret; 3406 } 3407 3408 regs = devm_ioremap_resource(gbe_dev->dev, &res); 3409 if (IS_ERR(regs)) { 3410 dev_err(gbe_dev->dev, 3411 "Failed to map gbenu switch module register base\n"); 3412 return PTR_ERR(regs); 3413 } 3414 gbe_dev->switch_regs = regs; 3415 3416 gbe_dev->sgmii_port_regs = gbe_dev->ss_regs + GBENU_SGMII_MODULE_OFFSET; 3417 3418 /* Although sgmii modules are mem mapped to one contiguous 3419 * region on GBENU devices, setting sgmii_port34_regs allows 3420 * consistent code when accessing sgmii api 3421 */ 3422 gbe_dev->sgmii_port34_regs = gbe_dev->sgmii_port_regs + 3423 (2 * GBENU_SGMII_MODULE_SIZE); 3424 3425 gbe_dev->host_port_regs = gbe_dev->switch_regs + GBENU_HOST_PORT_OFFSET; 3426 3427 for (i = 0; i < (gbe_dev->max_num_ports); i++) 3428 gbe_dev->hw_stats_regs[i] = gbe_dev->switch_regs + 3429 GBENU_HW_STATS_OFFSET + (GBENU_HW_STATS_REG_MAP_SZ * i); 3430 3431 gbe_dev->cpts_reg = gbe_dev->switch_regs + GBENU_CPTS_OFFSET; 3432 gbe_dev->ale_reg = gbe_dev->switch_regs + GBENU_ALE_OFFSET; 3433 gbe_dev->ale_ports = gbe_dev->max_num_ports; 3434 gbe_dev->host_port = GBENU_HOST_PORT_NUM; 3435 gbe_dev->ale_entries = GBE13_NUM_ALE_ENTRIES; 3436 gbe_dev->stats_en_mask = (1 << (gbe_dev->max_num_ports)) - 1; 3437 3438 /* Subsystem registers */ 3439 GBENU_SET_REG_OFS(gbe_dev, ss_regs, id_ver); 3440 3441 /* Switch module registers */ 3442 GBENU_SET_REG_OFS(gbe_dev, switch_regs, id_ver); 3443 GBENU_SET_REG_OFS(gbe_dev, switch_regs, control); 3444 GBENU_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en); 3445 GBENU_SET_REG_OFS(gbe_dev, switch_regs, ptype); 3446 3447 /* Host port registers */ 3448 GBENU_SET_REG_OFS(gbe_dev, host_port_regs, port_vlan); 3449 GBENU_SET_REG_OFS(gbe_dev, host_port_regs, rx_maxlen); 3450 3451 /* For NU only. 2U does not need tx_pri_map. 3452 * NU cppi port 0 tx pkt streaming interface has (n-1)*8 egress threads 3453 * while 2U has only 1 such thread 3454 */ 3455 GBENU_SET_REG_OFS(gbe_dev, host_port_regs, tx_pri_map); 3456 return 0; 3457 } 3458 3459 static int gbe_probe(struct netcp_device *netcp_device, struct device *dev, 3460 struct device_node *node, void **inst_priv) 3461 { 3462 struct device_node *interfaces, *interface; 3463 struct device_node *secondary_ports; 3464 struct cpsw_ale_params ale_params; 3465 struct gbe_priv *gbe_dev; 3466 u32 slave_num; 3467 int i, ret = 0; 3468 3469 if (!node) { 3470 dev_err(dev, "device tree info unavailable\n"); 3471 return -ENODEV; 3472 } 3473 3474 gbe_dev = devm_kzalloc(dev, sizeof(struct gbe_priv), GFP_KERNEL); 3475 if (!gbe_dev) 3476 return -ENOMEM; 3477 3478 if (of_device_is_compatible(node, "ti,netcp-gbe-5") || 3479 of_device_is_compatible(node, "ti,netcp-gbe")) { 3480 gbe_dev->max_num_slaves = 4; 3481 } else if (of_device_is_compatible(node, "ti,netcp-gbe-9")) { 3482 gbe_dev->max_num_slaves = 8; 3483 } else if (of_device_is_compatible(node, "ti,netcp-gbe-2")) { 3484 gbe_dev->max_num_slaves = 1; 3485 } else if (of_device_is_compatible(node, "ti,netcp-xgbe")) { 3486 gbe_dev->max_num_slaves = 2; 3487 } else { 3488 dev_err(dev, "device tree node for unknown device\n"); 3489 return -EINVAL; 3490 } 3491 gbe_dev->max_num_ports = gbe_dev->max_num_slaves + 1; 3492 3493 gbe_dev->dev = dev; 3494 gbe_dev->netcp_device = netcp_device; 3495 gbe_dev->rx_packet_max = NETCP_MAX_FRAME_SIZE; 3496 3497 /* init the hw stats lock */ 3498 spin_lock_init(&gbe_dev->hw_stats_lock); 3499 3500 if (of_find_property(node, "enable-ale", NULL)) { 3501 gbe_dev->enable_ale = true; 3502 dev_info(dev, "ALE enabled\n"); 3503 } else { 3504 gbe_dev->enable_ale = false; 3505 dev_dbg(dev, "ALE bypass enabled*\n"); 3506 } 3507 3508 ret = of_property_read_u32(node, "tx-queue", 3509 &gbe_dev->tx_queue_id); 3510 if (ret < 0) { 3511 dev_err(dev, "missing tx_queue parameter\n"); 3512 gbe_dev->tx_queue_id = GBE_TX_QUEUE; 3513 } 3514 3515 ret = of_property_read_string(node, "tx-channel", 3516 &gbe_dev->dma_chan_name); 3517 if (ret < 0) { 3518 dev_err(dev, "missing \"tx-channel\" parameter\n"); 3519 return -EINVAL; 3520 } 3521 3522 if (!strcmp(node->name, "gbe")) { 3523 ret = get_gbe_resource_version(gbe_dev, node); 3524 if (ret) 3525 return ret; 3526 3527 dev_dbg(dev, "ss_version: 0x%08x\n", gbe_dev->ss_version); 3528 3529 if (gbe_dev->ss_version == GBE_SS_VERSION_14) 3530 ret = set_gbe_ethss14_priv(gbe_dev, node); 3531 else if (IS_SS_ID_MU(gbe_dev)) 3532 ret = set_gbenu_ethss_priv(gbe_dev, node); 3533 else 3534 ret = -ENODEV; 3535 3536 } else if (!strcmp(node->name, "xgbe")) { 3537 ret = set_xgbe_ethss10_priv(gbe_dev, node); 3538 if (ret) 3539 return ret; 3540 ret = netcp_xgbe_serdes_init(gbe_dev->xgbe_serdes_regs, 3541 gbe_dev->ss_regs); 3542 } else { 3543 dev_err(dev, "unknown GBE node(%s)\n", node->name); 3544 ret = -ENODEV; 3545 } 3546 3547 if (ret) 3548 return ret; 3549 3550 interfaces = of_get_child_by_name(node, "interfaces"); 3551 if (!interfaces) 3552 dev_err(dev, "could not find interfaces\n"); 3553 3554 ret = netcp_txpipe_init(&gbe_dev->tx_pipe, netcp_device, 3555 gbe_dev->dma_chan_name, gbe_dev->tx_queue_id); 3556 if (ret) 3557 return ret; 3558 3559 ret = netcp_txpipe_open(&gbe_dev->tx_pipe); 3560 if (ret) 3561 return ret; 3562 3563 /* Create network interfaces */ 3564 INIT_LIST_HEAD(&gbe_dev->gbe_intf_head); 3565 for_each_child_of_node(interfaces, interface) { 3566 ret = of_property_read_u32(interface, "slave-port", &slave_num); 3567 if (ret) { 3568 dev_err(dev, "missing slave-port parameter, skipping interface configuration for %s\n", 3569 interface->name); 3570 continue; 3571 } 3572 gbe_dev->num_slaves++; 3573 if (gbe_dev->num_slaves >= gbe_dev->max_num_slaves) { 3574 of_node_put(interface); 3575 break; 3576 } 3577 } 3578 of_node_put(interfaces); 3579 3580 if (!gbe_dev->num_slaves) 3581 dev_warn(dev, "No network interface configured\n"); 3582 3583 /* Initialize Secondary slave ports */ 3584 secondary_ports = of_get_child_by_name(node, "secondary-slave-ports"); 3585 INIT_LIST_HEAD(&gbe_dev->secondary_slaves); 3586 if (secondary_ports && (gbe_dev->num_slaves < gbe_dev->max_num_slaves)) 3587 init_secondary_ports(gbe_dev, secondary_ports); 3588 of_node_put(secondary_ports); 3589 3590 if (!gbe_dev->num_slaves) { 3591 dev_err(dev, 3592 "No network interface or secondary ports configured\n"); 3593 ret = -ENODEV; 3594 goto free_sec_ports; 3595 } 3596 3597 memset(&ale_params, 0, sizeof(ale_params)); 3598 ale_params.dev = gbe_dev->dev; 3599 ale_params.ale_regs = gbe_dev->ale_reg; 3600 ale_params.ale_ageout = GBE_DEFAULT_ALE_AGEOUT; 3601 ale_params.ale_entries = gbe_dev->ale_entries; 3602 ale_params.ale_ports = gbe_dev->ale_ports; 3603 3604 gbe_dev->ale = cpsw_ale_create(&ale_params); 3605 if (!gbe_dev->ale) { 3606 dev_err(gbe_dev->dev, "error initializing ale engine\n"); 3607 ret = -ENODEV; 3608 goto free_sec_ports; 3609 } else { 3610 dev_dbg(gbe_dev->dev, "Created a gbe ale engine\n"); 3611 } 3612 3613 gbe_dev->cpts = cpts_create(gbe_dev->dev, gbe_dev->cpts_reg, node); 3614 if (IS_ENABLED(CONFIG_TI_CPTS) && IS_ERR(gbe_dev->cpts)) { 3615 ret = PTR_ERR(gbe_dev->cpts); 3616 goto free_sec_ports; 3617 } 3618 3619 /* initialize host port */ 3620 gbe_init_host_port(gbe_dev); 3621 3622 spin_lock_bh(&gbe_dev->hw_stats_lock); 3623 for (i = 0; i < gbe_dev->num_stats_mods; i++) { 3624 if (gbe_dev->ss_version == GBE_SS_VERSION_14) 3625 gbe_reset_mod_stats_ver14(gbe_dev, i); 3626 else 3627 gbe_reset_mod_stats(gbe_dev, i); 3628 } 3629 spin_unlock_bh(&gbe_dev->hw_stats_lock); 3630 3631 init_timer(&gbe_dev->timer); 3632 gbe_dev->timer.data = (unsigned long)gbe_dev; 3633 gbe_dev->timer.function = netcp_ethss_timer; 3634 gbe_dev->timer.expires = jiffies + GBE_TIMER_INTERVAL; 3635 add_timer(&gbe_dev->timer); 3636 *inst_priv = gbe_dev; 3637 return 0; 3638 3639 free_sec_ports: 3640 free_secondary_ports(gbe_dev); 3641 return ret; 3642 } 3643 3644 static int gbe_attach(void *inst_priv, struct net_device *ndev, 3645 struct device_node *node, void **intf_priv) 3646 { 3647 struct gbe_priv *gbe_dev = inst_priv; 3648 struct gbe_intf *gbe_intf; 3649 int ret; 3650 3651 if (!node) { 3652 dev_err(gbe_dev->dev, "interface node not available\n"); 3653 return -ENODEV; 3654 } 3655 3656 gbe_intf = devm_kzalloc(gbe_dev->dev, sizeof(*gbe_intf), GFP_KERNEL); 3657 if (!gbe_intf) 3658 return -ENOMEM; 3659 3660 gbe_intf->ndev = ndev; 3661 gbe_intf->dev = gbe_dev->dev; 3662 gbe_intf->gbe_dev = gbe_dev; 3663 3664 gbe_intf->slave = devm_kzalloc(gbe_dev->dev, 3665 sizeof(*gbe_intf->slave), 3666 GFP_KERNEL); 3667 if (!gbe_intf->slave) { 3668 ret = -ENOMEM; 3669 goto fail; 3670 } 3671 3672 if (init_slave(gbe_dev, gbe_intf->slave, node)) { 3673 ret = -ENODEV; 3674 goto fail; 3675 } 3676 3677 gbe_intf->tx_pipe = gbe_dev->tx_pipe; 3678 ndev->ethtool_ops = &keystone_ethtool_ops; 3679 list_add_tail(&gbe_intf->gbe_intf_list, &gbe_dev->gbe_intf_head); 3680 *intf_priv = gbe_intf; 3681 return 0; 3682 3683 fail: 3684 if (gbe_intf->slave) 3685 devm_kfree(gbe_dev->dev, gbe_intf->slave); 3686 if (gbe_intf) 3687 devm_kfree(gbe_dev->dev, gbe_intf); 3688 return ret; 3689 } 3690 3691 static int gbe_release(void *intf_priv) 3692 { 3693 struct gbe_intf *gbe_intf = intf_priv; 3694 3695 gbe_intf->ndev->ethtool_ops = NULL; 3696 list_del(&gbe_intf->gbe_intf_list); 3697 devm_kfree(gbe_intf->dev, gbe_intf->slave); 3698 devm_kfree(gbe_intf->dev, gbe_intf); 3699 return 0; 3700 } 3701 3702 static int gbe_remove(struct netcp_device *netcp_device, void *inst_priv) 3703 { 3704 struct gbe_priv *gbe_dev = inst_priv; 3705 3706 del_timer_sync(&gbe_dev->timer); 3707 cpts_release(gbe_dev->cpts); 3708 cpsw_ale_stop(gbe_dev->ale); 3709 cpsw_ale_destroy(gbe_dev->ale); 3710 netcp_txpipe_close(&gbe_dev->tx_pipe); 3711 free_secondary_ports(gbe_dev); 3712 3713 if (!list_empty(&gbe_dev->gbe_intf_head)) 3714 dev_alert(gbe_dev->dev, 3715 "unreleased ethss interfaces present\n"); 3716 3717 return 0; 3718 } 3719 3720 static struct netcp_module gbe_module = { 3721 .name = GBE_MODULE_NAME, 3722 .owner = THIS_MODULE, 3723 .primary = true, 3724 .probe = gbe_probe, 3725 .open = gbe_open, 3726 .close = gbe_close, 3727 .remove = gbe_remove, 3728 .attach = gbe_attach, 3729 .release = gbe_release, 3730 .add_addr = gbe_add_addr, 3731 .del_addr = gbe_del_addr, 3732 .add_vid = gbe_add_vid, 3733 .del_vid = gbe_del_vid, 3734 .ioctl = gbe_ioctl, 3735 }; 3736 3737 static struct netcp_module xgbe_module = { 3738 .name = XGBE_MODULE_NAME, 3739 .owner = THIS_MODULE, 3740 .primary = true, 3741 .probe = gbe_probe, 3742 .open = gbe_open, 3743 .close = gbe_close, 3744 .remove = gbe_remove, 3745 .attach = gbe_attach, 3746 .release = gbe_release, 3747 .add_addr = gbe_add_addr, 3748 .del_addr = gbe_del_addr, 3749 .add_vid = gbe_add_vid, 3750 .del_vid = gbe_del_vid, 3751 .ioctl = gbe_ioctl, 3752 }; 3753 3754 static int __init keystone_gbe_init(void) 3755 { 3756 int ret; 3757 3758 ret = netcp_register_module(&gbe_module); 3759 if (ret) 3760 return ret; 3761 3762 ret = netcp_register_module(&xgbe_module); 3763 if (ret) 3764 return ret; 3765 3766 return 0; 3767 } 3768 module_init(keystone_gbe_init); 3769 3770 static void __exit keystone_gbe_exit(void) 3771 { 3772 netcp_unregister_module(&gbe_module); 3773 netcp_unregister_module(&xgbe_module); 3774 } 3775 module_exit(keystone_gbe_exit); 3776 3777 MODULE_LICENSE("GPL v2"); 3778 MODULE_DESCRIPTION("TI NETCP ETHSS driver for Keystone SOCs"); 3779 MODULE_AUTHOR("Sandeep Nair <sandeep_n@ti.com"); 3780