1 /* 2 * Keystone GBE and XGBE subsystem code 3 * 4 * Copyright (C) 2014 Texas Instruments Incorporated 5 * Authors: Sandeep Nair <sandeep_n@ti.com> 6 * Sandeep Paulraj <s-paulraj@ti.com> 7 * Cyril Chemparathy <cyril@ti.com> 8 * Santosh Shilimkar <santosh.shilimkar@ti.com> 9 * Wingman Kwok <w-kwok2@ti.com> 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation version 2. 14 * 15 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 16 * kind, whether express or implied; without even the implied warranty 17 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 */ 20 21 #include <linux/io.h> 22 #include <linux/module.h> 23 #include <linux/of_mdio.h> 24 #include <linux/of_address.h> 25 #include <linux/if_vlan.h> 26 #include <linux/ethtool.h> 27 28 #include "cpsw_ale.h" 29 #include "netcp.h" 30 31 #define NETCP_DRIVER_NAME "TI KeyStone Ethernet Driver" 32 #define NETCP_DRIVER_VERSION "v1.0" 33 34 #define GBE_IDENT(reg) ((reg >> 16) & 0xffff) 35 #define GBE_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 36 #define GBE_MINOR_VERSION(reg) (reg & 0xff) 37 #define GBE_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 38 39 /* 1G Ethernet SS defines */ 40 #define GBE_MODULE_NAME "netcp-gbe" 41 #define GBE_SS_VERSION_14 0x4ed21104 42 43 #define GBE_SS_REG_INDEX 0 44 #define GBE_SGMII34_REG_INDEX 1 45 #define GBE_SM_REG_INDEX 2 46 /* offset relative to base of GBE_SS_REG_INDEX */ 47 #define GBE13_SGMII_MODULE_OFFSET 0x100 48 /* offset relative to base of GBE_SM_REG_INDEX */ 49 #define GBE13_HOST_PORT_OFFSET 0x34 50 #define GBE13_SLAVE_PORT_OFFSET 0x60 51 #define GBE13_EMAC_OFFSET 0x100 52 #define GBE13_SLAVE_PORT2_OFFSET 0x200 53 #define GBE13_HW_STATS_OFFSET 0x300 54 #define GBE13_ALE_OFFSET 0x600 55 #define GBE13_HOST_PORT_NUM 0 56 #define GBE13_NUM_ALE_ENTRIES 1024 57 58 /* 1G Ethernet NU SS defines */ 59 #define GBENU_MODULE_NAME "netcp-gbenu" 60 #define GBE_SS_ID_NU 0x4ee6 61 #define GBE_SS_ID_2U 0x4ee8 62 63 #define IS_SS_ID_MU(d) \ 64 ((GBE_IDENT((d)->ss_version) == GBE_SS_ID_NU) || \ 65 (GBE_IDENT((d)->ss_version) == GBE_SS_ID_2U)) 66 67 #define IS_SS_ID_NU(d) \ 68 (GBE_IDENT((d)->ss_version) == GBE_SS_ID_NU) 69 70 #define GBENU_SS_REG_INDEX 0 71 #define GBENU_SM_REG_INDEX 1 72 #define GBENU_SGMII_MODULE_OFFSET 0x100 73 #define GBENU_HOST_PORT_OFFSET 0x1000 74 #define GBENU_SLAVE_PORT_OFFSET 0x2000 75 #define GBENU_EMAC_OFFSET 0x2330 76 #define GBENU_HW_STATS_OFFSET 0x1a000 77 #define GBENU_ALE_OFFSET 0x1e000 78 #define GBENU_HOST_PORT_NUM 0 79 #define GBENU_NUM_ALE_ENTRIES 1024 80 #define GBENU_SGMII_MODULE_SIZE 0x100 81 82 /* 10G Ethernet SS defines */ 83 #define XGBE_MODULE_NAME "netcp-xgbe" 84 #define XGBE_SS_VERSION_10 0x4ee42100 85 86 #define XGBE_SS_REG_INDEX 0 87 #define XGBE_SM_REG_INDEX 1 88 #define XGBE_SERDES_REG_INDEX 2 89 90 /* offset relative to base of XGBE_SS_REG_INDEX */ 91 #define XGBE10_SGMII_MODULE_OFFSET 0x100 92 /* offset relative to base of XGBE_SM_REG_INDEX */ 93 #define XGBE10_HOST_PORT_OFFSET 0x34 94 #define XGBE10_SLAVE_PORT_OFFSET 0x64 95 #define XGBE10_EMAC_OFFSET 0x400 96 #define XGBE10_ALE_OFFSET 0x700 97 #define XGBE10_HW_STATS_OFFSET 0x800 98 #define XGBE10_HOST_PORT_NUM 0 99 #define XGBE10_NUM_ALE_ENTRIES 1024 100 101 #define GBE_TIMER_INTERVAL (HZ / 2) 102 103 /* Soft reset register values */ 104 #define SOFT_RESET_MASK BIT(0) 105 #define SOFT_RESET BIT(0) 106 #define DEVICE_EMACSL_RESET_POLL_COUNT 100 107 #define GMACSL_RET_WARN_RESET_INCOMPLETE -2 108 109 #define MACSL_RX_ENABLE_CSF BIT(23) 110 #define MACSL_ENABLE_EXT_CTL BIT(18) 111 #define MACSL_XGMII_ENABLE BIT(13) 112 #define MACSL_XGIG_MODE BIT(8) 113 #define MACSL_GIG_MODE BIT(7) 114 #define MACSL_GMII_ENABLE BIT(5) 115 #define MACSL_FULLDUPLEX BIT(0) 116 117 #define GBE_CTL_P0_ENABLE BIT(2) 118 #define GBE13_REG_VAL_STAT_ENABLE_ALL 0xff 119 #define XGBE_REG_VAL_STAT_ENABLE_ALL 0xf 120 #define GBE_STATS_CD_SEL BIT(28) 121 122 #define GBE_PORT_MASK(x) (BIT(x) - 1) 123 #define GBE_MASK_NO_PORTS 0 124 125 #define GBE_DEF_1G_MAC_CONTROL \ 126 (MACSL_GIG_MODE | MACSL_GMII_ENABLE | \ 127 MACSL_ENABLE_EXT_CTL | MACSL_RX_ENABLE_CSF) 128 129 #define GBE_DEF_10G_MAC_CONTROL \ 130 (MACSL_XGIG_MODE | MACSL_XGMII_ENABLE | \ 131 MACSL_ENABLE_EXT_CTL | MACSL_RX_ENABLE_CSF) 132 133 #define GBE_STATSA_MODULE 0 134 #define GBE_STATSB_MODULE 1 135 #define GBE_STATSC_MODULE 2 136 #define GBE_STATSD_MODULE 3 137 138 #define GBENU_STATS0_MODULE 0 139 #define GBENU_STATS1_MODULE 1 140 #define GBENU_STATS2_MODULE 2 141 #define GBENU_STATS3_MODULE 3 142 #define GBENU_STATS4_MODULE 4 143 #define GBENU_STATS5_MODULE 5 144 #define GBENU_STATS6_MODULE 6 145 #define GBENU_STATS7_MODULE 7 146 #define GBENU_STATS8_MODULE 8 147 148 #define XGBE_STATS0_MODULE 0 149 #define XGBE_STATS1_MODULE 1 150 #define XGBE_STATS2_MODULE 2 151 152 /* s: 0-based slave_port */ 153 #define SGMII_BASE(d, s) \ 154 (((s) < 2) ? (d)->sgmii_port_regs : (d)->sgmii_port34_regs) 155 156 #define GBE_TX_QUEUE 648 157 #define GBE_TXHOOK_ORDER 0 158 #define GBE_DEFAULT_ALE_AGEOUT 30 159 #define SLAVE_LINK_IS_XGMII(s) ((s)->link_interface >= XGMII_LINK_MAC_PHY) 160 #define NETCP_LINK_STATE_INVALID -1 161 162 #define GBE_SET_REG_OFS(p, rb, rn) p->rb##_ofs.rn = \ 163 offsetof(struct gbe##_##rb, rn) 164 #define GBENU_SET_REG_OFS(p, rb, rn) p->rb##_ofs.rn = \ 165 offsetof(struct gbenu##_##rb, rn) 166 #define XGBE_SET_REG_OFS(p, rb, rn) p->rb##_ofs.rn = \ 167 offsetof(struct xgbe##_##rb, rn) 168 #define GBE_REG_ADDR(p, rb, rn) (p->rb + p->rb##_ofs.rn) 169 170 #define HOST_TX_PRI_MAP_DEFAULT 0x00000000 171 172 struct xgbe_ss_regs { 173 u32 id_ver; 174 u32 synce_count; 175 u32 synce_mux; 176 u32 control; 177 }; 178 179 struct xgbe_switch_regs { 180 u32 id_ver; 181 u32 control; 182 u32 emcontrol; 183 u32 stat_port_en; 184 u32 ptype; 185 u32 soft_idle; 186 u32 thru_rate; 187 u32 gap_thresh; 188 u32 tx_start_wds; 189 u32 flow_control; 190 u32 cppi_thresh; 191 }; 192 193 struct xgbe_port_regs { 194 u32 blk_cnt; 195 u32 port_vlan; 196 u32 tx_pri_map; 197 u32 sa_lo; 198 u32 sa_hi; 199 u32 ts_ctl; 200 u32 ts_seq_ltype; 201 u32 ts_vlan; 202 u32 ts_ctl_ltype2; 203 u32 ts_ctl2; 204 u32 control; 205 }; 206 207 struct xgbe_host_port_regs { 208 u32 blk_cnt; 209 u32 port_vlan; 210 u32 tx_pri_map; 211 u32 src_id; 212 u32 rx_pri_map; 213 u32 rx_maxlen; 214 }; 215 216 struct xgbe_emac_regs { 217 u32 id_ver; 218 u32 mac_control; 219 u32 mac_status; 220 u32 soft_reset; 221 u32 rx_maxlen; 222 u32 __reserved_0; 223 u32 rx_pause; 224 u32 tx_pause; 225 u32 em_control; 226 u32 __reserved_1; 227 u32 tx_gap; 228 u32 rsvd[4]; 229 }; 230 231 struct xgbe_host_hw_stats { 232 u32 rx_good_frames; 233 u32 rx_broadcast_frames; 234 u32 rx_multicast_frames; 235 u32 __rsvd_0[3]; 236 u32 rx_oversized_frames; 237 u32 __rsvd_1; 238 u32 rx_undersized_frames; 239 u32 __rsvd_2; 240 u32 overrun_type4; 241 u32 overrun_type5; 242 u32 rx_bytes; 243 u32 tx_good_frames; 244 u32 tx_broadcast_frames; 245 u32 tx_multicast_frames; 246 u32 __rsvd_3[9]; 247 u32 tx_bytes; 248 u32 tx_64byte_frames; 249 u32 tx_65_to_127byte_frames; 250 u32 tx_128_to_255byte_frames; 251 u32 tx_256_to_511byte_frames; 252 u32 tx_512_to_1023byte_frames; 253 u32 tx_1024byte_frames; 254 u32 net_bytes; 255 u32 rx_sof_overruns; 256 u32 rx_mof_overruns; 257 u32 rx_dma_overruns; 258 }; 259 260 struct xgbe_hw_stats { 261 u32 rx_good_frames; 262 u32 rx_broadcast_frames; 263 u32 rx_multicast_frames; 264 u32 rx_pause_frames; 265 u32 rx_crc_errors; 266 u32 rx_align_code_errors; 267 u32 rx_oversized_frames; 268 u32 rx_jabber_frames; 269 u32 rx_undersized_frames; 270 u32 rx_fragments; 271 u32 overrun_type4; 272 u32 overrun_type5; 273 u32 rx_bytes; 274 u32 tx_good_frames; 275 u32 tx_broadcast_frames; 276 u32 tx_multicast_frames; 277 u32 tx_pause_frames; 278 u32 tx_deferred_frames; 279 u32 tx_collision_frames; 280 u32 tx_single_coll_frames; 281 u32 tx_mult_coll_frames; 282 u32 tx_excessive_collisions; 283 u32 tx_late_collisions; 284 u32 tx_underrun; 285 u32 tx_carrier_sense_errors; 286 u32 tx_bytes; 287 u32 tx_64byte_frames; 288 u32 tx_65_to_127byte_frames; 289 u32 tx_128_to_255byte_frames; 290 u32 tx_256_to_511byte_frames; 291 u32 tx_512_to_1023byte_frames; 292 u32 tx_1024byte_frames; 293 u32 net_bytes; 294 u32 rx_sof_overruns; 295 u32 rx_mof_overruns; 296 u32 rx_dma_overruns; 297 }; 298 299 struct gbenu_ss_regs { 300 u32 id_ver; 301 u32 synce_count; /* NU */ 302 u32 synce_mux; /* NU */ 303 u32 control; /* 2U */ 304 u32 __rsvd_0[2]; /* 2U */ 305 u32 rgmii_status; /* 2U */ 306 u32 ss_status; /* 2U */ 307 }; 308 309 struct gbenu_switch_regs { 310 u32 id_ver; 311 u32 control; 312 u32 __rsvd_0[2]; 313 u32 emcontrol; 314 u32 stat_port_en; 315 u32 ptype; /* NU */ 316 u32 soft_idle; 317 u32 thru_rate; /* NU */ 318 u32 gap_thresh; /* NU */ 319 u32 tx_start_wds; /* NU */ 320 u32 eee_prescale; /* 2U */ 321 u32 tx_g_oflow_thresh_set; /* NU */ 322 u32 tx_g_oflow_thresh_clr; /* NU */ 323 u32 tx_g_buf_thresh_set_l; /* NU */ 324 u32 tx_g_buf_thresh_set_h; /* NU */ 325 u32 tx_g_buf_thresh_clr_l; /* NU */ 326 u32 tx_g_buf_thresh_clr_h; /* NU */ 327 }; 328 329 struct gbenu_port_regs { 330 u32 __rsvd_0; 331 u32 control; 332 u32 max_blks; /* 2U */ 333 u32 mem_align1; 334 u32 blk_cnt; 335 u32 port_vlan; 336 u32 tx_pri_map; /* NU */ 337 u32 pri_ctl; /* 2U */ 338 u32 rx_pri_map; 339 u32 rx_maxlen; 340 u32 tx_blks_pri; /* NU */ 341 u32 __rsvd_1; 342 u32 idle2lpi; /* 2U */ 343 u32 lpi2idle; /* 2U */ 344 u32 eee_status; /* 2U */ 345 u32 __rsvd_2; 346 u32 __rsvd_3[176]; /* NU: more to add */ 347 u32 __rsvd_4[2]; 348 u32 sa_lo; 349 u32 sa_hi; 350 u32 ts_ctl; 351 u32 ts_seq_ltype; 352 u32 ts_vlan; 353 u32 ts_ctl_ltype2; 354 u32 ts_ctl2; 355 }; 356 357 struct gbenu_host_port_regs { 358 u32 __rsvd_0; 359 u32 control; 360 u32 flow_id_offset; /* 2U */ 361 u32 __rsvd_1; 362 u32 blk_cnt; 363 u32 port_vlan; 364 u32 tx_pri_map; /* NU */ 365 u32 pri_ctl; 366 u32 rx_pri_map; 367 u32 rx_maxlen; 368 u32 tx_blks_pri; /* NU */ 369 u32 __rsvd_2; 370 u32 idle2lpi; /* 2U */ 371 u32 lpi2wake; /* 2U */ 372 u32 eee_status; /* 2U */ 373 u32 __rsvd_3; 374 u32 __rsvd_4[184]; /* NU */ 375 u32 host_blks_pri; /* NU */ 376 }; 377 378 struct gbenu_emac_regs { 379 u32 mac_control; 380 u32 mac_status; 381 u32 soft_reset; 382 u32 boff_test; 383 u32 rx_pause; 384 u32 __rsvd_0[11]; /* NU */ 385 u32 tx_pause; 386 u32 __rsvd_1[11]; /* NU */ 387 u32 em_control; 388 u32 tx_gap; 389 }; 390 391 /* Some hw stat regs are applicable to slave port only. 392 * This is handled by gbenu_et_stats struct. Also some 393 * are for SS version NU and some are for 2U. 394 */ 395 struct gbenu_hw_stats { 396 u32 rx_good_frames; 397 u32 rx_broadcast_frames; 398 u32 rx_multicast_frames; 399 u32 rx_pause_frames; /* slave */ 400 u32 rx_crc_errors; 401 u32 rx_align_code_errors; /* slave */ 402 u32 rx_oversized_frames; 403 u32 rx_jabber_frames; /* slave */ 404 u32 rx_undersized_frames; 405 u32 rx_fragments; /* slave */ 406 u32 ale_drop; 407 u32 ale_overrun_drop; 408 u32 rx_bytes; 409 u32 tx_good_frames; 410 u32 tx_broadcast_frames; 411 u32 tx_multicast_frames; 412 u32 tx_pause_frames; /* slave */ 413 u32 tx_deferred_frames; /* slave */ 414 u32 tx_collision_frames; /* slave */ 415 u32 tx_single_coll_frames; /* slave */ 416 u32 tx_mult_coll_frames; /* slave */ 417 u32 tx_excessive_collisions; /* slave */ 418 u32 tx_late_collisions; /* slave */ 419 u32 rx_ipg_error; /* slave 10G only */ 420 u32 tx_carrier_sense_errors; /* slave */ 421 u32 tx_bytes; 422 u32 tx_64B_frames; 423 u32 tx_65_to_127B_frames; 424 u32 tx_128_to_255B_frames; 425 u32 tx_256_to_511B_frames; 426 u32 tx_512_to_1023B_frames; 427 u32 tx_1024B_frames; 428 u32 net_bytes; 429 u32 rx_bottom_fifo_drop; 430 u32 rx_port_mask_drop; 431 u32 rx_top_fifo_drop; 432 u32 ale_rate_limit_drop; 433 u32 ale_vid_ingress_drop; 434 u32 ale_da_eq_sa_drop; 435 u32 __rsvd_0[3]; 436 u32 ale_unknown_ucast; 437 u32 ale_unknown_ucast_bytes; 438 u32 ale_unknown_mcast; 439 u32 ale_unknown_mcast_bytes; 440 u32 ale_unknown_bcast; 441 u32 ale_unknown_bcast_bytes; 442 u32 ale_pol_match; 443 u32 ale_pol_match_red; /* NU */ 444 u32 ale_pol_match_yellow; /* NU */ 445 u32 __rsvd_1[44]; 446 u32 tx_mem_protect_err; 447 /* following NU only */ 448 u32 tx_pri0; 449 u32 tx_pri1; 450 u32 tx_pri2; 451 u32 tx_pri3; 452 u32 tx_pri4; 453 u32 tx_pri5; 454 u32 tx_pri6; 455 u32 tx_pri7; 456 u32 tx_pri0_bcnt; 457 u32 tx_pri1_bcnt; 458 u32 tx_pri2_bcnt; 459 u32 tx_pri3_bcnt; 460 u32 tx_pri4_bcnt; 461 u32 tx_pri5_bcnt; 462 u32 tx_pri6_bcnt; 463 u32 tx_pri7_bcnt; 464 u32 tx_pri0_drop; 465 u32 tx_pri1_drop; 466 u32 tx_pri2_drop; 467 u32 tx_pri3_drop; 468 u32 tx_pri4_drop; 469 u32 tx_pri5_drop; 470 u32 tx_pri6_drop; 471 u32 tx_pri7_drop; 472 u32 tx_pri0_drop_bcnt; 473 u32 tx_pri1_drop_bcnt; 474 u32 tx_pri2_drop_bcnt; 475 u32 tx_pri3_drop_bcnt; 476 u32 tx_pri4_drop_bcnt; 477 u32 tx_pri5_drop_bcnt; 478 u32 tx_pri6_drop_bcnt; 479 u32 tx_pri7_drop_bcnt; 480 }; 481 482 #define GBENU_HW_STATS_REG_MAP_SZ 0x200 483 484 struct gbe_ss_regs { 485 u32 id_ver; 486 u32 synce_count; 487 u32 synce_mux; 488 }; 489 490 struct gbe_ss_regs_ofs { 491 u16 id_ver; 492 u16 control; 493 }; 494 495 struct gbe_switch_regs { 496 u32 id_ver; 497 u32 control; 498 u32 soft_reset; 499 u32 stat_port_en; 500 u32 ptype; 501 u32 soft_idle; 502 u32 thru_rate; 503 u32 gap_thresh; 504 u32 tx_start_wds; 505 u32 flow_control; 506 }; 507 508 struct gbe_switch_regs_ofs { 509 u16 id_ver; 510 u16 control; 511 u16 soft_reset; 512 u16 emcontrol; 513 u16 stat_port_en; 514 u16 ptype; 515 u16 flow_control; 516 }; 517 518 struct gbe_port_regs { 519 u32 max_blks; 520 u32 blk_cnt; 521 u32 port_vlan; 522 u32 tx_pri_map; 523 u32 sa_lo; 524 u32 sa_hi; 525 u32 ts_ctl; 526 u32 ts_seq_ltype; 527 u32 ts_vlan; 528 u32 ts_ctl_ltype2; 529 u32 ts_ctl2; 530 }; 531 532 struct gbe_port_regs_ofs { 533 u16 port_vlan; 534 u16 tx_pri_map; 535 u16 sa_lo; 536 u16 sa_hi; 537 u16 ts_ctl; 538 u16 ts_seq_ltype; 539 u16 ts_vlan; 540 u16 ts_ctl_ltype2; 541 u16 ts_ctl2; 542 u16 rx_maxlen; /* 2U, NU */ 543 }; 544 545 struct gbe_host_port_regs { 546 u32 src_id; 547 u32 port_vlan; 548 u32 rx_pri_map; 549 u32 rx_maxlen; 550 }; 551 552 struct gbe_host_port_regs_ofs { 553 u16 port_vlan; 554 u16 tx_pri_map; 555 u16 rx_maxlen; 556 }; 557 558 struct gbe_emac_regs { 559 u32 id_ver; 560 u32 mac_control; 561 u32 mac_status; 562 u32 soft_reset; 563 u32 rx_maxlen; 564 u32 __reserved_0; 565 u32 rx_pause; 566 u32 tx_pause; 567 u32 __reserved_1; 568 u32 rx_pri_map; 569 u32 rsvd[6]; 570 }; 571 572 struct gbe_emac_regs_ofs { 573 u16 mac_control; 574 u16 soft_reset; 575 u16 rx_maxlen; 576 }; 577 578 struct gbe_hw_stats { 579 u32 rx_good_frames; 580 u32 rx_broadcast_frames; 581 u32 rx_multicast_frames; 582 u32 rx_pause_frames; 583 u32 rx_crc_errors; 584 u32 rx_align_code_errors; 585 u32 rx_oversized_frames; 586 u32 rx_jabber_frames; 587 u32 rx_undersized_frames; 588 u32 rx_fragments; 589 u32 __pad_0[2]; 590 u32 rx_bytes; 591 u32 tx_good_frames; 592 u32 tx_broadcast_frames; 593 u32 tx_multicast_frames; 594 u32 tx_pause_frames; 595 u32 tx_deferred_frames; 596 u32 tx_collision_frames; 597 u32 tx_single_coll_frames; 598 u32 tx_mult_coll_frames; 599 u32 tx_excessive_collisions; 600 u32 tx_late_collisions; 601 u32 tx_underrun; 602 u32 tx_carrier_sense_errors; 603 u32 tx_bytes; 604 u32 tx_64byte_frames; 605 u32 tx_65_to_127byte_frames; 606 u32 tx_128_to_255byte_frames; 607 u32 tx_256_to_511byte_frames; 608 u32 tx_512_to_1023byte_frames; 609 u32 tx_1024byte_frames; 610 u32 net_bytes; 611 u32 rx_sof_overruns; 612 u32 rx_mof_overruns; 613 u32 rx_dma_overruns; 614 }; 615 616 #define GBE_MAX_HW_STAT_MODS 9 617 #define GBE_HW_STATS_REG_MAP_SZ 0x100 618 619 struct gbe_slave { 620 void __iomem *port_regs; 621 void __iomem *emac_regs; 622 struct gbe_port_regs_ofs port_regs_ofs; 623 struct gbe_emac_regs_ofs emac_regs_ofs; 624 int slave_num; /* 0 based logical number */ 625 int port_num; /* actual port number */ 626 atomic_t link_state; 627 bool open; 628 struct phy_device *phy; 629 u32 link_interface; 630 u32 mac_control; 631 u8 phy_port_t; 632 struct device_node *phy_node; 633 struct list_head slave_list; 634 }; 635 636 struct gbe_priv { 637 struct device *dev; 638 struct netcp_device *netcp_device; 639 struct timer_list timer; 640 u32 num_slaves; 641 u32 ale_entries; 642 u32 ale_ports; 643 bool enable_ale; 644 u8 max_num_slaves; 645 u8 max_num_ports; /* max_num_slaves + 1 */ 646 u8 num_stats_mods; 647 struct netcp_tx_pipe tx_pipe; 648 649 int host_port; 650 u32 rx_packet_max; 651 u32 ss_version; 652 u32 stats_en_mask; 653 654 void __iomem *ss_regs; 655 void __iomem *switch_regs; 656 void __iomem *host_port_regs; 657 void __iomem *ale_reg; 658 void __iomem *sgmii_port_regs; 659 void __iomem *sgmii_port34_regs; 660 void __iomem *xgbe_serdes_regs; 661 void __iomem *hw_stats_regs[GBE_MAX_HW_STAT_MODS]; 662 663 struct gbe_ss_regs_ofs ss_regs_ofs; 664 struct gbe_switch_regs_ofs switch_regs_ofs; 665 struct gbe_host_port_regs_ofs host_port_regs_ofs; 666 667 struct cpsw_ale *ale; 668 unsigned int tx_queue_id; 669 const char *dma_chan_name; 670 671 struct list_head gbe_intf_head; 672 struct list_head secondary_slaves; 673 struct net_device *dummy_ndev; 674 675 u64 *hw_stats; 676 u32 *hw_stats_prev; 677 const struct netcp_ethtool_stat *et_stats; 678 int num_et_stats; 679 /* Lock for updating the hwstats */ 680 spinlock_t hw_stats_lock; 681 }; 682 683 struct gbe_intf { 684 struct net_device *ndev; 685 struct device *dev; 686 struct gbe_priv *gbe_dev; 687 struct netcp_tx_pipe tx_pipe; 688 struct gbe_slave *slave; 689 struct list_head gbe_intf_list; 690 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 691 }; 692 693 static struct netcp_module gbe_module; 694 static struct netcp_module xgbe_module; 695 696 /* Statistic management */ 697 struct netcp_ethtool_stat { 698 char desc[ETH_GSTRING_LEN]; 699 int type; 700 u32 size; 701 int offset; 702 }; 703 704 #define GBE_STATSA_INFO(field) \ 705 { \ 706 "GBE_A:"#field, GBE_STATSA_MODULE, \ 707 FIELD_SIZEOF(struct gbe_hw_stats, field), \ 708 offsetof(struct gbe_hw_stats, field) \ 709 } 710 711 #define GBE_STATSB_INFO(field) \ 712 { \ 713 "GBE_B:"#field, GBE_STATSB_MODULE, \ 714 FIELD_SIZEOF(struct gbe_hw_stats, field), \ 715 offsetof(struct gbe_hw_stats, field) \ 716 } 717 718 #define GBE_STATSC_INFO(field) \ 719 { \ 720 "GBE_C:"#field, GBE_STATSC_MODULE, \ 721 FIELD_SIZEOF(struct gbe_hw_stats, field), \ 722 offsetof(struct gbe_hw_stats, field) \ 723 } 724 725 #define GBE_STATSD_INFO(field) \ 726 { \ 727 "GBE_D:"#field, GBE_STATSD_MODULE, \ 728 FIELD_SIZEOF(struct gbe_hw_stats, field), \ 729 offsetof(struct gbe_hw_stats, field) \ 730 } 731 732 static const struct netcp_ethtool_stat gbe13_et_stats[] = { 733 /* GBE module A */ 734 GBE_STATSA_INFO(rx_good_frames), 735 GBE_STATSA_INFO(rx_broadcast_frames), 736 GBE_STATSA_INFO(rx_multicast_frames), 737 GBE_STATSA_INFO(rx_pause_frames), 738 GBE_STATSA_INFO(rx_crc_errors), 739 GBE_STATSA_INFO(rx_align_code_errors), 740 GBE_STATSA_INFO(rx_oversized_frames), 741 GBE_STATSA_INFO(rx_jabber_frames), 742 GBE_STATSA_INFO(rx_undersized_frames), 743 GBE_STATSA_INFO(rx_fragments), 744 GBE_STATSA_INFO(rx_bytes), 745 GBE_STATSA_INFO(tx_good_frames), 746 GBE_STATSA_INFO(tx_broadcast_frames), 747 GBE_STATSA_INFO(tx_multicast_frames), 748 GBE_STATSA_INFO(tx_pause_frames), 749 GBE_STATSA_INFO(tx_deferred_frames), 750 GBE_STATSA_INFO(tx_collision_frames), 751 GBE_STATSA_INFO(tx_single_coll_frames), 752 GBE_STATSA_INFO(tx_mult_coll_frames), 753 GBE_STATSA_INFO(tx_excessive_collisions), 754 GBE_STATSA_INFO(tx_late_collisions), 755 GBE_STATSA_INFO(tx_underrun), 756 GBE_STATSA_INFO(tx_carrier_sense_errors), 757 GBE_STATSA_INFO(tx_bytes), 758 GBE_STATSA_INFO(tx_64byte_frames), 759 GBE_STATSA_INFO(tx_65_to_127byte_frames), 760 GBE_STATSA_INFO(tx_128_to_255byte_frames), 761 GBE_STATSA_INFO(tx_256_to_511byte_frames), 762 GBE_STATSA_INFO(tx_512_to_1023byte_frames), 763 GBE_STATSA_INFO(tx_1024byte_frames), 764 GBE_STATSA_INFO(net_bytes), 765 GBE_STATSA_INFO(rx_sof_overruns), 766 GBE_STATSA_INFO(rx_mof_overruns), 767 GBE_STATSA_INFO(rx_dma_overruns), 768 /* GBE module B */ 769 GBE_STATSB_INFO(rx_good_frames), 770 GBE_STATSB_INFO(rx_broadcast_frames), 771 GBE_STATSB_INFO(rx_multicast_frames), 772 GBE_STATSB_INFO(rx_pause_frames), 773 GBE_STATSB_INFO(rx_crc_errors), 774 GBE_STATSB_INFO(rx_align_code_errors), 775 GBE_STATSB_INFO(rx_oversized_frames), 776 GBE_STATSB_INFO(rx_jabber_frames), 777 GBE_STATSB_INFO(rx_undersized_frames), 778 GBE_STATSB_INFO(rx_fragments), 779 GBE_STATSB_INFO(rx_bytes), 780 GBE_STATSB_INFO(tx_good_frames), 781 GBE_STATSB_INFO(tx_broadcast_frames), 782 GBE_STATSB_INFO(tx_multicast_frames), 783 GBE_STATSB_INFO(tx_pause_frames), 784 GBE_STATSB_INFO(tx_deferred_frames), 785 GBE_STATSB_INFO(tx_collision_frames), 786 GBE_STATSB_INFO(tx_single_coll_frames), 787 GBE_STATSB_INFO(tx_mult_coll_frames), 788 GBE_STATSB_INFO(tx_excessive_collisions), 789 GBE_STATSB_INFO(tx_late_collisions), 790 GBE_STATSB_INFO(tx_underrun), 791 GBE_STATSB_INFO(tx_carrier_sense_errors), 792 GBE_STATSB_INFO(tx_bytes), 793 GBE_STATSB_INFO(tx_64byte_frames), 794 GBE_STATSB_INFO(tx_65_to_127byte_frames), 795 GBE_STATSB_INFO(tx_128_to_255byte_frames), 796 GBE_STATSB_INFO(tx_256_to_511byte_frames), 797 GBE_STATSB_INFO(tx_512_to_1023byte_frames), 798 GBE_STATSB_INFO(tx_1024byte_frames), 799 GBE_STATSB_INFO(net_bytes), 800 GBE_STATSB_INFO(rx_sof_overruns), 801 GBE_STATSB_INFO(rx_mof_overruns), 802 GBE_STATSB_INFO(rx_dma_overruns), 803 /* GBE module C */ 804 GBE_STATSC_INFO(rx_good_frames), 805 GBE_STATSC_INFO(rx_broadcast_frames), 806 GBE_STATSC_INFO(rx_multicast_frames), 807 GBE_STATSC_INFO(rx_pause_frames), 808 GBE_STATSC_INFO(rx_crc_errors), 809 GBE_STATSC_INFO(rx_align_code_errors), 810 GBE_STATSC_INFO(rx_oversized_frames), 811 GBE_STATSC_INFO(rx_jabber_frames), 812 GBE_STATSC_INFO(rx_undersized_frames), 813 GBE_STATSC_INFO(rx_fragments), 814 GBE_STATSC_INFO(rx_bytes), 815 GBE_STATSC_INFO(tx_good_frames), 816 GBE_STATSC_INFO(tx_broadcast_frames), 817 GBE_STATSC_INFO(tx_multicast_frames), 818 GBE_STATSC_INFO(tx_pause_frames), 819 GBE_STATSC_INFO(tx_deferred_frames), 820 GBE_STATSC_INFO(tx_collision_frames), 821 GBE_STATSC_INFO(tx_single_coll_frames), 822 GBE_STATSC_INFO(tx_mult_coll_frames), 823 GBE_STATSC_INFO(tx_excessive_collisions), 824 GBE_STATSC_INFO(tx_late_collisions), 825 GBE_STATSC_INFO(tx_underrun), 826 GBE_STATSC_INFO(tx_carrier_sense_errors), 827 GBE_STATSC_INFO(tx_bytes), 828 GBE_STATSC_INFO(tx_64byte_frames), 829 GBE_STATSC_INFO(tx_65_to_127byte_frames), 830 GBE_STATSC_INFO(tx_128_to_255byte_frames), 831 GBE_STATSC_INFO(tx_256_to_511byte_frames), 832 GBE_STATSC_INFO(tx_512_to_1023byte_frames), 833 GBE_STATSC_INFO(tx_1024byte_frames), 834 GBE_STATSC_INFO(net_bytes), 835 GBE_STATSC_INFO(rx_sof_overruns), 836 GBE_STATSC_INFO(rx_mof_overruns), 837 GBE_STATSC_INFO(rx_dma_overruns), 838 /* GBE module D */ 839 GBE_STATSD_INFO(rx_good_frames), 840 GBE_STATSD_INFO(rx_broadcast_frames), 841 GBE_STATSD_INFO(rx_multicast_frames), 842 GBE_STATSD_INFO(rx_pause_frames), 843 GBE_STATSD_INFO(rx_crc_errors), 844 GBE_STATSD_INFO(rx_align_code_errors), 845 GBE_STATSD_INFO(rx_oversized_frames), 846 GBE_STATSD_INFO(rx_jabber_frames), 847 GBE_STATSD_INFO(rx_undersized_frames), 848 GBE_STATSD_INFO(rx_fragments), 849 GBE_STATSD_INFO(rx_bytes), 850 GBE_STATSD_INFO(tx_good_frames), 851 GBE_STATSD_INFO(tx_broadcast_frames), 852 GBE_STATSD_INFO(tx_multicast_frames), 853 GBE_STATSD_INFO(tx_pause_frames), 854 GBE_STATSD_INFO(tx_deferred_frames), 855 GBE_STATSD_INFO(tx_collision_frames), 856 GBE_STATSD_INFO(tx_single_coll_frames), 857 GBE_STATSD_INFO(tx_mult_coll_frames), 858 GBE_STATSD_INFO(tx_excessive_collisions), 859 GBE_STATSD_INFO(tx_late_collisions), 860 GBE_STATSD_INFO(tx_underrun), 861 GBE_STATSD_INFO(tx_carrier_sense_errors), 862 GBE_STATSD_INFO(tx_bytes), 863 GBE_STATSD_INFO(tx_64byte_frames), 864 GBE_STATSD_INFO(tx_65_to_127byte_frames), 865 GBE_STATSD_INFO(tx_128_to_255byte_frames), 866 GBE_STATSD_INFO(tx_256_to_511byte_frames), 867 GBE_STATSD_INFO(tx_512_to_1023byte_frames), 868 GBE_STATSD_INFO(tx_1024byte_frames), 869 GBE_STATSD_INFO(net_bytes), 870 GBE_STATSD_INFO(rx_sof_overruns), 871 GBE_STATSD_INFO(rx_mof_overruns), 872 GBE_STATSD_INFO(rx_dma_overruns), 873 }; 874 875 /* This is the size of entries in GBENU_STATS_HOST */ 876 #define GBENU_ET_STATS_HOST_SIZE 52 877 878 #define GBENU_STATS_HOST(field) \ 879 { \ 880 "GBE_HOST:"#field, GBENU_STATS0_MODULE, \ 881 FIELD_SIZEOF(struct gbenu_hw_stats, field), \ 882 offsetof(struct gbenu_hw_stats, field) \ 883 } 884 885 /* This is the size of entries in GBENU_STATS_PORT */ 886 #define GBENU_ET_STATS_PORT_SIZE 65 887 888 #define GBENU_STATS_P1(field) \ 889 { \ 890 "GBE_P1:"#field, GBENU_STATS1_MODULE, \ 891 FIELD_SIZEOF(struct gbenu_hw_stats, field), \ 892 offsetof(struct gbenu_hw_stats, field) \ 893 } 894 895 #define GBENU_STATS_P2(field) \ 896 { \ 897 "GBE_P2:"#field, GBENU_STATS2_MODULE, \ 898 FIELD_SIZEOF(struct gbenu_hw_stats, field), \ 899 offsetof(struct gbenu_hw_stats, field) \ 900 } 901 902 #define GBENU_STATS_P3(field) \ 903 { \ 904 "GBE_P3:"#field, GBENU_STATS3_MODULE, \ 905 FIELD_SIZEOF(struct gbenu_hw_stats, field), \ 906 offsetof(struct gbenu_hw_stats, field) \ 907 } 908 909 #define GBENU_STATS_P4(field) \ 910 { \ 911 "GBE_P4:"#field, GBENU_STATS4_MODULE, \ 912 FIELD_SIZEOF(struct gbenu_hw_stats, field), \ 913 offsetof(struct gbenu_hw_stats, field) \ 914 } 915 916 #define GBENU_STATS_P5(field) \ 917 { \ 918 "GBE_P5:"#field, GBENU_STATS5_MODULE, \ 919 FIELD_SIZEOF(struct gbenu_hw_stats, field), \ 920 offsetof(struct gbenu_hw_stats, field) \ 921 } 922 923 #define GBENU_STATS_P6(field) \ 924 { \ 925 "GBE_P6:"#field, GBENU_STATS6_MODULE, \ 926 FIELD_SIZEOF(struct gbenu_hw_stats, field), \ 927 offsetof(struct gbenu_hw_stats, field) \ 928 } 929 930 #define GBENU_STATS_P7(field) \ 931 { \ 932 "GBE_P7:"#field, GBENU_STATS7_MODULE, \ 933 FIELD_SIZEOF(struct gbenu_hw_stats, field), \ 934 offsetof(struct gbenu_hw_stats, field) \ 935 } 936 937 #define GBENU_STATS_P8(field) \ 938 { \ 939 "GBE_P8:"#field, GBENU_STATS8_MODULE, \ 940 FIELD_SIZEOF(struct gbenu_hw_stats, field), \ 941 offsetof(struct gbenu_hw_stats, field) \ 942 } 943 944 static const struct netcp_ethtool_stat gbenu_et_stats[] = { 945 /* GBENU Host Module */ 946 GBENU_STATS_HOST(rx_good_frames), 947 GBENU_STATS_HOST(rx_broadcast_frames), 948 GBENU_STATS_HOST(rx_multicast_frames), 949 GBENU_STATS_HOST(rx_crc_errors), 950 GBENU_STATS_HOST(rx_oversized_frames), 951 GBENU_STATS_HOST(rx_undersized_frames), 952 GBENU_STATS_HOST(ale_drop), 953 GBENU_STATS_HOST(ale_overrun_drop), 954 GBENU_STATS_HOST(rx_bytes), 955 GBENU_STATS_HOST(tx_good_frames), 956 GBENU_STATS_HOST(tx_broadcast_frames), 957 GBENU_STATS_HOST(tx_multicast_frames), 958 GBENU_STATS_HOST(tx_bytes), 959 GBENU_STATS_HOST(tx_64B_frames), 960 GBENU_STATS_HOST(tx_65_to_127B_frames), 961 GBENU_STATS_HOST(tx_128_to_255B_frames), 962 GBENU_STATS_HOST(tx_256_to_511B_frames), 963 GBENU_STATS_HOST(tx_512_to_1023B_frames), 964 GBENU_STATS_HOST(tx_1024B_frames), 965 GBENU_STATS_HOST(net_bytes), 966 GBENU_STATS_HOST(rx_bottom_fifo_drop), 967 GBENU_STATS_HOST(rx_port_mask_drop), 968 GBENU_STATS_HOST(rx_top_fifo_drop), 969 GBENU_STATS_HOST(ale_rate_limit_drop), 970 GBENU_STATS_HOST(ale_vid_ingress_drop), 971 GBENU_STATS_HOST(ale_da_eq_sa_drop), 972 GBENU_STATS_HOST(ale_unknown_ucast), 973 GBENU_STATS_HOST(ale_unknown_ucast_bytes), 974 GBENU_STATS_HOST(ale_unknown_mcast), 975 GBENU_STATS_HOST(ale_unknown_mcast_bytes), 976 GBENU_STATS_HOST(ale_unknown_bcast), 977 GBENU_STATS_HOST(ale_unknown_bcast_bytes), 978 GBENU_STATS_HOST(ale_pol_match), 979 GBENU_STATS_HOST(ale_pol_match_red), 980 GBENU_STATS_HOST(ale_pol_match_yellow), 981 GBENU_STATS_HOST(tx_mem_protect_err), 982 GBENU_STATS_HOST(tx_pri0_drop), 983 GBENU_STATS_HOST(tx_pri1_drop), 984 GBENU_STATS_HOST(tx_pri2_drop), 985 GBENU_STATS_HOST(tx_pri3_drop), 986 GBENU_STATS_HOST(tx_pri4_drop), 987 GBENU_STATS_HOST(tx_pri5_drop), 988 GBENU_STATS_HOST(tx_pri6_drop), 989 GBENU_STATS_HOST(tx_pri7_drop), 990 GBENU_STATS_HOST(tx_pri0_drop_bcnt), 991 GBENU_STATS_HOST(tx_pri1_drop_bcnt), 992 GBENU_STATS_HOST(tx_pri2_drop_bcnt), 993 GBENU_STATS_HOST(tx_pri3_drop_bcnt), 994 GBENU_STATS_HOST(tx_pri4_drop_bcnt), 995 GBENU_STATS_HOST(tx_pri5_drop_bcnt), 996 GBENU_STATS_HOST(tx_pri6_drop_bcnt), 997 GBENU_STATS_HOST(tx_pri7_drop_bcnt), 998 /* GBENU Module 1 */ 999 GBENU_STATS_P1(rx_good_frames), 1000 GBENU_STATS_P1(rx_broadcast_frames), 1001 GBENU_STATS_P1(rx_multicast_frames), 1002 GBENU_STATS_P1(rx_pause_frames), 1003 GBENU_STATS_P1(rx_crc_errors), 1004 GBENU_STATS_P1(rx_align_code_errors), 1005 GBENU_STATS_P1(rx_oversized_frames), 1006 GBENU_STATS_P1(rx_jabber_frames), 1007 GBENU_STATS_P1(rx_undersized_frames), 1008 GBENU_STATS_P1(rx_fragments), 1009 GBENU_STATS_P1(ale_drop), 1010 GBENU_STATS_P1(ale_overrun_drop), 1011 GBENU_STATS_P1(rx_bytes), 1012 GBENU_STATS_P1(tx_good_frames), 1013 GBENU_STATS_P1(tx_broadcast_frames), 1014 GBENU_STATS_P1(tx_multicast_frames), 1015 GBENU_STATS_P1(tx_pause_frames), 1016 GBENU_STATS_P1(tx_deferred_frames), 1017 GBENU_STATS_P1(tx_collision_frames), 1018 GBENU_STATS_P1(tx_single_coll_frames), 1019 GBENU_STATS_P1(tx_mult_coll_frames), 1020 GBENU_STATS_P1(tx_excessive_collisions), 1021 GBENU_STATS_P1(tx_late_collisions), 1022 GBENU_STATS_P1(rx_ipg_error), 1023 GBENU_STATS_P1(tx_carrier_sense_errors), 1024 GBENU_STATS_P1(tx_bytes), 1025 GBENU_STATS_P1(tx_64B_frames), 1026 GBENU_STATS_P1(tx_65_to_127B_frames), 1027 GBENU_STATS_P1(tx_128_to_255B_frames), 1028 GBENU_STATS_P1(tx_256_to_511B_frames), 1029 GBENU_STATS_P1(tx_512_to_1023B_frames), 1030 GBENU_STATS_P1(tx_1024B_frames), 1031 GBENU_STATS_P1(net_bytes), 1032 GBENU_STATS_P1(rx_bottom_fifo_drop), 1033 GBENU_STATS_P1(rx_port_mask_drop), 1034 GBENU_STATS_P1(rx_top_fifo_drop), 1035 GBENU_STATS_P1(ale_rate_limit_drop), 1036 GBENU_STATS_P1(ale_vid_ingress_drop), 1037 GBENU_STATS_P1(ale_da_eq_sa_drop), 1038 GBENU_STATS_P1(ale_unknown_ucast), 1039 GBENU_STATS_P1(ale_unknown_ucast_bytes), 1040 GBENU_STATS_P1(ale_unknown_mcast), 1041 GBENU_STATS_P1(ale_unknown_mcast_bytes), 1042 GBENU_STATS_P1(ale_unknown_bcast), 1043 GBENU_STATS_P1(ale_unknown_bcast_bytes), 1044 GBENU_STATS_P1(ale_pol_match), 1045 GBENU_STATS_P1(ale_pol_match_red), 1046 GBENU_STATS_P1(ale_pol_match_yellow), 1047 GBENU_STATS_P1(tx_mem_protect_err), 1048 GBENU_STATS_P1(tx_pri0_drop), 1049 GBENU_STATS_P1(tx_pri1_drop), 1050 GBENU_STATS_P1(tx_pri2_drop), 1051 GBENU_STATS_P1(tx_pri3_drop), 1052 GBENU_STATS_P1(tx_pri4_drop), 1053 GBENU_STATS_P1(tx_pri5_drop), 1054 GBENU_STATS_P1(tx_pri6_drop), 1055 GBENU_STATS_P1(tx_pri7_drop), 1056 GBENU_STATS_P1(tx_pri0_drop_bcnt), 1057 GBENU_STATS_P1(tx_pri1_drop_bcnt), 1058 GBENU_STATS_P1(tx_pri2_drop_bcnt), 1059 GBENU_STATS_P1(tx_pri3_drop_bcnt), 1060 GBENU_STATS_P1(tx_pri4_drop_bcnt), 1061 GBENU_STATS_P1(tx_pri5_drop_bcnt), 1062 GBENU_STATS_P1(tx_pri6_drop_bcnt), 1063 GBENU_STATS_P1(tx_pri7_drop_bcnt), 1064 /* GBENU Module 2 */ 1065 GBENU_STATS_P2(rx_good_frames), 1066 GBENU_STATS_P2(rx_broadcast_frames), 1067 GBENU_STATS_P2(rx_multicast_frames), 1068 GBENU_STATS_P2(rx_pause_frames), 1069 GBENU_STATS_P2(rx_crc_errors), 1070 GBENU_STATS_P2(rx_align_code_errors), 1071 GBENU_STATS_P2(rx_oversized_frames), 1072 GBENU_STATS_P2(rx_jabber_frames), 1073 GBENU_STATS_P2(rx_undersized_frames), 1074 GBENU_STATS_P2(rx_fragments), 1075 GBENU_STATS_P2(ale_drop), 1076 GBENU_STATS_P2(ale_overrun_drop), 1077 GBENU_STATS_P2(rx_bytes), 1078 GBENU_STATS_P2(tx_good_frames), 1079 GBENU_STATS_P2(tx_broadcast_frames), 1080 GBENU_STATS_P2(tx_multicast_frames), 1081 GBENU_STATS_P2(tx_pause_frames), 1082 GBENU_STATS_P2(tx_deferred_frames), 1083 GBENU_STATS_P2(tx_collision_frames), 1084 GBENU_STATS_P2(tx_single_coll_frames), 1085 GBENU_STATS_P2(tx_mult_coll_frames), 1086 GBENU_STATS_P2(tx_excessive_collisions), 1087 GBENU_STATS_P2(tx_late_collisions), 1088 GBENU_STATS_P2(rx_ipg_error), 1089 GBENU_STATS_P2(tx_carrier_sense_errors), 1090 GBENU_STATS_P2(tx_bytes), 1091 GBENU_STATS_P2(tx_64B_frames), 1092 GBENU_STATS_P2(tx_65_to_127B_frames), 1093 GBENU_STATS_P2(tx_128_to_255B_frames), 1094 GBENU_STATS_P2(tx_256_to_511B_frames), 1095 GBENU_STATS_P2(tx_512_to_1023B_frames), 1096 GBENU_STATS_P2(tx_1024B_frames), 1097 GBENU_STATS_P2(net_bytes), 1098 GBENU_STATS_P2(rx_bottom_fifo_drop), 1099 GBENU_STATS_P2(rx_port_mask_drop), 1100 GBENU_STATS_P2(rx_top_fifo_drop), 1101 GBENU_STATS_P2(ale_rate_limit_drop), 1102 GBENU_STATS_P2(ale_vid_ingress_drop), 1103 GBENU_STATS_P2(ale_da_eq_sa_drop), 1104 GBENU_STATS_P2(ale_unknown_ucast), 1105 GBENU_STATS_P2(ale_unknown_ucast_bytes), 1106 GBENU_STATS_P2(ale_unknown_mcast), 1107 GBENU_STATS_P2(ale_unknown_mcast_bytes), 1108 GBENU_STATS_P2(ale_unknown_bcast), 1109 GBENU_STATS_P2(ale_unknown_bcast_bytes), 1110 GBENU_STATS_P2(ale_pol_match), 1111 GBENU_STATS_P2(ale_pol_match_red), 1112 GBENU_STATS_P2(ale_pol_match_yellow), 1113 GBENU_STATS_P2(tx_mem_protect_err), 1114 GBENU_STATS_P2(tx_pri0_drop), 1115 GBENU_STATS_P2(tx_pri1_drop), 1116 GBENU_STATS_P2(tx_pri2_drop), 1117 GBENU_STATS_P2(tx_pri3_drop), 1118 GBENU_STATS_P2(tx_pri4_drop), 1119 GBENU_STATS_P2(tx_pri5_drop), 1120 GBENU_STATS_P2(tx_pri6_drop), 1121 GBENU_STATS_P2(tx_pri7_drop), 1122 GBENU_STATS_P2(tx_pri0_drop_bcnt), 1123 GBENU_STATS_P2(tx_pri1_drop_bcnt), 1124 GBENU_STATS_P2(tx_pri2_drop_bcnt), 1125 GBENU_STATS_P2(tx_pri3_drop_bcnt), 1126 GBENU_STATS_P2(tx_pri4_drop_bcnt), 1127 GBENU_STATS_P2(tx_pri5_drop_bcnt), 1128 GBENU_STATS_P2(tx_pri6_drop_bcnt), 1129 GBENU_STATS_P2(tx_pri7_drop_bcnt), 1130 /* GBENU Module 3 */ 1131 GBENU_STATS_P3(rx_good_frames), 1132 GBENU_STATS_P3(rx_broadcast_frames), 1133 GBENU_STATS_P3(rx_multicast_frames), 1134 GBENU_STATS_P3(rx_pause_frames), 1135 GBENU_STATS_P3(rx_crc_errors), 1136 GBENU_STATS_P3(rx_align_code_errors), 1137 GBENU_STATS_P3(rx_oversized_frames), 1138 GBENU_STATS_P3(rx_jabber_frames), 1139 GBENU_STATS_P3(rx_undersized_frames), 1140 GBENU_STATS_P3(rx_fragments), 1141 GBENU_STATS_P3(ale_drop), 1142 GBENU_STATS_P3(ale_overrun_drop), 1143 GBENU_STATS_P3(rx_bytes), 1144 GBENU_STATS_P3(tx_good_frames), 1145 GBENU_STATS_P3(tx_broadcast_frames), 1146 GBENU_STATS_P3(tx_multicast_frames), 1147 GBENU_STATS_P3(tx_pause_frames), 1148 GBENU_STATS_P3(tx_deferred_frames), 1149 GBENU_STATS_P3(tx_collision_frames), 1150 GBENU_STATS_P3(tx_single_coll_frames), 1151 GBENU_STATS_P3(tx_mult_coll_frames), 1152 GBENU_STATS_P3(tx_excessive_collisions), 1153 GBENU_STATS_P3(tx_late_collisions), 1154 GBENU_STATS_P3(rx_ipg_error), 1155 GBENU_STATS_P3(tx_carrier_sense_errors), 1156 GBENU_STATS_P3(tx_bytes), 1157 GBENU_STATS_P3(tx_64B_frames), 1158 GBENU_STATS_P3(tx_65_to_127B_frames), 1159 GBENU_STATS_P3(tx_128_to_255B_frames), 1160 GBENU_STATS_P3(tx_256_to_511B_frames), 1161 GBENU_STATS_P3(tx_512_to_1023B_frames), 1162 GBENU_STATS_P3(tx_1024B_frames), 1163 GBENU_STATS_P3(net_bytes), 1164 GBENU_STATS_P3(rx_bottom_fifo_drop), 1165 GBENU_STATS_P3(rx_port_mask_drop), 1166 GBENU_STATS_P3(rx_top_fifo_drop), 1167 GBENU_STATS_P3(ale_rate_limit_drop), 1168 GBENU_STATS_P3(ale_vid_ingress_drop), 1169 GBENU_STATS_P3(ale_da_eq_sa_drop), 1170 GBENU_STATS_P3(ale_unknown_ucast), 1171 GBENU_STATS_P3(ale_unknown_ucast_bytes), 1172 GBENU_STATS_P3(ale_unknown_mcast), 1173 GBENU_STATS_P3(ale_unknown_mcast_bytes), 1174 GBENU_STATS_P3(ale_unknown_bcast), 1175 GBENU_STATS_P3(ale_unknown_bcast_bytes), 1176 GBENU_STATS_P3(ale_pol_match), 1177 GBENU_STATS_P3(ale_pol_match_red), 1178 GBENU_STATS_P3(ale_pol_match_yellow), 1179 GBENU_STATS_P3(tx_mem_protect_err), 1180 GBENU_STATS_P3(tx_pri0_drop), 1181 GBENU_STATS_P3(tx_pri1_drop), 1182 GBENU_STATS_P3(tx_pri2_drop), 1183 GBENU_STATS_P3(tx_pri3_drop), 1184 GBENU_STATS_P3(tx_pri4_drop), 1185 GBENU_STATS_P3(tx_pri5_drop), 1186 GBENU_STATS_P3(tx_pri6_drop), 1187 GBENU_STATS_P3(tx_pri7_drop), 1188 GBENU_STATS_P3(tx_pri0_drop_bcnt), 1189 GBENU_STATS_P3(tx_pri1_drop_bcnt), 1190 GBENU_STATS_P3(tx_pri2_drop_bcnt), 1191 GBENU_STATS_P3(tx_pri3_drop_bcnt), 1192 GBENU_STATS_P3(tx_pri4_drop_bcnt), 1193 GBENU_STATS_P3(tx_pri5_drop_bcnt), 1194 GBENU_STATS_P3(tx_pri6_drop_bcnt), 1195 GBENU_STATS_P3(tx_pri7_drop_bcnt), 1196 /* GBENU Module 4 */ 1197 GBENU_STATS_P4(rx_good_frames), 1198 GBENU_STATS_P4(rx_broadcast_frames), 1199 GBENU_STATS_P4(rx_multicast_frames), 1200 GBENU_STATS_P4(rx_pause_frames), 1201 GBENU_STATS_P4(rx_crc_errors), 1202 GBENU_STATS_P4(rx_align_code_errors), 1203 GBENU_STATS_P4(rx_oversized_frames), 1204 GBENU_STATS_P4(rx_jabber_frames), 1205 GBENU_STATS_P4(rx_undersized_frames), 1206 GBENU_STATS_P4(rx_fragments), 1207 GBENU_STATS_P4(ale_drop), 1208 GBENU_STATS_P4(ale_overrun_drop), 1209 GBENU_STATS_P4(rx_bytes), 1210 GBENU_STATS_P4(tx_good_frames), 1211 GBENU_STATS_P4(tx_broadcast_frames), 1212 GBENU_STATS_P4(tx_multicast_frames), 1213 GBENU_STATS_P4(tx_pause_frames), 1214 GBENU_STATS_P4(tx_deferred_frames), 1215 GBENU_STATS_P4(tx_collision_frames), 1216 GBENU_STATS_P4(tx_single_coll_frames), 1217 GBENU_STATS_P4(tx_mult_coll_frames), 1218 GBENU_STATS_P4(tx_excessive_collisions), 1219 GBENU_STATS_P4(tx_late_collisions), 1220 GBENU_STATS_P4(rx_ipg_error), 1221 GBENU_STATS_P4(tx_carrier_sense_errors), 1222 GBENU_STATS_P4(tx_bytes), 1223 GBENU_STATS_P4(tx_64B_frames), 1224 GBENU_STATS_P4(tx_65_to_127B_frames), 1225 GBENU_STATS_P4(tx_128_to_255B_frames), 1226 GBENU_STATS_P4(tx_256_to_511B_frames), 1227 GBENU_STATS_P4(tx_512_to_1023B_frames), 1228 GBENU_STATS_P4(tx_1024B_frames), 1229 GBENU_STATS_P4(net_bytes), 1230 GBENU_STATS_P4(rx_bottom_fifo_drop), 1231 GBENU_STATS_P4(rx_port_mask_drop), 1232 GBENU_STATS_P4(rx_top_fifo_drop), 1233 GBENU_STATS_P4(ale_rate_limit_drop), 1234 GBENU_STATS_P4(ale_vid_ingress_drop), 1235 GBENU_STATS_P4(ale_da_eq_sa_drop), 1236 GBENU_STATS_P4(ale_unknown_ucast), 1237 GBENU_STATS_P4(ale_unknown_ucast_bytes), 1238 GBENU_STATS_P4(ale_unknown_mcast), 1239 GBENU_STATS_P4(ale_unknown_mcast_bytes), 1240 GBENU_STATS_P4(ale_unknown_bcast), 1241 GBENU_STATS_P4(ale_unknown_bcast_bytes), 1242 GBENU_STATS_P4(ale_pol_match), 1243 GBENU_STATS_P4(ale_pol_match_red), 1244 GBENU_STATS_P4(ale_pol_match_yellow), 1245 GBENU_STATS_P4(tx_mem_protect_err), 1246 GBENU_STATS_P4(tx_pri0_drop), 1247 GBENU_STATS_P4(tx_pri1_drop), 1248 GBENU_STATS_P4(tx_pri2_drop), 1249 GBENU_STATS_P4(tx_pri3_drop), 1250 GBENU_STATS_P4(tx_pri4_drop), 1251 GBENU_STATS_P4(tx_pri5_drop), 1252 GBENU_STATS_P4(tx_pri6_drop), 1253 GBENU_STATS_P4(tx_pri7_drop), 1254 GBENU_STATS_P4(tx_pri0_drop_bcnt), 1255 GBENU_STATS_P4(tx_pri1_drop_bcnt), 1256 GBENU_STATS_P4(tx_pri2_drop_bcnt), 1257 GBENU_STATS_P4(tx_pri3_drop_bcnt), 1258 GBENU_STATS_P4(tx_pri4_drop_bcnt), 1259 GBENU_STATS_P4(tx_pri5_drop_bcnt), 1260 GBENU_STATS_P4(tx_pri6_drop_bcnt), 1261 GBENU_STATS_P4(tx_pri7_drop_bcnt), 1262 /* GBENU Module 5 */ 1263 GBENU_STATS_P5(rx_good_frames), 1264 GBENU_STATS_P5(rx_broadcast_frames), 1265 GBENU_STATS_P5(rx_multicast_frames), 1266 GBENU_STATS_P5(rx_pause_frames), 1267 GBENU_STATS_P5(rx_crc_errors), 1268 GBENU_STATS_P5(rx_align_code_errors), 1269 GBENU_STATS_P5(rx_oversized_frames), 1270 GBENU_STATS_P5(rx_jabber_frames), 1271 GBENU_STATS_P5(rx_undersized_frames), 1272 GBENU_STATS_P5(rx_fragments), 1273 GBENU_STATS_P5(ale_drop), 1274 GBENU_STATS_P5(ale_overrun_drop), 1275 GBENU_STATS_P5(rx_bytes), 1276 GBENU_STATS_P5(tx_good_frames), 1277 GBENU_STATS_P5(tx_broadcast_frames), 1278 GBENU_STATS_P5(tx_multicast_frames), 1279 GBENU_STATS_P5(tx_pause_frames), 1280 GBENU_STATS_P5(tx_deferred_frames), 1281 GBENU_STATS_P5(tx_collision_frames), 1282 GBENU_STATS_P5(tx_single_coll_frames), 1283 GBENU_STATS_P5(tx_mult_coll_frames), 1284 GBENU_STATS_P5(tx_excessive_collisions), 1285 GBENU_STATS_P5(tx_late_collisions), 1286 GBENU_STATS_P5(rx_ipg_error), 1287 GBENU_STATS_P5(tx_carrier_sense_errors), 1288 GBENU_STATS_P5(tx_bytes), 1289 GBENU_STATS_P5(tx_64B_frames), 1290 GBENU_STATS_P5(tx_65_to_127B_frames), 1291 GBENU_STATS_P5(tx_128_to_255B_frames), 1292 GBENU_STATS_P5(tx_256_to_511B_frames), 1293 GBENU_STATS_P5(tx_512_to_1023B_frames), 1294 GBENU_STATS_P5(tx_1024B_frames), 1295 GBENU_STATS_P5(net_bytes), 1296 GBENU_STATS_P5(rx_bottom_fifo_drop), 1297 GBENU_STATS_P5(rx_port_mask_drop), 1298 GBENU_STATS_P5(rx_top_fifo_drop), 1299 GBENU_STATS_P5(ale_rate_limit_drop), 1300 GBENU_STATS_P5(ale_vid_ingress_drop), 1301 GBENU_STATS_P5(ale_da_eq_sa_drop), 1302 GBENU_STATS_P5(ale_unknown_ucast), 1303 GBENU_STATS_P5(ale_unknown_ucast_bytes), 1304 GBENU_STATS_P5(ale_unknown_mcast), 1305 GBENU_STATS_P5(ale_unknown_mcast_bytes), 1306 GBENU_STATS_P5(ale_unknown_bcast), 1307 GBENU_STATS_P5(ale_unknown_bcast_bytes), 1308 GBENU_STATS_P5(ale_pol_match), 1309 GBENU_STATS_P5(ale_pol_match_red), 1310 GBENU_STATS_P5(ale_pol_match_yellow), 1311 GBENU_STATS_P5(tx_mem_protect_err), 1312 GBENU_STATS_P5(tx_pri0_drop), 1313 GBENU_STATS_P5(tx_pri1_drop), 1314 GBENU_STATS_P5(tx_pri2_drop), 1315 GBENU_STATS_P5(tx_pri3_drop), 1316 GBENU_STATS_P5(tx_pri4_drop), 1317 GBENU_STATS_P5(tx_pri5_drop), 1318 GBENU_STATS_P5(tx_pri6_drop), 1319 GBENU_STATS_P5(tx_pri7_drop), 1320 GBENU_STATS_P5(tx_pri0_drop_bcnt), 1321 GBENU_STATS_P5(tx_pri1_drop_bcnt), 1322 GBENU_STATS_P5(tx_pri2_drop_bcnt), 1323 GBENU_STATS_P5(tx_pri3_drop_bcnt), 1324 GBENU_STATS_P5(tx_pri4_drop_bcnt), 1325 GBENU_STATS_P5(tx_pri5_drop_bcnt), 1326 GBENU_STATS_P5(tx_pri6_drop_bcnt), 1327 GBENU_STATS_P5(tx_pri7_drop_bcnt), 1328 /* GBENU Module 6 */ 1329 GBENU_STATS_P6(rx_good_frames), 1330 GBENU_STATS_P6(rx_broadcast_frames), 1331 GBENU_STATS_P6(rx_multicast_frames), 1332 GBENU_STATS_P6(rx_pause_frames), 1333 GBENU_STATS_P6(rx_crc_errors), 1334 GBENU_STATS_P6(rx_align_code_errors), 1335 GBENU_STATS_P6(rx_oversized_frames), 1336 GBENU_STATS_P6(rx_jabber_frames), 1337 GBENU_STATS_P6(rx_undersized_frames), 1338 GBENU_STATS_P6(rx_fragments), 1339 GBENU_STATS_P6(ale_drop), 1340 GBENU_STATS_P6(ale_overrun_drop), 1341 GBENU_STATS_P6(rx_bytes), 1342 GBENU_STATS_P6(tx_good_frames), 1343 GBENU_STATS_P6(tx_broadcast_frames), 1344 GBENU_STATS_P6(tx_multicast_frames), 1345 GBENU_STATS_P6(tx_pause_frames), 1346 GBENU_STATS_P6(tx_deferred_frames), 1347 GBENU_STATS_P6(tx_collision_frames), 1348 GBENU_STATS_P6(tx_single_coll_frames), 1349 GBENU_STATS_P6(tx_mult_coll_frames), 1350 GBENU_STATS_P6(tx_excessive_collisions), 1351 GBENU_STATS_P6(tx_late_collisions), 1352 GBENU_STATS_P6(rx_ipg_error), 1353 GBENU_STATS_P6(tx_carrier_sense_errors), 1354 GBENU_STATS_P6(tx_bytes), 1355 GBENU_STATS_P6(tx_64B_frames), 1356 GBENU_STATS_P6(tx_65_to_127B_frames), 1357 GBENU_STATS_P6(tx_128_to_255B_frames), 1358 GBENU_STATS_P6(tx_256_to_511B_frames), 1359 GBENU_STATS_P6(tx_512_to_1023B_frames), 1360 GBENU_STATS_P6(tx_1024B_frames), 1361 GBENU_STATS_P6(net_bytes), 1362 GBENU_STATS_P6(rx_bottom_fifo_drop), 1363 GBENU_STATS_P6(rx_port_mask_drop), 1364 GBENU_STATS_P6(rx_top_fifo_drop), 1365 GBENU_STATS_P6(ale_rate_limit_drop), 1366 GBENU_STATS_P6(ale_vid_ingress_drop), 1367 GBENU_STATS_P6(ale_da_eq_sa_drop), 1368 GBENU_STATS_P6(ale_unknown_ucast), 1369 GBENU_STATS_P6(ale_unknown_ucast_bytes), 1370 GBENU_STATS_P6(ale_unknown_mcast), 1371 GBENU_STATS_P6(ale_unknown_mcast_bytes), 1372 GBENU_STATS_P6(ale_unknown_bcast), 1373 GBENU_STATS_P6(ale_unknown_bcast_bytes), 1374 GBENU_STATS_P6(ale_pol_match), 1375 GBENU_STATS_P6(ale_pol_match_red), 1376 GBENU_STATS_P6(ale_pol_match_yellow), 1377 GBENU_STATS_P6(tx_mem_protect_err), 1378 GBENU_STATS_P6(tx_pri0_drop), 1379 GBENU_STATS_P6(tx_pri1_drop), 1380 GBENU_STATS_P6(tx_pri2_drop), 1381 GBENU_STATS_P6(tx_pri3_drop), 1382 GBENU_STATS_P6(tx_pri4_drop), 1383 GBENU_STATS_P6(tx_pri5_drop), 1384 GBENU_STATS_P6(tx_pri6_drop), 1385 GBENU_STATS_P6(tx_pri7_drop), 1386 GBENU_STATS_P6(tx_pri0_drop_bcnt), 1387 GBENU_STATS_P6(tx_pri1_drop_bcnt), 1388 GBENU_STATS_P6(tx_pri2_drop_bcnt), 1389 GBENU_STATS_P6(tx_pri3_drop_bcnt), 1390 GBENU_STATS_P6(tx_pri4_drop_bcnt), 1391 GBENU_STATS_P6(tx_pri5_drop_bcnt), 1392 GBENU_STATS_P6(tx_pri6_drop_bcnt), 1393 GBENU_STATS_P6(tx_pri7_drop_bcnt), 1394 /* GBENU Module 7 */ 1395 GBENU_STATS_P7(rx_good_frames), 1396 GBENU_STATS_P7(rx_broadcast_frames), 1397 GBENU_STATS_P7(rx_multicast_frames), 1398 GBENU_STATS_P7(rx_pause_frames), 1399 GBENU_STATS_P7(rx_crc_errors), 1400 GBENU_STATS_P7(rx_align_code_errors), 1401 GBENU_STATS_P7(rx_oversized_frames), 1402 GBENU_STATS_P7(rx_jabber_frames), 1403 GBENU_STATS_P7(rx_undersized_frames), 1404 GBENU_STATS_P7(rx_fragments), 1405 GBENU_STATS_P7(ale_drop), 1406 GBENU_STATS_P7(ale_overrun_drop), 1407 GBENU_STATS_P7(rx_bytes), 1408 GBENU_STATS_P7(tx_good_frames), 1409 GBENU_STATS_P7(tx_broadcast_frames), 1410 GBENU_STATS_P7(tx_multicast_frames), 1411 GBENU_STATS_P7(tx_pause_frames), 1412 GBENU_STATS_P7(tx_deferred_frames), 1413 GBENU_STATS_P7(tx_collision_frames), 1414 GBENU_STATS_P7(tx_single_coll_frames), 1415 GBENU_STATS_P7(tx_mult_coll_frames), 1416 GBENU_STATS_P7(tx_excessive_collisions), 1417 GBENU_STATS_P7(tx_late_collisions), 1418 GBENU_STATS_P7(rx_ipg_error), 1419 GBENU_STATS_P7(tx_carrier_sense_errors), 1420 GBENU_STATS_P7(tx_bytes), 1421 GBENU_STATS_P7(tx_64B_frames), 1422 GBENU_STATS_P7(tx_65_to_127B_frames), 1423 GBENU_STATS_P7(tx_128_to_255B_frames), 1424 GBENU_STATS_P7(tx_256_to_511B_frames), 1425 GBENU_STATS_P7(tx_512_to_1023B_frames), 1426 GBENU_STATS_P7(tx_1024B_frames), 1427 GBENU_STATS_P7(net_bytes), 1428 GBENU_STATS_P7(rx_bottom_fifo_drop), 1429 GBENU_STATS_P7(rx_port_mask_drop), 1430 GBENU_STATS_P7(rx_top_fifo_drop), 1431 GBENU_STATS_P7(ale_rate_limit_drop), 1432 GBENU_STATS_P7(ale_vid_ingress_drop), 1433 GBENU_STATS_P7(ale_da_eq_sa_drop), 1434 GBENU_STATS_P7(ale_unknown_ucast), 1435 GBENU_STATS_P7(ale_unknown_ucast_bytes), 1436 GBENU_STATS_P7(ale_unknown_mcast), 1437 GBENU_STATS_P7(ale_unknown_mcast_bytes), 1438 GBENU_STATS_P7(ale_unknown_bcast), 1439 GBENU_STATS_P7(ale_unknown_bcast_bytes), 1440 GBENU_STATS_P7(ale_pol_match), 1441 GBENU_STATS_P7(ale_pol_match_red), 1442 GBENU_STATS_P7(ale_pol_match_yellow), 1443 GBENU_STATS_P7(tx_mem_protect_err), 1444 GBENU_STATS_P7(tx_pri0_drop), 1445 GBENU_STATS_P7(tx_pri1_drop), 1446 GBENU_STATS_P7(tx_pri2_drop), 1447 GBENU_STATS_P7(tx_pri3_drop), 1448 GBENU_STATS_P7(tx_pri4_drop), 1449 GBENU_STATS_P7(tx_pri5_drop), 1450 GBENU_STATS_P7(tx_pri6_drop), 1451 GBENU_STATS_P7(tx_pri7_drop), 1452 GBENU_STATS_P7(tx_pri0_drop_bcnt), 1453 GBENU_STATS_P7(tx_pri1_drop_bcnt), 1454 GBENU_STATS_P7(tx_pri2_drop_bcnt), 1455 GBENU_STATS_P7(tx_pri3_drop_bcnt), 1456 GBENU_STATS_P7(tx_pri4_drop_bcnt), 1457 GBENU_STATS_P7(tx_pri5_drop_bcnt), 1458 GBENU_STATS_P7(tx_pri6_drop_bcnt), 1459 GBENU_STATS_P7(tx_pri7_drop_bcnt), 1460 /* GBENU Module 8 */ 1461 GBENU_STATS_P8(rx_good_frames), 1462 GBENU_STATS_P8(rx_broadcast_frames), 1463 GBENU_STATS_P8(rx_multicast_frames), 1464 GBENU_STATS_P8(rx_pause_frames), 1465 GBENU_STATS_P8(rx_crc_errors), 1466 GBENU_STATS_P8(rx_align_code_errors), 1467 GBENU_STATS_P8(rx_oversized_frames), 1468 GBENU_STATS_P8(rx_jabber_frames), 1469 GBENU_STATS_P8(rx_undersized_frames), 1470 GBENU_STATS_P8(rx_fragments), 1471 GBENU_STATS_P8(ale_drop), 1472 GBENU_STATS_P8(ale_overrun_drop), 1473 GBENU_STATS_P8(rx_bytes), 1474 GBENU_STATS_P8(tx_good_frames), 1475 GBENU_STATS_P8(tx_broadcast_frames), 1476 GBENU_STATS_P8(tx_multicast_frames), 1477 GBENU_STATS_P8(tx_pause_frames), 1478 GBENU_STATS_P8(tx_deferred_frames), 1479 GBENU_STATS_P8(tx_collision_frames), 1480 GBENU_STATS_P8(tx_single_coll_frames), 1481 GBENU_STATS_P8(tx_mult_coll_frames), 1482 GBENU_STATS_P8(tx_excessive_collisions), 1483 GBENU_STATS_P8(tx_late_collisions), 1484 GBENU_STATS_P8(rx_ipg_error), 1485 GBENU_STATS_P8(tx_carrier_sense_errors), 1486 GBENU_STATS_P8(tx_bytes), 1487 GBENU_STATS_P8(tx_64B_frames), 1488 GBENU_STATS_P8(tx_65_to_127B_frames), 1489 GBENU_STATS_P8(tx_128_to_255B_frames), 1490 GBENU_STATS_P8(tx_256_to_511B_frames), 1491 GBENU_STATS_P8(tx_512_to_1023B_frames), 1492 GBENU_STATS_P8(tx_1024B_frames), 1493 GBENU_STATS_P8(net_bytes), 1494 GBENU_STATS_P8(rx_bottom_fifo_drop), 1495 GBENU_STATS_P8(rx_port_mask_drop), 1496 GBENU_STATS_P8(rx_top_fifo_drop), 1497 GBENU_STATS_P8(ale_rate_limit_drop), 1498 GBENU_STATS_P8(ale_vid_ingress_drop), 1499 GBENU_STATS_P8(ale_da_eq_sa_drop), 1500 GBENU_STATS_P8(ale_unknown_ucast), 1501 GBENU_STATS_P8(ale_unknown_ucast_bytes), 1502 GBENU_STATS_P8(ale_unknown_mcast), 1503 GBENU_STATS_P8(ale_unknown_mcast_bytes), 1504 GBENU_STATS_P8(ale_unknown_bcast), 1505 GBENU_STATS_P8(ale_unknown_bcast_bytes), 1506 GBENU_STATS_P8(ale_pol_match), 1507 GBENU_STATS_P8(ale_pol_match_red), 1508 GBENU_STATS_P8(ale_pol_match_yellow), 1509 GBENU_STATS_P8(tx_mem_protect_err), 1510 GBENU_STATS_P8(tx_pri0_drop), 1511 GBENU_STATS_P8(tx_pri1_drop), 1512 GBENU_STATS_P8(tx_pri2_drop), 1513 GBENU_STATS_P8(tx_pri3_drop), 1514 GBENU_STATS_P8(tx_pri4_drop), 1515 GBENU_STATS_P8(tx_pri5_drop), 1516 GBENU_STATS_P8(tx_pri6_drop), 1517 GBENU_STATS_P8(tx_pri7_drop), 1518 GBENU_STATS_P8(tx_pri0_drop_bcnt), 1519 GBENU_STATS_P8(tx_pri1_drop_bcnt), 1520 GBENU_STATS_P8(tx_pri2_drop_bcnt), 1521 GBENU_STATS_P8(tx_pri3_drop_bcnt), 1522 GBENU_STATS_P8(tx_pri4_drop_bcnt), 1523 GBENU_STATS_P8(tx_pri5_drop_bcnt), 1524 GBENU_STATS_P8(tx_pri6_drop_bcnt), 1525 GBENU_STATS_P8(tx_pri7_drop_bcnt), 1526 }; 1527 1528 #define XGBE_STATS0_INFO(field) \ 1529 { \ 1530 "GBE_0:"#field, XGBE_STATS0_MODULE, \ 1531 FIELD_SIZEOF(struct xgbe_hw_stats, field), \ 1532 offsetof(struct xgbe_hw_stats, field) \ 1533 } 1534 1535 #define XGBE_STATS1_INFO(field) \ 1536 { \ 1537 "GBE_1:"#field, XGBE_STATS1_MODULE, \ 1538 FIELD_SIZEOF(struct xgbe_hw_stats, field), \ 1539 offsetof(struct xgbe_hw_stats, field) \ 1540 } 1541 1542 #define XGBE_STATS2_INFO(field) \ 1543 { \ 1544 "GBE_2:"#field, XGBE_STATS2_MODULE, \ 1545 FIELD_SIZEOF(struct xgbe_hw_stats, field), \ 1546 offsetof(struct xgbe_hw_stats, field) \ 1547 } 1548 1549 static const struct netcp_ethtool_stat xgbe10_et_stats[] = { 1550 /* GBE module 0 */ 1551 XGBE_STATS0_INFO(rx_good_frames), 1552 XGBE_STATS0_INFO(rx_broadcast_frames), 1553 XGBE_STATS0_INFO(rx_multicast_frames), 1554 XGBE_STATS0_INFO(rx_oversized_frames), 1555 XGBE_STATS0_INFO(rx_undersized_frames), 1556 XGBE_STATS0_INFO(overrun_type4), 1557 XGBE_STATS0_INFO(overrun_type5), 1558 XGBE_STATS0_INFO(rx_bytes), 1559 XGBE_STATS0_INFO(tx_good_frames), 1560 XGBE_STATS0_INFO(tx_broadcast_frames), 1561 XGBE_STATS0_INFO(tx_multicast_frames), 1562 XGBE_STATS0_INFO(tx_bytes), 1563 XGBE_STATS0_INFO(tx_64byte_frames), 1564 XGBE_STATS0_INFO(tx_65_to_127byte_frames), 1565 XGBE_STATS0_INFO(tx_128_to_255byte_frames), 1566 XGBE_STATS0_INFO(tx_256_to_511byte_frames), 1567 XGBE_STATS0_INFO(tx_512_to_1023byte_frames), 1568 XGBE_STATS0_INFO(tx_1024byte_frames), 1569 XGBE_STATS0_INFO(net_bytes), 1570 XGBE_STATS0_INFO(rx_sof_overruns), 1571 XGBE_STATS0_INFO(rx_mof_overruns), 1572 XGBE_STATS0_INFO(rx_dma_overruns), 1573 /* XGBE module 1 */ 1574 XGBE_STATS1_INFO(rx_good_frames), 1575 XGBE_STATS1_INFO(rx_broadcast_frames), 1576 XGBE_STATS1_INFO(rx_multicast_frames), 1577 XGBE_STATS1_INFO(rx_pause_frames), 1578 XGBE_STATS1_INFO(rx_crc_errors), 1579 XGBE_STATS1_INFO(rx_align_code_errors), 1580 XGBE_STATS1_INFO(rx_oversized_frames), 1581 XGBE_STATS1_INFO(rx_jabber_frames), 1582 XGBE_STATS1_INFO(rx_undersized_frames), 1583 XGBE_STATS1_INFO(rx_fragments), 1584 XGBE_STATS1_INFO(overrun_type4), 1585 XGBE_STATS1_INFO(overrun_type5), 1586 XGBE_STATS1_INFO(rx_bytes), 1587 XGBE_STATS1_INFO(tx_good_frames), 1588 XGBE_STATS1_INFO(tx_broadcast_frames), 1589 XGBE_STATS1_INFO(tx_multicast_frames), 1590 XGBE_STATS1_INFO(tx_pause_frames), 1591 XGBE_STATS1_INFO(tx_deferred_frames), 1592 XGBE_STATS1_INFO(tx_collision_frames), 1593 XGBE_STATS1_INFO(tx_single_coll_frames), 1594 XGBE_STATS1_INFO(tx_mult_coll_frames), 1595 XGBE_STATS1_INFO(tx_excessive_collisions), 1596 XGBE_STATS1_INFO(tx_late_collisions), 1597 XGBE_STATS1_INFO(tx_underrun), 1598 XGBE_STATS1_INFO(tx_carrier_sense_errors), 1599 XGBE_STATS1_INFO(tx_bytes), 1600 XGBE_STATS1_INFO(tx_64byte_frames), 1601 XGBE_STATS1_INFO(tx_65_to_127byte_frames), 1602 XGBE_STATS1_INFO(tx_128_to_255byte_frames), 1603 XGBE_STATS1_INFO(tx_256_to_511byte_frames), 1604 XGBE_STATS1_INFO(tx_512_to_1023byte_frames), 1605 XGBE_STATS1_INFO(tx_1024byte_frames), 1606 XGBE_STATS1_INFO(net_bytes), 1607 XGBE_STATS1_INFO(rx_sof_overruns), 1608 XGBE_STATS1_INFO(rx_mof_overruns), 1609 XGBE_STATS1_INFO(rx_dma_overruns), 1610 /* XGBE module 2 */ 1611 XGBE_STATS2_INFO(rx_good_frames), 1612 XGBE_STATS2_INFO(rx_broadcast_frames), 1613 XGBE_STATS2_INFO(rx_multicast_frames), 1614 XGBE_STATS2_INFO(rx_pause_frames), 1615 XGBE_STATS2_INFO(rx_crc_errors), 1616 XGBE_STATS2_INFO(rx_align_code_errors), 1617 XGBE_STATS2_INFO(rx_oversized_frames), 1618 XGBE_STATS2_INFO(rx_jabber_frames), 1619 XGBE_STATS2_INFO(rx_undersized_frames), 1620 XGBE_STATS2_INFO(rx_fragments), 1621 XGBE_STATS2_INFO(overrun_type4), 1622 XGBE_STATS2_INFO(overrun_type5), 1623 XGBE_STATS2_INFO(rx_bytes), 1624 XGBE_STATS2_INFO(tx_good_frames), 1625 XGBE_STATS2_INFO(tx_broadcast_frames), 1626 XGBE_STATS2_INFO(tx_multicast_frames), 1627 XGBE_STATS2_INFO(tx_pause_frames), 1628 XGBE_STATS2_INFO(tx_deferred_frames), 1629 XGBE_STATS2_INFO(tx_collision_frames), 1630 XGBE_STATS2_INFO(tx_single_coll_frames), 1631 XGBE_STATS2_INFO(tx_mult_coll_frames), 1632 XGBE_STATS2_INFO(tx_excessive_collisions), 1633 XGBE_STATS2_INFO(tx_late_collisions), 1634 XGBE_STATS2_INFO(tx_underrun), 1635 XGBE_STATS2_INFO(tx_carrier_sense_errors), 1636 XGBE_STATS2_INFO(tx_bytes), 1637 XGBE_STATS2_INFO(tx_64byte_frames), 1638 XGBE_STATS2_INFO(tx_65_to_127byte_frames), 1639 XGBE_STATS2_INFO(tx_128_to_255byte_frames), 1640 XGBE_STATS2_INFO(tx_256_to_511byte_frames), 1641 XGBE_STATS2_INFO(tx_512_to_1023byte_frames), 1642 XGBE_STATS2_INFO(tx_1024byte_frames), 1643 XGBE_STATS2_INFO(net_bytes), 1644 XGBE_STATS2_INFO(rx_sof_overruns), 1645 XGBE_STATS2_INFO(rx_mof_overruns), 1646 XGBE_STATS2_INFO(rx_dma_overruns), 1647 }; 1648 1649 #define for_each_intf(i, priv) \ 1650 list_for_each_entry((i), &(priv)->gbe_intf_head, gbe_intf_list) 1651 1652 #define for_each_sec_slave(slave, priv) \ 1653 list_for_each_entry((slave), &(priv)->secondary_slaves, slave_list) 1654 1655 #define first_sec_slave(priv) \ 1656 list_first_entry(&priv->secondary_slaves, \ 1657 struct gbe_slave, slave_list) 1658 1659 static void keystone_get_drvinfo(struct net_device *ndev, 1660 struct ethtool_drvinfo *info) 1661 { 1662 strncpy(info->driver, NETCP_DRIVER_NAME, sizeof(info->driver)); 1663 strncpy(info->version, NETCP_DRIVER_VERSION, sizeof(info->version)); 1664 } 1665 1666 static u32 keystone_get_msglevel(struct net_device *ndev) 1667 { 1668 struct netcp_intf *netcp = netdev_priv(ndev); 1669 1670 return netcp->msg_enable; 1671 } 1672 1673 static void keystone_set_msglevel(struct net_device *ndev, u32 value) 1674 { 1675 struct netcp_intf *netcp = netdev_priv(ndev); 1676 1677 netcp->msg_enable = value; 1678 } 1679 1680 static void keystone_get_stat_strings(struct net_device *ndev, 1681 uint32_t stringset, uint8_t *data) 1682 { 1683 struct netcp_intf *netcp = netdev_priv(ndev); 1684 struct gbe_intf *gbe_intf; 1685 struct gbe_priv *gbe_dev; 1686 int i; 1687 1688 gbe_intf = netcp_module_get_intf_data(&gbe_module, netcp); 1689 if (!gbe_intf) 1690 return; 1691 gbe_dev = gbe_intf->gbe_dev; 1692 1693 switch (stringset) { 1694 case ETH_SS_STATS: 1695 for (i = 0; i < gbe_dev->num_et_stats; i++) { 1696 memcpy(data, gbe_dev->et_stats[i].desc, 1697 ETH_GSTRING_LEN); 1698 data += ETH_GSTRING_LEN; 1699 } 1700 break; 1701 case ETH_SS_TEST: 1702 break; 1703 } 1704 } 1705 1706 static int keystone_get_sset_count(struct net_device *ndev, int stringset) 1707 { 1708 struct netcp_intf *netcp = netdev_priv(ndev); 1709 struct gbe_intf *gbe_intf; 1710 struct gbe_priv *gbe_dev; 1711 1712 gbe_intf = netcp_module_get_intf_data(&gbe_module, netcp); 1713 if (!gbe_intf) 1714 return -EINVAL; 1715 gbe_dev = gbe_intf->gbe_dev; 1716 1717 switch (stringset) { 1718 case ETH_SS_TEST: 1719 return 0; 1720 case ETH_SS_STATS: 1721 return gbe_dev->num_et_stats; 1722 default: 1723 return -EINVAL; 1724 } 1725 } 1726 1727 static void gbe_reset_mod_stats(struct gbe_priv *gbe_dev, int stats_mod) 1728 { 1729 void __iomem *base = gbe_dev->hw_stats_regs[stats_mod]; 1730 u32 __iomem *p_stats_entry; 1731 int i; 1732 1733 for (i = 0; i < gbe_dev->num_et_stats; i++) { 1734 if (gbe_dev->et_stats[i].type == stats_mod) { 1735 p_stats_entry = base + gbe_dev->et_stats[i].offset; 1736 gbe_dev->hw_stats[i] = 0; 1737 gbe_dev->hw_stats_prev[i] = readl(p_stats_entry); 1738 } 1739 } 1740 } 1741 1742 static inline void gbe_update_hw_stats_entry(struct gbe_priv *gbe_dev, 1743 int et_stats_entry) 1744 { 1745 void __iomem *base = NULL; 1746 u32 __iomem *p_stats_entry; 1747 u32 curr, delta; 1748 1749 /* The hw_stats_regs pointers are already 1750 * properly set to point to the right base: 1751 */ 1752 base = gbe_dev->hw_stats_regs[gbe_dev->et_stats[et_stats_entry].type]; 1753 p_stats_entry = base + gbe_dev->et_stats[et_stats_entry].offset; 1754 curr = readl(p_stats_entry); 1755 delta = curr - gbe_dev->hw_stats_prev[et_stats_entry]; 1756 gbe_dev->hw_stats_prev[et_stats_entry] = curr; 1757 gbe_dev->hw_stats[et_stats_entry] += delta; 1758 } 1759 1760 static void gbe_update_stats(struct gbe_priv *gbe_dev, uint64_t *data) 1761 { 1762 int i; 1763 1764 for (i = 0; i < gbe_dev->num_et_stats; i++) { 1765 gbe_update_hw_stats_entry(gbe_dev, i); 1766 1767 if (data) 1768 data[i] = gbe_dev->hw_stats[i]; 1769 } 1770 } 1771 1772 static inline void gbe_stats_mod_visible_ver14(struct gbe_priv *gbe_dev, 1773 int stats_mod) 1774 { 1775 u32 val; 1776 1777 val = readl(GBE_REG_ADDR(gbe_dev, switch_regs, stat_port_en)); 1778 1779 switch (stats_mod) { 1780 case GBE_STATSA_MODULE: 1781 case GBE_STATSB_MODULE: 1782 val &= ~GBE_STATS_CD_SEL; 1783 break; 1784 case GBE_STATSC_MODULE: 1785 case GBE_STATSD_MODULE: 1786 val |= GBE_STATS_CD_SEL; 1787 break; 1788 default: 1789 return; 1790 } 1791 1792 /* make the stat module visible */ 1793 writel(val, GBE_REG_ADDR(gbe_dev, switch_regs, stat_port_en)); 1794 } 1795 1796 static void gbe_reset_mod_stats_ver14(struct gbe_priv *gbe_dev, int stats_mod) 1797 { 1798 gbe_stats_mod_visible_ver14(gbe_dev, stats_mod); 1799 gbe_reset_mod_stats(gbe_dev, stats_mod); 1800 } 1801 1802 static void gbe_update_stats_ver14(struct gbe_priv *gbe_dev, uint64_t *data) 1803 { 1804 u32 half_num_et_stats = (gbe_dev->num_et_stats / 2); 1805 int et_entry, j, pair; 1806 1807 for (pair = 0; pair < 2; pair++) { 1808 gbe_stats_mod_visible_ver14(gbe_dev, (pair ? 1809 GBE_STATSC_MODULE : 1810 GBE_STATSA_MODULE)); 1811 1812 for (j = 0; j < half_num_et_stats; j++) { 1813 et_entry = pair * half_num_et_stats + j; 1814 gbe_update_hw_stats_entry(gbe_dev, et_entry); 1815 1816 if (data) 1817 data[et_entry] = gbe_dev->hw_stats[et_entry]; 1818 } 1819 } 1820 } 1821 1822 static void keystone_get_ethtool_stats(struct net_device *ndev, 1823 struct ethtool_stats *stats, 1824 uint64_t *data) 1825 { 1826 struct netcp_intf *netcp = netdev_priv(ndev); 1827 struct gbe_intf *gbe_intf; 1828 struct gbe_priv *gbe_dev; 1829 1830 gbe_intf = netcp_module_get_intf_data(&gbe_module, netcp); 1831 if (!gbe_intf) 1832 return; 1833 1834 gbe_dev = gbe_intf->gbe_dev; 1835 spin_lock_bh(&gbe_dev->hw_stats_lock); 1836 if (gbe_dev->ss_version == GBE_SS_VERSION_14) 1837 gbe_update_stats_ver14(gbe_dev, data); 1838 else 1839 gbe_update_stats(gbe_dev, data); 1840 spin_unlock_bh(&gbe_dev->hw_stats_lock); 1841 } 1842 1843 static int keystone_get_link_ksettings(struct net_device *ndev, 1844 struct ethtool_link_ksettings *cmd) 1845 { 1846 struct netcp_intf *netcp = netdev_priv(ndev); 1847 struct phy_device *phy = ndev->phydev; 1848 struct gbe_intf *gbe_intf; 1849 int ret; 1850 1851 if (!phy) 1852 return -EINVAL; 1853 1854 gbe_intf = netcp_module_get_intf_data(&gbe_module, netcp); 1855 if (!gbe_intf) 1856 return -EINVAL; 1857 1858 if (!gbe_intf->slave) 1859 return -EINVAL; 1860 1861 ret = phy_ethtool_ksettings_get(phy, cmd); 1862 if (!ret) 1863 cmd->base.port = gbe_intf->slave->phy_port_t; 1864 1865 return ret; 1866 } 1867 1868 static int keystone_set_link_ksettings(struct net_device *ndev, 1869 const struct ethtool_link_ksettings *cmd) 1870 { 1871 struct netcp_intf *netcp = netdev_priv(ndev); 1872 struct phy_device *phy = ndev->phydev; 1873 struct gbe_intf *gbe_intf; 1874 u8 port = cmd->base.port; 1875 u32 advertising, supported; 1876 u32 features; 1877 1878 ethtool_convert_link_mode_to_legacy_u32(&advertising, 1879 cmd->link_modes.advertising); 1880 ethtool_convert_link_mode_to_legacy_u32(&supported, 1881 cmd->link_modes.supported); 1882 features = advertising & supported; 1883 1884 if (!phy) 1885 return -EINVAL; 1886 1887 gbe_intf = netcp_module_get_intf_data(&gbe_module, netcp); 1888 if (!gbe_intf) 1889 return -EINVAL; 1890 1891 if (!gbe_intf->slave) 1892 return -EINVAL; 1893 1894 if (port != gbe_intf->slave->phy_port_t) { 1895 if ((port == PORT_TP) && !(features & ADVERTISED_TP)) 1896 return -EINVAL; 1897 1898 if ((port == PORT_AUI) && !(features & ADVERTISED_AUI)) 1899 return -EINVAL; 1900 1901 if ((port == PORT_BNC) && !(features & ADVERTISED_BNC)) 1902 return -EINVAL; 1903 1904 if ((port == PORT_MII) && !(features & ADVERTISED_MII)) 1905 return -EINVAL; 1906 1907 if ((port == PORT_FIBRE) && !(features & ADVERTISED_FIBRE)) 1908 return -EINVAL; 1909 } 1910 1911 gbe_intf->slave->phy_port_t = port; 1912 return phy_ethtool_ksettings_set(phy, cmd); 1913 } 1914 1915 static const struct ethtool_ops keystone_ethtool_ops = { 1916 .get_drvinfo = keystone_get_drvinfo, 1917 .get_link = ethtool_op_get_link, 1918 .get_msglevel = keystone_get_msglevel, 1919 .set_msglevel = keystone_set_msglevel, 1920 .get_strings = keystone_get_stat_strings, 1921 .get_sset_count = keystone_get_sset_count, 1922 .get_ethtool_stats = keystone_get_ethtool_stats, 1923 .get_link_ksettings = keystone_get_link_ksettings, 1924 .set_link_ksettings = keystone_set_link_ksettings, 1925 }; 1926 1927 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 1928 ((mac)[2] << 16) | ((mac)[3] << 24)) 1929 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 1930 1931 static void gbe_set_slave_mac(struct gbe_slave *slave, 1932 struct gbe_intf *gbe_intf) 1933 { 1934 struct net_device *ndev = gbe_intf->ndev; 1935 1936 writel(mac_hi(ndev->dev_addr), GBE_REG_ADDR(slave, port_regs, sa_hi)); 1937 writel(mac_lo(ndev->dev_addr), GBE_REG_ADDR(slave, port_regs, sa_lo)); 1938 } 1939 1940 static int gbe_get_slave_port(struct gbe_priv *priv, u32 slave_num) 1941 { 1942 if (priv->host_port == 0) 1943 return slave_num + 1; 1944 1945 return slave_num; 1946 } 1947 1948 static void netcp_ethss_link_state_action(struct gbe_priv *gbe_dev, 1949 struct net_device *ndev, 1950 struct gbe_slave *slave, 1951 int up) 1952 { 1953 struct phy_device *phy = slave->phy; 1954 u32 mac_control = 0; 1955 1956 if (up) { 1957 mac_control = slave->mac_control; 1958 if (phy && (phy->speed == SPEED_1000)) { 1959 mac_control |= MACSL_GIG_MODE; 1960 mac_control &= ~MACSL_XGIG_MODE; 1961 } else if (phy && (phy->speed == SPEED_10000)) { 1962 mac_control |= MACSL_XGIG_MODE; 1963 mac_control &= ~MACSL_GIG_MODE; 1964 } 1965 1966 writel(mac_control, GBE_REG_ADDR(slave, emac_regs, 1967 mac_control)); 1968 1969 cpsw_ale_control_set(gbe_dev->ale, slave->port_num, 1970 ALE_PORT_STATE, 1971 ALE_PORT_STATE_FORWARD); 1972 1973 if (ndev && slave->open && 1974 slave->link_interface != SGMII_LINK_MAC_PHY && 1975 slave->link_interface != XGMII_LINK_MAC_PHY) 1976 netif_carrier_on(ndev); 1977 } else { 1978 writel(mac_control, GBE_REG_ADDR(slave, emac_regs, 1979 mac_control)); 1980 cpsw_ale_control_set(gbe_dev->ale, slave->port_num, 1981 ALE_PORT_STATE, 1982 ALE_PORT_STATE_DISABLE); 1983 if (ndev && 1984 slave->link_interface != SGMII_LINK_MAC_PHY && 1985 slave->link_interface != XGMII_LINK_MAC_PHY) 1986 netif_carrier_off(ndev); 1987 } 1988 1989 if (phy) 1990 phy_print_status(phy); 1991 } 1992 1993 static bool gbe_phy_link_status(struct gbe_slave *slave) 1994 { 1995 return !slave->phy || slave->phy->link; 1996 } 1997 1998 static void netcp_ethss_update_link_state(struct gbe_priv *gbe_dev, 1999 struct gbe_slave *slave, 2000 struct net_device *ndev) 2001 { 2002 int sp = slave->slave_num; 2003 int phy_link_state, sgmii_link_state = 1, link_state; 2004 2005 if (!slave->open) 2006 return; 2007 2008 if (!SLAVE_LINK_IS_XGMII(slave)) { 2009 sgmii_link_state = 2010 netcp_sgmii_get_port_link(SGMII_BASE(gbe_dev, sp), sp); 2011 } 2012 2013 phy_link_state = gbe_phy_link_status(slave); 2014 link_state = phy_link_state & sgmii_link_state; 2015 2016 if (atomic_xchg(&slave->link_state, link_state) != link_state) 2017 netcp_ethss_link_state_action(gbe_dev, ndev, slave, 2018 link_state); 2019 } 2020 2021 static void xgbe_adjust_link(struct net_device *ndev) 2022 { 2023 struct netcp_intf *netcp = netdev_priv(ndev); 2024 struct gbe_intf *gbe_intf; 2025 2026 gbe_intf = netcp_module_get_intf_data(&xgbe_module, netcp); 2027 if (!gbe_intf) 2028 return; 2029 2030 netcp_ethss_update_link_state(gbe_intf->gbe_dev, gbe_intf->slave, 2031 ndev); 2032 } 2033 2034 static void gbe_adjust_link(struct net_device *ndev) 2035 { 2036 struct netcp_intf *netcp = netdev_priv(ndev); 2037 struct gbe_intf *gbe_intf; 2038 2039 gbe_intf = netcp_module_get_intf_data(&gbe_module, netcp); 2040 if (!gbe_intf) 2041 return; 2042 2043 netcp_ethss_update_link_state(gbe_intf->gbe_dev, gbe_intf->slave, 2044 ndev); 2045 } 2046 2047 static void gbe_adjust_link_sec_slaves(struct net_device *ndev) 2048 { 2049 struct gbe_priv *gbe_dev = netdev_priv(ndev); 2050 struct gbe_slave *slave; 2051 2052 for_each_sec_slave(slave, gbe_dev) 2053 netcp_ethss_update_link_state(gbe_dev, slave, NULL); 2054 } 2055 2056 /* Reset EMAC 2057 * Soft reset is set and polled until clear, or until a timeout occurs 2058 */ 2059 static int gbe_port_reset(struct gbe_slave *slave) 2060 { 2061 u32 i, v; 2062 2063 /* Set the soft reset bit */ 2064 writel(SOFT_RESET, GBE_REG_ADDR(slave, emac_regs, soft_reset)); 2065 2066 /* Wait for the bit to clear */ 2067 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { 2068 v = readl(GBE_REG_ADDR(slave, emac_regs, soft_reset)); 2069 if ((v & SOFT_RESET_MASK) != SOFT_RESET) 2070 return 0; 2071 } 2072 2073 /* Timeout on the reset */ 2074 return GMACSL_RET_WARN_RESET_INCOMPLETE; 2075 } 2076 2077 /* Configure EMAC */ 2078 static void gbe_port_config(struct gbe_priv *gbe_dev, struct gbe_slave *slave, 2079 int max_rx_len) 2080 { 2081 void __iomem *rx_maxlen_reg; 2082 u32 xgmii_mode; 2083 2084 if (max_rx_len > NETCP_MAX_FRAME_SIZE) 2085 max_rx_len = NETCP_MAX_FRAME_SIZE; 2086 2087 /* Enable correct MII mode at SS level */ 2088 if ((gbe_dev->ss_version == XGBE_SS_VERSION_10) && 2089 (slave->link_interface >= XGMII_LINK_MAC_PHY)) { 2090 xgmii_mode = readl(GBE_REG_ADDR(gbe_dev, ss_regs, control)); 2091 xgmii_mode |= (1 << slave->slave_num); 2092 writel(xgmii_mode, GBE_REG_ADDR(gbe_dev, ss_regs, control)); 2093 } 2094 2095 if (IS_SS_ID_MU(gbe_dev)) 2096 rx_maxlen_reg = GBE_REG_ADDR(slave, port_regs, rx_maxlen); 2097 else 2098 rx_maxlen_reg = GBE_REG_ADDR(slave, emac_regs, rx_maxlen); 2099 2100 writel(max_rx_len, rx_maxlen_reg); 2101 writel(slave->mac_control, GBE_REG_ADDR(slave, emac_regs, mac_control)); 2102 } 2103 2104 static void gbe_sgmii_rtreset(struct gbe_priv *priv, 2105 struct gbe_slave *slave, bool set) 2106 { 2107 if (SLAVE_LINK_IS_XGMII(slave)) 2108 return; 2109 2110 netcp_sgmii_rtreset(SGMII_BASE(priv, slave->slave_num), 2111 slave->slave_num, set); 2112 } 2113 2114 static void gbe_slave_stop(struct gbe_intf *intf) 2115 { 2116 struct gbe_priv *gbe_dev = intf->gbe_dev; 2117 struct gbe_slave *slave = intf->slave; 2118 2119 gbe_sgmii_rtreset(gbe_dev, slave, true); 2120 gbe_port_reset(slave); 2121 /* Disable forwarding */ 2122 cpsw_ale_control_set(gbe_dev->ale, slave->port_num, 2123 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 2124 cpsw_ale_del_mcast(gbe_dev->ale, intf->ndev->broadcast, 2125 1 << slave->port_num, 0, 0); 2126 2127 if (!slave->phy) 2128 return; 2129 2130 phy_stop(slave->phy); 2131 phy_disconnect(slave->phy); 2132 slave->phy = NULL; 2133 } 2134 2135 static void gbe_sgmii_config(struct gbe_priv *priv, struct gbe_slave *slave) 2136 { 2137 if (SLAVE_LINK_IS_XGMII(slave)) 2138 return; 2139 2140 netcp_sgmii_reset(SGMII_BASE(priv, slave->slave_num), slave->slave_num); 2141 netcp_sgmii_config(SGMII_BASE(priv, slave->slave_num), slave->slave_num, 2142 slave->link_interface); 2143 } 2144 2145 static int gbe_slave_open(struct gbe_intf *gbe_intf) 2146 { 2147 struct gbe_priv *priv = gbe_intf->gbe_dev; 2148 struct gbe_slave *slave = gbe_intf->slave; 2149 phy_interface_t phy_mode; 2150 bool has_phy = false; 2151 2152 void (*hndlr)(struct net_device *) = gbe_adjust_link; 2153 2154 gbe_sgmii_config(priv, slave); 2155 gbe_port_reset(slave); 2156 gbe_sgmii_rtreset(priv, slave, false); 2157 gbe_port_config(priv, slave, priv->rx_packet_max); 2158 gbe_set_slave_mac(slave, gbe_intf); 2159 /* enable forwarding */ 2160 cpsw_ale_control_set(priv->ale, slave->port_num, 2161 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 2162 cpsw_ale_add_mcast(priv->ale, gbe_intf->ndev->broadcast, 2163 1 << slave->port_num, 0, 0, ALE_MCAST_FWD_2); 2164 2165 if (slave->link_interface == SGMII_LINK_MAC_PHY) { 2166 has_phy = true; 2167 phy_mode = PHY_INTERFACE_MODE_SGMII; 2168 slave->phy_port_t = PORT_MII; 2169 } else if (slave->link_interface == XGMII_LINK_MAC_PHY) { 2170 has_phy = true; 2171 phy_mode = PHY_INTERFACE_MODE_NA; 2172 slave->phy_port_t = PORT_FIBRE; 2173 } 2174 2175 if (has_phy) { 2176 if (priv->ss_version == XGBE_SS_VERSION_10) 2177 hndlr = xgbe_adjust_link; 2178 2179 slave->phy = of_phy_connect(gbe_intf->ndev, 2180 slave->phy_node, 2181 hndlr, 0, 2182 phy_mode); 2183 if (!slave->phy) { 2184 dev_err(priv->dev, "phy not found on slave %d\n", 2185 slave->slave_num); 2186 return -ENODEV; 2187 } 2188 dev_dbg(priv->dev, "phy found: id is: 0x%s\n", 2189 phydev_name(slave->phy)); 2190 phy_start(slave->phy); 2191 phy_read_status(slave->phy); 2192 } 2193 return 0; 2194 } 2195 2196 static void gbe_init_host_port(struct gbe_priv *priv) 2197 { 2198 int bypass_en = 1; 2199 2200 /* Host Tx Pri */ 2201 if (IS_SS_ID_NU(priv)) 2202 writel(HOST_TX_PRI_MAP_DEFAULT, 2203 GBE_REG_ADDR(priv, host_port_regs, tx_pri_map)); 2204 2205 /* Max length register */ 2206 writel(NETCP_MAX_FRAME_SIZE, GBE_REG_ADDR(priv, host_port_regs, 2207 rx_maxlen)); 2208 2209 cpsw_ale_start(priv->ale); 2210 2211 if (priv->enable_ale) 2212 bypass_en = 0; 2213 2214 cpsw_ale_control_set(priv->ale, 0, ALE_BYPASS, bypass_en); 2215 2216 cpsw_ale_control_set(priv->ale, 0, ALE_NO_PORT_VLAN, 1); 2217 2218 cpsw_ale_control_set(priv->ale, priv->host_port, 2219 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 2220 2221 cpsw_ale_control_set(priv->ale, 0, 2222 ALE_PORT_UNKNOWN_VLAN_MEMBER, 2223 GBE_PORT_MASK(priv->ale_ports)); 2224 2225 cpsw_ale_control_set(priv->ale, 0, 2226 ALE_PORT_UNKNOWN_MCAST_FLOOD, 2227 GBE_PORT_MASK(priv->ale_ports - 1)); 2228 2229 cpsw_ale_control_set(priv->ale, 0, 2230 ALE_PORT_UNKNOWN_REG_MCAST_FLOOD, 2231 GBE_PORT_MASK(priv->ale_ports)); 2232 2233 cpsw_ale_control_set(priv->ale, 0, 2234 ALE_PORT_UNTAGGED_EGRESS, 2235 GBE_PORT_MASK(priv->ale_ports)); 2236 } 2237 2238 static void gbe_add_mcast_addr(struct gbe_intf *gbe_intf, u8 *addr) 2239 { 2240 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2241 u16 vlan_id; 2242 2243 cpsw_ale_add_mcast(gbe_dev->ale, addr, 2244 GBE_PORT_MASK(gbe_dev->ale_ports), 0, 0, 2245 ALE_MCAST_FWD_2); 2246 for_each_set_bit(vlan_id, gbe_intf->active_vlans, VLAN_N_VID) { 2247 cpsw_ale_add_mcast(gbe_dev->ale, addr, 2248 GBE_PORT_MASK(gbe_dev->ale_ports), 2249 ALE_VLAN, vlan_id, ALE_MCAST_FWD_2); 2250 } 2251 } 2252 2253 static void gbe_add_ucast_addr(struct gbe_intf *gbe_intf, u8 *addr) 2254 { 2255 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2256 u16 vlan_id; 2257 2258 cpsw_ale_add_ucast(gbe_dev->ale, addr, gbe_dev->host_port, 0, 0); 2259 2260 for_each_set_bit(vlan_id, gbe_intf->active_vlans, VLAN_N_VID) 2261 cpsw_ale_add_ucast(gbe_dev->ale, addr, gbe_dev->host_port, 2262 ALE_VLAN, vlan_id); 2263 } 2264 2265 static void gbe_del_mcast_addr(struct gbe_intf *gbe_intf, u8 *addr) 2266 { 2267 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2268 u16 vlan_id; 2269 2270 cpsw_ale_del_mcast(gbe_dev->ale, addr, 0, 0, 0); 2271 2272 for_each_set_bit(vlan_id, gbe_intf->active_vlans, VLAN_N_VID) { 2273 cpsw_ale_del_mcast(gbe_dev->ale, addr, 0, ALE_VLAN, vlan_id); 2274 } 2275 } 2276 2277 static void gbe_del_ucast_addr(struct gbe_intf *gbe_intf, u8 *addr) 2278 { 2279 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2280 u16 vlan_id; 2281 2282 cpsw_ale_del_ucast(gbe_dev->ale, addr, gbe_dev->host_port, 0, 0); 2283 2284 for_each_set_bit(vlan_id, gbe_intf->active_vlans, VLAN_N_VID) { 2285 cpsw_ale_del_ucast(gbe_dev->ale, addr, gbe_dev->host_port, 2286 ALE_VLAN, vlan_id); 2287 } 2288 } 2289 2290 static int gbe_add_addr(void *intf_priv, struct netcp_addr *naddr) 2291 { 2292 struct gbe_intf *gbe_intf = intf_priv; 2293 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2294 2295 dev_dbg(gbe_dev->dev, "ethss adding address %pM, type %d\n", 2296 naddr->addr, naddr->type); 2297 2298 switch (naddr->type) { 2299 case ADDR_MCAST: 2300 case ADDR_BCAST: 2301 gbe_add_mcast_addr(gbe_intf, naddr->addr); 2302 break; 2303 case ADDR_UCAST: 2304 case ADDR_DEV: 2305 gbe_add_ucast_addr(gbe_intf, naddr->addr); 2306 break; 2307 case ADDR_ANY: 2308 /* nothing to do for promiscuous */ 2309 default: 2310 break; 2311 } 2312 2313 return 0; 2314 } 2315 2316 static int gbe_del_addr(void *intf_priv, struct netcp_addr *naddr) 2317 { 2318 struct gbe_intf *gbe_intf = intf_priv; 2319 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2320 2321 dev_dbg(gbe_dev->dev, "ethss deleting address %pM, type %d\n", 2322 naddr->addr, naddr->type); 2323 2324 switch (naddr->type) { 2325 case ADDR_MCAST: 2326 case ADDR_BCAST: 2327 gbe_del_mcast_addr(gbe_intf, naddr->addr); 2328 break; 2329 case ADDR_UCAST: 2330 case ADDR_DEV: 2331 gbe_del_ucast_addr(gbe_intf, naddr->addr); 2332 break; 2333 case ADDR_ANY: 2334 /* nothing to do for promiscuous */ 2335 default: 2336 break; 2337 } 2338 2339 return 0; 2340 } 2341 2342 static int gbe_add_vid(void *intf_priv, int vid) 2343 { 2344 struct gbe_intf *gbe_intf = intf_priv; 2345 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2346 2347 set_bit(vid, gbe_intf->active_vlans); 2348 2349 cpsw_ale_add_vlan(gbe_dev->ale, vid, 2350 GBE_PORT_MASK(gbe_dev->ale_ports), 2351 GBE_MASK_NO_PORTS, 2352 GBE_PORT_MASK(gbe_dev->ale_ports), 2353 GBE_PORT_MASK(gbe_dev->ale_ports - 1)); 2354 2355 return 0; 2356 } 2357 2358 static int gbe_del_vid(void *intf_priv, int vid) 2359 { 2360 struct gbe_intf *gbe_intf = intf_priv; 2361 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2362 2363 cpsw_ale_del_vlan(gbe_dev->ale, vid, 0); 2364 clear_bit(vid, gbe_intf->active_vlans); 2365 return 0; 2366 } 2367 2368 static int gbe_ioctl(void *intf_priv, struct ifreq *req, int cmd) 2369 { 2370 struct gbe_intf *gbe_intf = intf_priv; 2371 struct phy_device *phy = gbe_intf->slave->phy; 2372 int ret = -EOPNOTSUPP; 2373 2374 if (phy) 2375 ret = phy_mii_ioctl(phy, req, cmd); 2376 2377 return ret; 2378 } 2379 2380 static void netcp_ethss_timer(unsigned long arg) 2381 { 2382 struct gbe_priv *gbe_dev = (struct gbe_priv *)arg; 2383 struct gbe_intf *gbe_intf; 2384 struct gbe_slave *slave; 2385 2386 /* Check & update SGMII link state of interfaces */ 2387 for_each_intf(gbe_intf, gbe_dev) { 2388 if (!gbe_intf->slave->open) 2389 continue; 2390 netcp_ethss_update_link_state(gbe_dev, gbe_intf->slave, 2391 gbe_intf->ndev); 2392 } 2393 2394 /* Check & update SGMII link state of secondary ports */ 2395 for_each_sec_slave(slave, gbe_dev) { 2396 netcp_ethss_update_link_state(gbe_dev, slave, NULL); 2397 } 2398 2399 /* A timer runs as a BH, no need to block them */ 2400 spin_lock(&gbe_dev->hw_stats_lock); 2401 2402 if (gbe_dev->ss_version == GBE_SS_VERSION_14) 2403 gbe_update_stats_ver14(gbe_dev, NULL); 2404 else 2405 gbe_update_stats(gbe_dev, NULL); 2406 2407 spin_unlock(&gbe_dev->hw_stats_lock); 2408 2409 gbe_dev->timer.expires = jiffies + GBE_TIMER_INTERVAL; 2410 add_timer(&gbe_dev->timer); 2411 } 2412 2413 static int gbe_tx_hook(int order, void *data, struct netcp_packet *p_info) 2414 { 2415 struct gbe_intf *gbe_intf = data; 2416 2417 p_info->tx_pipe = &gbe_intf->tx_pipe; 2418 return 0; 2419 } 2420 2421 static int gbe_open(void *intf_priv, struct net_device *ndev) 2422 { 2423 struct gbe_intf *gbe_intf = intf_priv; 2424 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev; 2425 struct netcp_intf *netcp = netdev_priv(ndev); 2426 struct gbe_slave *slave = gbe_intf->slave; 2427 int port_num = slave->port_num; 2428 u32 reg; 2429 int ret; 2430 2431 reg = readl(GBE_REG_ADDR(gbe_dev, switch_regs, id_ver)); 2432 dev_dbg(gbe_dev->dev, "initializing gbe version %d.%d (%d) GBE identification value 0x%x\n", 2433 GBE_MAJOR_VERSION(reg), GBE_MINOR_VERSION(reg), 2434 GBE_RTL_VERSION(reg), GBE_IDENT(reg)); 2435 2436 /* For 10G and on NetCP 1.5, use directed to port */ 2437 if ((gbe_dev->ss_version == XGBE_SS_VERSION_10) || IS_SS_ID_MU(gbe_dev)) 2438 gbe_intf->tx_pipe.flags = SWITCH_TO_PORT_IN_TAGINFO; 2439 2440 if (gbe_dev->enable_ale) 2441 gbe_intf->tx_pipe.switch_to_port = 0; 2442 else 2443 gbe_intf->tx_pipe.switch_to_port = port_num; 2444 2445 dev_dbg(gbe_dev->dev, 2446 "opened TX channel %s: %p with to port %d, flags %d\n", 2447 gbe_intf->tx_pipe.dma_chan_name, 2448 gbe_intf->tx_pipe.dma_channel, 2449 gbe_intf->tx_pipe.switch_to_port, 2450 gbe_intf->tx_pipe.flags); 2451 2452 gbe_slave_stop(gbe_intf); 2453 2454 /* disable priority elevation and enable statistics on all ports */ 2455 writel(0, GBE_REG_ADDR(gbe_dev, switch_regs, ptype)); 2456 2457 /* Control register */ 2458 writel(GBE_CTL_P0_ENABLE, GBE_REG_ADDR(gbe_dev, switch_regs, control)); 2459 2460 /* All statistics enabled and STAT AB visible by default */ 2461 writel(gbe_dev->stats_en_mask, GBE_REG_ADDR(gbe_dev, switch_regs, 2462 stat_port_en)); 2463 2464 ret = gbe_slave_open(gbe_intf); 2465 if (ret) 2466 goto fail; 2467 2468 netcp_register_txhook(netcp, GBE_TXHOOK_ORDER, gbe_tx_hook, 2469 gbe_intf); 2470 2471 slave->open = true; 2472 netcp_ethss_update_link_state(gbe_dev, slave, ndev); 2473 return 0; 2474 2475 fail: 2476 gbe_slave_stop(gbe_intf); 2477 return ret; 2478 } 2479 2480 static int gbe_close(void *intf_priv, struct net_device *ndev) 2481 { 2482 struct gbe_intf *gbe_intf = intf_priv; 2483 struct netcp_intf *netcp = netdev_priv(ndev); 2484 2485 gbe_slave_stop(gbe_intf); 2486 netcp_unregister_txhook(netcp, GBE_TXHOOK_ORDER, gbe_tx_hook, 2487 gbe_intf); 2488 2489 gbe_intf->slave->open = false; 2490 atomic_set(&gbe_intf->slave->link_state, NETCP_LINK_STATE_INVALID); 2491 return 0; 2492 } 2493 2494 static int init_slave(struct gbe_priv *gbe_dev, struct gbe_slave *slave, 2495 struct device_node *node) 2496 { 2497 int port_reg_num; 2498 u32 port_reg_ofs, emac_reg_ofs; 2499 u32 port_reg_blk_sz, emac_reg_blk_sz; 2500 2501 if (of_property_read_u32(node, "slave-port", &slave->slave_num)) { 2502 dev_err(gbe_dev->dev, "missing slave-port parameter\n"); 2503 return -EINVAL; 2504 } 2505 2506 if (of_property_read_u32(node, "link-interface", 2507 &slave->link_interface)) { 2508 dev_warn(gbe_dev->dev, 2509 "missing link-interface value defaulting to 1G mac-phy link\n"); 2510 slave->link_interface = SGMII_LINK_MAC_PHY; 2511 } 2512 2513 slave->open = false; 2514 slave->phy_node = of_parse_phandle(node, "phy-handle", 0); 2515 slave->port_num = gbe_get_slave_port(gbe_dev, slave->slave_num); 2516 2517 if (slave->link_interface >= XGMII_LINK_MAC_PHY) 2518 slave->mac_control = GBE_DEF_10G_MAC_CONTROL; 2519 else 2520 slave->mac_control = GBE_DEF_1G_MAC_CONTROL; 2521 2522 /* Emac regs memmap are contiguous but port regs are not */ 2523 port_reg_num = slave->slave_num; 2524 if (gbe_dev->ss_version == GBE_SS_VERSION_14) { 2525 if (slave->slave_num > 1) { 2526 port_reg_ofs = GBE13_SLAVE_PORT2_OFFSET; 2527 port_reg_num -= 2; 2528 } else { 2529 port_reg_ofs = GBE13_SLAVE_PORT_OFFSET; 2530 } 2531 emac_reg_ofs = GBE13_EMAC_OFFSET; 2532 port_reg_blk_sz = 0x30; 2533 emac_reg_blk_sz = 0x40; 2534 } else if (IS_SS_ID_MU(gbe_dev)) { 2535 port_reg_ofs = GBENU_SLAVE_PORT_OFFSET; 2536 emac_reg_ofs = GBENU_EMAC_OFFSET; 2537 port_reg_blk_sz = 0x1000; 2538 emac_reg_blk_sz = 0x1000; 2539 } else if (gbe_dev->ss_version == XGBE_SS_VERSION_10) { 2540 port_reg_ofs = XGBE10_SLAVE_PORT_OFFSET; 2541 emac_reg_ofs = XGBE10_EMAC_OFFSET; 2542 port_reg_blk_sz = 0x30; 2543 emac_reg_blk_sz = 0x40; 2544 } else { 2545 dev_err(gbe_dev->dev, "unknown ethss(0x%x)\n", 2546 gbe_dev->ss_version); 2547 return -EINVAL; 2548 } 2549 2550 slave->port_regs = gbe_dev->switch_regs + port_reg_ofs + 2551 (port_reg_blk_sz * port_reg_num); 2552 slave->emac_regs = gbe_dev->switch_regs + emac_reg_ofs + 2553 (emac_reg_blk_sz * slave->slave_num); 2554 2555 if (gbe_dev->ss_version == GBE_SS_VERSION_14) { 2556 /* Initialize slave port register offsets */ 2557 GBE_SET_REG_OFS(slave, port_regs, port_vlan); 2558 GBE_SET_REG_OFS(slave, port_regs, tx_pri_map); 2559 GBE_SET_REG_OFS(slave, port_regs, sa_lo); 2560 GBE_SET_REG_OFS(slave, port_regs, sa_hi); 2561 GBE_SET_REG_OFS(slave, port_regs, ts_ctl); 2562 GBE_SET_REG_OFS(slave, port_regs, ts_seq_ltype); 2563 GBE_SET_REG_OFS(slave, port_regs, ts_vlan); 2564 GBE_SET_REG_OFS(slave, port_regs, ts_ctl_ltype2); 2565 GBE_SET_REG_OFS(slave, port_regs, ts_ctl2); 2566 2567 /* Initialize EMAC register offsets */ 2568 GBE_SET_REG_OFS(slave, emac_regs, mac_control); 2569 GBE_SET_REG_OFS(slave, emac_regs, soft_reset); 2570 GBE_SET_REG_OFS(slave, emac_regs, rx_maxlen); 2571 2572 } else if (IS_SS_ID_MU(gbe_dev)) { 2573 /* Initialize slave port register offsets */ 2574 GBENU_SET_REG_OFS(slave, port_regs, port_vlan); 2575 GBENU_SET_REG_OFS(slave, port_regs, tx_pri_map); 2576 GBENU_SET_REG_OFS(slave, port_regs, sa_lo); 2577 GBENU_SET_REG_OFS(slave, port_regs, sa_hi); 2578 GBENU_SET_REG_OFS(slave, port_regs, ts_ctl); 2579 GBENU_SET_REG_OFS(slave, port_regs, ts_seq_ltype); 2580 GBENU_SET_REG_OFS(slave, port_regs, ts_vlan); 2581 GBENU_SET_REG_OFS(slave, port_regs, ts_ctl_ltype2); 2582 GBENU_SET_REG_OFS(slave, port_regs, ts_ctl2); 2583 GBENU_SET_REG_OFS(slave, port_regs, rx_maxlen); 2584 2585 /* Initialize EMAC register offsets */ 2586 GBENU_SET_REG_OFS(slave, emac_regs, mac_control); 2587 GBENU_SET_REG_OFS(slave, emac_regs, soft_reset); 2588 2589 } else if (gbe_dev->ss_version == XGBE_SS_VERSION_10) { 2590 /* Initialize slave port register offsets */ 2591 XGBE_SET_REG_OFS(slave, port_regs, port_vlan); 2592 XGBE_SET_REG_OFS(slave, port_regs, tx_pri_map); 2593 XGBE_SET_REG_OFS(slave, port_regs, sa_lo); 2594 XGBE_SET_REG_OFS(slave, port_regs, sa_hi); 2595 XGBE_SET_REG_OFS(slave, port_regs, ts_ctl); 2596 XGBE_SET_REG_OFS(slave, port_regs, ts_seq_ltype); 2597 XGBE_SET_REG_OFS(slave, port_regs, ts_vlan); 2598 XGBE_SET_REG_OFS(slave, port_regs, ts_ctl_ltype2); 2599 XGBE_SET_REG_OFS(slave, port_regs, ts_ctl2); 2600 2601 /* Initialize EMAC register offsets */ 2602 XGBE_SET_REG_OFS(slave, emac_regs, mac_control); 2603 XGBE_SET_REG_OFS(slave, emac_regs, soft_reset); 2604 XGBE_SET_REG_OFS(slave, emac_regs, rx_maxlen); 2605 } 2606 2607 atomic_set(&slave->link_state, NETCP_LINK_STATE_INVALID); 2608 return 0; 2609 } 2610 2611 static void init_secondary_ports(struct gbe_priv *gbe_dev, 2612 struct device_node *node) 2613 { 2614 struct device *dev = gbe_dev->dev; 2615 phy_interface_t phy_mode; 2616 struct gbe_priv **priv; 2617 struct device_node *port; 2618 struct gbe_slave *slave; 2619 bool mac_phy_link = false; 2620 2621 for_each_child_of_node(node, port) { 2622 slave = devm_kzalloc(dev, sizeof(*slave), GFP_KERNEL); 2623 if (!slave) { 2624 dev_err(dev, 2625 "memomry alloc failed for secondary port(%s), skipping...\n", 2626 port->name); 2627 continue; 2628 } 2629 2630 if (init_slave(gbe_dev, slave, port)) { 2631 dev_err(dev, 2632 "Failed to initialize secondary port(%s), skipping...\n", 2633 port->name); 2634 devm_kfree(dev, slave); 2635 continue; 2636 } 2637 2638 gbe_sgmii_config(gbe_dev, slave); 2639 gbe_port_reset(slave); 2640 gbe_port_config(gbe_dev, slave, gbe_dev->rx_packet_max); 2641 list_add_tail(&slave->slave_list, &gbe_dev->secondary_slaves); 2642 gbe_dev->num_slaves++; 2643 if ((slave->link_interface == SGMII_LINK_MAC_PHY) || 2644 (slave->link_interface == XGMII_LINK_MAC_PHY)) 2645 mac_phy_link = true; 2646 2647 slave->open = true; 2648 if (gbe_dev->num_slaves >= gbe_dev->max_num_slaves) { 2649 of_node_put(port); 2650 break; 2651 } 2652 } 2653 2654 /* of_phy_connect() is needed only for MAC-PHY interface */ 2655 if (!mac_phy_link) 2656 return; 2657 2658 /* Allocate dummy netdev device for attaching to phy device */ 2659 gbe_dev->dummy_ndev = alloc_netdev(sizeof(gbe_dev), "dummy", 2660 NET_NAME_UNKNOWN, ether_setup); 2661 if (!gbe_dev->dummy_ndev) { 2662 dev_err(dev, 2663 "Failed to allocate dummy netdev for secondary ports, skipping phy_connect()...\n"); 2664 return; 2665 } 2666 priv = netdev_priv(gbe_dev->dummy_ndev); 2667 *priv = gbe_dev; 2668 2669 if (slave->link_interface == SGMII_LINK_MAC_PHY) { 2670 phy_mode = PHY_INTERFACE_MODE_SGMII; 2671 slave->phy_port_t = PORT_MII; 2672 } else { 2673 phy_mode = PHY_INTERFACE_MODE_NA; 2674 slave->phy_port_t = PORT_FIBRE; 2675 } 2676 2677 for_each_sec_slave(slave, gbe_dev) { 2678 if ((slave->link_interface != SGMII_LINK_MAC_PHY) && 2679 (slave->link_interface != XGMII_LINK_MAC_PHY)) 2680 continue; 2681 slave->phy = 2682 of_phy_connect(gbe_dev->dummy_ndev, 2683 slave->phy_node, 2684 gbe_adjust_link_sec_slaves, 2685 0, phy_mode); 2686 if (!slave->phy) { 2687 dev_err(dev, "phy not found for slave %d\n", 2688 slave->slave_num); 2689 slave->phy = NULL; 2690 } else { 2691 dev_dbg(dev, "phy found: id is: 0x%s\n", 2692 phydev_name(slave->phy)); 2693 phy_start(slave->phy); 2694 phy_read_status(slave->phy); 2695 } 2696 } 2697 } 2698 2699 static void free_secondary_ports(struct gbe_priv *gbe_dev) 2700 { 2701 struct gbe_slave *slave; 2702 2703 while (!list_empty(&gbe_dev->secondary_slaves)) { 2704 slave = first_sec_slave(gbe_dev); 2705 2706 if (slave->phy) 2707 phy_disconnect(slave->phy); 2708 list_del(&slave->slave_list); 2709 } 2710 if (gbe_dev->dummy_ndev) 2711 free_netdev(gbe_dev->dummy_ndev); 2712 } 2713 2714 static int set_xgbe_ethss10_priv(struct gbe_priv *gbe_dev, 2715 struct device_node *node) 2716 { 2717 struct resource res; 2718 void __iomem *regs; 2719 int ret, i; 2720 2721 ret = of_address_to_resource(node, XGBE_SS_REG_INDEX, &res); 2722 if (ret) { 2723 dev_err(gbe_dev->dev, 2724 "Can't xlate xgbe of node(%s) ss address at %d\n", 2725 node->name, XGBE_SS_REG_INDEX); 2726 return ret; 2727 } 2728 2729 regs = devm_ioremap_resource(gbe_dev->dev, &res); 2730 if (IS_ERR(regs)) { 2731 dev_err(gbe_dev->dev, "Failed to map xgbe ss register base\n"); 2732 return PTR_ERR(regs); 2733 } 2734 gbe_dev->ss_regs = regs; 2735 2736 ret = of_address_to_resource(node, XGBE_SM_REG_INDEX, &res); 2737 if (ret) { 2738 dev_err(gbe_dev->dev, 2739 "Can't xlate xgbe of node(%s) sm address at %d\n", 2740 node->name, XGBE_SM_REG_INDEX); 2741 return ret; 2742 } 2743 2744 regs = devm_ioremap_resource(gbe_dev->dev, &res); 2745 if (IS_ERR(regs)) { 2746 dev_err(gbe_dev->dev, "Failed to map xgbe sm register base\n"); 2747 return PTR_ERR(regs); 2748 } 2749 gbe_dev->switch_regs = regs; 2750 2751 ret = of_address_to_resource(node, XGBE_SERDES_REG_INDEX, &res); 2752 if (ret) { 2753 dev_err(gbe_dev->dev, 2754 "Can't xlate xgbe serdes of node(%s) address at %d\n", 2755 node->name, XGBE_SERDES_REG_INDEX); 2756 return ret; 2757 } 2758 2759 regs = devm_ioremap_resource(gbe_dev->dev, &res); 2760 if (IS_ERR(regs)) { 2761 dev_err(gbe_dev->dev, "Failed to map xgbe serdes register base\n"); 2762 return PTR_ERR(regs); 2763 } 2764 gbe_dev->xgbe_serdes_regs = regs; 2765 2766 gbe_dev->num_stats_mods = gbe_dev->max_num_ports; 2767 gbe_dev->et_stats = xgbe10_et_stats; 2768 gbe_dev->num_et_stats = ARRAY_SIZE(xgbe10_et_stats); 2769 2770 gbe_dev->hw_stats = devm_kzalloc(gbe_dev->dev, 2771 gbe_dev->num_et_stats * sizeof(u64), 2772 GFP_KERNEL); 2773 if (!gbe_dev->hw_stats) { 2774 dev_err(gbe_dev->dev, "hw_stats memory allocation failed\n"); 2775 return -ENOMEM; 2776 } 2777 2778 gbe_dev->hw_stats_prev = 2779 devm_kzalloc(gbe_dev->dev, 2780 gbe_dev->num_et_stats * sizeof(u32), 2781 GFP_KERNEL); 2782 if (!gbe_dev->hw_stats_prev) { 2783 dev_err(gbe_dev->dev, 2784 "hw_stats_prev memory allocation failed\n"); 2785 return -ENOMEM; 2786 } 2787 2788 gbe_dev->ss_version = XGBE_SS_VERSION_10; 2789 gbe_dev->sgmii_port_regs = gbe_dev->ss_regs + 2790 XGBE10_SGMII_MODULE_OFFSET; 2791 gbe_dev->host_port_regs = gbe_dev->ss_regs + XGBE10_HOST_PORT_OFFSET; 2792 2793 for (i = 0; i < gbe_dev->max_num_ports; i++) 2794 gbe_dev->hw_stats_regs[i] = gbe_dev->switch_regs + 2795 XGBE10_HW_STATS_OFFSET + (GBE_HW_STATS_REG_MAP_SZ * i); 2796 2797 gbe_dev->ale_reg = gbe_dev->switch_regs + XGBE10_ALE_OFFSET; 2798 gbe_dev->ale_ports = gbe_dev->max_num_ports; 2799 gbe_dev->host_port = XGBE10_HOST_PORT_NUM; 2800 gbe_dev->ale_entries = XGBE10_NUM_ALE_ENTRIES; 2801 gbe_dev->stats_en_mask = (1 << (gbe_dev->max_num_ports)) - 1; 2802 2803 /* Subsystem registers */ 2804 XGBE_SET_REG_OFS(gbe_dev, ss_regs, id_ver); 2805 XGBE_SET_REG_OFS(gbe_dev, ss_regs, control); 2806 2807 /* Switch module registers */ 2808 XGBE_SET_REG_OFS(gbe_dev, switch_regs, id_ver); 2809 XGBE_SET_REG_OFS(gbe_dev, switch_regs, control); 2810 XGBE_SET_REG_OFS(gbe_dev, switch_regs, ptype); 2811 XGBE_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en); 2812 XGBE_SET_REG_OFS(gbe_dev, switch_regs, flow_control); 2813 2814 /* Host port registers */ 2815 XGBE_SET_REG_OFS(gbe_dev, host_port_regs, port_vlan); 2816 XGBE_SET_REG_OFS(gbe_dev, host_port_regs, tx_pri_map); 2817 XGBE_SET_REG_OFS(gbe_dev, host_port_regs, rx_maxlen); 2818 return 0; 2819 } 2820 2821 static int get_gbe_resource_version(struct gbe_priv *gbe_dev, 2822 struct device_node *node) 2823 { 2824 struct resource res; 2825 void __iomem *regs; 2826 int ret; 2827 2828 ret = of_address_to_resource(node, GBE_SS_REG_INDEX, &res); 2829 if (ret) { 2830 dev_err(gbe_dev->dev, 2831 "Can't translate of node(%s) of gbe ss address at %d\n", 2832 node->name, GBE_SS_REG_INDEX); 2833 return ret; 2834 } 2835 2836 regs = devm_ioremap_resource(gbe_dev->dev, &res); 2837 if (IS_ERR(regs)) { 2838 dev_err(gbe_dev->dev, "Failed to map gbe register base\n"); 2839 return PTR_ERR(regs); 2840 } 2841 gbe_dev->ss_regs = regs; 2842 gbe_dev->ss_version = readl(gbe_dev->ss_regs); 2843 return 0; 2844 } 2845 2846 static int set_gbe_ethss14_priv(struct gbe_priv *gbe_dev, 2847 struct device_node *node) 2848 { 2849 struct resource res; 2850 void __iomem *regs; 2851 int i, ret; 2852 2853 ret = of_address_to_resource(node, GBE_SGMII34_REG_INDEX, &res); 2854 if (ret) { 2855 dev_err(gbe_dev->dev, 2856 "Can't translate of gbe node(%s) address at index %d\n", 2857 node->name, GBE_SGMII34_REG_INDEX); 2858 return ret; 2859 } 2860 2861 regs = devm_ioremap_resource(gbe_dev->dev, &res); 2862 if (IS_ERR(regs)) { 2863 dev_err(gbe_dev->dev, 2864 "Failed to map gbe sgmii port34 register base\n"); 2865 return PTR_ERR(regs); 2866 } 2867 gbe_dev->sgmii_port34_regs = regs; 2868 2869 ret = of_address_to_resource(node, GBE_SM_REG_INDEX, &res); 2870 if (ret) { 2871 dev_err(gbe_dev->dev, 2872 "Can't translate of gbe node(%s) address at index %d\n", 2873 node->name, GBE_SM_REG_INDEX); 2874 return ret; 2875 } 2876 2877 regs = devm_ioremap_resource(gbe_dev->dev, &res); 2878 if (IS_ERR(regs)) { 2879 dev_err(gbe_dev->dev, 2880 "Failed to map gbe switch module register base\n"); 2881 return PTR_ERR(regs); 2882 } 2883 gbe_dev->switch_regs = regs; 2884 2885 gbe_dev->num_stats_mods = gbe_dev->max_num_slaves; 2886 gbe_dev->et_stats = gbe13_et_stats; 2887 gbe_dev->num_et_stats = ARRAY_SIZE(gbe13_et_stats); 2888 2889 gbe_dev->hw_stats = devm_kzalloc(gbe_dev->dev, 2890 gbe_dev->num_et_stats * sizeof(u64), 2891 GFP_KERNEL); 2892 if (!gbe_dev->hw_stats) { 2893 dev_err(gbe_dev->dev, "hw_stats memory allocation failed\n"); 2894 return -ENOMEM; 2895 } 2896 2897 gbe_dev->hw_stats_prev = 2898 devm_kzalloc(gbe_dev->dev, 2899 gbe_dev->num_et_stats * sizeof(u32), 2900 GFP_KERNEL); 2901 if (!gbe_dev->hw_stats_prev) { 2902 dev_err(gbe_dev->dev, 2903 "hw_stats_prev memory allocation failed\n"); 2904 return -ENOMEM; 2905 } 2906 2907 gbe_dev->sgmii_port_regs = gbe_dev->ss_regs + GBE13_SGMII_MODULE_OFFSET; 2908 gbe_dev->host_port_regs = gbe_dev->switch_regs + GBE13_HOST_PORT_OFFSET; 2909 2910 /* K2HK has only 2 hw stats modules visible at a time, so 2911 * module 0 & 2 points to one base and 2912 * module 1 & 3 points to the other base 2913 */ 2914 for (i = 0; i < gbe_dev->max_num_slaves; i++) { 2915 gbe_dev->hw_stats_regs[i] = 2916 gbe_dev->switch_regs + GBE13_HW_STATS_OFFSET + 2917 (GBE_HW_STATS_REG_MAP_SZ * (i & 0x1)); 2918 } 2919 2920 gbe_dev->ale_reg = gbe_dev->switch_regs + GBE13_ALE_OFFSET; 2921 gbe_dev->ale_ports = gbe_dev->max_num_ports; 2922 gbe_dev->host_port = GBE13_HOST_PORT_NUM; 2923 gbe_dev->ale_entries = GBE13_NUM_ALE_ENTRIES; 2924 gbe_dev->stats_en_mask = GBE13_REG_VAL_STAT_ENABLE_ALL; 2925 2926 /* Subsystem registers */ 2927 GBE_SET_REG_OFS(gbe_dev, ss_regs, id_ver); 2928 2929 /* Switch module registers */ 2930 GBE_SET_REG_OFS(gbe_dev, switch_regs, id_ver); 2931 GBE_SET_REG_OFS(gbe_dev, switch_regs, control); 2932 GBE_SET_REG_OFS(gbe_dev, switch_regs, soft_reset); 2933 GBE_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en); 2934 GBE_SET_REG_OFS(gbe_dev, switch_regs, ptype); 2935 GBE_SET_REG_OFS(gbe_dev, switch_regs, flow_control); 2936 2937 /* Host port registers */ 2938 GBE_SET_REG_OFS(gbe_dev, host_port_regs, port_vlan); 2939 GBE_SET_REG_OFS(gbe_dev, host_port_regs, rx_maxlen); 2940 return 0; 2941 } 2942 2943 static int set_gbenu_ethss_priv(struct gbe_priv *gbe_dev, 2944 struct device_node *node) 2945 { 2946 struct resource res; 2947 void __iomem *regs; 2948 int i, ret; 2949 2950 gbe_dev->num_stats_mods = gbe_dev->max_num_ports; 2951 gbe_dev->et_stats = gbenu_et_stats; 2952 2953 if (IS_SS_ID_NU(gbe_dev)) 2954 gbe_dev->num_et_stats = GBENU_ET_STATS_HOST_SIZE + 2955 (gbe_dev->max_num_slaves * GBENU_ET_STATS_PORT_SIZE); 2956 else 2957 gbe_dev->num_et_stats = GBENU_ET_STATS_HOST_SIZE + 2958 GBENU_ET_STATS_PORT_SIZE; 2959 2960 gbe_dev->hw_stats = devm_kzalloc(gbe_dev->dev, 2961 gbe_dev->num_et_stats * sizeof(u64), 2962 GFP_KERNEL); 2963 if (!gbe_dev->hw_stats) { 2964 dev_err(gbe_dev->dev, "hw_stats memory allocation failed\n"); 2965 return -ENOMEM; 2966 } 2967 2968 gbe_dev->hw_stats_prev = 2969 devm_kzalloc(gbe_dev->dev, 2970 gbe_dev->num_et_stats * sizeof(u32), 2971 GFP_KERNEL); 2972 if (!gbe_dev->hw_stats_prev) { 2973 dev_err(gbe_dev->dev, 2974 "hw_stats_prev memory allocation failed\n"); 2975 return -ENOMEM; 2976 } 2977 2978 ret = of_address_to_resource(node, GBENU_SM_REG_INDEX, &res); 2979 if (ret) { 2980 dev_err(gbe_dev->dev, 2981 "Can't translate of gbenu node(%s) addr at index %d\n", 2982 node->name, GBENU_SM_REG_INDEX); 2983 return ret; 2984 } 2985 2986 regs = devm_ioremap_resource(gbe_dev->dev, &res); 2987 if (IS_ERR(regs)) { 2988 dev_err(gbe_dev->dev, 2989 "Failed to map gbenu switch module register base\n"); 2990 return PTR_ERR(regs); 2991 } 2992 gbe_dev->switch_regs = regs; 2993 2994 gbe_dev->sgmii_port_regs = gbe_dev->ss_regs + GBENU_SGMII_MODULE_OFFSET; 2995 2996 /* Although sgmii modules are mem mapped to one contiguous 2997 * region on GBENU devices, setting sgmii_port34_regs allows 2998 * consistent code when accessing sgmii api 2999 */ 3000 gbe_dev->sgmii_port34_regs = gbe_dev->sgmii_port_regs + 3001 (2 * GBENU_SGMII_MODULE_SIZE); 3002 3003 gbe_dev->host_port_regs = gbe_dev->switch_regs + GBENU_HOST_PORT_OFFSET; 3004 3005 for (i = 0; i < (gbe_dev->max_num_ports); i++) 3006 gbe_dev->hw_stats_regs[i] = gbe_dev->switch_regs + 3007 GBENU_HW_STATS_OFFSET + (GBENU_HW_STATS_REG_MAP_SZ * i); 3008 3009 gbe_dev->ale_reg = gbe_dev->switch_regs + GBENU_ALE_OFFSET; 3010 gbe_dev->ale_ports = gbe_dev->max_num_ports; 3011 gbe_dev->host_port = GBENU_HOST_PORT_NUM; 3012 gbe_dev->ale_entries = GBE13_NUM_ALE_ENTRIES; 3013 gbe_dev->stats_en_mask = (1 << (gbe_dev->max_num_ports)) - 1; 3014 3015 /* Subsystem registers */ 3016 GBENU_SET_REG_OFS(gbe_dev, ss_regs, id_ver); 3017 3018 /* Switch module registers */ 3019 GBENU_SET_REG_OFS(gbe_dev, switch_regs, id_ver); 3020 GBENU_SET_REG_OFS(gbe_dev, switch_regs, control); 3021 GBENU_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en); 3022 GBENU_SET_REG_OFS(gbe_dev, switch_regs, ptype); 3023 3024 /* Host port registers */ 3025 GBENU_SET_REG_OFS(gbe_dev, host_port_regs, port_vlan); 3026 GBENU_SET_REG_OFS(gbe_dev, host_port_regs, rx_maxlen); 3027 3028 /* For NU only. 2U does not need tx_pri_map. 3029 * NU cppi port 0 tx pkt streaming interface has (n-1)*8 egress threads 3030 * while 2U has only 1 such thread 3031 */ 3032 GBENU_SET_REG_OFS(gbe_dev, host_port_regs, tx_pri_map); 3033 return 0; 3034 } 3035 3036 static int gbe_probe(struct netcp_device *netcp_device, struct device *dev, 3037 struct device_node *node, void **inst_priv) 3038 { 3039 struct device_node *interfaces, *interface; 3040 struct device_node *secondary_ports; 3041 struct cpsw_ale_params ale_params; 3042 struct gbe_priv *gbe_dev; 3043 u32 slave_num; 3044 int i, ret = 0; 3045 3046 if (!node) { 3047 dev_err(dev, "device tree info unavailable\n"); 3048 return -ENODEV; 3049 } 3050 3051 gbe_dev = devm_kzalloc(dev, sizeof(struct gbe_priv), GFP_KERNEL); 3052 if (!gbe_dev) 3053 return -ENOMEM; 3054 3055 if (of_device_is_compatible(node, "ti,netcp-gbe-5") || 3056 of_device_is_compatible(node, "ti,netcp-gbe")) { 3057 gbe_dev->max_num_slaves = 4; 3058 } else if (of_device_is_compatible(node, "ti,netcp-gbe-9")) { 3059 gbe_dev->max_num_slaves = 8; 3060 } else if (of_device_is_compatible(node, "ti,netcp-gbe-2")) { 3061 gbe_dev->max_num_slaves = 1; 3062 } else if (of_device_is_compatible(node, "ti,netcp-xgbe")) { 3063 gbe_dev->max_num_slaves = 2; 3064 } else { 3065 dev_err(dev, "device tree node for unknown device\n"); 3066 return -EINVAL; 3067 } 3068 gbe_dev->max_num_ports = gbe_dev->max_num_slaves + 1; 3069 3070 gbe_dev->dev = dev; 3071 gbe_dev->netcp_device = netcp_device; 3072 gbe_dev->rx_packet_max = NETCP_MAX_FRAME_SIZE; 3073 3074 /* init the hw stats lock */ 3075 spin_lock_init(&gbe_dev->hw_stats_lock); 3076 3077 if (of_find_property(node, "enable-ale", NULL)) { 3078 gbe_dev->enable_ale = true; 3079 dev_info(dev, "ALE enabled\n"); 3080 } else { 3081 gbe_dev->enable_ale = false; 3082 dev_dbg(dev, "ALE bypass enabled*\n"); 3083 } 3084 3085 ret = of_property_read_u32(node, "tx-queue", 3086 &gbe_dev->tx_queue_id); 3087 if (ret < 0) { 3088 dev_err(dev, "missing tx_queue parameter\n"); 3089 gbe_dev->tx_queue_id = GBE_TX_QUEUE; 3090 } 3091 3092 ret = of_property_read_string(node, "tx-channel", 3093 &gbe_dev->dma_chan_name); 3094 if (ret < 0) { 3095 dev_err(dev, "missing \"tx-channel\" parameter\n"); 3096 return -EINVAL; 3097 } 3098 3099 if (!strcmp(node->name, "gbe")) { 3100 ret = get_gbe_resource_version(gbe_dev, node); 3101 if (ret) 3102 return ret; 3103 3104 dev_dbg(dev, "ss_version: 0x%08x\n", gbe_dev->ss_version); 3105 3106 if (gbe_dev->ss_version == GBE_SS_VERSION_14) 3107 ret = set_gbe_ethss14_priv(gbe_dev, node); 3108 else if (IS_SS_ID_MU(gbe_dev)) 3109 ret = set_gbenu_ethss_priv(gbe_dev, node); 3110 else 3111 ret = -ENODEV; 3112 3113 } else if (!strcmp(node->name, "xgbe")) { 3114 ret = set_xgbe_ethss10_priv(gbe_dev, node); 3115 if (ret) 3116 return ret; 3117 ret = netcp_xgbe_serdes_init(gbe_dev->xgbe_serdes_regs, 3118 gbe_dev->ss_regs); 3119 } else { 3120 dev_err(dev, "unknown GBE node(%s)\n", node->name); 3121 ret = -ENODEV; 3122 } 3123 3124 if (ret) 3125 return ret; 3126 3127 interfaces = of_get_child_by_name(node, "interfaces"); 3128 if (!interfaces) 3129 dev_err(dev, "could not find interfaces\n"); 3130 3131 ret = netcp_txpipe_init(&gbe_dev->tx_pipe, netcp_device, 3132 gbe_dev->dma_chan_name, gbe_dev->tx_queue_id); 3133 if (ret) 3134 return ret; 3135 3136 ret = netcp_txpipe_open(&gbe_dev->tx_pipe); 3137 if (ret) 3138 return ret; 3139 3140 /* Create network interfaces */ 3141 INIT_LIST_HEAD(&gbe_dev->gbe_intf_head); 3142 for_each_child_of_node(interfaces, interface) { 3143 ret = of_property_read_u32(interface, "slave-port", &slave_num); 3144 if (ret) { 3145 dev_err(dev, "missing slave-port parameter, skipping interface configuration for %s\n", 3146 interface->name); 3147 continue; 3148 } 3149 gbe_dev->num_slaves++; 3150 if (gbe_dev->num_slaves >= gbe_dev->max_num_slaves) { 3151 of_node_put(interface); 3152 break; 3153 } 3154 } 3155 of_node_put(interfaces); 3156 3157 if (!gbe_dev->num_slaves) 3158 dev_warn(dev, "No network interface configured\n"); 3159 3160 /* Initialize Secondary slave ports */ 3161 secondary_ports = of_get_child_by_name(node, "secondary-slave-ports"); 3162 INIT_LIST_HEAD(&gbe_dev->secondary_slaves); 3163 if (secondary_ports && (gbe_dev->num_slaves < gbe_dev->max_num_slaves)) 3164 init_secondary_ports(gbe_dev, secondary_ports); 3165 of_node_put(secondary_ports); 3166 3167 if (!gbe_dev->num_slaves) { 3168 dev_err(dev, 3169 "No network interface or secondary ports configured\n"); 3170 ret = -ENODEV; 3171 goto free_sec_ports; 3172 } 3173 3174 memset(&ale_params, 0, sizeof(ale_params)); 3175 ale_params.dev = gbe_dev->dev; 3176 ale_params.ale_regs = gbe_dev->ale_reg; 3177 ale_params.ale_ageout = GBE_DEFAULT_ALE_AGEOUT; 3178 ale_params.ale_entries = gbe_dev->ale_entries; 3179 ale_params.ale_ports = gbe_dev->ale_ports; 3180 3181 gbe_dev->ale = cpsw_ale_create(&ale_params); 3182 if (!gbe_dev->ale) { 3183 dev_err(gbe_dev->dev, "error initializing ale engine\n"); 3184 ret = -ENODEV; 3185 goto free_sec_ports; 3186 } else { 3187 dev_dbg(gbe_dev->dev, "Created a gbe ale engine\n"); 3188 } 3189 3190 /* initialize host port */ 3191 gbe_init_host_port(gbe_dev); 3192 3193 spin_lock_bh(&gbe_dev->hw_stats_lock); 3194 for (i = 0; i < gbe_dev->num_stats_mods; i++) { 3195 if (gbe_dev->ss_version == GBE_SS_VERSION_14) 3196 gbe_reset_mod_stats_ver14(gbe_dev, i); 3197 else 3198 gbe_reset_mod_stats(gbe_dev, i); 3199 } 3200 spin_unlock_bh(&gbe_dev->hw_stats_lock); 3201 3202 init_timer(&gbe_dev->timer); 3203 gbe_dev->timer.data = (unsigned long)gbe_dev; 3204 gbe_dev->timer.function = netcp_ethss_timer; 3205 gbe_dev->timer.expires = jiffies + GBE_TIMER_INTERVAL; 3206 add_timer(&gbe_dev->timer); 3207 *inst_priv = gbe_dev; 3208 return 0; 3209 3210 free_sec_ports: 3211 free_secondary_ports(gbe_dev); 3212 return ret; 3213 } 3214 3215 static int gbe_attach(void *inst_priv, struct net_device *ndev, 3216 struct device_node *node, void **intf_priv) 3217 { 3218 struct gbe_priv *gbe_dev = inst_priv; 3219 struct gbe_intf *gbe_intf; 3220 int ret; 3221 3222 if (!node) { 3223 dev_err(gbe_dev->dev, "interface node not available\n"); 3224 return -ENODEV; 3225 } 3226 3227 gbe_intf = devm_kzalloc(gbe_dev->dev, sizeof(*gbe_intf), GFP_KERNEL); 3228 if (!gbe_intf) 3229 return -ENOMEM; 3230 3231 gbe_intf->ndev = ndev; 3232 gbe_intf->dev = gbe_dev->dev; 3233 gbe_intf->gbe_dev = gbe_dev; 3234 3235 gbe_intf->slave = devm_kzalloc(gbe_dev->dev, 3236 sizeof(*gbe_intf->slave), 3237 GFP_KERNEL); 3238 if (!gbe_intf->slave) { 3239 ret = -ENOMEM; 3240 goto fail; 3241 } 3242 3243 if (init_slave(gbe_dev, gbe_intf->slave, node)) { 3244 ret = -ENODEV; 3245 goto fail; 3246 } 3247 3248 gbe_intf->tx_pipe = gbe_dev->tx_pipe; 3249 ndev->ethtool_ops = &keystone_ethtool_ops; 3250 list_add_tail(&gbe_intf->gbe_intf_list, &gbe_dev->gbe_intf_head); 3251 *intf_priv = gbe_intf; 3252 return 0; 3253 3254 fail: 3255 if (gbe_intf->slave) 3256 devm_kfree(gbe_dev->dev, gbe_intf->slave); 3257 if (gbe_intf) 3258 devm_kfree(gbe_dev->dev, gbe_intf); 3259 return ret; 3260 } 3261 3262 static int gbe_release(void *intf_priv) 3263 { 3264 struct gbe_intf *gbe_intf = intf_priv; 3265 3266 gbe_intf->ndev->ethtool_ops = NULL; 3267 list_del(&gbe_intf->gbe_intf_list); 3268 devm_kfree(gbe_intf->dev, gbe_intf->slave); 3269 devm_kfree(gbe_intf->dev, gbe_intf); 3270 return 0; 3271 } 3272 3273 static int gbe_remove(struct netcp_device *netcp_device, void *inst_priv) 3274 { 3275 struct gbe_priv *gbe_dev = inst_priv; 3276 3277 del_timer_sync(&gbe_dev->timer); 3278 cpsw_ale_stop(gbe_dev->ale); 3279 cpsw_ale_destroy(gbe_dev->ale); 3280 netcp_txpipe_close(&gbe_dev->tx_pipe); 3281 free_secondary_ports(gbe_dev); 3282 3283 if (!list_empty(&gbe_dev->gbe_intf_head)) 3284 dev_alert(gbe_dev->dev, 3285 "unreleased ethss interfaces present\n"); 3286 3287 return 0; 3288 } 3289 3290 static struct netcp_module gbe_module = { 3291 .name = GBE_MODULE_NAME, 3292 .owner = THIS_MODULE, 3293 .primary = true, 3294 .probe = gbe_probe, 3295 .open = gbe_open, 3296 .close = gbe_close, 3297 .remove = gbe_remove, 3298 .attach = gbe_attach, 3299 .release = gbe_release, 3300 .add_addr = gbe_add_addr, 3301 .del_addr = gbe_del_addr, 3302 .add_vid = gbe_add_vid, 3303 .del_vid = gbe_del_vid, 3304 .ioctl = gbe_ioctl, 3305 }; 3306 3307 static struct netcp_module xgbe_module = { 3308 .name = XGBE_MODULE_NAME, 3309 .owner = THIS_MODULE, 3310 .primary = true, 3311 .probe = gbe_probe, 3312 .open = gbe_open, 3313 .close = gbe_close, 3314 .remove = gbe_remove, 3315 .attach = gbe_attach, 3316 .release = gbe_release, 3317 .add_addr = gbe_add_addr, 3318 .del_addr = gbe_del_addr, 3319 .add_vid = gbe_add_vid, 3320 .del_vid = gbe_del_vid, 3321 .ioctl = gbe_ioctl, 3322 }; 3323 3324 static int __init keystone_gbe_init(void) 3325 { 3326 int ret; 3327 3328 ret = netcp_register_module(&gbe_module); 3329 if (ret) 3330 return ret; 3331 3332 ret = netcp_register_module(&xgbe_module); 3333 if (ret) 3334 return ret; 3335 3336 return 0; 3337 } 3338 module_init(keystone_gbe_init); 3339 3340 static void __exit keystone_gbe_exit(void) 3341 { 3342 netcp_unregister_module(&gbe_module); 3343 netcp_unregister_module(&xgbe_module); 3344 } 3345 module_exit(keystone_gbe_exit); 3346 3347 MODULE_LICENSE("GPL v2"); 3348 MODULE_DESCRIPTION("TI NETCP ETHSS driver for Keystone SOCs"); 3349 MODULE_AUTHOR("Sandeep Nair <sandeep_n@ti.com"); 3350