1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Texas Instruments ICSSG Ethernet driver 3 * 4 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 */ 7 8 #ifndef __NET_TI_ICSSG_PRUETH_H 9 #define __NET_TI_ICSSG_PRUETH_H 10 11 #include <linux/etherdevice.h> 12 #include <linux/genalloc.h> 13 #include <linux/if_vlan.h> 14 #include <linux/interrupt.h> 15 #include <linux/kernel.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/of.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_mdio.h> 23 #include <linux/of_net.h> 24 #include <linux/of_platform.h> 25 #include <linux/phy.h> 26 #include <linux/remoteproc/pruss.h> 27 #include <linux/pruss_driver.h> 28 #include <linux/ptp_clock_kernel.h> 29 #include <linux/remoteproc.h> 30 31 #include <linux/dma-mapping.h> 32 #include <linux/dma/ti-cppi5.h> 33 #include <linux/dma/k3-udma-glue.h> 34 35 #include <net/devlink.h> 36 37 #include "icssg_config.h" 38 #include "icssg_switch_map.h" 39 40 #define PRUETH_MAX_MTU (2000 - ETH_HLEN - ETH_FCS_LEN) 41 #define PRUETH_MIN_PKT_SIZE (VLAN_ETH_ZLEN) 42 #define PRUETH_MAX_PKT_SIZE (PRUETH_MAX_MTU + ETH_HLEN + ETH_FCS_LEN) 43 44 #define ICSS_SLICE0 0 45 #define ICSS_SLICE1 1 46 47 #define ICSS_FW_PRU 0 48 #define ICSS_FW_RTU 1 49 50 #define ICSSG_MAX_RFLOWS 8 /* per slice */ 51 52 /* Number of ICSSG related stats */ 53 #define ICSSG_NUM_STATS 60 54 #define ICSSG_NUM_STANDARD_STATS 31 55 56 /* Firmware status codes */ 57 #define ICSS_HS_FW_READY 0x55555555 58 #define ICSS_HS_FW_DEAD 0xDEAD0000 /* lower 16 bits contain error code */ 59 60 /* Firmware command codes */ 61 #define ICSS_HS_CMD_BUSY 0x40000000 62 #define ICSS_HS_CMD_DONE 0x80000000 63 #define ICSS_HS_CMD_CANCEL 0x10000000 64 65 /* Firmware commands */ 66 #define ICSS_CMD_SPAD 0x20 67 #define ICSS_CMD_RXTX 0x10 68 #define ICSS_CMD_ADD_FDB 0x1 69 #define ICSS_CMD_DEL_FDB 0x2 70 #define ICSS_CMD_SET_RUN 0x4 71 #define ICSS_CMD_GET_FDB_SLOT 0x5 72 #define ICSS_CMD_ENABLE_VLAN 0x5 73 #define ICSS_CMD_DISABLE_VLAN 0x6 74 #define ICSS_CMD_ADD_FILTER 0x7 75 #define ICSS_CMD_ADD_MAC 0x8 76 77 /* In switch mode there are 3 real ports i.e. 3 mac addrs. 78 * however Linux sees only the host side port. The other 2 ports 79 * are the switch ports. 80 * In emac mode there are 2 real ports i.e. 2 mac addrs. 81 * Linux sees both the ports. 82 */ 83 enum prueth_port { 84 PRUETH_PORT_HOST = 0, /* host side port */ 85 PRUETH_PORT_MII0, /* physical port RG/SG MII 0 */ 86 PRUETH_PORT_MII1, /* physical port RG/SG MII 1 */ 87 PRUETH_PORT_INVALID, /* Invalid prueth port */ 88 }; 89 90 enum prueth_mac { 91 PRUETH_MAC0 = 0, 92 PRUETH_MAC1, 93 PRUETH_NUM_MACS, 94 PRUETH_MAC_INVALID, 95 }; 96 97 struct prueth_tx_chn { 98 struct device *dma_dev; 99 struct napi_struct napi_tx; 100 struct k3_cppi_desc_pool *desc_pool; 101 struct k3_udma_glue_tx_channel *tx_chn; 102 struct prueth_emac *emac; 103 u32 id; 104 u32 descs_num; 105 unsigned int irq; 106 char name[32]; 107 }; 108 109 struct prueth_rx_chn { 110 struct device *dev; 111 struct device *dma_dev; 112 struct k3_cppi_desc_pool *desc_pool; 113 struct k3_udma_glue_rx_channel *rx_chn; 114 u32 descs_num; 115 unsigned int irq[ICSSG_MAX_RFLOWS]; /* separate irq per flow */ 116 char name[32]; 117 }; 118 119 /* There are 4 Tx DMA channels, but the highest priority is CH3 (thread 3) 120 * and lower three are lower priority channels or threads. 121 */ 122 #define PRUETH_MAX_TX_QUEUES 4 123 124 /* data for each emac port */ 125 struct prueth_emac { 126 bool fw_running; 127 struct prueth *prueth; 128 struct net_device *ndev; 129 u8 mac_addr[6]; 130 struct napi_struct napi_rx; 131 u32 msg_enable; 132 133 int link; 134 int speed; 135 int duplex; 136 137 const char *phy_id; 138 struct device_node *phy_node; 139 phy_interface_t phy_if; 140 enum prueth_port port_id; 141 142 /* DMA related */ 143 struct prueth_tx_chn tx_chns[PRUETH_MAX_TX_QUEUES]; 144 struct completion tdown_complete; 145 atomic_t tdown_cnt; 146 struct prueth_rx_chn rx_chns; 147 int rx_flow_id_base; 148 int tx_ch_num; 149 150 spinlock_t lock; /* serialize access */ 151 152 unsigned long state; 153 struct completion cmd_complete; 154 /* Mutex to serialize access to firmware command interface */ 155 struct mutex cmd_lock; 156 struct work_struct rx_mode_work; 157 struct workqueue_struct *cmd_wq; 158 159 struct pruss_mem_region dram; 160 161 struct delayed_work stats_work; 162 u64 stats[ICSSG_NUM_STATS]; 163 }; 164 165 /** 166 * struct prueth_pdata - PRUeth platform data 167 * @fdqring_mode: Free desc queue mode 168 * @quirk_10m_link_issue: 10M link detect errata 169 */ 170 struct prueth_pdata { 171 enum k3_ring_mode fdqring_mode; 172 u32 quirk_10m_link_issue:1; 173 }; 174 175 /** 176 * struct prueth - PRUeth structure 177 * @dev: device 178 * @pruss: pruss handle 179 * @pru: rproc instances of PRUs 180 * @rtu: rproc instances of RTUs 181 * @txpru: rproc instances of TX_PRUs 182 * @shram: PRUSS shared RAM region 183 * @sram_pool: MSMC RAM pool for buffers 184 * @msmcram: MSMC RAM region 185 * @eth_node: DT node for the port 186 * @emac: private EMAC data structure 187 * @registered_netdevs: list of registered netdevs 188 * @miig_rt: regmap to mii_g_rt block 189 * @mii_rt: regmap to mii_rt block 190 * @pru_id: ID for each of the PRUs 191 * @pdev: pointer to ICSSG platform device 192 * @pdata: pointer to platform data for ICSSG driver 193 * @icssg_hwcmdseq: seq counter or HWQ messages 194 * @emacs_initialized: num of EMACs/ext ports that are up/running 195 */ 196 struct prueth { 197 struct device *dev; 198 struct pruss *pruss; 199 struct rproc *pru[PRUSS_NUM_PRUS]; 200 struct rproc *rtu[PRUSS_NUM_PRUS]; 201 struct rproc *txpru[PRUSS_NUM_PRUS]; 202 struct pruss_mem_region shram; 203 struct gen_pool *sram_pool; 204 struct pruss_mem_region msmcram; 205 206 struct device_node *eth_node[PRUETH_NUM_MACS]; 207 struct prueth_emac *emac[PRUETH_NUM_MACS]; 208 struct net_device *registered_netdevs[PRUETH_NUM_MACS]; 209 struct regmap *miig_rt; 210 struct regmap *mii_rt; 211 212 enum pruss_pru_id pru_id[PRUSS_NUM_PRUS]; 213 struct platform_device *pdev; 214 struct prueth_pdata pdata; 215 u8 icssg_hwcmdseq; 216 217 int emacs_initialized; 218 }; 219 220 /* get PRUSS SLICE number from prueth_emac */ 221 static inline int prueth_emac_slice(struct prueth_emac *emac) 222 { 223 switch (emac->port_id) { 224 case PRUETH_PORT_MII0: 225 return ICSS_SLICE0; 226 case PRUETH_PORT_MII1: 227 return ICSS_SLICE1; 228 default: 229 return -EINVAL; 230 } 231 } 232 233 /* Classifier helpers */ 234 void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac); 235 void icssg_class_set_host_mac_addr(struct regmap *miig_rt, const u8 *mac); 236 void icssg_class_disable(struct regmap *miig_rt, int slice); 237 void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti); 238 void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr); 239 240 /* config helpers */ 241 void icssg_config_ipg(struct prueth_emac *emac); 242 int icssg_config(struct prueth *prueth, struct prueth_emac *emac, 243 int slice); 244 int emac_set_port_state(struct prueth_emac *emac, 245 enum icssg_port_state_cmd state); 246 void icssg_config_set_speed(struct prueth_emac *emac); 247 248 /* Buffer queue helpers */ 249 int icssg_queue_pop(struct prueth *prueth, u8 queue); 250 void icssg_queue_push(struct prueth *prueth, int queue, u16 addr); 251 u32 icssg_queue_level(struct prueth *prueth, int queue); 252 253 #define prueth_napi_to_tx_chn(pnapi) \ 254 container_of(pnapi, struct prueth_tx_chn, napi_tx) 255 256 void emac_stats_work_handler(struct work_struct *work); 257 void emac_update_hardware_stats(struct prueth_emac *emac); 258 int emac_get_stat_by_name(struct prueth_emac *emac, char *stat_name); 259 #endif /* __NET_TI_ICSSG_PRUETH_H */ 260