1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Texas Instruments ICSSG Ethernet driver 3 * 4 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 */ 7 8 #ifndef __NET_TI_ICSSG_PRUETH_H 9 #define __NET_TI_ICSSG_PRUETH_H 10 11 #include <linux/etherdevice.h> 12 #include <linux/genalloc.h> 13 #include <linux/if_vlan.h> 14 #include <linux/interrupt.h> 15 #include <linux/kernel.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/of.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_mdio.h> 23 #include <linux/of_net.h> 24 #include <linux/of_platform.h> 25 #include <linux/phy.h> 26 #include <linux/remoteproc/pruss.h> 27 #include <linux/pruss_driver.h> 28 #include <linux/ptp_clock_kernel.h> 29 #include <linux/remoteproc.h> 30 31 #include <linux/dma-mapping.h> 32 #include <linux/dma/ti-cppi5.h> 33 #include <linux/dma/k3-udma-glue.h> 34 35 #include <net/devlink.h> 36 37 #include "icssg_config.h" 38 #include "icssg_switch_map.h" 39 40 #define PRUETH_MAX_MTU (2000 - ETH_HLEN - ETH_FCS_LEN) 41 #define PRUETH_MIN_PKT_SIZE (VLAN_ETH_ZLEN) 42 #define PRUETH_MAX_PKT_SIZE (PRUETH_MAX_MTU + ETH_HLEN + ETH_FCS_LEN) 43 44 #define ICSS_SLICE0 0 45 #define ICSS_SLICE1 1 46 47 #define ICSS_FW_PRU 0 48 #define ICSS_FW_RTU 1 49 50 #define ICSSG_MAX_RFLOWS 8 /* per slice */ 51 52 /* Number of ICSSG related stats */ 53 #define ICSSG_NUM_STATS 60 54 55 /* Firmware status codes */ 56 #define ICSS_HS_FW_READY 0x55555555 57 #define ICSS_HS_FW_DEAD 0xDEAD0000 /* lower 16 bits contain error code */ 58 59 /* Firmware command codes */ 60 #define ICSS_HS_CMD_BUSY 0x40000000 61 #define ICSS_HS_CMD_DONE 0x80000000 62 #define ICSS_HS_CMD_CANCEL 0x10000000 63 64 /* Firmware commands */ 65 #define ICSS_CMD_SPAD 0x20 66 #define ICSS_CMD_RXTX 0x10 67 #define ICSS_CMD_ADD_FDB 0x1 68 #define ICSS_CMD_DEL_FDB 0x2 69 #define ICSS_CMD_SET_RUN 0x4 70 #define ICSS_CMD_GET_FDB_SLOT 0x5 71 #define ICSS_CMD_ENABLE_VLAN 0x5 72 #define ICSS_CMD_DISABLE_VLAN 0x6 73 #define ICSS_CMD_ADD_FILTER 0x7 74 #define ICSS_CMD_ADD_MAC 0x8 75 76 /* In switch mode there are 3 real ports i.e. 3 mac addrs. 77 * however Linux sees only the host side port. The other 2 ports 78 * are the switch ports. 79 * In emac mode there are 2 real ports i.e. 2 mac addrs. 80 * Linux sees both the ports. 81 */ 82 enum prueth_port { 83 PRUETH_PORT_HOST = 0, /* host side port */ 84 PRUETH_PORT_MII0, /* physical port RG/SG MII 0 */ 85 PRUETH_PORT_MII1, /* physical port RG/SG MII 1 */ 86 PRUETH_PORT_INVALID, /* Invalid prueth port */ 87 }; 88 89 enum prueth_mac { 90 PRUETH_MAC0 = 0, 91 PRUETH_MAC1, 92 PRUETH_NUM_MACS, 93 PRUETH_MAC_INVALID, 94 }; 95 96 struct prueth_tx_chn { 97 struct device *dma_dev; 98 struct napi_struct napi_tx; 99 struct k3_cppi_desc_pool *desc_pool; 100 struct k3_udma_glue_tx_channel *tx_chn; 101 struct prueth_emac *emac; 102 u32 id; 103 u32 descs_num; 104 unsigned int irq; 105 char name[32]; 106 }; 107 108 struct prueth_rx_chn { 109 struct device *dev; 110 struct device *dma_dev; 111 struct k3_cppi_desc_pool *desc_pool; 112 struct k3_udma_glue_rx_channel *rx_chn; 113 u32 descs_num; 114 unsigned int irq[ICSSG_MAX_RFLOWS]; /* separate irq per flow */ 115 char name[32]; 116 }; 117 118 /* There are 4 Tx DMA channels, but the highest priority is CH3 (thread 3) 119 * and lower three are lower priority channels or threads. 120 */ 121 #define PRUETH_MAX_TX_QUEUES 4 122 123 /* data for each emac port */ 124 struct prueth_emac { 125 bool fw_running; 126 struct prueth *prueth; 127 struct net_device *ndev; 128 u8 mac_addr[6]; 129 struct napi_struct napi_rx; 130 u32 msg_enable; 131 132 int link; 133 int speed; 134 int duplex; 135 136 const char *phy_id; 137 struct device_node *phy_node; 138 phy_interface_t phy_if; 139 enum prueth_port port_id; 140 141 /* DMA related */ 142 struct prueth_tx_chn tx_chns[PRUETH_MAX_TX_QUEUES]; 143 struct completion tdown_complete; 144 atomic_t tdown_cnt; 145 struct prueth_rx_chn rx_chns; 146 int rx_flow_id_base; 147 int tx_ch_num; 148 149 spinlock_t lock; /* serialize access */ 150 151 unsigned long state; 152 struct completion cmd_complete; 153 /* Mutex to serialize access to firmware command interface */ 154 struct mutex cmd_lock; 155 struct work_struct rx_mode_work; 156 struct workqueue_struct *cmd_wq; 157 158 struct pruss_mem_region dram; 159 160 struct delayed_work stats_work; 161 u64 stats[ICSSG_NUM_STATS]; 162 }; 163 164 /** 165 * struct prueth_pdata - PRUeth platform data 166 * @fdqring_mode: Free desc queue mode 167 * @quirk_10m_link_issue: 10M link detect errata 168 */ 169 struct prueth_pdata { 170 enum k3_ring_mode fdqring_mode; 171 u32 quirk_10m_link_issue:1; 172 }; 173 174 /** 175 * struct prueth - PRUeth structure 176 * @dev: device 177 * @pruss: pruss handle 178 * @pru: rproc instances of PRUs 179 * @rtu: rproc instances of RTUs 180 * @txpru: rproc instances of TX_PRUs 181 * @shram: PRUSS shared RAM region 182 * @sram_pool: MSMC RAM pool for buffers 183 * @msmcram: MSMC RAM region 184 * @eth_node: DT node for the port 185 * @emac: private EMAC data structure 186 * @registered_netdevs: list of registered netdevs 187 * @miig_rt: regmap to mii_g_rt block 188 * @mii_rt: regmap to mii_rt block 189 * @pru_id: ID for each of the PRUs 190 * @pdev: pointer to ICSSG platform device 191 * @pdata: pointer to platform data for ICSSG driver 192 * @icssg_hwcmdseq: seq counter or HWQ messages 193 * @emacs_initialized: num of EMACs/ext ports that are up/running 194 */ 195 struct prueth { 196 struct device *dev; 197 struct pruss *pruss; 198 struct rproc *pru[PRUSS_NUM_PRUS]; 199 struct rproc *rtu[PRUSS_NUM_PRUS]; 200 struct rproc *txpru[PRUSS_NUM_PRUS]; 201 struct pruss_mem_region shram; 202 struct gen_pool *sram_pool; 203 struct pruss_mem_region msmcram; 204 205 struct device_node *eth_node[PRUETH_NUM_MACS]; 206 struct prueth_emac *emac[PRUETH_NUM_MACS]; 207 struct net_device *registered_netdevs[PRUETH_NUM_MACS]; 208 struct regmap *miig_rt; 209 struct regmap *mii_rt; 210 211 enum pruss_pru_id pru_id[PRUSS_NUM_PRUS]; 212 struct platform_device *pdev; 213 struct prueth_pdata pdata; 214 u8 icssg_hwcmdseq; 215 216 int emacs_initialized; 217 }; 218 219 /* get PRUSS SLICE number from prueth_emac */ 220 static inline int prueth_emac_slice(struct prueth_emac *emac) 221 { 222 switch (emac->port_id) { 223 case PRUETH_PORT_MII0: 224 return ICSS_SLICE0; 225 case PRUETH_PORT_MII1: 226 return ICSS_SLICE1; 227 default: 228 return -EINVAL; 229 } 230 } 231 232 /* Classifier helpers */ 233 void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac); 234 void icssg_class_set_host_mac_addr(struct regmap *miig_rt, const u8 *mac); 235 void icssg_class_disable(struct regmap *miig_rt, int slice); 236 void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti); 237 void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr); 238 239 /* config helpers */ 240 void icssg_config_ipg(struct prueth_emac *emac); 241 int icssg_config(struct prueth *prueth, struct prueth_emac *emac, 242 int slice); 243 int emac_set_port_state(struct prueth_emac *emac, 244 enum icssg_port_state_cmd state); 245 void icssg_config_set_speed(struct prueth_emac *emac); 246 247 /* Buffer queue helpers */ 248 int icssg_queue_pop(struct prueth *prueth, u8 queue); 249 void icssg_queue_push(struct prueth *prueth, int queue, u16 addr); 250 u32 icssg_queue_level(struct prueth *prueth, int queue); 251 252 #define prueth_napi_to_tx_chn(pnapi) \ 253 container_of(pnapi, struct prueth_tx_chn, napi_tx) 254 255 void emac_stats_work_handler(struct work_struct *work); 256 void emac_update_hardware_stats(struct prueth_emac *emac); 257 #endif /* __NET_TI_ICSSG_PRUETH_H */ 258