1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Texas Instruments ICSSG Ethernet driver 3 * 4 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 */ 7 8 #ifndef __NET_TI_ICSSG_PRUETH_H 9 #define __NET_TI_ICSSG_PRUETH_H 10 11 #include <linux/etherdevice.h> 12 #include <linux/genalloc.h> 13 #include <linux/if_vlan.h> 14 #include <linux/interrupt.h> 15 #include <linux/kernel.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/of.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_mdio.h> 23 #include <linux/of_net.h> 24 #include <linux/of_platform.h> 25 #include <linux/phy.h> 26 #include <linux/remoteproc/pruss.h> 27 #include <linux/pruss_driver.h> 28 #include <linux/ptp_clock_kernel.h> 29 #include <linux/remoteproc.h> 30 31 #include <linux/dma-mapping.h> 32 #include <linux/dma/ti-cppi5.h> 33 #include <linux/dma/k3-udma-glue.h> 34 35 #include <net/devlink.h> 36 37 #include "icssg_switch_map.h" 38 39 #define ICSS_SLICE0 0 40 #define ICSS_SLICE1 1 41 42 #define ICSSG_MAX_RFLOWS 8 /* per slice */ 43 44 /* In switch mode there are 3 real ports i.e. 3 mac addrs. 45 * however Linux sees only the host side port. The other 2 ports 46 * are the switch ports. 47 * In emac mode there are 2 real ports i.e. 2 mac addrs. 48 * Linux sees both the ports. 49 */ 50 enum prueth_port { 51 PRUETH_PORT_HOST = 0, /* host side port */ 52 PRUETH_PORT_MII0, /* physical port RG/SG MII 0 */ 53 PRUETH_PORT_MII1, /* physical port RG/SG MII 1 */ 54 PRUETH_PORT_INVALID, /* Invalid prueth port */ 55 }; 56 57 enum prueth_mac { 58 PRUETH_MAC0 = 0, 59 PRUETH_MAC1, 60 PRUETH_NUM_MACS, 61 PRUETH_MAC_INVALID, 62 }; 63 64 struct prueth_tx_chn { 65 struct device *dma_dev; 66 struct napi_struct napi_tx; 67 struct k3_cppi_desc_pool *desc_pool; 68 struct k3_udma_glue_tx_channel *tx_chn; 69 struct prueth_emac *emac; 70 u32 id; 71 u32 descs_num; 72 unsigned int irq; 73 char name[32]; 74 }; 75 76 struct prueth_rx_chn { 77 struct device *dev; 78 struct device *dma_dev; 79 struct k3_cppi_desc_pool *desc_pool; 80 struct k3_udma_glue_rx_channel *rx_chn; 81 u32 descs_num; 82 unsigned int irq[ICSSG_MAX_RFLOWS]; /* separate irq per flow */ 83 char name[32]; 84 }; 85 86 /* There are 4 Tx DMA channels, but the highest priority is CH3 (thread 3) 87 * and lower three are lower priority channels or threads. 88 */ 89 #define PRUETH_MAX_TX_QUEUES 4 90 91 /* data for each emac port */ 92 struct prueth_emac { 93 bool fw_running; 94 struct prueth *prueth; 95 struct net_device *ndev; 96 u8 mac_addr[6]; 97 struct napi_struct napi_rx; 98 u32 msg_enable; 99 100 int link; 101 int speed; 102 int duplex; 103 104 const char *phy_id; 105 struct device_node *phy_node; 106 phy_interface_t phy_if; 107 enum prueth_port port_id; 108 109 /* DMA related */ 110 struct prueth_tx_chn tx_chns[PRUETH_MAX_TX_QUEUES]; 111 struct completion tdown_complete; 112 atomic_t tdown_cnt; 113 struct prueth_rx_chn rx_chns; 114 int rx_flow_id_base; 115 int tx_ch_num; 116 117 spinlock_t lock; /* serialize access */ 118 119 unsigned long state; 120 struct completion cmd_complete; 121 /* Mutex to serialize access to firmware command interface */ 122 struct mutex cmd_lock; 123 struct work_struct rx_mode_work; 124 struct workqueue_struct *cmd_wq; 125 126 struct pruss_mem_region dram; 127 }; 128 129 /** 130 * struct prueth_pdata - PRUeth platform data 131 * @fdqring_mode: Free desc queue mode 132 * @quirk_10m_link_issue: 10M link detect errata 133 */ 134 struct prueth_pdata { 135 enum k3_ring_mode fdqring_mode; 136 u32 quirk_10m_link_issue:1; 137 }; 138 139 /** 140 * struct prueth - PRUeth structure 141 * @dev: device 142 * @pruss: pruss handle 143 * @pru: rproc instances of PRUs 144 * @rtu: rproc instances of RTUs 145 * @txpru: rproc instances of TX_PRUs 146 * @shram: PRUSS shared RAM region 147 * @sram_pool: MSMC RAM pool for buffers 148 * @msmcram: MSMC RAM region 149 * @eth_node: DT node for the port 150 * @emac: private EMAC data structure 151 * @registered_netdevs: list of registered netdevs 152 * @miig_rt: regmap to mii_g_rt block 153 * @mii_rt: regmap to mii_rt block 154 * @pru_id: ID for each of the PRUs 155 * @pdev: pointer to ICSSG platform device 156 * @pdata: pointer to platform data for ICSSG driver 157 * @icssg_hwcmdseq: seq counter or HWQ messages 158 * @emacs_initialized: num of EMACs/ext ports that are up/running 159 */ 160 struct prueth { 161 struct device *dev; 162 struct pruss *pruss; 163 struct rproc *pru[PRUSS_NUM_PRUS]; 164 struct rproc *rtu[PRUSS_NUM_PRUS]; 165 struct rproc *txpru[PRUSS_NUM_PRUS]; 166 struct pruss_mem_region shram; 167 struct gen_pool *sram_pool; 168 struct pruss_mem_region msmcram; 169 170 struct device_node *eth_node[PRUETH_NUM_MACS]; 171 struct prueth_emac *emac[PRUETH_NUM_MACS]; 172 struct net_device *registered_netdevs[PRUETH_NUM_MACS]; 173 struct regmap *miig_rt; 174 struct regmap *mii_rt; 175 176 enum pruss_pru_id pru_id[PRUSS_NUM_PRUS]; 177 struct platform_device *pdev; 178 struct prueth_pdata pdata; 179 u8 icssg_hwcmdseq; 180 181 int emacs_initialized; 182 }; 183 184 /* get PRUSS SLICE number from prueth_emac */ 185 static inline int prueth_emac_slice(struct prueth_emac *emac) 186 { 187 switch (emac->port_id) { 188 case PRUETH_PORT_MII0: 189 return ICSS_SLICE0; 190 case PRUETH_PORT_MII1: 191 return ICSS_SLICE1; 192 default: 193 return -EINVAL; 194 } 195 } 196 197 /* Classifier helpers */ 198 void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac); 199 void icssg_class_set_host_mac_addr(struct regmap *miig_rt, const u8 *mac); 200 void icssg_class_disable(struct regmap *miig_rt, int slice); 201 void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti); 202 void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr); 203 204 /* config helpers */ 205 void icssg_config_ipg(struct prueth_emac *emac); 206 int icssg_config(struct prueth *prueth, struct prueth_emac *emac, 207 int slice); 208 int emac_set_port_state(struct prueth_emac *emac, 209 enum icssg_port_state_cmd state); 210 void icssg_config_set_speed(struct prueth_emac *emac); 211 212 /* Buffer queue helpers */ 213 int icssg_queue_pop(struct prueth *prueth, u8 queue); 214 void icssg_queue_push(struct prueth *prueth, int queue, u16 addr); 215 u32 icssg_queue_level(struct prueth *prueth, int queue); 216 217 #endif /* __NET_TI_ICSSG_PRUETH_H */ 218