1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Texas Instruments ICSSG Ethernet driver 3 * 4 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 */ 7 8 #ifndef __NET_TI_ICSSG_PRUETH_H 9 #define __NET_TI_ICSSG_PRUETH_H 10 11 #include <linux/etherdevice.h> 12 #include <linux/genalloc.h> 13 #include <linux/if_vlan.h> 14 #include <linux/interrupt.h> 15 #include <linux/kernel.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/of.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_mdio.h> 23 #include <linux/of_net.h> 24 #include <linux/of_platform.h> 25 #include <linux/phy.h> 26 #include <linux/remoteproc/pruss.h> 27 #include <linux/pruss_driver.h> 28 #include <linux/ptp_clock_kernel.h> 29 #include <linux/remoteproc.h> 30 31 #include <linux/dma-mapping.h> 32 #include <linux/dma/ti-cppi5.h> 33 #include <linux/dma/k3-udma-glue.h> 34 35 #include <net/devlink.h> 36 37 #include "icssg_config.h" 38 #include "icssg_switch_map.h" 39 40 #define PRUETH_MAX_MTU (2000 - ETH_HLEN - ETH_FCS_LEN) 41 #define PRUETH_MIN_PKT_SIZE (VLAN_ETH_ZLEN) 42 #define PRUETH_MAX_PKT_SIZE (PRUETH_MAX_MTU + ETH_HLEN + ETH_FCS_LEN) 43 44 #define ICSS_SLICE0 0 45 #define ICSS_SLICE1 1 46 47 #define ICSS_FW_PRU 0 48 #define ICSS_FW_RTU 1 49 50 #define ICSSG_MAX_RFLOWS 8 /* per slice */ 51 52 /* Number of ICSSG related stats */ 53 #define ICSSG_NUM_STATS 60 54 #define ICSSG_NUM_STANDARD_STATS 31 55 #define ICSSG_NUM_ETHTOOL_STATS (ICSSG_NUM_STATS - ICSSG_NUM_STANDARD_STATS) 56 57 /* Firmware status codes */ 58 #define ICSS_HS_FW_READY 0x55555555 59 #define ICSS_HS_FW_DEAD 0xDEAD0000 /* lower 16 bits contain error code */ 60 61 /* Firmware command codes */ 62 #define ICSS_HS_CMD_BUSY 0x40000000 63 #define ICSS_HS_CMD_DONE 0x80000000 64 #define ICSS_HS_CMD_CANCEL 0x10000000 65 66 /* Firmware commands */ 67 #define ICSS_CMD_SPAD 0x20 68 #define ICSS_CMD_RXTX 0x10 69 #define ICSS_CMD_ADD_FDB 0x1 70 #define ICSS_CMD_DEL_FDB 0x2 71 #define ICSS_CMD_SET_RUN 0x4 72 #define ICSS_CMD_GET_FDB_SLOT 0x5 73 #define ICSS_CMD_ENABLE_VLAN 0x5 74 #define ICSS_CMD_DISABLE_VLAN 0x6 75 #define ICSS_CMD_ADD_FILTER 0x7 76 #define ICSS_CMD_ADD_MAC 0x8 77 78 /* In switch mode there are 3 real ports i.e. 3 mac addrs. 79 * however Linux sees only the host side port. The other 2 ports 80 * are the switch ports. 81 * In emac mode there are 2 real ports i.e. 2 mac addrs. 82 * Linux sees both the ports. 83 */ 84 enum prueth_port { 85 PRUETH_PORT_HOST = 0, /* host side port */ 86 PRUETH_PORT_MII0, /* physical port RG/SG MII 0 */ 87 PRUETH_PORT_MII1, /* physical port RG/SG MII 1 */ 88 PRUETH_PORT_INVALID, /* Invalid prueth port */ 89 }; 90 91 enum prueth_mac { 92 PRUETH_MAC0 = 0, 93 PRUETH_MAC1, 94 PRUETH_NUM_MACS, 95 PRUETH_MAC_INVALID, 96 }; 97 98 struct prueth_tx_chn { 99 struct device *dma_dev; 100 struct napi_struct napi_tx; 101 struct k3_cppi_desc_pool *desc_pool; 102 struct k3_udma_glue_tx_channel *tx_chn; 103 struct prueth_emac *emac; 104 u32 id; 105 u32 descs_num; 106 unsigned int irq; 107 char name[32]; 108 }; 109 110 struct prueth_rx_chn { 111 struct device *dev; 112 struct device *dma_dev; 113 struct k3_cppi_desc_pool *desc_pool; 114 struct k3_udma_glue_rx_channel *rx_chn; 115 u32 descs_num; 116 unsigned int irq[ICSSG_MAX_RFLOWS]; /* separate irq per flow */ 117 char name[32]; 118 }; 119 120 /* There are 4 Tx DMA channels, but the highest priority is CH3 (thread 3) 121 * and lower three are lower priority channels or threads. 122 */ 123 #define PRUETH_MAX_TX_QUEUES 4 124 125 /* data for each emac port */ 126 struct prueth_emac { 127 bool fw_running; 128 struct prueth *prueth; 129 struct net_device *ndev; 130 u8 mac_addr[6]; 131 struct napi_struct napi_rx; 132 u32 msg_enable; 133 134 int link; 135 int speed; 136 int duplex; 137 138 const char *phy_id; 139 struct device_node *phy_node; 140 phy_interface_t phy_if; 141 enum prueth_port port_id; 142 143 /* DMA related */ 144 struct prueth_tx_chn tx_chns[PRUETH_MAX_TX_QUEUES]; 145 struct completion tdown_complete; 146 atomic_t tdown_cnt; 147 struct prueth_rx_chn rx_chns; 148 int rx_flow_id_base; 149 int tx_ch_num; 150 151 spinlock_t lock; /* serialize access */ 152 153 unsigned long state; 154 struct completion cmd_complete; 155 /* Mutex to serialize access to firmware command interface */ 156 struct mutex cmd_lock; 157 struct work_struct rx_mode_work; 158 struct workqueue_struct *cmd_wq; 159 160 struct pruss_mem_region dram; 161 162 struct delayed_work stats_work; 163 u64 stats[ICSSG_NUM_STATS]; 164 }; 165 166 /** 167 * struct prueth_pdata - PRUeth platform data 168 * @fdqring_mode: Free desc queue mode 169 * @quirk_10m_link_issue: 10M link detect errata 170 */ 171 struct prueth_pdata { 172 enum k3_ring_mode fdqring_mode; 173 u32 quirk_10m_link_issue:1; 174 }; 175 176 /** 177 * struct prueth - PRUeth structure 178 * @dev: device 179 * @pruss: pruss handle 180 * @pru: rproc instances of PRUs 181 * @rtu: rproc instances of RTUs 182 * @txpru: rproc instances of TX_PRUs 183 * @shram: PRUSS shared RAM region 184 * @sram_pool: MSMC RAM pool for buffers 185 * @msmcram: MSMC RAM region 186 * @eth_node: DT node for the port 187 * @emac: private EMAC data structure 188 * @registered_netdevs: list of registered netdevs 189 * @miig_rt: regmap to mii_g_rt block 190 * @mii_rt: regmap to mii_rt block 191 * @pru_id: ID for each of the PRUs 192 * @pdev: pointer to ICSSG platform device 193 * @pdata: pointer to platform data for ICSSG driver 194 * @icssg_hwcmdseq: seq counter or HWQ messages 195 * @emacs_initialized: num of EMACs/ext ports that are up/running 196 */ 197 struct prueth { 198 struct device *dev; 199 struct pruss *pruss; 200 struct rproc *pru[PRUSS_NUM_PRUS]; 201 struct rproc *rtu[PRUSS_NUM_PRUS]; 202 struct rproc *txpru[PRUSS_NUM_PRUS]; 203 struct pruss_mem_region shram; 204 struct gen_pool *sram_pool; 205 struct pruss_mem_region msmcram; 206 207 struct device_node *eth_node[PRUETH_NUM_MACS]; 208 struct prueth_emac *emac[PRUETH_NUM_MACS]; 209 struct net_device *registered_netdevs[PRUETH_NUM_MACS]; 210 struct regmap *miig_rt; 211 struct regmap *mii_rt; 212 213 enum pruss_pru_id pru_id[PRUSS_NUM_PRUS]; 214 struct platform_device *pdev; 215 struct prueth_pdata pdata; 216 u8 icssg_hwcmdseq; 217 218 int emacs_initialized; 219 }; 220 221 /* get PRUSS SLICE number from prueth_emac */ 222 static inline int prueth_emac_slice(struct prueth_emac *emac) 223 { 224 switch (emac->port_id) { 225 case PRUETH_PORT_MII0: 226 return ICSS_SLICE0; 227 case PRUETH_PORT_MII1: 228 return ICSS_SLICE1; 229 default: 230 return -EINVAL; 231 } 232 } 233 234 extern const struct ethtool_ops icssg_ethtool_ops; 235 236 /* Classifier helpers */ 237 void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac); 238 void icssg_class_set_host_mac_addr(struct regmap *miig_rt, const u8 *mac); 239 void icssg_class_disable(struct regmap *miig_rt, int slice); 240 void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti); 241 void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr); 242 243 /* config helpers */ 244 void icssg_config_ipg(struct prueth_emac *emac); 245 int icssg_config(struct prueth *prueth, struct prueth_emac *emac, 246 int slice); 247 int emac_set_port_state(struct prueth_emac *emac, 248 enum icssg_port_state_cmd state); 249 void icssg_config_set_speed(struct prueth_emac *emac); 250 251 /* Buffer queue helpers */ 252 int icssg_queue_pop(struct prueth *prueth, u8 queue); 253 void icssg_queue_push(struct prueth *prueth, int queue, u16 addr); 254 u32 icssg_queue_level(struct prueth *prueth, int queue); 255 256 #define prueth_napi_to_tx_chn(pnapi) \ 257 container_of(pnapi, struct prueth_tx_chn, napi_tx) 258 259 void emac_stats_work_handler(struct work_struct *work); 260 void emac_update_hardware_stats(struct prueth_emac *emac); 261 int emac_get_stat_by_name(struct prueth_emac *emac, char *stat_name); 262 #endif /* __NET_TI_ICSSG_PRUETH_H */ 263