1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Texas Instruments ICSSG Ethernet driver 3 * 4 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 */ 7 8 #ifndef __NET_TI_ICSSG_PRUETH_H 9 #define __NET_TI_ICSSG_PRUETH_H 10 11 #include <linux/etherdevice.h> 12 #include <linux/genalloc.h> 13 #include <linux/if_vlan.h> 14 #include <linux/interrupt.h> 15 #include <linux/kernel.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/of.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_mdio.h> 23 #include <linux/of_net.h> 24 #include <linux/of_platform.h> 25 #include <linux/phy.h> 26 #include <linux/remoteproc/pruss.h> 27 #include <linux/pruss_driver.h> 28 #include <linux/ptp_clock_kernel.h> 29 #include <linux/remoteproc.h> 30 31 #include <linux/dma-mapping.h> 32 #include <linux/dma/ti-cppi5.h> 33 #include <linux/dma/k3-udma-glue.h> 34 35 #include <net/devlink.h> 36 37 #include "icssg_config.h" 38 #include "icssg_switch_map.h" 39 40 #define PRUETH_MAX_MTU (2000 - ETH_HLEN - ETH_FCS_LEN) 41 #define PRUETH_MIN_PKT_SIZE (VLAN_ETH_ZLEN) 42 #define PRUETH_MAX_PKT_SIZE (PRUETH_MAX_MTU + ETH_HLEN + ETH_FCS_LEN) 43 44 #define ICSS_SLICE0 0 45 #define ICSS_SLICE1 1 46 47 #define ICSS_FW_PRU 0 48 #define ICSS_FW_RTU 1 49 50 #define ICSSG_MAX_RFLOWS 8 /* per slice */ 51 52 /* Firmware status codes */ 53 #define ICSS_HS_FW_READY 0x55555555 54 #define ICSS_HS_FW_DEAD 0xDEAD0000 /* lower 16 bits contain error code */ 55 56 /* Firmware command codes */ 57 #define ICSS_HS_CMD_BUSY 0x40000000 58 #define ICSS_HS_CMD_DONE 0x80000000 59 #define ICSS_HS_CMD_CANCEL 0x10000000 60 61 /* Firmware commands */ 62 #define ICSS_CMD_SPAD 0x20 63 #define ICSS_CMD_RXTX 0x10 64 #define ICSS_CMD_ADD_FDB 0x1 65 #define ICSS_CMD_DEL_FDB 0x2 66 #define ICSS_CMD_SET_RUN 0x4 67 #define ICSS_CMD_GET_FDB_SLOT 0x5 68 #define ICSS_CMD_ENABLE_VLAN 0x5 69 #define ICSS_CMD_DISABLE_VLAN 0x6 70 #define ICSS_CMD_ADD_FILTER 0x7 71 #define ICSS_CMD_ADD_MAC 0x8 72 73 /* In switch mode there are 3 real ports i.e. 3 mac addrs. 74 * however Linux sees only the host side port. The other 2 ports 75 * are the switch ports. 76 * In emac mode there are 2 real ports i.e. 2 mac addrs. 77 * Linux sees both the ports. 78 */ 79 enum prueth_port { 80 PRUETH_PORT_HOST = 0, /* host side port */ 81 PRUETH_PORT_MII0, /* physical port RG/SG MII 0 */ 82 PRUETH_PORT_MII1, /* physical port RG/SG MII 1 */ 83 PRUETH_PORT_INVALID, /* Invalid prueth port */ 84 }; 85 86 enum prueth_mac { 87 PRUETH_MAC0 = 0, 88 PRUETH_MAC1, 89 PRUETH_NUM_MACS, 90 PRUETH_MAC_INVALID, 91 }; 92 93 struct prueth_tx_chn { 94 struct device *dma_dev; 95 struct napi_struct napi_tx; 96 struct k3_cppi_desc_pool *desc_pool; 97 struct k3_udma_glue_tx_channel *tx_chn; 98 struct prueth_emac *emac; 99 u32 id; 100 u32 descs_num; 101 unsigned int irq; 102 char name[32]; 103 }; 104 105 struct prueth_rx_chn { 106 struct device *dev; 107 struct device *dma_dev; 108 struct k3_cppi_desc_pool *desc_pool; 109 struct k3_udma_glue_rx_channel *rx_chn; 110 u32 descs_num; 111 unsigned int irq[ICSSG_MAX_RFLOWS]; /* separate irq per flow */ 112 char name[32]; 113 }; 114 115 /* There are 4 Tx DMA channels, but the highest priority is CH3 (thread 3) 116 * and lower three are lower priority channels or threads. 117 */ 118 #define PRUETH_MAX_TX_QUEUES 4 119 120 /* data for each emac port */ 121 struct prueth_emac { 122 bool fw_running; 123 struct prueth *prueth; 124 struct net_device *ndev; 125 u8 mac_addr[6]; 126 struct napi_struct napi_rx; 127 u32 msg_enable; 128 129 int link; 130 int speed; 131 int duplex; 132 133 const char *phy_id; 134 struct device_node *phy_node; 135 phy_interface_t phy_if; 136 enum prueth_port port_id; 137 138 /* DMA related */ 139 struct prueth_tx_chn tx_chns[PRUETH_MAX_TX_QUEUES]; 140 struct completion tdown_complete; 141 atomic_t tdown_cnt; 142 struct prueth_rx_chn rx_chns; 143 int rx_flow_id_base; 144 int tx_ch_num; 145 146 spinlock_t lock; /* serialize access */ 147 148 unsigned long state; 149 struct completion cmd_complete; 150 /* Mutex to serialize access to firmware command interface */ 151 struct mutex cmd_lock; 152 struct work_struct rx_mode_work; 153 struct workqueue_struct *cmd_wq; 154 155 struct pruss_mem_region dram; 156 }; 157 158 /** 159 * struct prueth_pdata - PRUeth platform data 160 * @fdqring_mode: Free desc queue mode 161 * @quirk_10m_link_issue: 10M link detect errata 162 */ 163 struct prueth_pdata { 164 enum k3_ring_mode fdqring_mode; 165 u32 quirk_10m_link_issue:1; 166 }; 167 168 /** 169 * struct prueth - PRUeth structure 170 * @dev: device 171 * @pruss: pruss handle 172 * @pru: rproc instances of PRUs 173 * @rtu: rproc instances of RTUs 174 * @txpru: rproc instances of TX_PRUs 175 * @shram: PRUSS shared RAM region 176 * @sram_pool: MSMC RAM pool for buffers 177 * @msmcram: MSMC RAM region 178 * @eth_node: DT node for the port 179 * @emac: private EMAC data structure 180 * @registered_netdevs: list of registered netdevs 181 * @miig_rt: regmap to mii_g_rt block 182 * @mii_rt: regmap to mii_rt block 183 * @pru_id: ID for each of the PRUs 184 * @pdev: pointer to ICSSG platform device 185 * @pdata: pointer to platform data for ICSSG driver 186 * @icssg_hwcmdseq: seq counter or HWQ messages 187 * @emacs_initialized: num of EMACs/ext ports that are up/running 188 */ 189 struct prueth { 190 struct device *dev; 191 struct pruss *pruss; 192 struct rproc *pru[PRUSS_NUM_PRUS]; 193 struct rproc *rtu[PRUSS_NUM_PRUS]; 194 struct rproc *txpru[PRUSS_NUM_PRUS]; 195 struct pruss_mem_region shram; 196 struct gen_pool *sram_pool; 197 struct pruss_mem_region msmcram; 198 199 struct device_node *eth_node[PRUETH_NUM_MACS]; 200 struct prueth_emac *emac[PRUETH_NUM_MACS]; 201 struct net_device *registered_netdevs[PRUETH_NUM_MACS]; 202 struct regmap *miig_rt; 203 struct regmap *mii_rt; 204 205 enum pruss_pru_id pru_id[PRUSS_NUM_PRUS]; 206 struct platform_device *pdev; 207 struct prueth_pdata pdata; 208 u8 icssg_hwcmdseq; 209 210 int emacs_initialized; 211 }; 212 213 /* get PRUSS SLICE number from prueth_emac */ 214 static inline int prueth_emac_slice(struct prueth_emac *emac) 215 { 216 switch (emac->port_id) { 217 case PRUETH_PORT_MII0: 218 return ICSS_SLICE0; 219 case PRUETH_PORT_MII1: 220 return ICSS_SLICE1; 221 default: 222 return -EINVAL; 223 } 224 } 225 226 /* Classifier helpers */ 227 void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac); 228 void icssg_class_set_host_mac_addr(struct regmap *miig_rt, const u8 *mac); 229 void icssg_class_disable(struct regmap *miig_rt, int slice); 230 void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti); 231 void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr); 232 233 /* config helpers */ 234 void icssg_config_ipg(struct prueth_emac *emac); 235 int icssg_config(struct prueth *prueth, struct prueth_emac *emac, 236 int slice); 237 int emac_set_port_state(struct prueth_emac *emac, 238 enum icssg_port_state_cmd state); 239 void icssg_config_set_speed(struct prueth_emac *emac); 240 241 /* Buffer queue helpers */ 242 int icssg_queue_pop(struct prueth *prueth, u8 queue); 243 void icssg_queue_push(struct prueth *prueth, int queue, u16 addr); 244 u32 icssg_queue_level(struct prueth *prueth, int queue); 245 246 #define prueth_napi_to_tx_chn(pnapi) \ 247 container_of(pnapi, struct prueth_tx_chn, napi_tx) 248 249 #endif /* __NET_TI_ICSSG_PRUETH_H */ 250