1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Texas Instruments ICSSG Ethernet Driver 4 * 5 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ 6 * 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dma/ti-cppi5.h> 14 #include <linux/etherdevice.h> 15 #include <linux/genalloc.h> 16 #include <linux/if_vlan.h> 17 #include <linux/interrupt.h> 18 #include <linux/io-64-nonatomic-hi-lo.h> 19 #include <linux/kernel.h> 20 #include <linux/mfd/syscon.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/of_platform.h> 27 #include <linux/phy.h> 28 #include <linux/remoteproc/pruss.h> 29 #include <linux/regmap.h> 30 #include <linux/remoteproc.h> 31 32 #include "icssg_prueth.h" 33 #include "icssg_mii_rt.h" 34 #include "../k3-cppi-desc-pool.h" 35 36 #define PRUETH_MODULE_DESCRIPTION "PRUSS ICSSG Ethernet driver" 37 38 /* Netif debug messages possible */ 39 #define PRUETH_EMAC_DEBUG (NETIF_MSG_DRV | \ 40 NETIF_MSG_PROBE | \ 41 NETIF_MSG_LINK | \ 42 NETIF_MSG_TIMER | \ 43 NETIF_MSG_IFDOWN | \ 44 NETIF_MSG_IFUP | \ 45 NETIF_MSG_RX_ERR | \ 46 NETIF_MSG_TX_ERR | \ 47 NETIF_MSG_TX_QUEUED | \ 48 NETIF_MSG_INTR | \ 49 NETIF_MSG_TX_DONE | \ 50 NETIF_MSG_RX_STATUS | \ 51 NETIF_MSG_PKTDATA | \ 52 NETIF_MSG_HW | \ 53 NETIF_MSG_WOL) 54 55 #define prueth_napi_to_emac(napi) container_of(napi, struct prueth_emac, napi_rx) 56 57 /* CTRLMMR_ICSSG_RGMII_CTRL register bits */ 58 #define ICSSG_CTRL_RGMII_ID_MODE BIT(24) 59 60 #define IEP_DEFAULT_CYCLE_TIME_NS 1000000 /* 1 ms */ 61 62 static void prueth_cleanup_rx_chns(struct prueth_emac *emac, 63 struct prueth_rx_chn *rx_chn, 64 int max_rflows) 65 { 66 if (rx_chn->desc_pool) 67 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 68 69 if (rx_chn->rx_chn) 70 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 71 } 72 73 static void prueth_cleanup_tx_chns(struct prueth_emac *emac) 74 { 75 int i; 76 77 for (i = 0; i < emac->tx_ch_num; i++) { 78 struct prueth_tx_chn *tx_chn = &emac->tx_chns[i]; 79 80 if (tx_chn->desc_pool) 81 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 82 83 if (tx_chn->tx_chn) 84 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 85 86 /* Assume prueth_cleanup_tx_chns() is called at the 87 * end after all channel resources are freed 88 */ 89 memset(tx_chn, 0, sizeof(*tx_chn)); 90 } 91 } 92 93 static void prueth_ndev_del_tx_napi(struct prueth_emac *emac, int num) 94 { 95 int i; 96 97 for (i = 0; i < num; i++) { 98 struct prueth_tx_chn *tx_chn = &emac->tx_chns[i]; 99 100 if (tx_chn->irq) 101 free_irq(tx_chn->irq, tx_chn); 102 netif_napi_del(&tx_chn->napi_tx); 103 } 104 } 105 106 static void prueth_xmit_free(struct prueth_tx_chn *tx_chn, 107 struct cppi5_host_desc_t *desc) 108 { 109 struct cppi5_host_desc_t *first_desc, *next_desc; 110 dma_addr_t buf_dma, next_desc_dma; 111 u32 buf_dma_len; 112 113 first_desc = desc; 114 next_desc = first_desc; 115 116 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 117 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 118 119 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, 120 DMA_TO_DEVICE); 121 122 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 123 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 124 while (next_desc_dma) { 125 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 126 next_desc_dma); 127 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 128 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 129 130 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 131 DMA_TO_DEVICE); 132 133 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 134 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 135 136 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 137 } 138 139 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 140 } 141 142 static int emac_tx_complete_packets(struct prueth_emac *emac, int chn, 143 int budget) 144 { 145 struct net_device *ndev = emac->ndev; 146 struct cppi5_host_desc_t *desc_tx; 147 struct netdev_queue *netif_txq; 148 struct prueth_tx_chn *tx_chn; 149 unsigned int total_bytes = 0; 150 struct sk_buff *skb; 151 dma_addr_t desc_dma; 152 int res, num_tx = 0; 153 void **swdata; 154 155 tx_chn = &emac->tx_chns[chn]; 156 157 while (true) { 158 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 159 if (res == -ENODATA) 160 break; 161 162 /* teardown completion */ 163 if (cppi5_desc_is_tdcm(desc_dma)) { 164 if (atomic_dec_and_test(&emac->tdown_cnt)) 165 complete(&emac->tdown_complete); 166 break; 167 } 168 169 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 170 desc_dma); 171 swdata = cppi5_hdesc_get_swdata(desc_tx); 172 173 skb = *(swdata); 174 prueth_xmit_free(tx_chn, desc_tx); 175 176 ndev = skb->dev; 177 ndev->stats.tx_packets++; 178 ndev->stats.tx_bytes += skb->len; 179 total_bytes += skb->len; 180 napi_consume_skb(skb, budget); 181 num_tx++; 182 } 183 184 if (!num_tx) 185 return 0; 186 187 netif_txq = netdev_get_tx_queue(ndev, chn); 188 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 189 190 if (netif_tx_queue_stopped(netif_txq)) { 191 /* If the TX queue was stopped, wake it now 192 * if we have enough room. 193 */ 194 __netif_tx_lock(netif_txq, smp_processor_id()); 195 if (netif_running(ndev) && 196 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 197 MAX_SKB_FRAGS)) 198 netif_tx_wake_queue(netif_txq); 199 __netif_tx_unlock(netif_txq); 200 } 201 202 return num_tx; 203 } 204 205 static int emac_napi_tx_poll(struct napi_struct *napi_tx, int budget) 206 { 207 struct prueth_tx_chn *tx_chn = prueth_napi_to_tx_chn(napi_tx); 208 struct prueth_emac *emac = tx_chn->emac; 209 int num_tx_packets; 210 211 num_tx_packets = emac_tx_complete_packets(emac, tx_chn->id, budget); 212 213 if (num_tx_packets >= budget) 214 return budget; 215 216 if (napi_complete_done(napi_tx, num_tx_packets)) 217 enable_irq(tx_chn->irq); 218 219 return num_tx_packets; 220 } 221 222 static irqreturn_t prueth_tx_irq(int irq, void *dev_id) 223 { 224 struct prueth_tx_chn *tx_chn = dev_id; 225 226 disable_irq_nosync(irq); 227 napi_schedule(&tx_chn->napi_tx); 228 229 return IRQ_HANDLED; 230 } 231 232 static int prueth_ndev_add_tx_napi(struct prueth_emac *emac) 233 { 234 struct prueth *prueth = emac->prueth; 235 int i, ret; 236 237 for (i = 0; i < emac->tx_ch_num; i++) { 238 struct prueth_tx_chn *tx_chn = &emac->tx_chns[i]; 239 240 netif_napi_add_tx(emac->ndev, &tx_chn->napi_tx, emac_napi_tx_poll); 241 ret = request_irq(tx_chn->irq, prueth_tx_irq, 242 IRQF_TRIGGER_HIGH, tx_chn->name, 243 tx_chn); 244 if (ret) { 245 netif_napi_del(&tx_chn->napi_tx); 246 dev_err(prueth->dev, "unable to request TX IRQ %d\n", 247 tx_chn->irq); 248 goto fail; 249 } 250 } 251 252 return 0; 253 fail: 254 prueth_ndev_del_tx_napi(emac, i); 255 return ret; 256 } 257 258 static int prueth_init_tx_chns(struct prueth_emac *emac) 259 { 260 static const struct k3_ring_cfg ring_cfg = { 261 .elm_size = K3_RINGACC_RING_ELSIZE_8, 262 .mode = K3_RINGACC_RING_MODE_RING, 263 .flags = 0, 264 .size = PRUETH_MAX_TX_DESC, 265 }; 266 struct k3_udma_glue_tx_channel_cfg tx_cfg; 267 struct device *dev = emac->prueth->dev; 268 struct net_device *ndev = emac->ndev; 269 int ret, slice, i; 270 u32 hdesc_size; 271 272 slice = prueth_emac_slice(emac); 273 if (slice < 0) 274 return slice; 275 276 init_completion(&emac->tdown_complete); 277 278 hdesc_size = cppi5_hdesc_calc_size(true, PRUETH_NAV_PS_DATA_SIZE, 279 PRUETH_NAV_SW_DATA_SIZE); 280 memset(&tx_cfg, 0, sizeof(tx_cfg)); 281 tx_cfg.swdata_size = PRUETH_NAV_SW_DATA_SIZE; 282 tx_cfg.tx_cfg = ring_cfg; 283 tx_cfg.txcq_cfg = ring_cfg; 284 285 for (i = 0; i < emac->tx_ch_num; i++) { 286 struct prueth_tx_chn *tx_chn = &emac->tx_chns[i]; 287 288 /* To differentiate channels for SLICE0 vs SLICE1 */ 289 snprintf(tx_chn->name, sizeof(tx_chn->name), 290 "tx%d-%d", slice, i); 291 292 tx_chn->emac = emac; 293 tx_chn->id = i; 294 tx_chn->descs_num = PRUETH_MAX_TX_DESC; 295 296 tx_chn->tx_chn = 297 k3_udma_glue_request_tx_chn(dev, tx_chn->name, 298 &tx_cfg); 299 if (IS_ERR(tx_chn->tx_chn)) { 300 ret = PTR_ERR(tx_chn->tx_chn); 301 tx_chn->tx_chn = NULL; 302 netdev_err(ndev, 303 "Failed to request tx dma ch: %d\n", ret); 304 goto fail; 305 } 306 307 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 308 tx_chn->desc_pool = 309 k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 310 tx_chn->descs_num, 311 hdesc_size, 312 tx_chn->name); 313 if (IS_ERR(tx_chn->desc_pool)) { 314 ret = PTR_ERR(tx_chn->desc_pool); 315 tx_chn->desc_pool = NULL; 316 netdev_err(ndev, "Failed to create tx pool: %d\n", ret); 317 goto fail; 318 } 319 320 ret = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 321 if (ret < 0) { 322 netdev_err(ndev, "failed to get tx irq\n"); 323 goto fail; 324 } 325 tx_chn->irq = ret; 326 327 snprintf(tx_chn->name, sizeof(tx_chn->name), "%s-tx%d", 328 dev_name(dev), tx_chn->id); 329 } 330 331 return 0; 332 333 fail: 334 prueth_cleanup_tx_chns(emac); 335 return ret; 336 } 337 338 static int prueth_init_rx_chns(struct prueth_emac *emac, 339 struct prueth_rx_chn *rx_chn, 340 char *name, u32 max_rflows, 341 u32 max_desc_num) 342 { 343 struct k3_udma_glue_rx_channel_cfg rx_cfg; 344 struct device *dev = emac->prueth->dev; 345 struct net_device *ndev = emac->ndev; 346 u32 fdqring_id, hdesc_size; 347 int i, ret = 0, slice; 348 349 slice = prueth_emac_slice(emac); 350 if (slice < 0) 351 return slice; 352 353 /* To differentiate channels for SLICE0 vs SLICE1 */ 354 snprintf(rx_chn->name, sizeof(rx_chn->name), "%s%d", name, slice); 355 356 hdesc_size = cppi5_hdesc_calc_size(true, PRUETH_NAV_PS_DATA_SIZE, 357 PRUETH_NAV_SW_DATA_SIZE); 358 memset(&rx_cfg, 0, sizeof(rx_cfg)); 359 rx_cfg.swdata_size = PRUETH_NAV_SW_DATA_SIZE; 360 rx_cfg.flow_id_num = max_rflows; 361 rx_cfg.flow_id_base = -1; /* udmax will auto select flow id base */ 362 363 /* init all flows */ 364 rx_chn->dev = dev; 365 rx_chn->descs_num = max_desc_num; 366 367 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, rx_chn->name, 368 &rx_cfg); 369 if (IS_ERR(rx_chn->rx_chn)) { 370 ret = PTR_ERR(rx_chn->rx_chn); 371 rx_chn->rx_chn = NULL; 372 netdev_err(ndev, "Failed to request rx dma ch: %d\n", ret); 373 goto fail; 374 } 375 376 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 377 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 378 rx_chn->descs_num, 379 hdesc_size, 380 rx_chn->name); 381 if (IS_ERR(rx_chn->desc_pool)) { 382 ret = PTR_ERR(rx_chn->desc_pool); 383 rx_chn->desc_pool = NULL; 384 netdev_err(ndev, "Failed to create rx pool: %d\n", ret); 385 goto fail; 386 } 387 388 emac->rx_flow_id_base = k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 389 netdev_dbg(ndev, "flow id base = %d\n", emac->rx_flow_id_base); 390 391 fdqring_id = K3_RINGACC_RING_ID_ANY; 392 for (i = 0; i < rx_cfg.flow_id_num; i++) { 393 struct k3_ring_cfg rxring_cfg = { 394 .elm_size = K3_RINGACC_RING_ELSIZE_8, 395 .mode = K3_RINGACC_RING_MODE_RING, 396 .flags = 0, 397 }; 398 struct k3_ring_cfg fdqring_cfg = { 399 .elm_size = K3_RINGACC_RING_ELSIZE_8, 400 .flags = K3_RINGACC_RING_SHARED, 401 }; 402 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 403 .rx_cfg = rxring_cfg, 404 .rxfdq_cfg = fdqring_cfg, 405 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 406 .src_tag_lo_sel = 407 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 408 }; 409 410 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 411 rx_flow_cfg.rx_cfg.size = max_desc_num; 412 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 413 rx_flow_cfg.rxfdq_cfg.mode = emac->prueth->pdata.fdqring_mode; 414 415 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 416 i, &rx_flow_cfg); 417 if (ret) { 418 netdev_err(ndev, "Failed to init rx flow%d %d\n", 419 i, ret); 420 goto fail; 421 } 422 if (!i) 423 fdqring_id = k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 424 i); 425 ret = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 426 if (ret <= 0) { 427 if (!ret) 428 ret = -ENXIO; 429 netdev_err(ndev, "Failed to get rx dma irq"); 430 goto fail; 431 } 432 rx_chn->irq[i] = ret; 433 } 434 435 return 0; 436 437 fail: 438 prueth_cleanup_rx_chns(emac, rx_chn, max_rflows); 439 return ret; 440 } 441 442 static int prueth_dma_rx_push(struct prueth_emac *emac, 443 struct sk_buff *skb, 444 struct prueth_rx_chn *rx_chn) 445 { 446 struct net_device *ndev = emac->ndev; 447 struct cppi5_host_desc_t *desc_rx; 448 u32 pkt_len = skb_tailroom(skb); 449 dma_addr_t desc_dma; 450 dma_addr_t buf_dma; 451 void **swdata; 452 453 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 454 if (!desc_rx) { 455 netdev_err(ndev, "rx push: failed to allocate descriptor\n"); 456 return -ENOMEM; 457 } 458 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 459 460 buf_dma = dma_map_single(rx_chn->dma_dev, skb->data, pkt_len, DMA_FROM_DEVICE); 461 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 462 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 463 netdev_err(ndev, "rx push: failed to map rx pkt buffer\n"); 464 return -EINVAL; 465 } 466 467 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 468 PRUETH_NAV_PS_DATA_SIZE); 469 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 470 cppi5_hdesc_attach_buf(desc_rx, buf_dma, skb_tailroom(skb), buf_dma, skb_tailroom(skb)); 471 472 swdata = cppi5_hdesc_get_swdata(desc_rx); 473 *swdata = skb; 474 475 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, 476 desc_rx, desc_dma); 477 } 478 479 static u64 icssg_ts_to_ns(u32 hi_sw, u32 hi, u32 lo, u32 cycle_time_ns) 480 { 481 u32 iepcount_lo, iepcount_hi, hi_rollover_count; 482 u64 ns; 483 484 iepcount_lo = lo & GENMASK(19, 0); 485 iepcount_hi = (hi & GENMASK(11, 0)) << 12 | lo >> 20; 486 hi_rollover_count = hi >> 11; 487 488 ns = ((u64)hi_rollover_count) << 23 | (iepcount_hi + hi_sw); 489 ns = ns * cycle_time_ns + iepcount_lo; 490 491 return ns; 492 } 493 494 static void emac_rx_timestamp(struct prueth_emac *emac, 495 struct sk_buff *skb, u32 *psdata) 496 { 497 struct skb_shared_hwtstamps *ssh; 498 u64 ns; 499 500 u32 hi_sw = readl(emac->prueth->shram.va + 501 TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET); 502 ns = icssg_ts_to_ns(hi_sw, psdata[1], psdata[0], 503 IEP_DEFAULT_CYCLE_TIME_NS); 504 505 ssh = skb_hwtstamps(skb); 506 memset(ssh, 0, sizeof(*ssh)); 507 ssh->hwtstamp = ns_to_ktime(ns); 508 } 509 510 static int emac_rx_packet(struct prueth_emac *emac, u32 flow_id) 511 { 512 struct prueth_rx_chn *rx_chn = &emac->rx_chns; 513 u32 buf_dma_len, pkt_len, port_id = 0; 514 struct net_device *ndev = emac->ndev; 515 struct cppi5_host_desc_t *desc_rx; 516 struct sk_buff *skb, *new_skb; 517 dma_addr_t desc_dma, buf_dma; 518 void **swdata; 519 u32 *psdata; 520 int ret; 521 522 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_id, &desc_dma); 523 if (ret) { 524 if (ret != -ENODATA) 525 netdev_err(ndev, "rx pop: failed: %d\n", ret); 526 return ret; 527 } 528 529 if (cppi5_desc_is_tdcm(desc_dma)) /* Teardown ? */ 530 return 0; 531 532 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 533 534 swdata = cppi5_hdesc_get_swdata(desc_rx); 535 skb = *swdata; 536 537 psdata = cppi5_hdesc_get_psdata(desc_rx); 538 /* RX HW timestamp */ 539 if (emac->rx_ts_enabled) 540 emac_rx_timestamp(emac, skb, psdata); 541 542 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 543 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 544 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 545 /* firmware adds 4 CRC bytes, strip them */ 546 pkt_len -= 4; 547 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 548 549 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 550 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 551 552 skb->dev = ndev; 553 new_skb = netdev_alloc_skb_ip_align(ndev, PRUETH_MAX_PKT_SIZE); 554 /* if allocation fails we drop the packet but push the 555 * descriptor back to the ring with old skb to prevent a stall 556 */ 557 if (!new_skb) { 558 ndev->stats.rx_dropped++; 559 new_skb = skb; 560 } else { 561 /* send the filled skb up the n/w stack */ 562 skb_put(skb, pkt_len); 563 skb->protocol = eth_type_trans(skb, ndev); 564 napi_gro_receive(&emac->napi_rx, skb); 565 ndev->stats.rx_bytes += pkt_len; 566 ndev->stats.rx_packets++; 567 } 568 569 /* queue another RX DMA */ 570 ret = prueth_dma_rx_push(emac, new_skb, &emac->rx_chns); 571 if (WARN_ON(ret < 0)) { 572 dev_kfree_skb_any(new_skb); 573 ndev->stats.rx_errors++; 574 ndev->stats.rx_dropped++; 575 } 576 577 return ret; 578 } 579 580 static void prueth_rx_cleanup(void *data, dma_addr_t desc_dma) 581 { 582 struct prueth_rx_chn *rx_chn = data; 583 struct cppi5_host_desc_t *desc_rx; 584 struct sk_buff *skb; 585 dma_addr_t buf_dma; 586 u32 buf_dma_len; 587 void **swdata; 588 589 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 590 swdata = cppi5_hdesc_get_swdata(desc_rx); 591 skb = *swdata; 592 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 593 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 594 595 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, 596 DMA_FROM_DEVICE); 597 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 598 599 dev_kfree_skb_any(skb); 600 } 601 602 static int emac_get_tx_ts(struct prueth_emac *emac, 603 struct emac_tx_ts_response *rsp) 604 { 605 struct prueth *prueth = emac->prueth; 606 int slice = prueth_emac_slice(emac); 607 int addr; 608 609 addr = icssg_queue_pop(prueth, slice == 0 ? 610 ICSSG_TS_POP_SLICE0 : ICSSG_TS_POP_SLICE1); 611 if (addr < 0) 612 return addr; 613 614 memcpy_fromio(rsp, prueth->shram.va + addr, sizeof(*rsp)); 615 /* return buffer back for to pool */ 616 icssg_queue_push(prueth, slice == 0 ? 617 ICSSG_TS_PUSH_SLICE0 : ICSSG_TS_PUSH_SLICE1, addr); 618 619 return 0; 620 } 621 622 static void tx_ts_work(struct prueth_emac *emac) 623 { 624 struct skb_shared_hwtstamps ssh; 625 struct emac_tx_ts_response tsr; 626 struct sk_buff *skb; 627 int ret = 0; 628 u32 hi_sw; 629 u64 ns; 630 631 /* There may be more than one pending requests */ 632 while (1) { 633 ret = emac_get_tx_ts(emac, &tsr); 634 if (ret) /* nothing more */ 635 break; 636 637 if (tsr.cookie >= PRUETH_MAX_TX_TS_REQUESTS || 638 !emac->tx_ts_skb[tsr.cookie]) { 639 netdev_err(emac->ndev, "Invalid TX TS cookie 0x%x\n", 640 tsr.cookie); 641 break; 642 } 643 644 skb = emac->tx_ts_skb[tsr.cookie]; 645 emac->tx_ts_skb[tsr.cookie] = NULL; /* free slot */ 646 if (!skb) { 647 netdev_err(emac->ndev, "Driver Bug! got NULL skb\n"); 648 break; 649 } 650 651 hi_sw = readl(emac->prueth->shram.va + 652 TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET); 653 ns = icssg_ts_to_ns(hi_sw, tsr.hi_ts, tsr.lo_ts, 654 IEP_DEFAULT_CYCLE_TIME_NS); 655 656 memset(&ssh, 0, sizeof(ssh)); 657 ssh.hwtstamp = ns_to_ktime(ns); 658 659 skb_tstamp_tx(skb, &ssh); 660 dev_consume_skb_any(skb); 661 662 if (atomic_dec_and_test(&emac->tx_ts_pending)) /* no more? */ 663 break; 664 } 665 } 666 667 static int prueth_tx_ts_cookie_get(struct prueth_emac *emac) 668 { 669 int i; 670 671 /* search and get the next free slot */ 672 for (i = 0; i < PRUETH_MAX_TX_TS_REQUESTS; i++) { 673 if (!emac->tx_ts_skb[i]) { 674 emac->tx_ts_skb[i] = ERR_PTR(-EBUSY); /* reserve slot */ 675 return i; 676 } 677 } 678 679 return -EBUSY; 680 } 681 682 /** 683 * emac_ndo_start_xmit - EMAC Transmit function 684 * @skb: SKB pointer 685 * @ndev: EMAC network adapter 686 * 687 * Called by the system to transmit a packet - we queue the packet in 688 * EMAC hardware transmit queue 689 * Doesn't wait for completion we'll check for TX completion in 690 * emac_tx_complete_packets(). 691 * 692 * Return: enum netdev_tx 693 */ 694 static enum netdev_tx emac_ndo_start_xmit(struct sk_buff *skb, struct net_device *ndev) 695 { 696 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 697 struct prueth_emac *emac = netdev_priv(ndev); 698 struct netdev_queue *netif_txq; 699 struct prueth_tx_chn *tx_chn; 700 dma_addr_t desc_dma, buf_dma; 701 int i, ret = 0, q_idx; 702 bool in_tx_ts = 0; 703 int tx_ts_cookie; 704 void **swdata; 705 u32 pkt_len; 706 u32 *epib; 707 708 pkt_len = skb_headlen(skb); 709 q_idx = skb_get_queue_mapping(skb); 710 711 tx_chn = &emac->tx_chns[q_idx]; 712 netif_txq = netdev_get_tx_queue(ndev, q_idx); 713 714 /* Map the linear buffer */ 715 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, DMA_TO_DEVICE); 716 if (dma_mapping_error(tx_chn->dma_dev, buf_dma)) { 717 netdev_err(ndev, "tx: failed to map skb buffer\n"); 718 ret = NETDEV_TX_OK; 719 goto drop_free_skb; 720 } 721 722 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 723 if (!first_desc) { 724 netdev_dbg(ndev, "tx: failed to allocate descriptor\n"); 725 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, DMA_TO_DEVICE); 726 goto drop_stop_q_busy; 727 } 728 729 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 730 PRUETH_NAV_PS_DATA_SIZE); 731 cppi5_hdesc_set_pkttype(first_desc, 0); 732 epib = first_desc->epib; 733 epib[0] = 0; 734 epib[1] = 0; 735 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 736 emac->tx_ts_enabled) { 737 tx_ts_cookie = prueth_tx_ts_cookie_get(emac); 738 if (tx_ts_cookie >= 0) { 739 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 740 /* Request TX timestamp */ 741 epib[0] = (u32)tx_ts_cookie; 742 epib[1] = 0x80000000; /* TX TS request */ 743 emac->tx_ts_skb[tx_ts_cookie] = skb_get(skb); 744 in_tx_ts = 1; 745 } 746 } 747 748 /* set dst tag to indicate internal qid at the firmware which is at 749 * bit8..bit15. bit0..bit7 indicates port num for directed 750 * packets in case of switch mode operation 751 */ 752 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, (emac->port_id | (q_idx << 8))); 753 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 754 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 755 swdata = cppi5_hdesc_get_swdata(first_desc); 756 *swdata = skb; 757 758 /* Handle the case where skb is fragmented in pages */ 759 cur_desc = first_desc; 760 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 761 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 762 u32 frag_size = skb_frag_size(frag); 763 764 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 765 if (!next_desc) { 766 netdev_err(ndev, 767 "tx: failed to allocate frag. descriptor\n"); 768 goto free_desc_stop_q_busy_cleanup_tx_ts; 769 } 770 771 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 772 DMA_TO_DEVICE); 773 if (dma_mapping_error(tx_chn->dma_dev, buf_dma)) { 774 netdev_err(ndev, "tx: Failed to map skb page\n"); 775 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 776 ret = NETDEV_TX_OK; 777 goto cleanup_tx_ts; 778 } 779 780 cppi5_hdesc_reset_hbdesc(next_desc); 781 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 782 cppi5_hdesc_attach_buf(next_desc, 783 buf_dma, frag_size, buf_dma, frag_size); 784 785 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 786 next_desc); 787 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 788 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 789 790 pkt_len += frag_size; 791 cur_desc = next_desc; 792 } 793 WARN_ON_ONCE(pkt_len != skb->len); 794 795 /* report bql before sending packet */ 796 netdev_tx_sent_queue(netif_txq, pkt_len); 797 798 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 799 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 800 /* cppi5_desc_dump(first_desc, 64); */ 801 802 skb_tx_timestamp(skb); /* SW timestamp if SKBTX_IN_PROGRESS not set */ 803 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 804 if (ret) { 805 netdev_err(ndev, "tx: push failed: %d\n", ret); 806 goto drop_free_descs; 807 } 808 809 if (in_tx_ts) 810 atomic_inc(&emac->tx_ts_pending); 811 812 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 813 netif_tx_stop_queue(netif_txq); 814 /* Barrier, so that stop_queue visible to other cpus */ 815 smp_mb__after_atomic(); 816 817 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 818 MAX_SKB_FRAGS) 819 netif_tx_wake_queue(netif_txq); 820 } 821 822 return NETDEV_TX_OK; 823 824 cleanup_tx_ts: 825 if (in_tx_ts) { 826 dev_kfree_skb_any(emac->tx_ts_skb[tx_ts_cookie]); 827 emac->tx_ts_skb[tx_ts_cookie] = NULL; 828 } 829 830 drop_free_descs: 831 prueth_xmit_free(tx_chn, first_desc); 832 833 drop_free_skb: 834 dev_kfree_skb_any(skb); 835 836 /* error */ 837 ndev->stats.tx_dropped++; 838 netdev_err(ndev, "tx: error: %d\n", ret); 839 840 return ret; 841 842 free_desc_stop_q_busy_cleanup_tx_ts: 843 if (in_tx_ts) { 844 dev_kfree_skb_any(emac->tx_ts_skb[tx_ts_cookie]); 845 emac->tx_ts_skb[tx_ts_cookie] = NULL; 846 } 847 prueth_xmit_free(tx_chn, first_desc); 848 849 drop_stop_q_busy: 850 netif_tx_stop_queue(netif_txq); 851 return NETDEV_TX_BUSY; 852 } 853 854 static void prueth_tx_cleanup(void *data, dma_addr_t desc_dma) 855 { 856 struct prueth_tx_chn *tx_chn = data; 857 struct cppi5_host_desc_t *desc_tx; 858 struct sk_buff *skb; 859 void **swdata; 860 861 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 862 swdata = cppi5_hdesc_get_swdata(desc_tx); 863 skb = *(swdata); 864 prueth_xmit_free(tx_chn, desc_tx); 865 866 dev_kfree_skb_any(skb); 867 } 868 869 static irqreturn_t prueth_tx_ts_irq(int irq, void *dev_id) 870 { 871 struct prueth_emac *emac = dev_id; 872 873 /* currently only TX timestamp is being returned */ 874 tx_ts_work(emac); 875 876 return IRQ_HANDLED; 877 } 878 879 static irqreturn_t prueth_rx_irq(int irq, void *dev_id) 880 { 881 struct prueth_emac *emac = dev_id; 882 883 disable_irq_nosync(irq); 884 napi_schedule(&emac->napi_rx); 885 886 return IRQ_HANDLED; 887 } 888 889 struct icssg_firmwares { 890 char *pru; 891 char *rtu; 892 char *txpru; 893 }; 894 895 static struct icssg_firmwares icssg_emac_firmwares[] = { 896 { 897 .pru = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", 898 .rtu = "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", 899 .txpru = "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", 900 }, 901 { 902 .pru = "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", 903 .rtu = "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", 904 .txpru = "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf", 905 } 906 }; 907 908 static int prueth_emac_start(struct prueth *prueth, struct prueth_emac *emac) 909 { 910 struct icssg_firmwares *firmwares; 911 struct device *dev = prueth->dev; 912 int slice, ret; 913 914 firmwares = icssg_emac_firmwares; 915 916 slice = prueth_emac_slice(emac); 917 if (slice < 0) { 918 netdev_err(emac->ndev, "invalid port\n"); 919 return -EINVAL; 920 } 921 922 ret = icssg_config(prueth, emac, slice); 923 if (ret) 924 return ret; 925 926 ret = rproc_set_firmware(prueth->pru[slice], firmwares[slice].pru); 927 ret = rproc_boot(prueth->pru[slice]); 928 if (ret) { 929 dev_err(dev, "failed to boot PRU%d: %d\n", slice, ret); 930 return -EINVAL; 931 } 932 933 ret = rproc_set_firmware(prueth->rtu[slice], firmwares[slice].rtu); 934 ret = rproc_boot(prueth->rtu[slice]); 935 if (ret) { 936 dev_err(dev, "failed to boot RTU%d: %d\n", slice, ret); 937 goto halt_pru; 938 } 939 940 ret = rproc_set_firmware(prueth->txpru[slice], firmwares[slice].txpru); 941 ret = rproc_boot(prueth->txpru[slice]); 942 if (ret) { 943 dev_err(dev, "failed to boot TX_PRU%d: %d\n", slice, ret); 944 goto halt_rtu; 945 } 946 947 emac->fw_running = 1; 948 return 0; 949 950 halt_rtu: 951 rproc_shutdown(prueth->rtu[slice]); 952 953 halt_pru: 954 rproc_shutdown(prueth->pru[slice]); 955 956 return ret; 957 } 958 959 static void prueth_emac_stop(struct prueth_emac *emac) 960 { 961 struct prueth *prueth = emac->prueth; 962 int slice; 963 964 switch (emac->port_id) { 965 case PRUETH_PORT_MII0: 966 slice = ICSS_SLICE0; 967 break; 968 case PRUETH_PORT_MII1: 969 slice = ICSS_SLICE1; 970 break; 971 default: 972 netdev_err(emac->ndev, "invalid port\n"); 973 return; 974 } 975 976 emac->fw_running = 0; 977 rproc_shutdown(prueth->txpru[slice]); 978 rproc_shutdown(prueth->rtu[slice]); 979 rproc_shutdown(prueth->pru[slice]); 980 } 981 982 static void prueth_cleanup_tx_ts(struct prueth_emac *emac) 983 { 984 int i; 985 986 for (i = 0; i < PRUETH_MAX_TX_TS_REQUESTS; i++) { 987 if (emac->tx_ts_skb[i]) { 988 dev_kfree_skb_any(emac->tx_ts_skb[i]); 989 emac->tx_ts_skb[i] = NULL; 990 } 991 } 992 } 993 994 /* called back by PHY layer if there is change in link state of hw port*/ 995 static void emac_adjust_link(struct net_device *ndev) 996 { 997 struct prueth_emac *emac = netdev_priv(ndev); 998 struct phy_device *phydev = ndev->phydev; 999 struct prueth *prueth = emac->prueth; 1000 bool new_state = false; 1001 unsigned long flags; 1002 1003 if (phydev->link) { 1004 /* check the mode of operation - full/half duplex */ 1005 if (phydev->duplex != emac->duplex) { 1006 new_state = true; 1007 emac->duplex = phydev->duplex; 1008 } 1009 if (phydev->speed != emac->speed) { 1010 new_state = true; 1011 emac->speed = phydev->speed; 1012 } 1013 if (!emac->link) { 1014 new_state = true; 1015 emac->link = 1; 1016 } 1017 } else if (emac->link) { 1018 new_state = true; 1019 emac->link = 0; 1020 1021 /* f/w should support 100 & 1000 */ 1022 emac->speed = SPEED_1000; 1023 1024 /* half duplex may not be supported by f/w */ 1025 emac->duplex = DUPLEX_FULL; 1026 } 1027 1028 if (new_state) { 1029 phy_print_status(phydev); 1030 1031 /* update RGMII and MII configuration based on PHY negotiated 1032 * values 1033 */ 1034 if (emac->link) { 1035 /* Set the RGMII cfg for gig en and full duplex */ 1036 icssg_update_rgmii_cfg(prueth->miig_rt, emac); 1037 1038 /* update the Tx IPG based on 100M/1G speed */ 1039 spin_lock_irqsave(&emac->lock, flags); 1040 icssg_config_ipg(emac); 1041 spin_unlock_irqrestore(&emac->lock, flags); 1042 icssg_config_set_speed(emac); 1043 emac_set_port_state(emac, ICSSG_EMAC_PORT_FORWARD); 1044 1045 } else { 1046 emac_set_port_state(emac, ICSSG_EMAC_PORT_DISABLE); 1047 } 1048 } 1049 1050 if (emac->link) { 1051 /* reactivate the transmit queue */ 1052 netif_tx_wake_all_queues(ndev); 1053 } else { 1054 netif_tx_stop_all_queues(ndev); 1055 prueth_cleanup_tx_ts(emac); 1056 } 1057 } 1058 1059 static int emac_napi_rx_poll(struct napi_struct *napi_rx, int budget) 1060 { 1061 struct prueth_emac *emac = prueth_napi_to_emac(napi_rx); 1062 int rx_flow = PRUETH_RX_FLOW_DATA; 1063 int flow = PRUETH_MAX_RX_FLOWS; 1064 int num_rx = 0; 1065 int cur_budget; 1066 int ret; 1067 1068 while (flow--) { 1069 cur_budget = budget - num_rx; 1070 1071 while (cur_budget--) { 1072 ret = emac_rx_packet(emac, flow); 1073 if (ret) 1074 break; 1075 num_rx++; 1076 } 1077 1078 if (num_rx >= budget) 1079 break; 1080 } 1081 1082 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) 1083 enable_irq(emac->rx_chns.irq[rx_flow]); 1084 1085 return num_rx; 1086 } 1087 1088 static int prueth_prepare_rx_chan(struct prueth_emac *emac, 1089 struct prueth_rx_chn *chn, 1090 int buf_size) 1091 { 1092 struct sk_buff *skb; 1093 int i, ret; 1094 1095 for (i = 0; i < chn->descs_num; i++) { 1096 skb = __netdev_alloc_skb_ip_align(NULL, buf_size, GFP_KERNEL); 1097 if (!skb) 1098 return -ENOMEM; 1099 1100 ret = prueth_dma_rx_push(emac, skb, chn); 1101 if (ret < 0) { 1102 netdev_err(emac->ndev, 1103 "cannot submit skb for rx chan %s ret %d\n", 1104 chn->name, ret); 1105 kfree_skb(skb); 1106 return ret; 1107 } 1108 } 1109 1110 return 0; 1111 } 1112 1113 static void prueth_reset_tx_chan(struct prueth_emac *emac, int ch_num, 1114 bool free_skb) 1115 { 1116 int i; 1117 1118 for (i = 0; i < ch_num; i++) { 1119 if (free_skb) 1120 k3_udma_glue_reset_tx_chn(emac->tx_chns[i].tx_chn, 1121 &emac->tx_chns[i], 1122 prueth_tx_cleanup); 1123 k3_udma_glue_disable_tx_chn(emac->tx_chns[i].tx_chn); 1124 } 1125 } 1126 1127 static void prueth_reset_rx_chan(struct prueth_rx_chn *chn, 1128 int num_flows, bool disable) 1129 { 1130 int i; 1131 1132 for (i = 0; i < num_flows; i++) 1133 k3_udma_glue_reset_rx_chn(chn->rx_chn, i, chn, 1134 prueth_rx_cleanup, !!i); 1135 if (disable) 1136 k3_udma_glue_disable_rx_chn(chn->rx_chn); 1137 } 1138 1139 static int emac_phy_connect(struct prueth_emac *emac) 1140 { 1141 struct prueth *prueth = emac->prueth; 1142 struct net_device *ndev = emac->ndev; 1143 /* connect PHY */ 1144 ndev->phydev = of_phy_connect(emac->ndev, emac->phy_node, 1145 &emac_adjust_link, 0, 1146 emac->phy_if); 1147 if (!ndev->phydev) { 1148 dev_err(prueth->dev, "couldn't connect to phy %s\n", 1149 emac->phy_node->full_name); 1150 return -ENODEV; 1151 } 1152 1153 /* remove unsupported modes */ 1154 phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1155 phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1156 phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1157 phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1158 phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1159 1160 if (emac->phy_if == PHY_INTERFACE_MODE_MII) 1161 phy_set_max_speed(ndev->phydev, SPEED_100); 1162 1163 return 0; 1164 } 1165 1166 static u64 prueth_iep_gettime(void *clockops_data, struct ptp_system_timestamp *sts) 1167 { 1168 u32 hi_rollover_count, hi_rollover_count_r; 1169 struct prueth_emac *emac = clockops_data; 1170 struct prueth *prueth = emac->prueth; 1171 void __iomem *fw_hi_r_count_addr; 1172 void __iomem *fw_count_hi_addr; 1173 u32 iepcount_hi, iepcount_hi_r; 1174 unsigned long flags; 1175 u32 iepcount_lo; 1176 u64 ts = 0; 1177 1178 fw_count_hi_addr = prueth->shram.va + TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET; 1179 fw_hi_r_count_addr = prueth->shram.va + TIMESYNC_FW_WC_HI_ROLLOVER_COUNT_OFFSET; 1180 1181 local_irq_save(flags); 1182 do { 1183 iepcount_hi = icss_iep_get_count_hi(emac->iep); 1184 iepcount_hi += readl(fw_count_hi_addr); 1185 hi_rollover_count = readl(fw_hi_r_count_addr); 1186 ptp_read_system_prets(sts); 1187 iepcount_lo = icss_iep_get_count_low(emac->iep); 1188 ptp_read_system_postts(sts); 1189 1190 iepcount_hi_r = icss_iep_get_count_hi(emac->iep); 1191 iepcount_hi_r += readl(fw_count_hi_addr); 1192 hi_rollover_count_r = readl(fw_hi_r_count_addr); 1193 } while ((iepcount_hi_r != iepcount_hi) || 1194 (hi_rollover_count != hi_rollover_count_r)); 1195 local_irq_restore(flags); 1196 1197 ts = ((u64)hi_rollover_count) << 23 | iepcount_hi; 1198 ts = ts * (u64)IEP_DEFAULT_CYCLE_TIME_NS + iepcount_lo; 1199 1200 return ts; 1201 } 1202 1203 static void prueth_iep_settime(void *clockops_data, u64 ns) 1204 { 1205 struct icssg_setclock_desc __iomem *sc_descp; 1206 struct prueth_emac *emac = clockops_data; 1207 struct icssg_setclock_desc sc_desc; 1208 u64 cyclecount; 1209 u32 cycletime; 1210 int timeout; 1211 1212 if (!emac->fw_running) 1213 return; 1214 1215 sc_descp = emac->prueth->shram.va + TIMESYNC_FW_WC_SETCLOCK_DESC_OFFSET; 1216 1217 cycletime = IEP_DEFAULT_CYCLE_TIME_NS; 1218 cyclecount = ns / cycletime; 1219 1220 memset(&sc_desc, 0, sizeof(sc_desc)); 1221 sc_desc.margin = cycletime - 1000; 1222 sc_desc.cyclecounter0_set = cyclecount & GENMASK(31, 0); 1223 sc_desc.cyclecounter1_set = (cyclecount & GENMASK(63, 32)) >> 32; 1224 sc_desc.iepcount_set = ns % cycletime; 1225 sc_desc.CMP0_current = cycletime - 4; //Count from 0 to (cycle time)-4 1226 1227 memcpy_toio(sc_descp, &sc_desc, sizeof(sc_desc)); 1228 1229 writeb(1, &sc_descp->request); 1230 1231 timeout = 5; /* fw should take 2-3 ms */ 1232 while (timeout--) { 1233 if (readb(&sc_descp->acknowledgment)) 1234 return; 1235 1236 usleep_range(500, 1000); 1237 } 1238 1239 dev_err(emac->prueth->dev, "settime timeout\n"); 1240 } 1241 1242 static int prueth_perout_enable(void *clockops_data, 1243 struct ptp_perout_request *req, int on, 1244 u64 *cmp) 1245 { 1246 struct prueth_emac *emac = clockops_data; 1247 u32 reduction_factor = 0, offset = 0; 1248 struct timespec64 ts; 1249 u64 current_cycle; 1250 u64 start_offset; 1251 u64 ns_period; 1252 1253 if (!on) 1254 return 0; 1255 1256 /* Any firmware specific stuff for PPS/PEROUT handling */ 1257 ts.tv_sec = req->period.sec; 1258 ts.tv_nsec = req->period.nsec; 1259 ns_period = timespec64_to_ns(&ts); 1260 1261 /* f/w doesn't support period less than cycle time */ 1262 if (ns_period < IEP_DEFAULT_CYCLE_TIME_NS) 1263 return -ENXIO; 1264 1265 reduction_factor = ns_period / IEP_DEFAULT_CYCLE_TIME_NS; 1266 offset = ns_period % IEP_DEFAULT_CYCLE_TIME_NS; 1267 1268 /* f/w requires at least 1uS within a cycle so CMP 1269 * can trigger after SYNC is enabled 1270 */ 1271 if (offset < 5 * NSEC_PER_USEC) 1272 offset = 5 * NSEC_PER_USEC; 1273 1274 /* if offset is close to cycle time then we will miss 1275 * the CMP event for last tick when IEP rolls over. 1276 * In normal mode, IEP tick is 4ns. 1277 * In slow compensation it could be 0ns or 8ns at 1278 * every slow compensation cycle. 1279 */ 1280 if (offset > IEP_DEFAULT_CYCLE_TIME_NS - 8) 1281 offset = IEP_DEFAULT_CYCLE_TIME_NS - 8; 1282 1283 /* we're in shadow mode so need to set upper 32-bits */ 1284 *cmp = (u64)offset << 32; 1285 1286 writel(reduction_factor, emac->prueth->shram.va + 1287 TIMESYNC_FW_WC_SYNCOUT_REDUCTION_FACTOR_OFFSET); 1288 1289 current_cycle = icssg_read_time(emac->prueth->shram.va + 1290 TIMESYNC_FW_WC_CYCLECOUNT_OFFSET); 1291 1292 /* Rounding of current_cycle count to next second */ 1293 start_offset = roundup(current_cycle, MSEC_PER_SEC); 1294 1295 hi_lo_writeq(start_offset, emac->prueth->shram.va + 1296 TIMESYNC_FW_WC_SYNCOUT_START_TIME_CYCLECOUNT_OFFSET); 1297 1298 return 0; 1299 } 1300 1301 const struct icss_iep_clockops prueth_iep_clockops = { 1302 .settime = prueth_iep_settime, 1303 .gettime = prueth_iep_gettime, 1304 .perout_enable = prueth_perout_enable, 1305 }; 1306 1307 /** 1308 * emac_ndo_open - EMAC device open 1309 * @ndev: network adapter device 1310 * 1311 * Called when system wants to start the interface. 1312 * 1313 * Return: 0 for a successful open, or appropriate error code 1314 */ 1315 static int emac_ndo_open(struct net_device *ndev) 1316 { 1317 struct prueth_emac *emac = netdev_priv(ndev); 1318 int ret, i, num_data_chn = emac->tx_ch_num; 1319 struct prueth *prueth = emac->prueth; 1320 int slice = prueth_emac_slice(emac); 1321 struct device *dev = prueth->dev; 1322 int max_rx_flows; 1323 int rx_flow; 1324 1325 /* clear SMEM and MSMC settings for all slices */ 1326 if (!prueth->emacs_initialized) { 1327 memset_io(prueth->msmcram.va, 0, prueth->msmcram.size); 1328 memset_io(prueth->shram.va, 0, ICSSG_CONFIG_OFFSET_SLICE1 * PRUETH_NUM_MACS); 1329 } 1330 1331 /* set h/w MAC as user might have re-configured */ 1332 ether_addr_copy(emac->mac_addr, ndev->dev_addr); 1333 1334 icssg_class_set_mac_addr(prueth->miig_rt, slice, emac->mac_addr); 1335 icssg_ft1_set_mac_addr(prueth->miig_rt, slice, emac->mac_addr); 1336 1337 icssg_class_default(prueth->miig_rt, slice, 0); 1338 1339 /* Notify the stack of the actual queue counts. */ 1340 ret = netif_set_real_num_tx_queues(ndev, num_data_chn); 1341 if (ret) { 1342 dev_err(dev, "cannot set real number of tx queues\n"); 1343 return ret; 1344 } 1345 1346 init_completion(&emac->cmd_complete); 1347 ret = prueth_init_tx_chns(emac); 1348 if (ret) { 1349 dev_err(dev, "failed to init tx channel: %d\n", ret); 1350 return ret; 1351 } 1352 1353 max_rx_flows = PRUETH_MAX_RX_FLOWS; 1354 ret = prueth_init_rx_chns(emac, &emac->rx_chns, "rx", 1355 max_rx_flows, PRUETH_MAX_RX_DESC); 1356 if (ret) { 1357 dev_err(dev, "failed to init rx channel: %d\n", ret); 1358 goto cleanup_tx; 1359 } 1360 1361 ret = prueth_ndev_add_tx_napi(emac); 1362 if (ret) 1363 goto cleanup_rx; 1364 1365 /* we use only the highest priority flow for now i.e. @irq[3] */ 1366 rx_flow = PRUETH_RX_FLOW_DATA; 1367 ret = request_irq(emac->rx_chns.irq[rx_flow], prueth_rx_irq, 1368 IRQF_TRIGGER_HIGH, dev_name(dev), emac); 1369 if (ret) { 1370 dev_err(dev, "unable to request RX IRQ\n"); 1371 goto cleanup_napi; 1372 } 1373 1374 /* reset and start PRU firmware */ 1375 ret = prueth_emac_start(prueth, emac); 1376 if (ret) 1377 goto free_rx_irq; 1378 1379 icssg_mii_update_mtu(prueth->mii_rt, slice, ndev->max_mtu); 1380 1381 if (!prueth->emacs_initialized) { 1382 ret = icss_iep_init(emac->iep, &prueth_iep_clockops, 1383 emac, IEP_DEFAULT_CYCLE_TIME_NS); 1384 } 1385 1386 ret = request_threaded_irq(emac->tx_ts_irq, NULL, prueth_tx_ts_irq, 1387 IRQF_ONESHOT, dev_name(dev), emac); 1388 if (ret) 1389 goto stop; 1390 1391 /* Prepare RX */ 1392 ret = prueth_prepare_rx_chan(emac, &emac->rx_chns, PRUETH_MAX_PKT_SIZE); 1393 if (ret) 1394 goto free_tx_ts_irq; 1395 1396 ret = k3_udma_glue_enable_rx_chn(emac->rx_chns.rx_chn); 1397 if (ret) 1398 goto reset_rx_chn; 1399 1400 for (i = 0; i < emac->tx_ch_num; i++) { 1401 ret = k3_udma_glue_enable_tx_chn(emac->tx_chns[i].tx_chn); 1402 if (ret) 1403 goto reset_tx_chan; 1404 } 1405 1406 /* Enable NAPI in Tx and Rx direction */ 1407 for (i = 0; i < emac->tx_ch_num; i++) 1408 napi_enable(&emac->tx_chns[i].napi_tx); 1409 napi_enable(&emac->napi_rx); 1410 1411 /* start PHY */ 1412 phy_start(ndev->phydev); 1413 1414 prueth->emacs_initialized++; 1415 1416 queue_work(system_long_wq, &emac->stats_work.work); 1417 1418 return 0; 1419 1420 reset_tx_chan: 1421 /* Since interface is not yet up, there is wouldn't be 1422 * any SKB for completion. So set false to free_skb 1423 */ 1424 prueth_reset_tx_chan(emac, i, false); 1425 reset_rx_chn: 1426 prueth_reset_rx_chan(&emac->rx_chns, max_rx_flows, false); 1427 free_tx_ts_irq: 1428 free_irq(emac->tx_ts_irq, emac); 1429 stop: 1430 prueth_emac_stop(emac); 1431 free_rx_irq: 1432 free_irq(emac->rx_chns.irq[rx_flow], emac); 1433 cleanup_napi: 1434 prueth_ndev_del_tx_napi(emac, emac->tx_ch_num); 1435 cleanup_rx: 1436 prueth_cleanup_rx_chns(emac, &emac->rx_chns, max_rx_flows); 1437 cleanup_tx: 1438 prueth_cleanup_tx_chns(emac); 1439 1440 return ret; 1441 } 1442 1443 /** 1444 * emac_ndo_stop - EMAC device stop 1445 * @ndev: network adapter device 1446 * 1447 * Called when system wants to stop or down the interface. 1448 * 1449 * Return: Always 0 (Success) 1450 */ 1451 static int emac_ndo_stop(struct net_device *ndev) 1452 { 1453 struct prueth_emac *emac = netdev_priv(ndev); 1454 struct prueth *prueth = emac->prueth; 1455 int rx_flow = PRUETH_RX_FLOW_DATA; 1456 int max_rx_flows; 1457 int ret, i; 1458 1459 /* inform the upper layers. */ 1460 netif_tx_stop_all_queues(ndev); 1461 1462 /* block packets from wire */ 1463 if (ndev->phydev) 1464 phy_stop(ndev->phydev); 1465 1466 icssg_class_disable(prueth->miig_rt, prueth_emac_slice(emac)); 1467 1468 atomic_set(&emac->tdown_cnt, emac->tx_ch_num); 1469 /* ensure new tdown_cnt value is visible */ 1470 smp_mb__after_atomic(); 1471 /* tear down and disable UDMA channels */ 1472 reinit_completion(&emac->tdown_complete); 1473 for (i = 0; i < emac->tx_ch_num; i++) 1474 k3_udma_glue_tdown_tx_chn(emac->tx_chns[i].tx_chn, false); 1475 1476 ret = wait_for_completion_timeout(&emac->tdown_complete, 1477 msecs_to_jiffies(1000)); 1478 if (!ret) 1479 netdev_err(ndev, "tx teardown timeout\n"); 1480 1481 prueth_reset_tx_chan(emac, emac->tx_ch_num, true); 1482 for (i = 0; i < emac->tx_ch_num; i++) 1483 napi_disable(&emac->tx_chns[i].napi_tx); 1484 1485 max_rx_flows = PRUETH_MAX_RX_FLOWS; 1486 k3_udma_glue_tdown_rx_chn(emac->rx_chns.rx_chn, true); 1487 1488 prueth_reset_rx_chan(&emac->rx_chns, max_rx_flows, true); 1489 1490 napi_disable(&emac->napi_rx); 1491 1492 cancel_work_sync(&emac->rx_mode_work); 1493 1494 /* Destroying the queued work in ndo_stop() */ 1495 cancel_delayed_work_sync(&emac->stats_work); 1496 1497 /* stop PRUs */ 1498 prueth_emac_stop(emac); 1499 1500 if (prueth->emacs_initialized == 1) 1501 icss_iep_exit(emac->iep); 1502 1503 /* stop PRUs */ 1504 prueth_emac_stop(emac); 1505 1506 free_irq(emac->tx_ts_irq, emac); 1507 1508 free_irq(emac->rx_chns.irq[rx_flow], emac); 1509 prueth_ndev_del_tx_napi(emac, emac->tx_ch_num); 1510 prueth_cleanup_tx_chns(emac); 1511 1512 prueth_cleanup_rx_chns(emac, &emac->rx_chns, max_rx_flows); 1513 prueth_cleanup_tx_chns(emac); 1514 1515 prueth->emacs_initialized--; 1516 1517 return 0; 1518 } 1519 1520 static void emac_ndo_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1521 { 1522 ndev->stats.tx_errors++; 1523 } 1524 1525 static void emac_ndo_set_rx_mode_work(struct work_struct *work) 1526 { 1527 struct prueth_emac *emac = container_of(work, struct prueth_emac, rx_mode_work); 1528 struct net_device *ndev = emac->ndev; 1529 bool promisc, allmulti; 1530 1531 if (!netif_running(ndev)) 1532 return; 1533 1534 promisc = ndev->flags & IFF_PROMISC; 1535 allmulti = ndev->flags & IFF_ALLMULTI; 1536 emac_set_port_state(emac, ICSSG_EMAC_PORT_UC_FLOODING_DISABLE); 1537 emac_set_port_state(emac, ICSSG_EMAC_PORT_MC_FLOODING_DISABLE); 1538 1539 if (promisc) { 1540 emac_set_port_state(emac, ICSSG_EMAC_PORT_UC_FLOODING_ENABLE); 1541 emac_set_port_state(emac, ICSSG_EMAC_PORT_MC_FLOODING_ENABLE); 1542 return; 1543 } 1544 1545 if (allmulti) { 1546 emac_set_port_state(emac, ICSSG_EMAC_PORT_MC_FLOODING_ENABLE); 1547 return; 1548 } 1549 1550 if (!netdev_mc_empty(ndev)) { 1551 emac_set_port_state(emac, ICSSG_EMAC_PORT_MC_FLOODING_ENABLE); 1552 return; 1553 } 1554 } 1555 1556 /** 1557 * emac_ndo_set_rx_mode - EMAC set receive mode function 1558 * @ndev: The EMAC network adapter 1559 * 1560 * Called when system wants to set the receive mode of the device. 1561 * 1562 */ 1563 static void emac_ndo_set_rx_mode(struct net_device *ndev) 1564 { 1565 struct prueth_emac *emac = netdev_priv(ndev); 1566 1567 queue_work(emac->cmd_wq, &emac->rx_mode_work); 1568 } 1569 1570 static int emac_set_ts_config(struct net_device *ndev, struct ifreq *ifr) 1571 { 1572 struct prueth_emac *emac = netdev_priv(ndev); 1573 struct hwtstamp_config config; 1574 1575 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1576 return -EFAULT; 1577 1578 switch (config.tx_type) { 1579 case HWTSTAMP_TX_OFF: 1580 emac->tx_ts_enabled = 0; 1581 break; 1582 case HWTSTAMP_TX_ON: 1583 emac->tx_ts_enabled = 1; 1584 break; 1585 default: 1586 return -ERANGE; 1587 } 1588 1589 switch (config.rx_filter) { 1590 case HWTSTAMP_FILTER_NONE: 1591 emac->rx_ts_enabled = 0; 1592 break; 1593 case HWTSTAMP_FILTER_ALL: 1594 case HWTSTAMP_FILTER_SOME: 1595 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1596 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1597 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1598 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1599 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1600 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1601 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1602 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1603 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1604 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1605 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1606 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1607 case HWTSTAMP_FILTER_NTP_ALL: 1608 emac->rx_ts_enabled = 1; 1609 config.rx_filter = HWTSTAMP_FILTER_ALL; 1610 break; 1611 default: 1612 return -ERANGE; 1613 } 1614 1615 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1616 -EFAULT : 0; 1617 } 1618 1619 static int emac_get_ts_config(struct net_device *ndev, struct ifreq *ifr) 1620 { 1621 struct prueth_emac *emac = netdev_priv(ndev); 1622 struct hwtstamp_config config; 1623 1624 config.flags = 0; 1625 config.tx_type = emac->tx_ts_enabled ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1626 config.rx_filter = emac->rx_ts_enabled ? HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 1627 1628 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1629 -EFAULT : 0; 1630 } 1631 1632 static int emac_ndo_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd) 1633 { 1634 switch (cmd) { 1635 case SIOCGHWTSTAMP: 1636 return emac_get_ts_config(ndev, ifr); 1637 case SIOCSHWTSTAMP: 1638 return emac_set_ts_config(ndev, ifr); 1639 default: 1640 break; 1641 } 1642 1643 return phy_do_ioctl(ndev, ifr, cmd); 1644 } 1645 1646 static void emac_ndo_get_stats64(struct net_device *ndev, 1647 struct rtnl_link_stats64 *stats) 1648 { 1649 struct prueth_emac *emac = netdev_priv(ndev); 1650 1651 emac_update_hardware_stats(emac); 1652 1653 stats->rx_packets = emac_get_stat_by_name(emac, "rx_packets"); 1654 stats->rx_bytes = emac_get_stat_by_name(emac, "rx_bytes"); 1655 stats->tx_packets = emac_get_stat_by_name(emac, "tx_packets"); 1656 stats->tx_bytes = emac_get_stat_by_name(emac, "tx_bytes"); 1657 stats->rx_crc_errors = emac_get_stat_by_name(emac, "rx_crc_errors"); 1658 stats->rx_over_errors = emac_get_stat_by_name(emac, "rx_over_errors"); 1659 stats->multicast = emac_get_stat_by_name(emac, "rx_multicast_frames"); 1660 1661 stats->rx_errors = ndev->stats.rx_errors; 1662 stats->rx_dropped = ndev->stats.rx_dropped; 1663 stats->tx_errors = ndev->stats.tx_errors; 1664 stats->tx_dropped = ndev->stats.tx_dropped; 1665 } 1666 1667 static const struct net_device_ops emac_netdev_ops = { 1668 .ndo_open = emac_ndo_open, 1669 .ndo_stop = emac_ndo_stop, 1670 .ndo_start_xmit = emac_ndo_start_xmit, 1671 .ndo_set_mac_address = eth_mac_addr, 1672 .ndo_validate_addr = eth_validate_addr, 1673 .ndo_tx_timeout = emac_ndo_tx_timeout, 1674 .ndo_set_rx_mode = emac_ndo_set_rx_mode, 1675 .ndo_eth_ioctl = emac_ndo_ioctl, 1676 .ndo_get_stats64 = emac_ndo_get_stats64, 1677 }; 1678 1679 /* get emac_port corresponding to eth_node name */ 1680 static int prueth_node_port(struct device_node *eth_node) 1681 { 1682 u32 port_id; 1683 int ret; 1684 1685 ret = of_property_read_u32(eth_node, "reg", &port_id); 1686 if (ret) 1687 return ret; 1688 1689 if (port_id == 0) 1690 return PRUETH_PORT_MII0; 1691 else if (port_id == 1) 1692 return PRUETH_PORT_MII1; 1693 else 1694 return PRUETH_PORT_INVALID; 1695 } 1696 1697 /* get MAC instance corresponding to eth_node name */ 1698 static int prueth_node_mac(struct device_node *eth_node) 1699 { 1700 u32 port_id; 1701 int ret; 1702 1703 ret = of_property_read_u32(eth_node, "reg", &port_id); 1704 if (ret) 1705 return ret; 1706 1707 if (port_id == 0) 1708 return PRUETH_MAC0; 1709 else if (port_id == 1) 1710 return PRUETH_MAC1; 1711 else 1712 return PRUETH_MAC_INVALID; 1713 } 1714 1715 static int prueth_netdev_init(struct prueth *prueth, 1716 struct device_node *eth_node) 1717 { 1718 int ret, num_tx_chn = PRUETH_MAX_TX_QUEUES; 1719 struct prueth_emac *emac; 1720 struct net_device *ndev; 1721 enum prueth_port port; 1722 const char *irq_name; 1723 enum prueth_mac mac; 1724 1725 port = prueth_node_port(eth_node); 1726 if (port == PRUETH_PORT_INVALID) 1727 return -EINVAL; 1728 1729 mac = prueth_node_mac(eth_node); 1730 if (mac == PRUETH_MAC_INVALID) 1731 return -EINVAL; 1732 1733 ndev = alloc_etherdev_mq(sizeof(*emac), num_tx_chn); 1734 if (!ndev) 1735 return -ENOMEM; 1736 1737 emac = netdev_priv(ndev); 1738 emac->prueth = prueth; 1739 emac->ndev = ndev; 1740 emac->port_id = port; 1741 emac->cmd_wq = create_singlethread_workqueue("icssg_cmd_wq"); 1742 if (!emac->cmd_wq) { 1743 ret = -ENOMEM; 1744 goto free_ndev; 1745 } 1746 INIT_WORK(&emac->rx_mode_work, emac_ndo_set_rx_mode_work); 1747 1748 INIT_DELAYED_WORK(&emac->stats_work, emac_stats_work_handler); 1749 1750 ret = pruss_request_mem_region(prueth->pruss, 1751 port == PRUETH_PORT_MII0 ? 1752 PRUSS_MEM_DRAM0 : PRUSS_MEM_DRAM1, 1753 &emac->dram); 1754 if (ret) { 1755 dev_err(prueth->dev, "unable to get DRAM: %d\n", ret); 1756 ret = -ENOMEM; 1757 goto free_wq; 1758 } 1759 1760 emac->tx_ch_num = 1; 1761 1762 irq_name = "tx_ts0"; 1763 if (emac->port_id == PRUETH_PORT_MII1) 1764 irq_name = "tx_ts1"; 1765 emac->tx_ts_irq = platform_get_irq_byname_optional(prueth->pdev, irq_name); 1766 if (emac->tx_ts_irq < 0) { 1767 ret = dev_err_probe(prueth->dev, emac->tx_ts_irq, "could not get tx_ts_irq\n"); 1768 goto free; 1769 } 1770 1771 SET_NETDEV_DEV(ndev, prueth->dev); 1772 spin_lock_init(&emac->lock); 1773 mutex_init(&emac->cmd_lock); 1774 1775 emac->phy_node = of_parse_phandle(eth_node, "phy-handle", 0); 1776 if (!emac->phy_node && !of_phy_is_fixed_link(eth_node)) { 1777 dev_err(prueth->dev, "couldn't find phy-handle\n"); 1778 ret = -ENODEV; 1779 goto free; 1780 } else if (of_phy_is_fixed_link(eth_node)) { 1781 ret = of_phy_register_fixed_link(eth_node); 1782 if (ret) { 1783 ret = dev_err_probe(prueth->dev, ret, 1784 "failed to register fixed-link phy\n"); 1785 goto free; 1786 } 1787 1788 emac->phy_node = eth_node; 1789 } 1790 1791 ret = of_get_phy_mode(eth_node, &emac->phy_if); 1792 if (ret) { 1793 dev_err(prueth->dev, "could not get phy-mode property\n"); 1794 goto free; 1795 } 1796 1797 if (emac->phy_if != PHY_INTERFACE_MODE_MII && 1798 !phy_interface_mode_is_rgmii(emac->phy_if)) { 1799 dev_err(prueth->dev, "PHY mode unsupported %s\n", phy_modes(emac->phy_if)); 1800 ret = -EINVAL; 1801 goto free; 1802 } 1803 1804 /* AM65 SR2.0 has TX Internal delay always enabled by hardware 1805 * and it is not possible to disable TX Internal delay. The below 1806 * switch case block describes how we handle different phy modes 1807 * based on hardware restriction. 1808 */ 1809 switch (emac->phy_if) { 1810 case PHY_INTERFACE_MODE_RGMII_ID: 1811 emac->phy_if = PHY_INTERFACE_MODE_RGMII_RXID; 1812 break; 1813 case PHY_INTERFACE_MODE_RGMII_TXID: 1814 emac->phy_if = PHY_INTERFACE_MODE_RGMII; 1815 break; 1816 case PHY_INTERFACE_MODE_RGMII: 1817 case PHY_INTERFACE_MODE_RGMII_RXID: 1818 dev_err(prueth->dev, "RGMII mode without TX delay is not supported"); 1819 ret = -EINVAL; 1820 goto free; 1821 default: 1822 break; 1823 } 1824 1825 /* get mac address from DT and set private and netdev addr */ 1826 ret = of_get_ethdev_address(eth_node, ndev); 1827 if (!is_valid_ether_addr(ndev->dev_addr)) { 1828 eth_hw_addr_random(ndev); 1829 dev_warn(prueth->dev, "port %d: using random MAC addr: %pM\n", 1830 port, ndev->dev_addr); 1831 } 1832 ether_addr_copy(emac->mac_addr, ndev->dev_addr); 1833 1834 ndev->min_mtu = PRUETH_MIN_PKT_SIZE; 1835 ndev->max_mtu = PRUETH_MAX_MTU; 1836 ndev->netdev_ops = &emac_netdev_ops; 1837 ndev->ethtool_ops = &icssg_ethtool_ops; 1838 ndev->hw_features = NETIF_F_SG; 1839 ndev->features = ndev->hw_features; 1840 1841 netif_napi_add(ndev, &emac->napi_rx, emac_napi_rx_poll); 1842 prueth->emac[mac] = emac; 1843 1844 return 0; 1845 1846 free: 1847 pruss_release_mem_region(prueth->pruss, &emac->dram); 1848 free_wq: 1849 destroy_workqueue(emac->cmd_wq); 1850 free_ndev: 1851 emac->ndev = NULL; 1852 prueth->emac[mac] = NULL; 1853 free_netdev(ndev); 1854 1855 return ret; 1856 } 1857 1858 static void prueth_netdev_exit(struct prueth *prueth, 1859 struct device_node *eth_node) 1860 { 1861 struct prueth_emac *emac; 1862 enum prueth_mac mac; 1863 1864 mac = prueth_node_mac(eth_node); 1865 if (mac == PRUETH_MAC_INVALID) 1866 return; 1867 1868 emac = prueth->emac[mac]; 1869 if (!emac) 1870 return; 1871 1872 if (of_phy_is_fixed_link(emac->phy_node)) 1873 of_phy_deregister_fixed_link(emac->phy_node); 1874 1875 netif_napi_del(&emac->napi_rx); 1876 1877 pruss_release_mem_region(prueth->pruss, &emac->dram); 1878 destroy_workqueue(emac->cmd_wq); 1879 free_netdev(emac->ndev); 1880 prueth->emac[mac] = NULL; 1881 } 1882 1883 static int prueth_get_cores(struct prueth *prueth, int slice) 1884 { 1885 struct device *dev = prueth->dev; 1886 enum pruss_pru_id pruss_id; 1887 struct device_node *np; 1888 int idx = -1, ret; 1889 1890 np = dev->of_node; 1891 1892 switch (slice) { 1893 case ICSS_SLICE0: 1894 idx = 0; 1895 break; 1896 case ICSS_SLICE1: 1897 idx = 3; 1898 break; 1899 default: 1900 return -EINVAL; 1901 } 1902 1903 prueth->pru[slice] = pru_rproc_get(np, idx, &pruss_id); 1904 if (IS_ERR(prueth->pru[slice])) { 1905 ret = PTR_ERR(prueth->pru[slice]); 1906 prueth->pru[slice] = NULL; 1907 return dev_err_probe(dev, ret, "unable to get PRU%d\n", slice); 1908 } 1909 prueth->pru_id[slice] = pruss_id; 1910 1911 idx++; 1912 prueth->rtu[slice] = pru_rproc_get(np, idx, NULL); 1913 if (IS_ERR(prueth->rtu[slice])) { 1914 ret = PTR_ERR(prueth->rtu[slice]); 1915 prueth->rtu[slice] = NULL; 1916 return dev_err_probe(dev, ret, "unable to get RTU%d\n", slice); 1917 } 1918 1919 idx++; 1920 prueth->txpru[slice] = pru_rproc_get(np, idx, NULL); 1921 if (IS_ERR(prueth->txpru[slice])) { 1922 ret = PTR_ERR(prueth->txpru[slice]); 1923 prueth->txpru[slice] = NULL; 1924 return dev_err_probe(dev, ret, "unable to get TX_PRU%d\n", slice); 1925 } 1926 1927 return 0; 1928 } 1929 1930 static void prueth_put_cores(struct prueth *prueth, int slice) 1931 { 1932 if (prueth->txpru[slice]) 1933 pru_rproc_put(prueth->txpru[slice]); 1934 1935 if (prueth->rtu[slice]) 1936 pru_rproc_put(prueth->rtu[slice]); 1937 1938 if (prueth->pru[slice]) 1939 pru_rproc_put(prueth->pru[slice]); 1940 } 1941 1942 static const struct of_device_id prueth_dt_match[]; 1943 1944 static int prueth_probe(struct platform_device *pdev) 1945 { 1946 struct device_node *eth_node, *eth_ports_node; 1947 struct device_node *eth0_node = NULL; 1948 struct device_node *eth1_node = NULL; 1949 struct genpool_data_align gp_data = { 1950 .align = SZ_64K, 1951 }; 1952 const struct of_device_id *match; 1953 struct device *dev = &pdev->dev; 1954 struct device_node *np; 1955 struct prueth *prueth; 1956 struct pruss *pruss; 1957 u32 msmc_ram_size; 1958 int i, ret; 1959 1960 np = dev->of_node; 1961 1962 match = of_match_device(prueth_dt_match, dev); 1963 if (!match) 1964 return -ENODEV; 1965 1966 prueth = devm_kzalloc(dev, sizeof(*prueth), GFP_KERNEL); 1967 if (!prueth) 1968 return -ENOMEM; 1969 1970 dev_set_drvdata(dev, prueth); 1971 prueth->pdev = pdev; 1972 prueth->pdata = *(const struct prueth_pdata *)match->data; 1973 1974 prueth->dev = dev; 1975 eth_ports_node = of_get_child_by_name(np, "ethernet-ports"); 1976 if (!eth_ports_node) 1977 return -ENOENT; 1978 1979 for_each_child_of_node(eth_ports_node, eth_node) { 1980 u32 reg; 1981 1982 if (strcmp(eth_node->name, "port")) 1983 continue; 1984 ret = of_property_read_u32(eth_node, "reg", ®); 1985 if (ret < 0) { 1986 dev_err(dev, "%pOF error reading port_id %d\n", 1987 eth_node, ret); 1988 } 1989 1990 of_node_get(eth_node); 1991 1992 if (reg == 0) { 1993 eth0_node = eth_node; 1994 if (!of_device_is_available(eth0_node)) { 1995 of_node_put(eth0_node); 1996 eth0_node = NULL; 1997 } 1998 } else if (reg == 1) { 1999 eth1_node = eth_node; 2000 if (!of_device_is_available(eth1_node)) { 2001 of_node_put(eth1_node); 2002 eth1_node = NULL; 2003 } 2004 } else { 2005 dev_err(dev, "port reg should be 0 or 1\n"); 2006 } 2007 } 2008 2009 of_node_put(eth_ports_node); 2010 2011 /* At least one node must be present and available else we fail */ 2012 if (!eth0_node && !eth1_node) { 2013 dev_err(dev, "neither port0 nor port1 node available\n"); 2014 return -ENODEV; 2015 } 2016 2017 if (eth0_node == eth1_node) { 2018 dev_err(dev, "port0 and port1 can't have same reg\n"); 2019 of_node_put(eth0_node); 2020 return -ENODEV; 2021 } 2022 2023 prueth->eth_node[PRUETH_MAC0] = eth0_node; 2024 prueth->eth_node[PRUETH_MAC1] = eth1_node; 2025 2026 prueth->miig_rt = syscon_regmap_lookup_by_phandle(np, "ti,mii-g-rt"); 2027 if (IS_ERR(prueth->miig_rt)) { 2028 dev_err(dev, "couldn't get ti,mii-g-rt syscon regmap\n"); 2029 return -ENODEV; 2030 } 2031 2032 prueth->mii_rt = syscon_regmap_lookup_by_phandle(np, "ti,mii-rt"); 2033 if (IS_ERR(prueth->mii_rt)) { 2034 dev_err(dev, "couldn't get ti,mii-rt syscon regmap\n"); 2035 return -ENODEV; 2036 } 2037 2038 if (eth0_node) { 2039 ret = prueth_get_cores(prueth, ICSS_SLICE0); 2040 if (ret) 2041 goto put_cores; 2042 } 2043 2044 if (eth1_node) { 2045 ret = prueth_get_cores(prueth, ICSS_SLICE1); 2046 if (ret) 2047 goto put_cores; 2048 } 2049 2050 pruss = pruss_get(eth0_node ? 2051 prueth->pru[ICSS_SLICE0] : prueth->pru[ICSS_SLICE1]); 2052 if (IS_ERR(pruss)) { 2053 ret = PTR_ERR(pruss); 2054 dev_err(dev, "unable to get pruss handle\n"); 2055 goto put_cores; 2056 } 2057 2058 prueth->pruss = pruss; 2059 2060 ret = pruss_request_mem_region(pruss, PRUSS_MEM_SHRD_RAM2, 2061 &prueth->shram); 2062 if (ret) { 2063 dev_err(dev, "unable to get PRUSS SHRD RAM2: %d\n", ret); 2064 goto put_pruss; 2065 } 2066 2067 prueth->sram_pool = of_gen_pool_get(np, "sram", 0); 2068 if (!prueth->sram_pool) { 2069 dev_err(dev, "unable to get SRAM pool\n"); 2070 ret = -ENODEV; 2071 2072 goto put_mem; 2073 } 2074 2075 msmc_ram_size = MSMC_RAM_SIZE; 2076 2077 /* NOTE: FW bug needs buffer base to be 64KB aligned */ 2078 prueth->msmcram.va = 2079 (void __iomem *)gen_pool_alloc_algo(prueth->sram_pool, 2080 msmc_ram_size, 2081 gen_pool_first_fit_align, 2082 &gp_data); 2083 2084 if (!prueth->msmcram.va) { 2085 ret = -ENOMEM; 2086 dev_err(dev, "unable to allocate MSMC resource\n"); 2087 goto put_mem; 2088 } 2089 prueth->msmcram.pa = gen_pool_virt_to_phys(prueth->sram_pool, 2090 (unsigned long)prueth->msmcram.va); 2091 prueth->msmcram.size = msmc_ram_size; 2092 memset_io(prueth->msmcram.va, 0, msmc_ram_size); 2093 dev_dbg(dev, "sram: pa %llx va %p size %zx\n", prueth->msmcram.pa, 2094 prueth->msmcram.va, prueth->msmcram.size); 2095 2096 prueth->iep0 = icss_iep_get_idx(np, 0); 2097 if (IS_ERR(prueth->iep0)) { 2098 ret = dev_err_probe(dev, PTR_ERR(prueth->iep0), "iep0 get failed\n"); 2099 prueth->iep0 = NULL; 2100 goto free_pool; 2101 } 2102 2103 prueth->iep1 = icss_iep_get_idx(np, 1); 2104 if (IS_ERR(prueth->iep1)) { 2105 ret = dev_err_probe(dev, PTR_ERR(prueth->iep1), "iep1 get failed\n"); 2106 goto put_iep0; 2107 } 2108 2109 if (prueth->pdata.quirk_10m_link_issue) { 2110 /* Enable IEP1 for FW in 64bit mode as W/A for 10M FD link detect issue under TX 2111 * traffic. 2112 */ 2113 icss_iep_init_fw(prueth->iep1); 2114 } 2115 2116 /* setup netdev interfaces */ 2117 if (eth0_node) { 2118 ret = prueth_netdev_init(prueth, eth0_node); 2119 if (ret) { 2120 dev_err_probe(dev, ret, "netdev init %s failed\n", 2121 eth0_node->name); 2122 goto exit_iep; 2123 } 2124 prueth->emac[PRUETH_MAC0]->iep = prueth->iep0; 2125 } 2126 2127 if (eth1_node) { 2128 ret = prueth_netdev_init(prueth, eth1_node); 2129 if (ret) { 2130 dev_err_probe(dev, ret, "netdev init %s failed\n", 2131 eth1_node->name); 2132 goto netdev_exit; 2133 } 2134 2135 prueth->emac[PRUETH_MAC1]->iep = prueth->iep0; 2136 } 2137 2138 /* register the network devices */ 2139 if (eth0_node) { 2140 ret = register_netdev(prueth->emac[PRUETH_MAC0]->ndev); 2141 if (ret) { 2142 dev_err(dev, "can't register netdev for port MII0"); 2143 goto netdev_exit; 2144 } 2145 2146 prueth->registered_netdevs[PRUETH_MAC0] = prueth->emac[PRUETH_MAC0]->ndev; 2147 2148 ret = emac_phy_connect(prueth->emac[PRUETH_MAC0]); 2149 if (ret) { 2150 dev_err(dev, 2151 "can't connect to MII0 PHY, error -%d", ret); 2152 goto netdev_unregister; 2153 } 2154 phy_attached_info(prueth->emac[PRUETH_MAC0]->ndev->phydev); 2155 } 2156 2157 if (eth1_node) { 2158 ret = register_netdev(prueth->emac[PRUETH_MAC1]->ndev); 2159 if (ret) { 2160 dev_err(dev, "can't register netdev for port MII1"); 2161 goto netdev_unregister; 2162 } 2163 2164 prueth->registered_netdevs[PRUETH_MAC1] = prueth->emac[PRUETH_MAC1]->ndev; 2165 ret = emac_phy_connect(prueth->emac[PRUETH_MAC1]); 2166 if (ret) { 2167 dev_err(dev, 2168 "can't connect to MII1 PHY, error %d", ret); 2169 goto netdev_unregister; 2170 } 2171 phy_attached_info(prueth->emac[PRUETH_MAC1]->ndev->phydev); 2172 } 2173 2174 dev_info(dev, "TI PRU ethernet driver initialized: %s EMAC mode\n", 2175 (!eth0_node || !eth1_node) ? "single" : "dual"); 2176 2177 if (eth1_node) 2178 of_node_put(eth1_node); 2179 if (eth0_node) 2180 of_node_put(eth0_node); 2181 return 0; 2182 2183 netdev_unregister: 2184 for (i = 0; i < PRUETH_NUM_MACS; i++) { 2185 if (!prueth->registered_netdevs[i]) 2186 continue; 2187 if (prueth->emac[i]->ndev->phydev) { 2188 phy_disconnect(prueth->emac[i]->ndev->phydev); 2189 prueth->emac[i]->ndev->phydev = NULL; 2190 } 2191 unregister_netdev(prueth->registered_netdevs[i]); 2192 } 2193 2194 netdev_exit: 2195 for (i = 0; i < PRUETH_NUM_MACS; i++) { 2196 eth_node = prueth->eth_node[i]; 2197 if (!eth_node) 2198 continue; 2199 2200 prueth_netdev_exit(prueth, eth_node); 2201 } 2202 2203 exit_iep: 2204 if (prueth->pdata.quirk_10m_link_issue) 2205 icss_iep_exit_fw(prueth->iep1); 2206 icss_iep_put(prueth->iep1); 2207 2208 put_iep0: 2209 icss_iep_put(prueth->iep0); 2210 prueth->iep0 = NULL; 2211 prueth->iep1 = NULL; 2212 2213 free_pool: 2214 gen_pool_free(prueth->sram_pool, 2215 (unsigned long)prueth->msmcram.va, msmc_ram_size); 2216 2217 put_mem: 2218 pruss_release_mem_region(prueth->pruss, &prueth->shram); 2219 2220 put_pruss: 2221 pruss_put(prueth->pruss); 2222 2223 put_cores: 2224 if (eth1_node) { 2225 prueth_put_cores(prueth, ICSS_SLICE1); 2226 of_node_put(eth1_node); 2227 } 2228 2229 if (eth0_node) { 2230 prueth_put_cores(prueth, ICSS_SLICE0); 2231 of_node_put(eth0_node); 2232 } 2233 2234 return ret; 2235 } 2236 2237 static void prueth_remove(struct platform_device *pdev) 2238 { 2239 struct prueth *prueth = platform_get_drvdata(pdev); 2240 struct device_node *eth_node; 2241 int i; 2242 2243 for (i = 0; i < PRUETH_NUM_MACS; i++) { 2244 if (!prueth->registered_netdevs[i]) 2245 continue; 2246 phy_stop(prueth->emac[i]->ndev->phydev); 2247 phy_disconnect(prueth->emac[i]->ndev->phydev); 2248 prueth->emac[i]->ndev->phydev = NULL; 2249 unregister_netdev(prueth->registered_netdevs[i]); 2250 } 2251 2252 for (i = 0; i < PRUETH_NUM_MACS; i++) { 2253 eth_node = prueth->eth_node[i]; 2254 if (!eth_node) 2255 continue; 2256 2257 prueth_netdev_exit(prueth, eth_node); 2258 } 2259 2260 if (prueth->pdata.quirk_10m_link_issue) 2261 icss_iep_exit_fw(prueth->iep1); 2262 2263 icss_iep_put(prueth->iep1); 2264 icss_iep_put(prueth->iep0); 2265 2266 gen_pool_free(prueth->sram_pool, 2267 (unsigned long)prueth->msmcram.va, 2268 MSMC_RAM_SIZE); 2269 2270 pruss_release_mem_region(prueth->pruss, &prueth->shram); 2271 2272 pruss_put(prueth->pruss); 2273 2274 if (prueth->eth_node[PRUETH_MAC1]) 2275 prueth_put_cores(prueth, ICSS_SLICE1); 2276 2277 if (prueth->eth_node[PRUETH_MAC0]) 2278 prueth_put_cores(prueth, ICSS_SLICE0); 2279 } 2280 2281 #ifdef CONFIG_PM_SLEEP 2282 static int prueth_suspend(struct device *dev) 2283 { 2284 struct prueth *prueth = dev_get_drvdata(dev); 2285 struct net_device *ndev; 2286 int i, ret; 2287 2288 for (i = 0; i < PRUETH_NUM_MACS; i++) { 2289 ndev = prueth->registered_netdevs[i]; 2290 2291 if (!ndev) 2292 continue; 2293 2294 if (netif_running(ndev)) { 2295 netif_device_detach(ndev); 2296 ret = emac_ndo_stop(ndev); 2297 if (ret < 0) { 2298 netdev_err(ndev, "failed to stop: %d", ret); 2299 return ret; 2300 } 2301 } 2302 } 2303 2304 return 0; 2305 } 2306 2307 static int prueth_resume(struct device *dev) 2308 { 2309 struct prueth *prueth = dev_get_drvdata(dev); 2310 struct net_device *ndev; 2311 int i, ret; 2312 2313 for (i = 0; i < PRUETH_NUM_MACS; i++) { 2314 ndev = prueth->registered_netdevs[i]; 2315 2316 if (!ndev) 2317 continue; 2318 2319 if (netif_running(ndev)) { 2320 ret = emac_ndo_open(ndev); 2321 if (ret < 0) { 2322 netdev_err(ndev, "failed to start: %d", ret); 2323 return ret; 2324 } 2325 netif_device_attach(ndev); 2326 } 2327 } 2328 2329 return 0; 2330 } 2331 #endif /* CONFIG_PM_SLEEP */ 2332 2333 static const struct dev_pm_ops prueth_dev_pm_ops = { 2334 SET_SYSTEM_SLEEP_PM_OPS(prueth_suspend, prueth_resume) 2335 }; 2336 2337 static const struct prueth_pdata am654_icssg_pdata = { 2338 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2339 .quirk_10m_link_issue = 1, 2340 }; 2341 2342 static const struct of_device_id prueth_dt_match[] = { 2343 { .compatible = "ti,am654-icssg-prueth", .data = &am654_icssg_pdata }, 2344 { /* sentinel */ } 2345 }; 2346 MODULE_DEVICE_TABLE(of, prueth_dt_match); 2347 2348 static struct platform_driver prueth_driver = { 2349 .probe = prueth_probe, 2350 .remove_new = prueth_remove, 2351 .driver = { 2352 .name = "icssg-prueth", 2353 .of_match_table = prueth_dt_match, 2354 .pm = &prueth_dev_pm_ops, 2355 }, 2356 }; 2357 module_platform_driver(prueth_driver); 2358 2359 MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>"); 2360 MODULE_AUTHOR("Md Danish Anwar <danishanwar@ti.com>"); 2361 MODULE_DESCRIPTION("PRUSS ICSSG Ethernet Driver"); 2362 MODULE_LICENSE("GPL"); 2363