1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Texas Instruments ICSSG Ethernet Driver 4 * 5 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ 6 * 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dma/ti-cppi5.h> 14 #include <linux/etherdevice.h> 15 #include <linux/genalloc.h> 16 #include <linux/if_vlan.h> 17 #include <linux/interrupt.h> 18 #include <linux/kernel.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_mdio.h> 24 #include <linux/of_net.h> 25 #include <linux/of_platform.h> 26 #include <linux/phy.h> 27 #include <linux/remoteproc/pruss.h> 28 #include <linux/regmap.h> 29 #include <linux/remoteproc.h> 30 31 #include "icssg_prueth.h" 32 #include "icssg_mii_rt.h" 33 #include "../k3-cppi-desc-pool.h" 34 35 #define PRUETH_MODULE_DESCRIPTION "PRUSS ICSSG Ethernet driver" 36 37 /* Netif debug messages possible */ 38 #define PRUETH_EMAC_DEBUG (NETIF_MSG_DRV | \ 39 NETIF_MSG_PROBE | \ 40 NETIF_MSG_LINK | \ 41 NETIF_MSG_TIMER | \ 42 NETIF_MSG_IFDOWN | \ 43 NETIF_MSG_IFUP | \ 44 NETIF_MSG_RX_ERR | \ 45 NETIF_MSG_TX_ERR | \ 46 NETIF_MSG_TX_QUEUED | \ 47 NETIF_MSG_INTR | \ 48 NETIF_MSG_TX_DONE | \ 49 NETIF_MSG_RX_STATUS | \ 50 NETIF_MSG_PKTDATA | \ 51 NETIF_MSG_HW | \ 52 NETIF_MSG_WOL) 53 54 #define prueth_napi_to_emac(napi) container_of(napi, struct prueth_emac, napi_rx) 55 56 /* CTRLMMR_ICSSG_RGMII_CTRL register bits */ 57 #define ICSSG_CTRL_RGMII_ID_MODE BIT(24) 58 59 #define IEP_DEFAULT_CYCLE_TIME_NS 1000000 /* 1 ms */ 60 61 static void prueth_cleanup_rx_chns(struct prueth_emac *emac, 62 struct prueth_rx_chn *rx_chn, 63 int max_rflows) 64 { 65 if (rx_chn->desc_pool) 66 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 67 68 if (rx_chn->rx_chn) 69 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 70 } 71 72 static void prueth_cleanup_tx_chns(struct prueth_emac *emac) 73 { 74 int i; 75 76 for (i = 0; i < emac->tx_ch_num; i++) { 77 struct prueth_tx_chn *tx_chn = &emac->tx_chns[i]; 78 79 if (tx_chn->desc_pool) 80 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 81 82 if (tx_chn->tx_chn) 83 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 84 85 /* Assume prueth_cleanup_tx_chns() is called at the 86 * end after all channel resources are freed 87 */ 88 memset(tx_chn, 0, sizeof(*tx_chn)); 89 } 90 } 91 92 static void prueth_ndev_del_tx_napi(struct prueth_emac *emac, int num) 93 { 94 int i; 95 96 for (i = 0; i < num; i++) { 97 struct prueth_tx_chn *tx_chn = &emac->tx_chns[i]; 98 99 if (tx_chn->irq) 100 free_irq(tx_chn->irq, tx_chn); 101 netif_napi_del(&tx_chn->napi_tx); 102 } 103 } 104 105 static void prueth_xmit_free(struct prueth_tx_chn *tx_chn, 106 struct cppi5_host_desc_t *desc) 107 { 108 struct cppi5_host_desc_t *first_desc, *next_desc; 109 dma_addr_t buf_dma, next_desc_dma; 110 u32 buf_dma_len; 111 112 first_desc = desc; 113 next_desc = first_desc; 114 115 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 116 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 117 118 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, 119 DMA_TO_DEVICE); 120 121 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 122 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 123 while (next_desc_dma) { 124 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 125 next_desc_dma); 126 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 127 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 128 129 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 130 DMA_TO_DEVICE); 131 132 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 133 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 134 135 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 136 } 137 138 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 139 } 140 141 static int emac_tx_complete_packets(struct prueth_emac *emac, int chn, 142 int budget) 143 { 144 struct net_device *ndev = emac->ndev; 145 struct cppi5_host_desc_t *desc_tx; 146 struct netdev_queue *netif_txq; 147 struct prueth_tx_chn *tx_chn; 148 unsigned int total_bytes = 0; 149 struct sk_buff *skb; 150 dma_addr_t desc_dma; 151 int res, num_tx = 0; 152 void **swdata; 153 154 tx_chn = &emac->tx_chns[chn]; 155 156 while (true) { 157 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 158 if (res == -ENODATA) 159 break; 160 161 /* teardown completion */ 162 if (cppi5_desc_is_tdcm(desc_dma)) { 163 if (atomic_dec_and_test(&emac->tdown_cnt)) 164 complete(&emac->tdown_complete); 165 break; 166 } 167 168 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 169 desc_dma); 170 swdata = cppi5_hdesc_get_swdata(desc_tx); 171 172 skb = *(swdata); 173 prueth_xmit_free(tx_chn, desc_tx); 174 175 ndev = skb->dev; 176 ndev->stats.tx_packets++; 177 ndev->stats.tx_bytes += skb->len; 178 total_bytes += skb->len; 179 napi_consume_skb(skb, budget); 180 num_tx++; 181 } 182 183 if (!num_tx) 184 return 0; 185 186 netif_txq = netdev_get_tx_queue(ndev, chn); 187 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 188 189 if (netif_tx_queue_stopped(netif_txq)) { 190 /* If the TX queue was stopped, wake it now 191 * if we have enough room. 192 */ 193 __netif_tx_lock(netif_txq, smp_processor_id()); 194 if (netif_running(ndev) && 195 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 196 MAX_SKB_FRAGS)) 197 netif_tx_wake_queue(netif_txq); 198 __netif_tx_unlock(netif_txq); 199 } 200 201 return num_tx; 202 } 203 204 static int emac_napi_tx_poll(struct napi_struct *napi_tx, int budget) 205 { 206 struct prueth_tx_chn *tx_chn = prueth_napi_to_tx_chn(napi_tx); 207 struct prueth_emac *emac = tx_chn->emac; 208 int num_tx_packets; 209 210 num_tx_packets = emac_tx_complete_packets(emac, tx_chn->id, budget); 211 212 if (num_tx_packets >= budget) 213 return budget; 214 215 if (napi_complete_done(napi_tx, num_tx_packets)) 216 enable_irq(tx_chn->irq); 217 218 return num_tx_packets; 219 } 220 221 static irqreturn_t prueth_tx_irq(int irq, void *dev_id) 222 { 223 struct prueth_tx_chn *tx_chn = dev_id; 224 225 disable_irq_nosync(irq); 226 napi_schedule(&tx_chn->napi_tx); 227 228 return IRQ_HANDLED; 229 } 230 231 static int prueth_ndev_add_tx_napi(struct prueth_emac *emac) 232 { 233 struct prueth *prueth = emac->prueth; 234 int i, ret; 235 236 for (i = 0; i < emac->tx_ch_num; i++) { 237 struct prueth_tx_chn *tx_chn = &emac->tx_chns[i]; 238 239 netif_napi_add_tx(emac->ndev, &tx_chn->napi_tx, emac_napi_tx_poll); 240 ret = request_irq(tx_chn->irq, prueth_tx_irq, 241 IRQF_TRIGGER_HIGH, tx_chn->name, 242 tx_chn); 243 if (ret) { 244 netif_napi_del(&tx_chn->napi_tx); 245 dev_err(prueth->dev, "unable to request TX IRQ %d\n", 246 tx_chn->irq); 247 goto fail; 248 } 249 } 250 251 return 0; 252 fail: 253 prueth_ndev_del_tx_napi(emac, i); 254 return ret; 255 } 256 257 static int prueth_init_tx_chns(struct prueth_emac *emac) 258 { 259 static const struct k3_ring_cfg ring_cfg = { 260 .elm_size = K3_RINGACC_RING_ELSIZE_8, 261 .mode = K3_RINGACC_RING_MODE_RING, 262 .flags = 0, 263 .size = PRUETH_MAX_TX_DESC, 264 }; 265 struct k3_udma_glue_tx_channel_cfg tx_cfg; 266 struct device *dev = emac->prueth->dev; 267 struct net_device *ndev = emac->ndev; 268 int ret, slice, i; 269 u32 hdesc_size; 270 271 slice = prueth_emac_slice(emac); 272 if (slice < 0) 273 return slice; 274 275 init_completion(&emac->tdown_complete); 276 277 hdesc_size = cppi5_hdesc_calc_size(true, PRUETH_NAV_PS_DATA_SIZE, 278 PRUETH_NAV_SW_DATA_SIZE); 279 memset(&tx_cfg, 0, sizeof(tx_cfg)); 280 tx_cfg.swdata_size = PRUETH_NAV_SW_DATA_SIZE; 281 tx_cfg.tx_cfg = ring_cfg; 282 tx_cfg.txcq_cfg = ring_cfg; 283 284 for (i = 0; i < emac->tx_ch_num; i++) { 285 struct prueth_tx_chn *tx_chn = &emac->tx_chns[i]; 286 287 /* To differentiate channels for SLICE0 vs SLICE1 */ 288 snprintf(tx_chn->name, sizeof(tx_chn->name), 289 "tx%d-%d", slice, i); 290 291 tx_chn->emac = emac; 292 tx_chn->id = i; 293 tx_chn->descs_num = PRUETH_MAX_TX_DESC; 294 295 tx_chn->tx_chn = 296 k3_udma_glue_request_tx_chn(dev, tx_chn->name, 297 &tx_cfg); 298 if (IS_ERR(tx_chn->tx_chn)) { 299 ret = PTR_ERR(tx_chn->tx_chn); 300 tx_chn->tx_chn = NULL; 301 netdev_err(ndev, 302 "Failed to request tx dma ch: %d\n", ret); 303 goto fail; 304 } 305 306 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 307 tx_chn->desc_pool = 308 k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 309 tx_chn->descs_num, 310 hdesc_size, 311 tx_chn->name); 312 if (IS_ERR(tx_chn->desc_pool)) { 313 ret = PTR_ERR(tx_chn->desc_pool); 314 tx_chn->desc_pool = NULL; 315 netdev_err(ndev, "Failed to create tx pool: %d\n", ret); 316 goto fail; 317 } 318 319 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 320 if (tx_chn->irq <= 0) { 321 ret = -EINVAL; 322 netdev_err(ndev, "failed to get tx irq\n"); 323 goto fail; 324 } 325 326 snprintf(tx_chn->name, sizeof(tx_chn->name), "%s-tx%d", 327 dev_name(dev), tx_chn->id); 328 } 329 330 return 0; 331 332 fail: 333 prueth_cleanup_tx_chns(emac); 334 return ret; 335 } 336 337 static int prueth_init_rx_chns(struct prueth_emac *emac, 338 struct prueth_rx_chn *rx_chn, 339 char *name, u32 max_rflows, 340 u32 max_desc_num) 341 { 342 struct k3_udma_glue_rx_channel_cfg rx_cfg; 343 struct device *dev = emac->prueth->dev; 344 struct net_device *ndev = emac->ndev; 345 u32 fdqring_id, hdesc_size; 346 int i, ret = 0, slice; 347 348 slice = prueth_emac_slice(emac); 349 if (slice < 0) 350 return slice; 351 352 /* To differentiate channels for SLICE0 vs SLICE1 */ 353 snprintf(rx_chn->name, sizeof(rx_chn->name), "%s%d", name, slice); 354 355 hdesc_size = cppi5_hdesc_calc_size(true, PRUETH_NAV_PS_DATA_SIZE, 356 PRUETH_NAV_SW_DATA_SIZE); 357 memset(&rx_cfg, 0, sizeof(rx_cfg)); 358 rx_cfg.swdata_size = PRUETH_NAV_SW_DATA_SIZE; 359 rx_cfg.flow_id_num = max_rflows; 360 rx_cfg.flow_id_base = -1; /* udmax will auto select flow id base */ 361 362 /* init all flows */ 363 rx_chn->dev = dev; 364 rx_chn->descs_num = max_desc_num; 365 366 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, rx_chn->name, 367 &rx_cfg); 368 if (IS_ERR(rx_chn->rx_chn)) { 369 ret = PTR_ERR(rx_chn->rx_chn); 370 rx_chn->rx_chn = NULL; 371 netdev_err(ndev, "Failed to request rx dma ch: %d\n", ret); 372 goto fail; 373 } 374 375 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 376 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 377 rx_chn->descs_num, 378 hdesc_size, 379 rx_chn->name); 380 if (IS_ERR(rx_chn->desc_pool)) { 381 ret = PTR_ERR(rx_chn->desc_pool); 382 rx_chn->desc_pool = NULL; 383 netdev_err(ndev, "Failed to create rx pool: %d\n", ret); 384 goto fail; 385 } 386 387 emac->rx_flow_id_base = k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 388 netdev_dbg(ndev, "flow id base = %d\n", emac->rx_flow_id_base); 389 390 fdqring_id = K3_RINGACC_RING_ID_ANY; 391 for (i = 0; i < rx_cfg.flow_id_num; i++) { 392 struct k3_ring_cfg rxring_cfg = { 393 .elm_size = K3_RINGACC_RING_ELSIZE_8, 394 .mode = K3_RINGACC_RING_MODE_RING, 395 .flags = 0, 396 }; 397 struct k3_ring_cfg fdqring_cfg = { 398 .elm_size = K3_RINGACC_RING_ELSIZE_8, 399 .flags = K3_RINGACC_RING_SHARED, 400 }; 401 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 402 .rx_cfg = rxring_cfg, 403 .rxfdq_cfg = fdqring_cfg, 404 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 405 .src_tag_lo_sel = 406 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 407 }; 408 409 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 410 rx_flow_cfg.rx_cfg.size = max_desc_num; 411 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 412 rx_flow_cfg.rxfdq_cfg.mode = emac->prueth->pdata.fdqring_mode; 413 414 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 415 i, &rx_flow_cfg); 416 if (ret) { 417 netdev_err(ndev, "Failed to init rx flow%d %d\n", 418 i, ret); 419 goto fail; 420 } 421 if (!i) 422 fdqring_id = k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 423 i); 424 rx_chn->irq[i] = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 425 if (rx_chn->irq[i] <= 0) { 426 ret = rx_chn->irq[i]; 427 netdev_err(ndev, "Failed to get rx dma irq"); 428 goto fail; 429 } 430 } 431 432 return 0; 433 434 fail: 435 prueth_cleanup_rx_chns(emac, rx_chn, max_rflows); 436 return ret; 437 } 438 439 static int prueth_dma_rx_push(struct prueth_emac *emac, 440 struct sk_buff *skb, 441 struct prueth_rx_chn *rx_chn) 442 { 443 struct net_device *ndev = emac->ndev; 444 struct cppi5_host_desc_t *desc_rx; 445 u32 pkt_len = skb_tailroom(skb); 446 dma_addr_t desc_dma; 447 dma_addr_t buf_dma; 448 void **swdata; 449 450 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 451 if (!desc_rx) { 452 netdev_err(ndev, "rx push: failed to allocate descriptor\n"); 453 return -ENOMEM; 454 } 455 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 456 457 buf_dma = dma_map_single(rx_chn->dma_dev, skb->data, pkt_len, DMA_FROM_DEVICE); 458 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 459 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 460 netdev_err(ndev, "rx push: failed to map rx pkt buffer\n"); 461 return -EINVAL; 462 } 463 464 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 465 PRUETH_NAV_PS_DATA_SIZE); 466 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 467 cppi5_hdesc_attach_buf(desc_rx, buf_dma, skb_tailroom(skb), buf_dma, skb_tailroom(skb)); 468 469 swdata = cppi5_hdesc_get_swdata(desc_rx); 470 *swdata = skb; 471 472 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, 473 desc_rx, desc_dma); 474 } 475 476 static u64 icssg_ts_to_ns(u32 hi_sw, u32 hi, u32 lo, u32 cycle_time_ns) 477 { 478 u32 iepcount_lo, iepcount_hi, hi_rollover_count; 479 u64 ns; 480 481 iepcount_lo = lo & GENMASK(19, 0); 482 iepcount_hi = (hi & GENMASK(11, 0)) << 12 | lo >> 20; 483 hi_rollover_count = hi >> 11; 484 485 ns = ((u64)hi_rollover_count) << 23 | (iepcount_hi + hi_sw); 486 ns = ns * cycle_time_ns + iepcount_lo; 487 488 return ns; 489 } 490 491 static void emac_rx_timestamp(struct prueth_emac *emac, 492 struct sk_buff *skb, u32 *psdata) 493 { 494 struct skb_shared_hwtstamps *ssh; 495 u64 ns; 496 497 u32 hi_sw = readl(emac->prueth->shram.va + 498 TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET); 499 ns = icssg_ts_to_ns(hi_sw, psdata[1], psdata[0], 500 IEP_DEFAULT_CYCLE_TIME_NS); 501 502 ssh = skb_hwtstamps(skb); 503 memset(ssh, 0, sizeof(*ssh)); 504 ssh->hwtstamp = ns_to_ktime(ns); 505 } 506 507 static int emac_rx_packet(struct prueth_emac *emac, u32 flow_id) 508 { 509 struct prueth_rx_chn *rx_chn = &emac->rx_chns; 510 u32 buf_dma_len, pkt_len, port_id = 0; 511 struct net_device *ndev = emac->ndev; 512 struct cppi5_host_desc_t *desc_rx; 513 struct sk_buff *skb, *new_skb; 514 dma_addr_t desc_dma, buf_dma; 515 void **swdata; 516 u32 *psdata; 517 int ret; 518 519 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_id, &desc_dma); 520 if (ret) { 521 if (ret != -ENODATA) 522 netdev_err(ndev, "rx pop: failed: %d\n", ret); 523 return ret; 524 } 525 526 if (cppi5_desc_is_tdcm(desc_dma)) /* Teardown ? */ 527 return 0; 528 529 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 530 531 swdata = cppi5_hdesc_get_swdata(desc_rx); 532 skb = *swdata; 533 534 psdata = cppi5_hdesc_get_psdata(desc_rx); 535 /* RX HW timestamp */ 536 if (emac->rx_ts_enabled) 537 emac_rx_timestamp(emac, skb, psdata); 538 539 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 540 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 541 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 542 /* firmware adds 4 CRC bytes, strip them */ 543 pkt_len -= 4; 544 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 545 546 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 547 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 548 549 skb->dev = ndev; 550 new_skb = netdev_alloc_skb_ip_align(ndev, PRUETH_MAX_PKT_SIZE); 551 /* if allocation fails we drop the packet but push the 552 * descriptor back to the ring with old skb to prevent a stall 553 */ 554 if (!new_skb) { 555 ndev->stats.rx_dropped++; 556 new_skb = skb; 557 } else { 558 /* send the filled skb up the n/w stack */ 559 skb_put(skb, pkt_len); 560 skb->protocol = eth_type_trans(skb, ndev); 561 napi_gro_receive(&emac->napi_rx, skb); 562 ndev->stats.rx_bytes += pkt_len; 563 ndev->stats.rx_packets++; 564 } 565 566 /* queue another RX DMA */ 567 ret = prueth_dma_rx_push(emac, new_skb, &emac->rx_chns); 568 if (WARN_ON(ret < 0)) { 569 dev_kfree_skb_any(new_skb); 570 ndev->stats.rx_errors++; 571 ndev->stats.rx_dropped++; 572 } 573 574 return ret; 575 } 576 577 static void prueth_rx_cleanup(void *data, dma_addr_t desc_dma) 578 { 579 struct prueth_rx_chn *rx_chn = data; 580 struct cppi5_host_desc_t *desc_rx; 581 struct sk_buff *skb; 582 dma_addr_t buf_dma; 583 u32 buf_dma_len; 584 void **swdata; 585 586 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 587 swdata = cppi5_hdesc_get_swdata(desc_rx); 588 skb = *swdata; 589 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 590 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 591 592 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, 593 DMA_FROM_DEVICE); 594 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 595 596 dev_kfree_skb_any(skb); 597 } 598 599 static int emac_get_tx_ts(struct prueth_emac *emac, 600 struct emac_tx_ts_response *rsp) 601 { 602 struct prueth *prueth = emac->prueth; 603 int slice = prueth_emac_slice(emac); 604 int addr; 605 606 addr = icssg_queue_pop(prueth, slice == 0 ? 607 ICSSG_TS_POP_SLICE0 : ICSSG_TS_POP_SLICE1); 608 if (addr < 0) 609 return addr; 610 611 memcpy_fromio(rsp, prueth->shram.va + addr, sizeof(*rsp)); 612 /* return buffer back for to pool */ 613 icssg_queue_push(prueth, slice == 0 ? 614 ICSSG_TS_PUSH_SLICE0 : ICSSG_TS_PUSH_SLICE1, addr); 615 616 return 0; 617 } 618 619 static void tx_ts_work(struct prueth_emac *emac) 620 { 621 struct skb_shared_hwtstamps ssh; 622 struct emac_tx_ts_response tsr; 623 struct sk_buff *skb; 624 int ret = 0; 625 u32 hi_sw; 626 u64 ns; 627 628 /* There may be more than one pending requests */ 629 while (1) { 630 ret = emac_get_tx_ts(emac, &tsr); 631 if (ret) /* nothing more */ 632 break; 633 634 if (tsr.cookie >= PRUETH_MAX_TX_TS_REQUESTS || 635 !emac->tx_ts_skb[tsr.cookie]) { 636 netdev_err(emac->ndev, "Invalid TX TS cookie 0x%x\n", 637 tsr.cookie); 638 break; 639 } 640 641 skb = emac->tx_ts_skb[tsr.cookie]; 642 emac->tx_ts_skb[tsr.cookie] = NULL; /* free slot */ 643 if (!skb) { 644 netdev_err(emac->ndev, "Driver Bug! got NULL skb\n"); 645 break; 646 } 647 648 hi_sw = readl(emac->prueth->shram.va + 649 TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET); 650 ns = icssg_ts_to_ns(hi_sw, tsr.hi_ts, tsr.lo_ts, 651 IEP_DEFAULT_CYCLE_TIME_NS); 652 653 memset(&ssh, 0, sizeof(ssh)); 654 ssh.hwtstamp = ns_to_ktime(ns); 655 656 skb_tstamp_tx(skb, &ssh); 657 dev_consume_skb_any(skb); 658 659 if (atomic_dec_and_test(&emac->tx_ts_pending)) /* no more? */ 660 break; 661 } 662 } 663 664 static int prueth_tx_ts_cookie_get(struct prueth_emac *emac) 665 { 666 int i; 667 668 /* search and get the next free slot */ 669 for (i = 0; i < PRUETH_MAX_TX_TS_REQUESTS; i++) { 670 if (!emac->tx_ts_skb[i]) { 671 emac->tx_ts_skb[i] = ERR_PTR(-EBUSY); /* reserve slot */ 672 return i; 673 } 674 } 675 676 return -EBUSY; 677 } 678 679 /** 680 * emac_ndo_start_xmit - EMAC Transmit function 681 * @skb: SKB pointer 682 * @ndev: EMAC network adapter 683 * 684 * Called by the system to transmit a packet - we queue the packet in 685 * EMAC hardware transmit queue 686 * Doesn't wait for completion we'll check for TX completion in 687 * emac_tx_complete_packets(). 688 * 689 * Return: enum netdev_tx 690 */ 691 static enum netdev_tx emac_ndo_start_xmit(struct sk_buff *skb, struct net_device *ndev) 692 { 693 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 694 struct prueth_emac *emac = netdev_priv(ndev); 695 struct netdev_queue *netif_txq; 696 struct prueth_tx_chn *tx_chn; 697 dma_addr_t desc_dma, buf_dma; 698 int i, ret = 0, q_idx; 699 bool in_tx_ts = 0; 700 int tx_ts_cookie; 701 void **swdata; 702 u32 pkt_len; 703 u32 *epib; 704 705 pkt_len = skb_headlen(skb); 706 q_idx = skb_get_queue_mapping(skb); 707 708 tx_chn = &emac->tx_chns[q_idx]; 709 netif_txq = netdev_get_tx_queue(ndev, q_idx); 710 711 /* Map the linear buffer */ 712 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, DMA_TO_DEVICE); 713 if (dma_mapping_error(tx_chn->dma_dev, buf_dma)) { 714 netdev_err(ndev, "tx: failed to map skb buffer\n"); 715 ret = NETDEV_TX_OK; 716 goto drop_free_skb; 717 } 718 719 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 720 if (!first_desc) { 721 netdev_dbg(ndev, "tx: failed to allocate descriptor\n"); 722 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, DMA_TO_DEVICE); 723 goto drop_stop_q_busy; 724 } 725 726 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 727 PRUETH_NAV_PS_DATA_SIZE); 728 cppi5_hdesc_set_pkttype(first_desc, 0); 729 epib = first_desc->epib; 730 epib[0] = 0; 731 epib[1] = 0; 732 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 733 emac->tx_ts_enabled) { 734 tx_ts_cookie = prueth_tx_ts_cookie_get(emac); 735 if (tx_ts_cookie >= 0) { 736 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 737 /* Request TX timestamp */ 738 epib[0] = (u32)tx_ts_cookie; 739 epib[1] = 0x80000000; /* TX TS request */ 740 emac->tx_ts_skb[tx_ts_cookie] = skb_get(skb); 741 in_tx_ts = 1; 742 } 743 } 744 745 /* set dst tag to indicate internal qid at the firmware which is at 746 * bit8..bit15. bit0..bit7 indicates port num for directed 747 * packets in case of switch mode operation 748 */ 749 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, (emac->port_id | (q_idx << 8))); 750 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 751 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 752 swdata = cppi5_hdesc_get_swdata(first_desc); 753 *swdata = skb; 754 755 /* Handle the case where skb is fragmented in pages */ 756 cur_desc = first_desc; 757 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 758 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 759 u32 frag_size = skb_frag_size(frag); 760 761 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 762 if (!next_desc) { 763 netdev_err(ndev, 764 "tx: failed to allocate frag. descriptor\n"); 765 goto free_desc_stop_q_busy_cleanup_tx_ts; 766 } 767 768 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 769 DMA_TO_DEVICE); 770 if (dma_mapping_error(tx_chn->dma_dev, buf_dma)) { 771 netdev_err(ndev, "tx: Failed to map skb page\n"); 772 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 773 ret = NETDEV_TX_OK; 774 goto cleanup_tx_ts; 775 } 776 777 cppi5_hdesc_reset_hbdesc(next_desc); 778 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 779 cppi5_hdesc_attach_buf(next_desc, 780 buf_dma, frag_size, buf_dma, frag_size); 781 782 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 783 next_desc); 784 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 785 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 786 787 pkt_len += frag_size; 788 cur_desc = next_desc; 789 } 790 WARN_ON_ONCE(pkt_len != skb->len); 791 792 /* report bql before sending packet */ 793 netdev_tx_sent_queue(netif_txq, pkt_len); 794 795 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 796 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 797 /* cppi5_desc_dump(first_desc, 64); */ 798 799 skb_tx_timestamp(skb); /* SW timestamp if SKBTX_IN_PROGRESS not set */ 800 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 801 if (ret) { 802 netdev_err(ndev, "tx: push failed: %d\n", ret); 803 goto drop_free_descs; 804 } 805 806 if (in_tx_ts) 807 atomic_inc(&emac->tx_ts_pending); 808 809 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 810 netif_tx_stop_queue(netif_txq); 811 /* Barrier, so that stop_queue visible to other cpus */ 812 smp_mb__after_atomic(); 813 814 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 815 MAX_SKB_FRAGS) 816 netif_tx_wake_queue(netif_txq); 817 } 818 819 return NETDEV_TX_OK; 820 821 cleanup_tx_ts: 822 if (in_tx_ts) { 823 dev_kfree_skb_any(emac->tx_ts_skb[tx_ts_cookie]); 824 emac->tx_ts_skb[tx_ts_cookie] = NULL; 825 } 826 827 drop_free_descs: 828 prueth_xmit_free(tx_chn, first_desc); 829 830 drop_free_skb: 831 dev_kfree_skb_any(skb); 832 833 /* error */ 834 ndev->stats.tx_dropped++; 835 netdev_err(ndev, "tx: error: %d\n", ret); 836 837 return ret; 838 839 free_desc_stop_q_busy_cleanup_tx_ts: 840 if (in_tx_ts) { 841 dev_kfree_skb_any(emac->tx_ts_skb[tx_ts_cookie]); 842 emac->tx_ts_skb[tx_ts_cookie] = NULL; 843 } 844 prueth_xmit_free(tx_chn, first_desc); 845 846 drop_stop_q_busy: 847 netif_tx_stop_queue(netif_txq); 848 return NETDEV_TX_BUSY; 849 } 850 851 static void prueth_tx_cleanup(void *data, dma_addr_t desc_dma) 852 { 853 struct prueth_tx_chn *tx_chn = data; 854 struct cppi5_host_desc_t *desc_tx; 855 struct sk_buff *skb; 856 void **swdata; 857 858 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 859 swdata = cppi5_hdesc_get_swdata(desc_tx); 860 skb = *(swdata); 861 prueth_xmit_free(tx_chn, desc_tx); 862 863 dev_kfree_skb_any(skb); 864 } 865 866 static irqreturn_t prueth_tx_ts_irq(int irq, void *dev_id) 867 { 868 struct prueth_emac *emac = dev_id; 869 870 /* currently only TX timestamp is being returned */ 871 tx_ts_work(emac); 872 873 return IRQ_HANDLED; 874 } 875 876 static irqreturn_t prueth_rx_irq(int irq, void *dev_id) 877 { 878 struct prueth_emac *emac = dev_id; 879 880 disable_irq_nosync(irq); 881 napi_schedule(&emac->napi_rx); 882 883 return IRQ_HANDLED; 884 } 885 886 struct icssg_firmwares { 887 char *pru; 888 char *rtu; 889 char *txpru; 890 }; 891 892 static struct icssg_firmwares icssg_emac_firmwares[] = { 893 { 894 .pru = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", 895 .rtu = "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", 896 .txpru = "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", 897 }, 898 { 899 .pru = "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", 900 .rtu = "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", 901 .txpru = "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf", 902 } 903 }; 904 905 static int prueth_emac_start(struct prueth *prueth, struct prueth_emac *emac) 906 { 907 struct icssg_firmwares *firmwares; 908 struct device *dev = prueth->dev; 909 int slice, ret; 910 911 firmwares = icssg_emac_firmwares; 912 913 slice = prueth_emac_slice(emac); 914 if (slice < 0) { 915 netdev_err(emac->ndev, "invalid port\n"); 916 return -EINVAL; 917 } 918 919 ret = icssg_config(prueth, emac, slice); 920 if (ret) 921 return ret; 922 923 ret = rproc_set_firmware(prueth->pru[slice], firmwares[slice].pru); 924 ret = rproc_boot(prueth->pru[slice]); 925 if (ret) { 926 dev_err(dev, "failed to boot PRU%d: %d\n", slice, ret); 927 return -EINVAL; 928 } 929 930 ret = rproc_set_firmware(prueth->rtu[slice], firmwares[slice].rtu); 931 ret = rproc_boot(prueth->rtu[slice]); 932 if (ret) { 933 dev_err(dev, "failed to boot RTU%d: %d\n", slice, ret); 934 goto halt_pru; 935 } 936 937 ret = rproc_set_firmware(prueth->txpru[slice], firmwares[slice].txpru); 938 ret = rproc_boot(prueth->txpru[slice]); 939 if (ret) { 940 dev_err(dev, "failed to boot TX_PRU%d: %d\n", slice, ret); 941 goto halt_rtu; 942 } 943 944 emac->fw_running = 1; 945 return 0; 946 947 halt_rtu: 948 rproc_shutdown(prueth->rtu[slice]); 949 950 halt_pru: 951 rproc_shutdown(prueth->pru[slice]); 952 953 return ret; 954 } 955 956 static void prueth_emac_stop(struct prueth_emac *emac) 957 { 958 struct prueth *prueth = emac->prueth; 959 int slice; 960 961 switch (emac->port_id) { 962 case PRUETH_PORT_MII0: 963 slice = ICSS_SLICE0; 964 break; 965 case PRUETH_PORT_MII1: 966 slice = ICSS_SLICE1; 967 break; 968 default: 969 netdev_err(emac->ndev, "invalid port\n"); 970 return; 971 } 972 973 emac->fw_running = 0; 974 rproc_shutdown(prueth->txpru[slice]); 975 rproc_shutdown(prueth->rtu[slice]); 976 rproc_shutdown(prueth->pru[slice]); 977 } 978 979 static void prueth_cleanup_tx_ts(struct prueth_emac *emac) 980 { 981 int i; 982 983 for (i = 0; i < PRUETH_MAX_TX_TS_REQUESTS; i++) { 984 if (emac->tx_ts_skb[i]) { 985 dev_kfree_skb_any(emac->tx_ts_skb[i]); 986 emac->tx_ts_skb[i] = NULL; 987 } 988 } 989 } 990 991 /* called back by PHY layer if there is change in link state of hw port*/ 992 static void emac_adjust_link(struct net_device *ndev) 993 { 994 struct prueth_emac *emac = netdev_priv(ndev); 995 struct phy_device *phydev = ndev->phydev; 996 struct prueth *prueth = emac->prueth; 997 bool new_state = false; 998 unsigned long flags; 999 1000 if (phydev->link) { 1001 /* check the mode of operation - full/half duplex */ 1002 if (phydev->duplex != emac->duplex) { 1003 new_state = true; 1004 emac->duplex = phydev->duplex; 1005 } 1006 if (phydev->speed != emac->speed) { 1007 new_state = true; 1008 emac->speed = phydev->speed; 1009 } 1010 if (!emac->link) { 1011 new_state = true; 1012 emac->link = 1; 1013 } 1014 } else if (emac->link) { 1015 new_state = true; 1016 emac->link = 0; 1017 1018 /* f/w should support 100 & 1000 */ 1019 emac->speed = SPEED_1000; 1020 1021 /* half duplex may not be supported by f/w */ 1022 emac->duplex = DUPLEX_FULL; 1023 } 1024 1025 if (new_state) { 1026 phy_print_status(phydev); 1027 1028 /* update RGMII and MII configuration based on PHY negotiated 1029 * values 1030 */ 1031 if (emac->link) { 1032 /* Set the RGMII cfg for gig en and full duplex */ 1033 icssg_update_rgmii_cfg(prueth->miig_rt, emac); 1034 1035 /* update the Tx IPG based on 100M/1G speed */ 1036 spin_lock_irqsave(&emac->lock, flags); 1037 icssg_config_ipg(emac); 1038 spin_unlock_irqrestore(&emac->lock, flags); 1039 icssg_config_set_speed(emac); 1040 emac_set_port_state(emac, ICSSG_EMAC_PORT_FORWARD); 1041 1042 } else { 1043 emac_set_port_state(emac, ICSSG_EMAC_PORT_DISABLE); 1044 } 1045 } 1046 1047 if (emac->link) { 1048 /* reactivate the transmit queue */ 1049 netif_tx_wake_all_queues(ndev); 1050 } else { 1051 netif_tx_stop_all_queues(ndev); 1052 prueth_cleanup_tx_ts(emac); 1053 } 1054 } 1055 1056 static int emac_napi_rx_poll(struct napi_struct *napi_rx, int budget) 1057 { 1058 struct prueth_emac *emac = prueth_napi_to_emac(napi_rx); 1059 int rx_flow = PRUETH_RX_FLOW_DATA; 1060 int flow = PRUETH_MAX_RX_FLOWS; 1061 int num_rx = 0; 1062 int cur_budget; 1063 int ret; 1064 1065 while (flow--) { 1066 cur_budget = budget - num_rx; 1067 1068 while (cur_budget--) { 1069 ret = emac_rx_packet(emac, flow); 1070 if (ret) 1071 break; 1072 num_rx++; 1073 } 1074 1075 if (num_rx >= budget) 1076 break; 1077 } 1078 1079 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) 1080 enable_irq(emac->rx_chns.irq[rx_flow]); 1081 1082 return num_rx; 1083 } 1084 1085 static int prueth_prepare_rx_chan(struct prueth_emac *emac, 1086 struct prueth_rx_chn *chn, 1087 int buf_size) 1088 { 1089 struct sk_buff *skb; 1090 int i, ret; 1091 1092 for (i = 0; i < chn->descs_num; i++) { 1093 skb = __netdev_alloc_skb_ip_align(NULL, buf_size, GFP_KERNEL); 1094 if (!skb) 1095 return -ENOMEM; 1096 1097 ret = prueth_dma_rx_push(emac, skb, chn); 1098 if (ret < 0) { 1099 netdev_err(emac->ndev, 1100 "cannot submit skb for rx chan %s ret %d\n", 1101 chn->name, ret); 1102 kfree_skb(skb); 1103 return ret; 1104 } 1105 } 1106 1107 return 0; 1108 } 1109 1110 static void prueth_reset_tx_chan(struct prueth_emac *emac, int ch_num, 1111 bool free_skb) 1112 { 1113 int i; 1114 1115 for (i = 0; i < ch_num; i++) { 1116 if (free_skb) 1117 k3_udma_glue_reset_tx_chn(emac->tx_chns[i].tx_chn, 1118 &emac->tx_chns[i], 1119 prueth_tx_cleanup); 1120 k3_udma_glue_disable_tx_chn(emac->tx_chns[i].tx_chn); 1121 } 1122 } 1123 1124 static void prueth_reset_rx_chan(struct prueth_rx_chn *chn, 1125 int num_flows, bool disable) 1126 { 1127 int i; 1128 1129 for (i = 0; i < num_flows; i++) 1130 k3_udma_glue_reset_rx_chn(chn->rx_chn, i, chn, 1131 prueth_rx_cleanup, !!i); 1132 if (disable) 1133 k3_udma_glue_disable_rx_chn(chn->rx_chn); 1134 } 1135 1136 static int emac_phy_connect(struct prueth_emac *emac) 1137 { 1138 struct prueth *prueth = emac->prueth; 1139 struct net_device *ndev = emac->ndev; 1140 /* connect PHY */ 1141 ndev->phydev = of_phy_connect(emac->ndev, emac->phy_node, 1142 &emac_adjust_link, 0, 1143 emac->phy_if); 1144 if (!ndev->phydev) { 1145 dev_err(prueth->dev, "couldn't connect to phy %s\n", 1146 emac->phy_node->full_name); 1147 return -ENODEV; 1148 } 1149 1150 /* remove unsupported modes */ 1151 phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1152 phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1153 phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1154 phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1155 phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1156 phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1157 1158 if (emac->phy_if == PHY_INTERFACE_MODE_MII) 1159 phy_set_max_speed(ndev->phydev, SPEED_100); 1160 1161 return 0; 1162 } 1163 1164 static u64 prueth_iep_gettime(void *clockops_data, struct ptp_system_timestamp *sts) 1165 { 1166 u32 hi_rollover_count, hi_rollover_count_r; 1167 struct prueth_emac *emac = clockops_data; 1168 struct prueth *prueth = emac->prueth; 1169 void __iomem *fw_hi_r_count_addr; 1170 void __iomem *fw_count_hi_addr; 1171 u32 iepcount_hi, iepcount_hi_r; 1172 unsigned long flags; 1173 u32 iepcount_lo; 1174 u64 ts = 0; 1175 1176 fw_count_hi_addr = prueth->shram.va + TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET; 1177 fw_hi_r_count_addr = prueth->shram.va + TIMESYNC_FW_WC_HI_ROLLOVER_COUNT_OFFSET; 1178 1179 local_irq_save(flags); 1180 do { 1181 iepcount_hi = icss_iep_get_count_hi(emac->iep); 1182 iepcount_hi += readl(fw_count_hi_addr); 1183 hi_rollover_count = readl(fw_hi_r_count_addr); 1184 ptp_read_system_prets(sts); 1185 iepcount_lo = icss_iep_get_count_low(emac->iep); 1186 ptp_read_system_postts(sts); 1187 1188 iepcount_hi_r = icss_iep_get_count_hi(emac->iep); 1189 iepcount_hi_r += readl(fw_count_hi_addr); 1190 hi_rollover_count_r = readl(fw_hi_r_count_addr); 1191 } while ((iepcount_hi_r != iepcount_hi) || 1192 (hi_rollover_count != hi_rollover_count_r)); 1193 local_irq_restore(flags); 1194 1195 ts = ((u64)hi_rollover_count) << 23 | iepcount_hi; 1196 ts = ts * (u64)IEP_DEFAULT_CYCLE_TIME_NS + iepcount_lo; 1197 1198 return ts; 1199 } 1200 1201 static void prueth_iep_settime(void *clockops_data, u64 ns) 1202 { 1203 struct icssg_setclock_desc __iomem *sc_descp; 1204 struct prueth_emac *emac = clockops_data; 1205 struct icssg_setclock_desc sc_desc; 1206 u64 cyclecount; 1207 u32 cycletime; 1208 int timeout; 1209 1210 if (!emac->fw_running) 1211 return; 1212 1213 sc_descp = emac->prueth->shram.va + TIMESYNC_FW_WC_SETCLOCK_DESC_OFFSET; 1214 1215 cycletime = IEP_DEFAULT_CYCLE_TIME_NS; 1216 cyclecount = ns / cycletime; 1217 1218 memset(&sc_desc, 0, sizeof(sc_desc)); 1219 sc_desc.margin = cycletime - 1000; 1220 sc_desc.cyclecounter0_set = cyclecount & GENMASK(31, 0); 1221 sc_desc.cyclecounter1_set = (cyclecount & GENMASK(63, 32)) >> 32; 1222 sc_desc.iepcount_set = ns % cycletime; 1223 sc_desc.CMP0_current = cycletime - 4; //Count from 0 to (cycle time)-4 1224 1225 memcpy_toio(sc_descp, &sc_desc, sizeof(sc_desc)); 1226 1227 writeb(1, &sc_descp->request); 1228 1229 timeout = 5; /* fw should take 2-3 ms */ 1230 while (timeout--) { 1231 if (readb(&sc_descp->acknowledgment)) 1232 return; 1233 1234 usleep_range(500, 1000); 1235 } 1236 1237 dev_err(emac->prueth->dev, "settime timeout\n"); 1238 } 1239 1240 static int prueth_perout_enable(void *clockops_data, 1241 struct ptp_perout_request *req, int on, 1242 u64 *cmp) 1243 { 1244 struct prueth_emac *emac = clockops_data; 1245 u32 reduction_factor = 0, offset = 0; 1246 struct timespec64 ts; 1247 u64 ns_period; 1248 1249 if (!on) 1250 return 0; 1251 1252 /* Any firmware specific stuff for PPS/PEROUT handling */ 1253 ts.tv_sec = req->period.sec; 1254 ts.tv_nsec = req->period.nsec; 1255 ns_period = timespec64_to_ns(&ts); 1256 1257 /* f/w doesn't support period less than cycle time */ 1258 if (ns_period < IEP_DEFAULT_CYCLE_TIME_NS) 1259 return -ENXIO; 1260 1261 reduction_factor = ns_period / IEP_DEFAULT_CYCLE_TIME_NS; 1262 offset = ns_period % IEP_DEFAULT_CYCLE_TIME_NS; 1263 1264 /* f/w requires at least 1uS within a cycle so CMP 1265 * can trigger after SYNC is enabled 1266 */ 1267 if (offset < 5 * NSEC_PER_USEC) 1268 offset = 5 * NSEC_PER_USEC; 1269 1270 /* if offset is close to cycle time then we will miss 1271 * the CMP event for last tick when IEP rolls over. 1272 * In normal mode, IEP tick is 4ns. 1273 * In slow compensation it could be 0ns or 8ns at 1274 * every slow compensation cycle. 1275 */ 1276 if (offset > IEP_DEFAULT_CYCLE_TIME_NS - 8) 1277 offset = IEP_DEFAULT_CYCLE_TIME_NS - 8; 1278 1279 /* we're in shadow mode so need to set upper 32-bits */ 1280 *cmp = (u64)offset << 32; 1281 1282 writel(reduction_factor, emac->prueth->shram.va + 1283 TIMESYNC_FW_WC_SYNCOUT_REDUCTION_FACTOR_OFFSET); 1284 1285 writel(0, emac->prueth->shram.va + 1286 TIMESYNC_FW_WC_SYNCOUT_START_TIME_CYCLECOUNT_OFFSET); 1287 1288 return 0; 1289 } 1290 1291 const struct icss_iep_clockops prueth_iep_clockops = { 1292 .settime = prueth_iep_settime, 1293 .gettime = prueth_iep_gettime, 1294 .perout_enable = prueth_perout_enable, 1295 }; 1296 1297 /** 1298 * emac_ndo_open - EMAC device open 1299 * @ndev: network adapter device 1300 * 1301 * Called when system wants to start the interface. 1302 * 1303 * Return: 0 for a successful open, or appropriate error code 1304 */ 1305 static int emac_ndo_open(struct net_device *ndev) 1306 { 1307 struct prueth_emac *emac = netdev_priv(ndev); 1308 int ret, i, num_data_chn = emac->tx_ch_num; 1309 struct prueth *prueth = emac->prueth; 1310 int slice = prueth_emac_slice(emac); 1311 struct device *dev = prueth->dev; 1312 int max_rx_flows; 1313 int rx_flow; 1314 1315 /* clear SMEM and MSMC settings for all slices */ 1316 if (!prueth->emacs_initialized) { 1317 memset_io(prueth->msmcram.va, 0, prueth->msmcram.size); 1318 memset_io(prueth->shram.va, 0, ICSSG_CONFIG_OFFSET_SLICE1 * PRUETH_NUM_MACS); 1319 } 1320 1321 /* set h/w MAC as user might have re-configured */ 1322 ether_addr_copy(emac->mac_addr, ndev->dev_addr); 1323 1324 icssg_class_set_mac_addr(prueth->miig_rt, slice, emac->mac_addr); 1325 icssg_ft1_set_mac_addr(prueth->miig_rt, slice, emac->mac_addr); 1326 1327 icssg_class_default(prueth->miig_rt, slice, 0); 1328 1329 /* Notify the stack of the actual queue counts. */ 1330 ret = netif_set_real_num_tx_queues(ndev, num_data_chn); 1331 if (ret) { 1332 dev_err(dev, "cannot set real number of tx queues\n"); 1333 return ret; 1334 } 1335 1336 init_completion(&emac->cmd_complete); 1337 ret = prueth_init_tx_chns(emac); 1338 if (ret) { 1339 dev_err(dev, "failed to init tx channel: %d\n", ret); 1340 return ret; 1341 } 1342 1343 max_rx_flows = PRUETH_MAX_RX_FLOWS; 1344 ret = prueth_init_rx_chns(emac, &emac->rx_chns, "rx", 1345 max_rx_flows, PRUETH_MAX_RX_DESC); 1346 if (ret) { 1347 dev_err(dev, "failed to init rx channel: %d\n", ret); 1348 goto cleanup_tx; 1349 } 1350 1351 ret = prueth_ndev_add_tx_napi(emac); 1352 if (ret) 1353 goto cleanup_rx; 1354 1355 /* we use only the highest priority flow for now i.e. @irq[3] */ 1356 rx_flow = PRUETH_RX_FLOW_DATA; 1357 ret = request_irq(emac->rx_chns.irq[rx_flow], prueth_rx_irq, 1358 IRQF_TRIGGER_HIGH, dev_name(dev), emac); 1359 if (ret) { 1360 dev_err(dev, "unable to request RX IRQ\n"); 1361 goto cleanup_napi; 1362 } 1363 1364 /* reset and start PRU firmware */ 1365 ret = prueth_emac_start(prueth, emac); 1366 if (ret) 1367 goto free_rx_irq; 1368 1369 icssg_mii_update_mtu(prueth->mii_rt, slice, ndev->max_mtu); 1370 1371 if (!prueth->emacs_initialized) { 1372 ret = icss_iep_init(emac->iep, &prueth_iep_clockops, 1373 emac, IEP_DEFAULT_CYCLE_TIME_NS); 1374 } 1375 1376 ret = request_threaded_irq(emac->tx_ts_irq, NULL, prueth_tx_ts_irq, 1377 IRQF_ONESHOT, dev_name(dev), emac); 1378 if (ret) 1379 goto stop; 1380 1381 /* Prepare RX */ 1382 ret = prueth_prepare_rx_chan(emac, &emac->rx_chns, PRUETH_MAX_PKT_SIZE); 1383 if (ret) 1384 goto free_tx_ts_irq; 1385 1386 ret = k3_udma_glue_enable_rx_chn(emac->rx_chns.rx_chn); 1387 if (ret) 1388 goto reset_rx_chn; 1389 1390 for (i = 0; i < emac->tx_ch_num; i++) { 1391 ret = k3_udma_glue_enable_tx_chn(emac->tx_chns[i].tx_chn); 1392 if (ret) 1393 goto reset_tx_chan; 1394 } 1395 1396 /* Enable NAPI in Tx and Rx direction */ 1397 for (i = 0; i < emac->tx_ch_num; i++) 1398 napi_enable(&emac->tx_chns[i].napi_tx); 1399 napi_enable(&emac->napi_rx); 1400 1401 /* start PHY */ 1402 phy_start(ndev->phydev); 1403 1404 prueth->emacs_initialized++; 1405 1406 queue_work(system_long_wq, &emac->stats_work.work); 1407 1408 return 0; 1409 1410 reset_tx_chan: 1411 /* Since interface is not yet up, there is wouldn't be 1412 * any SKB for completion. So set false to free_skb 1413 */ 1414 prueth_reset_tx_chan(emac, i, false); 1415 reset_rx_chn: 1416 prueth_reset_rx_chan(&emac->rx_chns, max_rx_flows, false); 1417 free_tx_ts_irq: 1418 free_irq(emac->tx_ts_irq, emac); 1419 stop: 1420 prueth_emac_stop(emac); 1421 free_rx_irq: 1422 free_irq(emac->rx_chns.irq[rx_flow], emac); 1423 cleanup_napi: 1424 prueth_ndev_del_tx_napi(emac, emac->tx_ch_num); 1425 cleanup_rx: 1426 prueth_cleanup_rx_chns(emac, &emac->rx_chns, max_rx_flows); 1427 cleanup_tx: 1428 prueth_cleanup_tx_chns(emac); 1429 1430 return ret; 1431 } 1432 1433 /** 1434 * emac_ndo_stop - EMAC device stop 1435 * @ndev: network adapter device 1436 * 1437 * Called when system wants to stop or down the interface. 1438 * 1439 * Return: Always 0 (Success) 1440 */ 1441 static int emac_ndo_stop(struct net_device *ndev) 1442 { 1443 struct prueth_emac *emac = netdev_priv(ndev); 1444 struct prueth *prueth = emac->prueth; 1445 int rx_flow = PRUETH_RX_FLOW_DATA; 1446 int max_rx_flows; 1447 int ret, i; 1448 1449 /* inform the upper layers. */ 1450 netif_tx_stop_all_queues(ndev); 1451 1452 /* block packets from wire */ 1453 if (ndev->phydev) 1454 phy_stop(ndev->phydev); 1455 1456 icssg_class_disable(prueth->miig_rt, prueth_emac_slice(emac)); 1457 1458 atomic_set(&emac->tdown_cnt, emac->tx_ch_num); 1459 /* ensure new tdown_cnt value is visible */ 1460 smp_mb__after_atomic(); 1461 /* tear down and disable UDMA channels */ 1462 reinit_completion(&emac->tdown_complete); 1463 for (i = 0; i < emac->tx_ch_num; i++) 1464 k3_udma_glue_tdown_tx_chn(emac->tx_chns[i].tx_chn, false); 1465 1466 ret = wait_for_completion_timeout(&emac->tdown_complete, 1467 msecs_to_jiffies(1000)); 1468 if (!ret) 1469 netdev_err(ndev, "tx teardown timeout\n"); 1470 1471 prueth_reset_tx_chan(emac, emac->tx_ch_num, true); 1472 for (i = 0; i < emac->tx_ch_num; i++) 1473 napi_disable(&emac->tx_chns[i].napi_tx); 1474 1475 max_rx_flows = PRUETH_MAX_RX_FLOWS; 1476 k3_udma_glue_tdown_rx_chn(emac->rx_chns.rx_chn, true); 1477 1478 prueth_reset_rx_chan(&emac->rx_chns, max_rx_flows, true); 1479 1480 napi_disable(&emac->napi_rx); 1481 1482 cancel_work_sync(&emac->rx_mode_work); 1483 1484 /* Destroying the queued work in ndo_stop() */ 1485 cancel_delayed_work_sync(&emac->stats_work); 1486 1487 /* stop PRUs */ 1488 prueth_emac_stop(emac); 1489 1490 if (prueth->emacs_initialized == 1) 1491 icss_iep_exit(emac->iep); 1492 1493 /* stop PRUs */ 1494 prueth_emac_stop(emac); 1495 1496 free_irq(emac->tx_ts_irq, emac); 1497 1498 free_irq(emac->rx_chns.irq[rx_flow], emac); 1499 prueth_ndev_del_tx_napi(emac, emac->tx_ch_num); 1500 prueth_cleanup_tx_chns(emac); 1501 1502 prueth_cleanup_rx_chns(emac, &emac->rx_chns, max_rx_flows); 1503 prueth_cleanup_tx_chns(emac); 1504 1505 prueth->emacs_initialized--; 1506 1507 return 0; 1508 } 1509 1510 static void emac_ndo_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1511 { 1512 ndev->stats.tx_errors++; 1513 } 1514 1515 static void emac_ndo_set_rx_mode_work(struct work_struct *work) 1516 { 1517 struct prueth_emac *emac = container_of(work, struct prueth_emac, rx_mode_work); 1518 struct net_device *ndev = emac->ndev; 1519 bool promisc, allmulti; 1520 1521 if (!netif_running(ndev)) 1522 return; 1523 1524 promisc = ndev->flags & IFF_PROMISC; 1525 allmulti = ndev->flags & IFF_ALLMULTI; 1526 emac_set_port_state(emac, ICSSG_EMAC_PORT_UC_FLOODING_DISABLE); 1527 emac_set_port_state(emac, ICSSG_EMAC_PORT_MC_FLOODING_DISABLE); 1528 1529 if (promisc) { 1530 emac_set_port_state(emac, ICSSG_EMAC_PORT_UC_FLOODING_ENABLE); 1531 emac_set_port_state(emac, ICSSG_EMAC_PORT_MC_FLOODING_ENABLE); 1532 return; 1533 } 1534 1535 if (allmulti) { 1536 emac_set_port_state(emac, ICSSG_EMAC_PORT_MC_FLOODING_ENABLE); 1537 return; 1538 } 1539 1540 if (!netdev_mc_empty(ndev)) { 1541 emac_set_port_state(emac, ICSSG_EMAC_PORT_MC_FLOODING_ENABLE); 1542 return; 1543 } 1544 } 1545 1546 /** 1547 * emac_ndo_set_rx_mode - EMAC set receive mode function 1548 * @ndev: The EMAC network adapter 1549 * 1550 * Called when system wants to set the receive mode of the device. 1551 * 1552 */ 1553 static void emac_ndo_set_rx_mode(struct net_device *ndev) 1554 { 1555 struct prueth_emac *emac = netdev_priv(ndev); 1556 1557 queue_work(emac->cmd_wq, &emac->rx_mode_work); 1558 } 1559 1560 static int emac_set_ts_config(struct net_device *ndev, struct ifreq *ifr) 1561 { 1562 struct prueth_emac *emac = netdev_priv(ndev); 1563 struct hwtstamp_config config; 1564 1565 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1566 return -EFAULT; 1567 1568 switch (config.tx_type) { 1569 case HWTSTAMP_TX_OFF: 1570 emac->tx_ts_enabled = 0; 1571 break; 1572 case HWTSTAMP_TX_ON: 1573 emac->tx_ts_enabled = 1; 1574 break; 1575 default: 1576 return -ERANGE; 1577 } 1578 1579 switch (config.rx_filter) { 1580 case HWTSTAMP_FILTER_NONE: 1581 emac->rx_ts_enabled = 0; 1582 break; 1583 case HWTSTAMP_FILTER_ALL: 1584 case HWTSTAMP_FILTER_SOME: 1585 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1586 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1587 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1588 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1589 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1590 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1591 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1592 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1593 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1594 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1595 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1596 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1597 case HWTSTAMP_FILTER_NTP_ALL: 1598 emac->rx_ts_enabled = 1; 1599 config.rx_filter = HWTSTAMP_FILTER_ALL; 1600 break; 1601 default: 1602 return -ERANGE; 1603 } 1604 1605 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1606 -EFAULT : 0; 1607 } 1608 1609 static int emac_get_ts_config(struct net_device *ndev, struct ifreq *ifr) 1610 { 1611 struct prueth_emac *emac = netdev_priv(ndev); 1612 struct hwtstamp_config config; 1613 1614 config.flags = 0; 1615 config.tx_type = emac->tx_ts_enabled ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1616 config.rx_filter = emac->rx_ts_enabled ? HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 1617 1618 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1619 -EFAULT : 0; 1620 } 1621 1622 static int emac_ndo_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd) 1623 { 1624 switch (cmd) { 1625 case SIOCGHWTSTAMP: 1626 return emac_get_ts_config(ndev, ifr); 1627 case SIOCSHWTSTAMP: 1628 return emac_set_ts_config(ndev, ifr); 1629 default: 1630 break; 1631 } 1632 1633 return phy_do_ioctl(ndev, ifr, cmd); 1634 } 1635 1636 static void emac_ndo_get_stats64(struct net_device *ndev, 1637 struct rtnl_link_stats64 *stats) 1638 { 1639 struct prueth_emac *emac = netdev_priv(ndev); 1640 1641 emac_update_hardware_stats(emac); 1642 1643 stats->rx_packets = emac_get_stat_by_name(emac, "rx_packets"); 1644 stats->rx_bytes = emac_get_stat_by_name(emac, "rx_bytes"); 1645 stats->tx_packets = emac_get_stat_by_name(emac, "tx_packets"); 1646 stats->tx_bytes = emac_get_stat_by_name(emac, "tx_bytes"); 1647 stats->rx_crc_errors = emac_get_stat_by_name(emac, "rx_crc_errors"); 1648 stats->rx_over_errors = emac_get_stat_by_name(emac, "rx_over_errors"); 1649 stats->multicast = emac_get_stat_by_name(emac, "rx_multicast_frames"); 1650 1651 stats->rx_errors = ndev->stats.rx_errors; 1652 stats->rx_dropped = ndev->stats.rx_dropped; 1653 stats->tx_errors = ndev->stats.tx_errors; 1654 stats->tx_dropped = ndev->stats.tx_dropped; 1655 } 1656 1657 static const struct net_device_ops emac_netdev_ops = { 1658 .ndo_open = emac_ndo_open, 1659 .ndo_stop = emac_ndo_stop, 1660 .ndo_start_xmit = emac_ndo_start_xmit, 1661 .ndo_set_mac_address = eth_mac_addr, 1662 .ndo_validate_addr = eth_validate_addr, 1663 .ndo_tx_timeout = emac_ndo_tx_timeout, 1664 .ndo_set_rx_mode = emac_ndo_set_rx_mode, 1665 .ndo_eth_ioctl = emac_ndo_ioctl, 1666 .ndo_get_stats64 = emac_ndo_get_stats64, 1667 }; 1668 1669 /* get emac_port corresponding to eth_node name */ 1670 static int prueth_node_port(struct device_node *eth_node) 1671 { 1672 u32 port_id; 1673 int ret; 1674 1675 ret = of_property_read_u32(eth_node, "reg", &port_id); 1676 if (ret) 1677 return ret; 1678 1679 if (port_id == 0) 1680 return PRUETH_PORT_MII0; 1681 else if (port_id == 1) 1682 return PRUETH_PORT_MII1; 1683 else 1684 return PRUETH_PORT_INVALID; 1685 } 1686 1687 /* get MAC instance corresponding to eth_node name */ 1688 static int prueth_node_mac(struct device_node *eth_node) 1689 { 1690 u32 port_id; 1691 int ret; 1692 1693 ret = of_property_read_u32(eth_node, "reg", &port_id); 1694 if (ret) 1695 return ret; 1696 1697 if (port_id == 0) 1698 return PRUETH_MAC0; 1699 else if (port_id == 1) 1700 return PRUETH_MAC1; 1701 else 1702 return PRUETH_MAC_INVALID; 1703 } 1704 1705 static int prueth_netdev_init(struct prueth *prueth, 1706 struct device_node *eth_node) 1707 { 1708 int ret, num_tx_chn = PRUETH_MAX_TX_QUEUES; 1709 struct prueth_emac *emac; 1710 struct net_device *ndev; 1711 enum prueth_port port; 1712 const char *irq_name; 1713 enum prueth_mac mac; 1714 1715 port = prueth_node_port(eth_node); 1716 if (port == PRUETH_PORT_INVALID) 1717 return -EINVAL; 1718 1719 mac = prueth_node_mac(eth_node); 1720 if (mac == PRUETH_MAC_INVALID) 1721 return -EINVAL; 1722 1723 ndev = alloc_etherdev_mq(sizeof(*emac), num_tx_chn); 1724 if (!ndev) 1725 return -ENOMEM; 1726 1727 emac = netdev_priv(ndev); 1728 emac->prueth = prueth; 1729 emac->ndev = ndev; 1730 emac->port_id = port; 1731 emac->cmd_wq = create_singlethread_workqueue("icssg_cmd_wq"); 1732 if (!emac->cmd_wq) { 1733 ret = -ENOMEM; 1734 goto free_ndev; 1735 } 1736 INIT_WORK(&emac->rx_mode_work, emac_ndo_set_rx_mode_work); 1737 1738 INIT_DELAYED_WORK(&emac->stats_work, emac_stats_work_handler); 1739 1740 ret = pruss_request_mem_region(prueth->pruss, 1741 port == PRUETH_PORT_MII0 ? 1742 PRUSS_MEM_DRAM0 : PRUSS_MEM_DRAM1, 1743 &emac->dram); 1744 if (ret) { 1745 dev_err(prueth->dev, "unable to get DRAM: %d\n", ret); 1746 ret = -ENOMEM; 1747 goto free_wq; 1748 } 1749 1750 emac->tx_ch_num = 1; 1751 1752 irq_name = "tx_ts0"; 1753 if (emac->port_id == PRUETH_PORT_MII1) 1754 irq_name = "tx_ts1"; 1755 emac->tx_ts_irq = platform_get_irq_byname_optional(prueth->pdev, irq_name); 1756 if (emac->tx_ts_irq < 0) { 1757 ret = dev_err_probe(prueth->dev, emac->tx_ts_irq, "could not get tx_ts_irq\n"); 1758 goto free; 1759 } 1760 1761 SET_NETDEV_DEV(ndev, prueth->dev); 1762 spin_lock_init(&emac->lock); 1763 mutex_init(&emac->cmd_lock); 1764 1765 emac->phy_node = of_parse_phandle(eth_node, "phy-handle", 0); 1766 if (!emac->phy_node && !of_phy_is_fixed_link(eth_node)) { 1767 dev_err(prueth->dev, "couldn't find phy-handle\n"); 1768 ret = -ENODEV; 1769 goto free; 1770 } else if (of_phy_is_fixed_link(eth_node)) { 1771 ret = of_phy_register_fixed_link(eth_node); 1772 if (ret) { 1773 ret = dev_err_probe(prueth->dev, ret, 1774 "failed to register fixed-link phy\n"); 1775 goto free; 1776 } 1777 1778 emac->phy_node = eth_node; 1779 } 1780 1781 ret = of_get_phy_mode(eth_node, &emac->phy_if); 1782 if (ret) { 1783 dev_err(prueth->dev, "could not get phy-mode property\n"); 1784 goto free; 1785 } 1786 1787 if (emac->phy_if != PHY_INTERFACE_MODE_MII && 1788 !phy_interface_mode_is_rgmii(emac->phy_if)) { 1789 dev_err(prueth->dev, "PHY mode unsupported %s\n", phy_modes(emac->phy_if)); 1790 ret = -EINVAL; 1791 goto free; 1792 } 1793 1794 /* AM65 SR2.0 has TX Internal delay always enabled by hardware 1795 * and it is not possible to disable TX Internal delay. The below 1796 * switch case block describes how we handle different phy modes 1797 * based on hardware restriction. 1798 */ 1799 switch (emac->phy_if) { 1800 case PHY_INTERFACE_MODE_RGMII_ID: 1801 emac->phy_if = PHY_INTERFACE_MODE_RGMII_RXID; 1802 break; 1803 case PHY_INTERFACE_MODE_RGMII_TXID: 1804 emac->phy_if = PHY_INTERFACE_MODE_RGMII; 1805 break; 1806 case PHY_INTERFACE_MODE_RGMII: 1807 case PHY_INTERFACE_MODE_RGMII_RXID: 1808 dev_err(prueth->dev, "RGMII mode without TX delay is not supported"); 1809 ret = -EINVAL; 1810 goto free; 1811 default: 1812 break; 1813 } 1814 1815 /* get mac address from DT and set private and netdev addr */ 1816 ret = of_get_ethdev_address(eth_node, ndev); 1817 if (!is_valid_ether_addr(ndev->dev_addr)) { 1818 eth_hw_addr_random(ndev); 1819 dev_warn(prueth->dev, "port %d: using random MAC addr: %pM\n", 1820 port, ndev->dev_addr); 1821 } 1822 ether_addr_copy(emac->mac_addr, ndev->dev_addr); 1823 1824 ndev->min_mtu = PRUETH_MIN_PKT_SIZE; 1825 ndev->max_mtu = PRUETH_MAX_MTU; 1826 ndev->netdev_ops = &emac_netdev_ops; 1827 ndev->ethtool_ops = &icssg_ethtool_ops; 1828 ndev->hw_features = NETIF_F_SG; 1829 ndev->features = ndev->hw_features; 1830 1831 netif_napi_add(ndev, &emac->napi_rx, emac_napi_rx_poll); 1832 prueth->emac[mac] = emac; 1833 1834 return 0; 1835 1836 free: 1837 pruss_release_mem_region(prueth->pruss, &emac->dram); 1838 free_wq: 1839 destroy_workqueue(emac->cmd_wq); 1840 free_ndev: 1841 emac->ndev = NULL; 1842 prueth->emac[mac] = NULL; 1843 free_netdev(ndev); 1844 1845 return ret; 1846 } 1847 1848 static void prueth_netdev_exit(struct prueth *prueth, 1849 struct device_node *eth_node) 1850 { 1851 struct prueth_emac *emac; 1852 enum prueth_mac mac; 1853 1854 mac = prueth_node_mac(eth_node); 1855 if (mac == PRUETH_MAC_INVALID) 1856 return; 1857 1858 emac = prueth->emac[mac]; 1859 if (!emac) 1860 return; 1861 1862 if (of_phy_is_fixed_link(emac->phy_node)) 1863 of_phy_deregister_fixed_link(emac->phy_node); 1864 1865 netif_napi_del(&emac->napi_rx); 1866 1867 pruss_release_mem_region(prueth->pruss, &emac->dram); 1868 destroy_workqueue(emac->cmd_wq); 1869 free_netdev(emac->ndev); 1870 prueth->emac[mac] = NULL; 1871 } 1872 1873 static int prueth_get_cores(struct prueth *prueth, int slice) 1874 { 1875 struct device *dev = prueth->dev; 1876 enum pruss_pru_id pruss_id; 1877 struct device_node *np; 1878 int idx = -1, ret; 1879 1880 np = dev->of_node; 1881 1882 switch (slice) { 1883 case ICSS_SLICE0: 1884 idx = 0; 1885 break; 1886 case ICSS_SLICE1: 1887 idx = 3; 1888 break; 1889 default: 1890 return -EINVAL; 1891 } 1892 1893 prueth->pru[slice] = pru_rproc_get(np, idx, &pruss_id); 1894 if (IS_ERR(prueth->pru[slice])) { 1895 ret = PTR_ERR(prueth->pru[slice]); 1896 prueth->pru[slice] = NULL; 1897 return dev_err_probe(dev, ret, "unable to get PRU%d\n", slice); 1898 } 1899 prueth->pru_id[slice] = pruss_id; 1900 1901 idx++; 1902 prueth->rtu[slice] = pru_rproc_get(np, idx, NULL); 1903 if (IS_ERR(prueth->rtu[slice])) { 1904 ret = PTR_ERR(prueth->rtu[slice]); 1905 prueth->rtu[slice] = NULL; 1906 return dev_err_probe(dev, ret, "unable to get RTU%d\n", slice); 1907 } 1908 1909 idx++; 1910 prueth->txpru[slice] = pru_rproc_get(np, idx, NULL); 1911 if (IS_ERR(prueth->txpru[slice])) { 1912 ret = PTR_ERR(prueth->txpru[slice]); 1913 prueth->txpru[slice] = NULL; 1914 return dev_err_probe(dev, ret, "unable to get TX_PRU%d\n", slice); 1915 } 1916 1917 return 0; 1918 } 1919 1920 static void prueth_put_cores(struct prueth *prueth, int slice) 1921 { 1922 if (prueth->txpru[slice]) 1923 pru_rproc_put(prueth->txpru[slice]); 1924 1925 if (prueth->rtu[slice]) 1926 pru_rproc_put(prueth->rtu[slice]); 1927 1928 if (prueth->pru[slice]) 1929 pru_rproc_put(prueth->pru[slice]); 1930 } 1931 1932 static const struct of_device_id prueth_dt_match[]; 1933 1934 static int prueth_probe(struct platform_device *pdev) 1935 { 1936 struct device_node *eth_node, *eth_ports_node; 1937 struct device_node *eth0_node = NULL; 1938 struct device_node *eth1_node = NULL; 1939 struct genpool_data_align gp_data = { 1940 .align = SZ_64K, 1941 }; 1942 const struct of_device_id *match; 1943 struct device *dev = &pdev->dev; 1944 struct device_node *np; 1945 struct prueth *prueth; 1946 struct pruss *pruss; 1947 u32 msmc_ram_size; 1948 int i, ret; 1949 1950 np = dev->of_node; 1951 1952 match = of_match_device(prueth_dt_match, dev); 1953 if (!match) 1954 return -ENODEV; 1955 1956 prueth = devm_kzalloc(dev, sizeof(*prueth), GFP_KERNEL); 1957 if (!prueth) 1958 return -ENOMEM; 1959 1960 dev_set_drvdata(dev, prueth); 1961 prueth->pdev = pdev; 1962 prueth->pdata = *(const struct prueth_pdata *)match->data; 1963 1964 prueth->dev = dev; 1965 eth_ports_node = of_get_child_by_name(np, "ethernet-ports"); 1966 if (!eth_ports_node) 1967 return -ENOENT; 1968 1969 for_each_child_of_node(eth_ports_node, eth_node) { 1970 u32 reg; 1971 1972 if (strcmp(eth_node->name, "port")) 1973 continue; 1974 ret = of_property_read_u32(eth_node, "reg", ®); 1975 if (ret < 0) { 1976 dev_err(dev, "%pOF error reading port_id %d\n", 1977 eth_node, ret); 1978 } 1979 1980 of_node_get(eth_node); 1981 1982 if (reg == 0) { 1983 eth0_node = eth_node; 1984 if (!of_device_is_available(eth0_node)) { 1985 of_node_put(eth0_node); 1986 eth0_node = NULL; 1987 } 1988 } else if (reg == 1) { 1989 eth1_node = eth_node; 1990 if (!of_device_is_available(eth1_node)) { 1991 of_node_put(eth1_node); 1992 eth1_node = NULL; 1993 } 1994 } else { 1995 dev_err(dev, "port reg should be 0 or 1\n"); 1996 } 1997 } 1998 1999 of_node_put(eth_ports_node); 2000 2001 /* At least one node must be present and available else we fail */ 2002 if (!eth0_node && !eth1_node) { 2003 dev_err(dev, "neither port0 nor port1 node available\n"); 2004 return -ENODEV; 2005 } 2006 2007 if (eth0_node == eth1_node) { 2008 dev_err(dev, "port0 and port1 can't have same reg\n"); 2009 of_node_put(eth0_node); 2010 return -ENODEV; 2011 } 2012 2013 prueth->eth_node[PRUETH_MAC0] = eth0_node; 2014 prueth->eth_node[PRUETH_MAC1] = eth1_node; 2015 2016 prueth->miig_rt = syscon_regmap_lookup_by_phandle(np, "ti,mii-g-rt"); 2017 if (IS_ERR(prueth->miig_rt)) { 2018 dev_err(dev, "couldn't get ti,mii-g-rt syscon regmap\n"); 2019 return -ENODEV; 2020 } 2021 2022 prueth->mii_rt = syscon_regmap_lookup_by_phandle(np, "ti,mii-rt"); 2023 if (IS_ERR(prueth->mii_rt)) { 2024 dev_err(dev, "couldn't get ti,mii-rt syscon regmap\n"); 2025 return -ENODEV; 2026 } 2027 2028 if (eth0_node) { 2029 ret = prueth_get_cores(prueth, ICSS_SLICE0); 2030 if (ret) 2031 goto put_cores; 2032 } 2033 2034 if (eth1_node) { 2035 ret = prueth_get_cores(prueth, ICSS_SLICE1); 2036 if (ret) 2037 goto put_cores; 2038 } 2039 2040 pruss = pruss_get(eth0_node ? 2041 prueth->pru[ICSS_SLICE0] : prueth->pru[ICSS_SLICE1]); 2042 if (IS_ERR(pruss)) { 2043 ret = PTR_ERR(pruss); 2044 dev_err(dev, "unable to get pruss handle\n"); 2045 goto put_cores; 2046 } 2047 2048 prueth->pruss = pruss; 2049 2050 ret = pruss_request_mem_region(pruss, PRUSS_MEM_SHRD_RAM2, 2051 &prueth->shram); 2052 if (ret) { 2053 dev_err(dev, "unable to get PRUSS SHRD RAM2: %d\n", ret); 2054 pruss_put(prueth->pruss); 2055 } 2056 2057 prueth->sram_pool = of_gen_pool_get(np, "sram", 0); 2058 if (!prueth->sram_pool) { 2059 dev_err(dev, "unable to get SRAM pool\n"); 2060 ret = -ENODEV; 2061 2062 goto put_mem; 2063 } 2064 2065 msmc_ram_size = MSMC_RAM_SIZE; 2066 2067 /* NOTE: FW bug needs buffer base to be 64KB aligned */ 2068 prueth->msmcram.va = 2069 (void __iomem *)gen_pool_alloc_algo(prueth->sram_pool, 2070 msmc_ram_size, 2071 gen_pool_first_fit_align, 2072 &gp_data); 2073 2074 if (!prueth->msmcram.va) { 2075 ret = -ENOMEM; 2076 dev_err(dev, "unable to allocate MSMC resource\n"); 2077 goto put_mem; 2078 } 2079 prueth->msmcram.pa = gen_pool_virt_to_phys(prueth->sram_pool, 2080 (unsigned long)prueth->msmcram.va); 2081 prueth->msmcram.size = msmc_ram_size; 2082 memset_io(prueth->msmcram.va, 0, msmc_ram_size); 2083 dev_dbg(dev, "sram: pa %llx va %p size %zx\n", prueth->msmcram.pa, 2084 prueth->msmcram.va, prueth->msmcram.size); 2085 2086 prueth->iep0 = icss_iep_get_idx(np, 0); 2087 if (IS_ERR(prueth->iep0)) { 2088 ret = dev_err_probe(dev, PTR_ERR(prueth->iep0), "iep0 get failed\n"); 2089 prueth->iep0 = NULL; 2090 goto free_pool; 2091 } 2092 2093 /* setup netdev interfaces */ 2094 if (eth0_node) { 2095 ret = prueth_netdev_init(prueth, eth0_node); 2096 if (ret) { 2097 dev_err_probe(dev, ret, "netdev init %s failed\n", 2098 eth0_node->name); 2099 goto netdev_exit; 2100 } 2101 prueth->emac[PRUETH_MAC0]->iep = prueth->iep0; 2102 } 2103 2104 if (eth1_node) { 2105 ret = prueth_netdev_init(prueth, eth1_node); 2106 if (ret) { 2107 dev_err_probe(dev, ret, "netdev init %s failed\n", 2108 eth1_node->name); 2109 goto netdev_exit; 2110 } 2111 2112 prueth->emac[PRUETH_MAC1]->iep = prueth->iep0; 2113 } 2114 2115 /* register the network devices */ 2116 if (eth0_node) { 2117 ret = register_netdev(prueth->emac[PRUETH_MAC0]->ndev); 2118 if (ret) { 2119 dev_err(dev, "can't register netdev for port MII0"); 2120 goto netdev_exit; 2121 } 2122 2123 prueth->registered_netdevs[PRUETH_MAC0] = prueth->emac[PRUETH_MAC0]->ndev; 2124 2125 emac_phy_connect(prueth->emac[PRUETH_MAC0]); 2126 phy_attached_info(prueth->emac[PRUETH_MAC0]->ndev->phydev); 2127 } 2128 2129 if (eth1_node) { 2130 ret = register_netdev(prueth->emac[PRUETH_MAC1]->ndev); 2131 if (ret) { 2132 dev_err(dev, "can't register netdev for port MII1"); 2133 goto netdev_unregister; 2134 } 2135 2136 prueth->registered_netdevs[PRUETH_MAC1] = prueth->emac[PRUETH_MAC1]->ndev; 2137 emac_phy_connect(prueth->emac[PRUETH_MAC1]); 2138 phy_attached_info(prueth->emac[PRUETH_MAC1]->ndev->phydev); 2139 } 2140 2141 dev_info(dev, "TI PRU ethernet driver initialized: %s EMAC mode\n", 2142 (!eth0_node || !eth1_node) ? "single" : "dual"); 2143 2144 if (eth1_node) 2145 of_node_put(eth1_node); 2146 if (eth0_node) 2147 of_node_put(eth0_node); 2148 return 0; 2149 2150 netdev_unregister: 2151 for (i = 0; i < PRUETH_NUM_MACS; i++) { 2152 if (!prueth->registered_netdevs[i]) 2153 continue; 2154 if (prueth->emac[i]->ndev->phydev) { 2155 phy_disconnect(prueth->emac[i]->ndev->phydev); 2156 prueth->emac[i]->ndev->phydev = NULL; 2157 } 2158 unregister_netdev(prueth->registered_netdevs[i]); 2159 } 2160 2161 netdev_exit: 2162 for (i = 0; i < PRUETH_NUM_MACS; i++) { 2163 eth_node = prueth->eth_node[i]; 2164 if (!eth_node) 2165 continue; 2166 2167 prueth_netdev_exit(prueth, eth_node); 2168 } 2169 2170 free_pool: 2171 gen_pool_free(prueth->sram_pool, 2172 (unsigned long)prueth->msmcram.va, msmc_ram_size); 2173 2174 put_mem: 2175 pruss_release_mem_region(prueth->pruss, &prueth->shram); 2176 pruss_put(prueth->pruss); 2177 2178 put_cores: 2179 if (eth1_node) { 2180 prueth_put_cores(prueth, ICSS_SLICE1); 2181 of_node_put(eth1_node); 2182 } 2183 2184 if (eth0_node) { 2185 prueth_put_cores(prueth, ICSS_SLICE0); 2186 of_node_put(eth0_node); 2187 } 2188 2189 return ret; 2190 } 2191 2192 static void prueth_remove(struct platform_device *pdev) 2193 { 2194 struct prueth *prueth = platform_get_drvdata(pdev); 2195 struct device_node *eth_node; 2196 int i; 2197 2198 for (i = 0; i < PRUETH_NUM_MACS; i++) { 2199 if (!prueth->registered_netdevs[i]) 2200 continue; 2201 phy_stop(prueth->emac[i]->ndev->phydev); 2202 phy_disconnect(prueth->emac[i]->ndev->phydev); 2203 prueth->emac[i]->ndev->phydev = NULL; 2204 unregister_netdev(prueth->registered_netdevs[i]); 2205 } 2206 2207 for (i = 0; i < PRUETH_NUM_MACS; i++) { 2208 eth_node = prueth->eth_node[i]; 2209 if (!eth_node) 2210 continue; 2211 2212 prueth_netdev_exit(prueth, eth_node); 2213 } 2214 2215 icss_iep_put(prueth->iep0); 2216 2217 gen_pool_free(prueth->sram_pool, 2218 (unsigned long)prueth->msmcram.va, 2219 MSMC_RAM_SIZE); 2220 2221 pruss_release_mem_region(prueth->pruss, &prueth->shram); 2222 2223 pruss_put(prueth->pruss); 2224 2225 if (prueth->eth_node[PRUETH_MAC1]) 2226 prueth_put_cores(prueth, ICSS_SLICE1); 2227 2228 if (prueth->eth_node[PRUETH_MAC0]) 2229 prueth_put_cores(prueth, ICSS_SLICE0); 2230 } 2231 2232 #ifdef CONFIG_PM_SLEEP 2233 static int prueth_suspend(struct device *dev) 2234 { 2235 struct prueth *prueth = dev_get_drvdata(dev); 2236 struct net_device *ndev; 2237 int i, ret; 2238 2239 for (i = 0; i < PRUETH_NUM_MACS; i++) { 2240 ndev = prueth->registered_netdevs[i]; 2241 2242 if (!ndev) 2243 continue; 2244 2245 if (netif_running(ndev)) { 2246 netif_device_detach(ndev); 2247 ret = emac_ndo_stop(ndev); 2248 if (ret < 0) { 2249 netdev_err(ndev, "failed to stop: %d", ret); 2250 return ret; 2251 } 2252 } 2253 } 2254 2255 return 0; 2256 } 2257 2258 static int prueth_resume(struct device *dev) 2259 { 2260 struct prueth *prueth = dev_get_drvdata(dev); 2261 struct net_device *ndev; 2262 int i, ret; 2263 2264 for (i = 0; i < PRUETH_NUM_MACS; i++) { 2265 ndev = prueth->registered_netdevs[i]; 2266 2267 if (!ndev) 2268 continue; 2269 2270 if (netif_running(ndev)) { 2271 ret = emac_ndo_open(ndev); 2272 if (ret < 0) { 2273 netdev_err(ndev, "failed to start: %d", ret); 2274 return ret; 2275 } 2276 netif_device_attach(ndev); 2277 } 2278 } 2279 2280 return 0; 2281 } 2282 #endif /* CONFIG_PM_SLEEP */ 2283 2284 static const struct dev_pm_ops prueth_dev_pm_ops = { 2285 SET_SYSTEM_SLEEP_PM_OPS(prueth_suspend, prueth_resume) 2286 }; 2287 2288 static const struct prueth_pdata am654_icssg_pdata = { 2289 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2290 .quirk_10m_link_issue = 1, 2291 }; 2292 2293 static const struct of_device_id prueth_dt_match[] = { 2294 { .compatible = "ti,am654-icssg-prueth", .data = &am654_icssg_pdata }, 2295 { /* sentinel */ } 2296 }; 2297 MODULE_DEVICE_TABLE(of, prueth_dt_match); 2298 2299 static struct platform_driver prueth_driver = { 2300 .probe = prueth_probe, 2301 .remove_new = prueth_remove, 2302 .driver = { 2303 .name = "icssg-prueth", 2304 .of_match_table = prueth_dt_match, 2305 .pm = &prueth_dev_pm_ops, 2306 }, 2307 }; 2308 module_platform_driver(prueth_driver); 2309 2310 MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>"); 2311 MODULE_AUTHOR("Md Danish Anwar <danishanwar@ti.com>"); 2312 MODULE_DESCRIPTION("PRUSS ICSSG Ethernet Driver"); 2313 MODULE_LICENSE("GPL"); 2314