1 // SPDX-License-Identifier: GPL-2.0
2 
3 /* Texas Instruments ICSSG Ethernet Driver
4  *
5  * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
6  *
7  */
8 
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/dma/ti-cppi5.h>
14 #include <linux/etherdevice.h>
15 #include <linux/genalloc.h>
16 #include <linux/if_vlan.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_mdio.h>
24 #include <linux/of_net.h>
25 #include <linux/of_platform.h>
26 #include <linux/phy.h>
27 #include <linux/remoteproc/pruss.h>
28 #include <linux/regmap.h>
29 #include <linux/remoteproc.h>
30 
31 #include "icssg_prueth.h"
32 #include "icssg_mii_rt.h"
33 #include "../k3-cppi-desc-pool.h"
34 
35 #define PRUETH_MODULE_DESCRIPTION "PRUSS ICSSG Ethernet driver"
36 
37 /* Netif debug messages possible */
38 #define PRUETH_EMAC_DEBUG       (NETIF_MSG_DRV | \
39 				 NETIF_MSG_PROBE | \
40 				 NETIF_MSG_LINK | \
41 				 NETIF_MSG_TIMER | \
42 				 NETIF_MSG_IFDOWN | \
43 				 NETIF_MSG_IFUP | \
44 				 NETIF_MSG_RX_ERR | \
45 				 NETIF_MSG_TX_ERR | \
46 				 NETIF_MSG_TX_QUEUED | \
47 				 NETIF_MSG_INTR | \
48 				 NETIF_MSG_TX_DONE | \
49 				 NETIF_MSG_RX_STATUS | \
50 				 NETIF_MSG_PKTDATA | \
51 				 NETIF_MSG_HW | \
52 				 NETIF_MSG_WOL)
53 
54 #define prueth_napi_to_emac(napi) container_of(napi, struct prueth_emac, napi_rx)
55 
56 /* CTRLMMR_ICSSG_RGMII_CTRL register bits */
57 #define ICSSG_CTRL_RGMII_ID_MODE                BIT(24)
58 
59 #define IEP_DEFAULT_CYCLE_TIME_NS	1000000	/* 1 ms */
60 
61 static void prueth_cleanup_rx_chns(struct prueth_emac *emac,
62 				   struct prueth_rx_chn *rx_chn,
63 				   int max_rflows)
64 {
65 	if (rx_chn->desc_pool)
66 		k3_cppi_desc_pool_destroy(rx_chn->desc_pool);
67 
68 	if (rx_chn->rx_chn)
69 		k3_udma_glue_release_rx_chn(rx_chn->rx_chn);
70 }
71 
72 static void prueth_cleanup_tx_chns(struct prueth_emac *emac)
73 {
74 	int i;
75 
76 	for (i = 0; i < emac->tx_ch_num; i++) {
77 		struct prueth_tx_chn *tx_chn = &emac->tx_chns[i];
78 
79 		if (tx_chn->desc_pool)
80 			k3_cppi_desc_pool_destroy(tx_chn->desc_pool);
81 
82 		if (tx_chn->tx_chn)
83 			k3_udma_glue_release_tx_chn(tx_chn->tx_chn);
84 
85 		/* Assume prueth_cleanup_tx_chns() is called at the
86 		 * end after all channel resources are freed
87 		 */
88 		memset(tx_chn, 0, sizeof(*tx_chn));
89 	}
90 }
91 
92 static void prueth_ndev_del_tx_napi(struct prueth_emac *emac, int num)
93 {
94 	int i;
95 
96 	for (i = 0; i < num; i++) {
97 		struct prueth_tx_chn *tx_chn = &emac->tx_chns[i];
98 
99 		if (tx_chn->irq)
100 			free_irq(tx_chn->irq, tx_chn);
101 		netif_napi_del(&tx_chn->napi_tx);
102 	}
103 }
104 
105 static void prueth_xmit_free(struct prueth_tx_chn *tx_chn,
106 			     struct cppi5_host_desc_t *desc)
107 {
108 	struct cppi5_host_desc_t *first_desc, *next_desc;
109 	dma_addr_t buf_dma, next_desc_dma;
110 	u32 buf_dma_len;
111 
112 	first_desc = desc;
113 	next_desc = first_desc;
114 
115 	cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len);
116 	k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma);
117 
118 	dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len,
119 			 DMA_TO_DEVICE);
120 
121 	next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc);
122 	k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma);
123 	while (next_desc_dma) {
124 		next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool,
125 						       next_desc_dma);
126 		cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len);
127 		k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma);
128 
129 		dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len,
130 			       DMA_TO_DEVICE);
131 
132 		next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc);
133 		k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma);
134 
135 		k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc);
136 	}
137 
138 	k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc);
139 }
140 
141 static int emac_tx_complete_packets(struct prueth_emac *emac, int chn,
142 				    int budget)
143 {
144 	struct net_device *ndev = emac->ndev;
145 	struct cppi5_host_desc_t *desc_tx;
146 	struct netdev_queue *netif_txq;
147 	struct prueth_tx_chn *tx_chn;
148 	unsigned int total_bytes = 0;
149 	struct sk_buff *skb;
150 	dma_addr_t desc_dma;
151 	int res, num_tx = 0;
152 	void **swdata;
153 
154 	tx_chn = &emac->tx_chns[chn];
155 
156 	while (true) {
157 		res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma);
158 		if (res == -ENODATA)
159 			break;
160 
161 		/* teardown completion */
162 		if (cppi5_desc_is_tdcm(desc_dma)) {
163 			if (atomic_dec_and_test(&emac->tdown_cnt))
164 				complete(&emac->tdown_complete);
165 			break;
166 		}
167 
168 		desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool,
169 						     desc_dma);
170 		swdata = cppi5_hdesc_get_swdata(desc_tx);
171 
172 		skb = *(swdata);
173 		prueth_xmit_free(tx_chn, desc_tx);
174 
175 		ndev = skb->dev;
176 		ndev->stats.tx_packets++;
177 		ndev->stats.tx_bytes += skb->len;
178 		total_bytes += skb->len;
179 		napi_consume_skb(skb, budget);
180 		num_tx++;
181 	}
182 
183 	if (!num_tx)
184 		return 0;
185 
186 	netif_txq = netdev_get_tx_queue(ndev, chn);
187 	netdev_tx_completed_queue(netif_txq, num_tx, total_bytes);
188 
189 	if (netif_tx_queue_stopped(netif_txq)) {
190 		/* If the TX queue was stopped, wake it now
191 		 * if we have enough room.
192 		 */
193 		__netif_tx_lock(netif_txq, smp_processor_id());
194 		if (netif_running(ndev) &&
195 		    (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >=
196 		     MAX_SKB_FRAGS))
197 			netif_tx_wake_queue(netif_txq);
198 		__netif_tx_unlock(netif_txq);
199 	}
200 
201 	return num_tx;
202 }
203 
204 static int emac_napi_tx_poll(struct napi_struct *napi_tx, int budget)
205 {
206 	struct prueth_tx_chn *tx_chn = prueth_napi_to_tx_chn(napi_tx);
207 	struct prueth_emac *emac = tx_chn->emac;
208 	int num_tx_packets;
209 
210 	num_tx_packets = emac_tx_complete_packets(emac, tx_chn->id, budget);
211 
212 	if (num_tx_packets >= budget)
213 		return budget;
214 
215 	if (napi_complete_done(napi_tx, num_tx_packets))
216 		enable_irq(tx_chn->irq);
217 
218 	return num_tx_packets;
219 }
220 
221 static irqreturn_t prueth_tx_irq(int irq, void *dev_id)
222 {
223 	struct prueth_tx_chn *tx_chn = dev_id;
224 
225 	disable_irq_nosync(irq);
226 	napi_schedule(&tx_chn->napi_tx);
227 
228 	return IRQ_HANDLED;
229 }
230 
231 static int prueth_ndev_add_tx_napi(struct prueth_emac *emac)
232 {
233 	struct prueth *prueth = emac->prueth;
234 	int i, ret;
235 
236 	for (i = 0; i < emac->tx_ch_num; i++) {
237 		struct prueth_tx_chn *tx_chn = &emac->tx_chns[i];
238 
239 		netif_napi_add_tx(emac->ndev, &tx_chn->napi_tx, emac_napi_tx_poll);
240 		ret = request_irq(tx_chn->irq, prueth_tx_irq,
241 				  IRQF_TRIGGER_HIGH, tx_chn->name,
242 				  tx_chn);
243 		if (ret) {
244 			netif_napi_del(&tx_chn->napi_tx);
245 			dev_err(prueth->dev, "unable to request TX IRQ %d\n",
246 				tx_chn->irq);
247 			goto fail;
248 		}
249 	}
250 
251 	return 0;
252 fail:
253 	prueth_ndev_del_tx_napi(emac, i);
254 	return ret;
255 }
256 
257 static int prueth_init_tx_chns(struct prueth_emac *emac)
258 {
259 	static const struct k3_ring_cfg ring_cfg = {
260 		.elm_size = K3_RINGACC_RING_ELSIZE_8,
261 		.mode = K3_RINGACC_RING_MODE_RING,
262 		.flags = 0,
263 		.size = PRUETH_MAX_TX_DESC,
264 	};
265 	struct k3_udma_glue_tx_channel_cfg tx_cfg;
266 	struct device *dev = emac->prueth->dev;
267 	struct net_device *ndev = emac->ndev;
268 	int ret, slice, i;
269 	u32 hdesc_size;
270 
271 	slice = prueth_emac_slice(emac);
272 	if (slice < 0)
273 		return slice;
274 
275 	init_completion(&emac->tdown_complete);
276 
277 	hdesc_size = cppi5_hdesc_calc_size(true, PRUETH_NAV_PS_DATA_SIZE,
278 					   PRUETH_NAV_SW_DATA_SIZE);
279 	memset(&tx_cfg, 0, sizeof(tx_cfg));
280 	tx_cfg.swdata_size = PRUETH_NAV_SW_DATA_SIZE;
281 	tx_cfg.tx_cfg = ring_cfg;
282 	tx_cfg.txcq_cfg = ring_cfg;
283 
284 	for (i = 0; i < emac->tx_ch_num; i++) {
285 		struct prueth_tx_chn *tx_chn = &emac->tx_chns[i];
286 
287 		/* To differentiate channels for SLICE0 vs SLICE1 */
288 		snprintf(tx_chn->name, sizeof(tx_chn->name),
289 			 "tx%d-%d", slice, i);
290 
291 		tx_chn->emac = emac;
292 		tx_chn->id = i;
293 		tx_chn->descs_num = PRUETH_MAX_TX_DESC;
294 
295 		tx_chn->tx_chn =
296 			k3_udma_glue_request_tx_chn(dev, tx_chn->name,
297 						    &tx_cfg);
298 		if (IS_ERR(tx_chn->tx_chn)) {
299 			ret = PTR_ERR(tx_chn->tx_chn);
300 			tx_chn->tx_chn = NULL;
301 			netdev_err(ndev,
302 				   "Failed to request tx dma ch: %d\n", ret);
303 			goto fail;
304 		}
305 
306 		tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn);
307 		tx_chn->desc_pool =
308 			k3_cppi_desc_pool_create_name(tx_chn->dma_dev,
309 						      tx_chn->descs_num,
310 						      hdesc_size,
311 						      tx_chn->name);
312 		if (IS_ERR(tx_chn->desc_pool)) {
313 			ret = PTR_ERR(tx_chn->desc_pool);
314 			tx_chn->desc_pool = NULL;
315 			netdev_err(ndev, "Failed to create tx pool: %d\n", ret);
316 			goto fail;
317 		}
318 
319 		ret = k3_udma_glue_tx_get_irq(tx_chn->tx_chn);
320 		if (ret < 0) {
321 			netdev_err(ndev, "failed to get tx irq\n");
322 			goto fail;
323 		}
324 		tx_chn->irq = ret;
325 
326 		snprintf(tx_chn->name, sizeof(tx_chn->name), "%s-tx%d",
327 			 dev_name(dev), tx_chn->id);
328 	}
329 
330 	return 0;
331 
332 fail:
333 	prueth_cleanup_tx_chns(emac);
334 	return ret;
335 }
336 
337 static int prueth_init_rx_chns(struct prueth_emac *emac,
338 			       struct prueth_rx_chn *rx_chn,
339 			       char *name, u32 max_rflows,
340 			       u32 max_desc_num)
341 {
342 	struct k3_udma_glue_rx_channel_cfg rx_cfg;
343 	struct device *dev = emac->prueth->dev;
344 	struct net_device *ndev = emac->ndev;
345 	u32 fdqring_id, hdesc_size;
346 	int i, ret = 0, slice;
347 
348 	slice = prueth_emac_slice(emac);
349 	if (slice < 0)
350 		return slice;
351 
352 	/* To differentiate channels for SLICE0 vs SLICE1 */
353 	snprintf(rx_chn->name, sizeof(rx_chn->name), "%s%d", name, slice);
354 
355 	hdesc_size = cppi5_hdesc_calc_size(true, PRUETH_NAV_PS_DATA_SIZE,
356 					   PRUETH_NAV_SW_DATA_SIZE);
357 	memset(&rx_cfg, 0, sizeof(rx_cfg));
358 	rx_cfg.swdata_size = PRUETH_NAV_SW_DATA_SIZE;
359 	rx_cfg.flow_id_num = max_rflows;
360 	rx_cfg.flow_id_base = -1; /* udmax will auto select flow id base */
361 
362 	/* init all flows */
363 	rx_chn->dev = dev;
364 	rx_chn->descs_num = max_desc_num;
365 
366 	rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, rx_chn->name,
367 						     &rx_cfg);
368 	if (IS_ERR(rx_chn->rx_chn)) {
369 		ret = PTR_ERR(rx_chn->rx_chn);
370 		rx_chn->rx_chn = NULL;
371 		netdev_err(ndev, "Failed to request rx dma ch: %d\n", ret);
372 		goto fail;
373 	}
374 
375 	rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn);
376 	rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev,
377 							  rx_chn->descs_num,
378 							  hdesc_size,
379 							  rx_chn->name);
380 	if (IS_ERR(rx_chn->desc_pool)) {
381 		ret = PTR_ERR(rx_chn->desc_pool);
382 		rx_chn->desc_pool = NULL;
383 		netdev_err(ndev, "Failed to create rx pool: %d\n", ret);
384 		goto fail;
385 	}
386 
387 	emac->rx_flow_id_base = k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn);
388 	netdev_dbg(ndev, "flow id base = %d\n", emac->rx_flow_id_base);
389 
390 	fdqring_id = K3_RINGACC_RING_ID_ANY;
391 	for (i = 0; i < rx_cfg.flow_id_num; i++) {
392 		struct k3_ring_cfg rxring_cfg = {
393 			.elm_size = K3_RINGACC_RING_ELSIZE_8,
394 			.mode = K3_RINGACC_RING_MODE_RING,
395 			.flags = 0,
396 		};
397 		struct k3_ring_cfg fdqring_cfg = {
398 			.elm_size = K3_RINGACC_RING_ELSIZE_8,
399 			.flags = K3_RINGACC_RING_SHARED,
400 		};
401 		struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = {
402 			.rx_cfg = rxring_cfg,
403 			.rxfdq_cfg = fdqring_cfg,
404 			.ring_rxq_id = K3_RINGACC_RING_ID_ANY,
405 			.src_tag_lo_sel =
406 				K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG,
407 		};
408 
409 		rx_flow_cfg.ring_rxfdq0_id = fdqring_id;
410 		rx_flow_cfg.rx_cfg.size = max_desc_num;
411 		rx_flow_cfg.rxfdq_cfg.size = max_desc_num;
412 		rx_flow_cfg.rxfdq_cfg.mode = emac->prueth->pdata.fdqring_mode;
413 
414 		ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn,
415 						i, &rx_flow_cfg);
416 		if (ret) {
417 			netdev_err(ndev, "Failed to init rx flow%d %d\n",
418 				   i, ret);
419 			goto fail;
420 		}
421 		if (!i)
422 			fdqring_id = k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn,
423 								     i);
424 		ret = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i);
425 		if (ret <= 0) {
426 			if (!ret)
427 				ret = -ENXIO;
428 			netdev_err(ndev, "Failed to get rx dma irq");
429 			goto fail;
430 		}
431 		rx_chn->irq[i] = ret;
432 	}
433 
434 	return 0;
435 
436 fail:
437 	prueth_cleanup_rx_chns(emac, rx_chn, max_rflows);
438 	return ret;
439 }
440 
441 static int prueth_dma_rx_push(struct prueth_emac *emac,
442 			      struct sk_buff *skb,
443 			      struct prueth_rx_chn *rx_chn)
444 {
445 	struct net_device *ndev = emac->ndev;
446 	struct cppi5_host_desc_t *desc_rx;
447 	u32 pkt_len = skb_tailroom(skb);
448 	dma_addr_t desc_dma;
449 	dma_addr_t buf_dma;
450 	void **swdata;
451 
452 	desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool);
453 	if (!desc_rx) {
454 		netdev_err(ndev, "rx push: failed to allocate descriptor\n");
455 		return -ENOMEM;
456 	}
457 	desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx);
458 
459 	buf_dma = dma_map_single(rx_chn->dma_dev, skb->data, pkt_len, DMA_FROM_DEVICE);
460 	if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) {
461 		k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx);
462 		netdev_err(ndev, "rx push: failed to map rx pkt buffer\n");
463 		return -EINVAL;
464 	}
465 
466 	cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT,
467 			 PRUETH_NAV_PS_DATA_SIZE);
468 	k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma);
469 	cppi5_hdesc_attach_buf(desc_rx, buf_dma, skb_tailroom(skb), buf_dma, skb_tailroom(skb));
470 
471 	swdata = cppi5_hdesc_get_swdata(desc_rx);
472 	*swdata = skb;
473 
474 	return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0,
475 					desc_rx, desc_dma);
476 }
477 
478 static u64 icssg_ts_to_ns(u32 hi_sw, u32 hi, u32 lo, u32 cycle_time_ns)
479 {
480 	u32 iepcount_lo, iepcount_hi, hi_rollover_count;
481 	u64 ns;
482 
483 	iepcount_lo = lo & GENMASK(19, 0);
484 	iepcount_hi = (hi & GENMASK(11, 0)) << 12 | lo >> 20;
485 	hi_rollover_count = hi >> 11;
486 
487 	ns = ((u64)hi_rollover_count) << 23 | (iepcount_hi + hi_sw);
488 	ns = ns * cycle_time_ns + iepcount_lo;
489 
490 	return ns;
491 }
492 
493 static void emac_rx_timestamp(struct prueth_emac *emac,
494 			      struct sk_buff *skb, u32 *psdata)
495 {
496 	struct skb_shared_hwtstamps *ssh;
497 	u64 ns;
498 
499 	u32 hi_sw = readl(emac->prueth->shram.va +
500 			  TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET);
501 	ns = icssg_ts_to_ns(hi_sw, psdata[1], psdata[0],
502 			    IEP_DEFAULT_CYCLE_TIME_NS);
503 
504 	ssh = skb_hwtstamps(skb);
505 	memset(ssh, 0, sizeof(*ssh));
506 	ssh->hwtstamp = ns_to_ktime(ns);
507 }
508 
509 static int emac_rx_packet(struct prueth_emac *emac, u32 flow_id)
510 {
511 	struct prueth_rx_chn *rx_chn = &emac->rx_chns;
512 	u32 buf_dma_len, pkt_len, port_id = 0;
513 	struct net_device *ndev = emac->ndev;
514 	struct cppi5_host_desc_t *desc_rx;
515 	struct sk_buff *skb, *new_skb;
516 	dma_addr_t desc_dma, buf_dma;
517 	void **swdata;
518 	u32 *psdata;
519 	int ret;
520 
521 	ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_id, &desc_dma);
522 	if (ret) {
523 		if (ret != -ENODATA)
524 			netdev_err(ndev, "rx pop: failed: %d\n", ret);
525 		return ret;
526 	}
527 
528 	if (cppi5_desc_is_tdcm(desc_dma)) /* Teardown ? */
529 		return 0;
530 
531 	desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma);
532 
533 	swdata = cppi5_hdesc_get_swdata(desc_rx);
534 	skb = *swdata;
535 
536 	psdata = cppi5_hdesc_get_psdata(desc_rx);
537 	/* RX HW timestamp */
538 	if (emac->rx_ts_enabled)
539 		emac_rx_timestamp(emac, skb, psdata);
540 
541 	cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len);
542 	k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma);
543 	pkt_len = cppi5_hdesc_get_pktlen(desc_rx);
544 	/* firmware adds 4 CRC bytes, strip them */
545 	pkt_len -= 4;
546 	cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL);
547 
548 	dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE);
549 	k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx);
550 
551 	skb->dev = ndev;
552 	new_skb = netdev_alloc_skb_ip_align(ndev, PRUETH_MAX_PKT_SIZE);
553 	/* if allocation fails we drop the packet but push the
554 	 * descriptor back to the ring with old skb to prevent a stall
555 	 */
556 	if (!new_skb) {
557 		ndev->stats.rx_dropped++;
558 		new_skb = skb;
559 	} else {
560 		/* send the filled skb up the n/w stack */
561 		skb_put(skb, pkt_len);
562 		skb->protocol = eth_type_trans(skb, ndev);
563 		napi_gro_receive(&emac->napi_rx, skb);
564 		ndev->stats.rx_bytes += pkt_len;
565 		ndev->stats.rx_packets++;
566 	}
567 
568 	/* queue another RX DMA */
569 	ret = prueth_dma_rx_push(emac, new_skb, &emac->rx_chns);
570 	if (WARN_ON(ret < 0)) {
571 		dev_kfree_skb_any(new_skb);
572 		ndev->stats.rx_errors++;
573 		ndev->stats.rx_dropped++;
574 	}
575 
576 	return ret;
577 }
578 
579 static void prueth_rx_cleanup(void *data, dma_addr_t desc_dma)
580 {
581 	struct prueth_rx_chn *rx_chn = data;
582 	struct cppi5_host_desc_t *desc_rx;
583 	struct sk_buff *skb;
584 	dma_addr_t buf_dma;
585 	u32 buf_dma_len;
586 	void **swdata;
587 
588 	desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma);
589 	swdata = cppi5_hdesc_get_swdata(desc_rx);
590 	skb = *swdata;
591 	cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len);
592 	k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma);
593 
594 	dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len,
595 			 DMA_FROM_DEVICE);
596 	k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx);
597 
598 	dev_kfree_skb_any(skb);
599 }
600 
601 static int emac_get_tx_ts(struct prueth_emac *emac,
602 			  struct emac_tx_ts_response *rsp)
603 {
604 	struct prueth *prueth = emac->prueth;
605 	int slice = prueth_emac_slice(emac);
606 	int addr;
607 
608 	addr = icssg_queue_pop(prueth, slice == 0 ?
609 			       ICSSG_TS_POP_SLICE0 : ICSSG_TS_POP_SLICE1);
610 	if (addr < 0)
611 		return addr;
612 
613 	memcpy_fromio(rsp, prueth->shram.va + addr, sizeof(*rsp));
614 	/* return buffer back for to pool */
615 	icssg_queue_push(prueth, slice == 0 ?
616 			 ICSSG_TS_PUSH_SLICE0 : ICSSG_TS_PUSH_SLICE1, addr);
617 
618 	return 0;
619 }
620 
621 static void tx_ts_work(struct prueth_emac *emac)
622 {
623 	struct skb_shared_hwtstamps ssh;
624 	struct emac_tx_ts_response tsr;
625 	struct sk_buff *skb;
626 	int ret = 0;
627 	u32 hi_sw;
628 	u64 ns;
629 
630 	/* There may be more than one pending requests */
631 	while (1) {
632 		ret = emac_get_tx_ts(emac, &tsr);
633 		if (ret) /* nothing more */
634 			break;
635 
636 		if (tsr.cookie >= PRUETH_MAX_TX_TS_REQUESTS ||
637 		    !emac->tx_ts_skb[tsr.cookie]) {
638 			netdev_err(emac->ndev, "Invalid TX TS cookie 0x%x\n",
639 				   tsr.cookie);
640 			break;
641 		}
642 
643 		skb = emac->tx_ts_skb[tsr.cookie];
644 		emac->tx_ts_skb[tsr.cookie] = NULL;	/* free slot */
645 		if (!skb) {
646 			netdev_err(emac->ndev, "Driver Bug! got NULL skb\n");
647 			break;
648 		}
649 
650 		hi_sw = readl(emac->prueth->shram.va +
651 			      TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET);
652 		ns = icssg_ts_to_ns(hi_sw, tsr.hi_ts, tsr.lo_ts,
653 				    IEP_DEFAULT_CYCLE_TIME_NS);
654 
655 		memset(&ssh, 0, sizeof(ssh));
656 		ssh.hwtstamp = ns_to_ktime(ns);
657 
658 		skb_tstamp_tx(skb, &ssh);
659 		dev_consume_skb_any(skb);
660 
661 		if (atomic_dec_and_test(&emac->tx_ts_pending))	/* no more? */
662 			break;
663 	}
664 }
665 
666 static int prueth_tx_ts_cookie_get(struct prueth_emac *emac)
667 {
668 	int i;
669 
670 	/* search and get the next free slot */
671 	for (i = 0; i < PRUETH_MAX_TX_TS_REQUESTS; i++) {
672 		if (!emac->tx_ts_skb[i]) {
673 			emac->tx_ts_skb[i] = ERR_PTR(-EBUSY); /* reserve slot */
674 			return i;
675 		}
676 	}
677 
678 	return -EBUSY;
679 }
680 
681 /**
682  * emac_ndo_start_xmit - EMAC Transmit function
683  * @skb: SKB pointer
684  * @ndev: EMAC network adapter
685  *
686  * Called by the system to transmit a packet  - we queue the packet in
687  * EMAC hardware transmit queue
688  * Doesn't wait for completion we'll check for TX completion in
689  * emac_tx_complete_packets().
690  *
691  * Return: enum netdev_tx
692  */
693 static enum netdev_tx emac_ndo_start_xmit(struct sk_buff *skb, struct net_device *ndev)
694 {
695 	struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc;
696 	struct prueth_emac *emac = netdev_priv(ndev);
697 	struct netdev_queue *netif_txq;
698 	struct prueth_tx_chn *tx_chn;
699 	dma_addr_t desc_dma, buf_dma;
700 	int i, ret = 0, q_idx;
701 	bool in_tx_ts = 0;
702 	int tx_ts_cookie;
703 	void **swdata;
704 	u32 pkt_len;
705 	u32 *epib;
706 
707 	pkt_len = skb_headlen(skb);
708 	q_idx = skb_get_queue_mapping(skb);
709 
710 	tx_chn = &emac->tx_chns[q_idx];
711 	netif_txq = netdev_get_tx_queue(ndev, q_idx);
712 
713 	/* Map the linear buffer */
714 	buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, DMA_TO_DEVICE);
715 	if (dma_mapping_error(tx_chn->dma_dev, buf_dma)) {
716 		netdev_err(ndev, "tx: failed to map skb buffer\n");
717 		ret = NETDEV_TX_OK;
718 		goto drop_free_skb;
719 	}
720 
721 	first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool);
722 	if (!first_desc) {
723 		netdev_dbg(ndev, "tx: failed to allocate descriptor\n");
724 		dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, DMA_TO_DEVICE);
725 		goto drop_stop_q_busy;
726 	}
727 
728 	cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT,
729 			 PRUETH_NAV_PS_DATA_SIZE);
730 	cppi5_hdesc_set_pkttype(first_desc, 0);
731 	epib = first_desc->epib;
732 	epib[0] = 0;
733 	epib[1] = 0;
734 	if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
735 	    emac->tx_ts_enabled) {
736 		tx_ts_cookie = prueth_tx_ts_cookie_get(emac);
737 		if (tx_ts_cookie >= 0) {
738 			skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
739 			/* Request TX timestamp */
740 			epib[0] = (u32)tx_ts_cookie;
741 			epib[1] = 0x80000000;	/* TX TS request */
742 			emac->tx_ts_skb[tx_ts_cookie] = skb_get(skb);
743 			in_tx_ts = 1;
744 		}
745 	}
746 
747 	/* set dst tag to indicate internal qid at the firmware which is at
748 	 * bit8..bit15. bit0..bit7 indicates port num for directed
749 	 * packets in case of switch mode operation
750 	 */
751 	cppi5_desc_set_tags_ids(&first_desc->hdr, 0, (emac->port_id | (q_idx << 8)));
752 	k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma);
753 	cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len);
754 	swdata = cppi5_hdesc_get_swdata(first_desc);
755 	*swdata = skb;
756 
757 	/* Handle the case where skb is fragmented in pages */
758 	cur_desc = first_desc;
759 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
760 		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
761 		u32 frag_size = skb_frag_size(frag);
762 
763 		next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool);
764 		if (!next_desc) {
765 			netdev_err(ndev,
766 				   "tx: failed to allocate frag. descriptor\n");
767 			goto free_desc_stop_q_busy_cleanup_tx_ts;
768 		}
769 
770 		buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size,
771 					   DMA_TO_DEVICE);
772 		if (dma_mapping_error(tx_chn->dma_dev, buf_dma)) {
773 			netdev_err(ndev, "tx: Failed to map skb page\n");
774 			k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc);
775 			ret = NETDEV_TX_OK;
776 			goto cleanup_tx_ts;
777 		}
778 
779 		cppi5_hdesc_reset_hbdesc(next_desc);
780 		k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma);
781 		cppi5_hdesc_attach_buf(next_desc,
782 				       buf_dma, frag_size, buf_dma, frag_size);
783 
784 		desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool,
785 						      next_desc);
786 		k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma);
787 		cppi5_hdesc_link_hbdesc(cur_desc, desc_dma);
788 
789 		pkt_len += frag_size;
790 		cur_desc = next_desc;
791 	}
792 	WARN_ON_ONCE(pkt_len != skb->len);
793 
794 	/* report bql before sending packet */
795 	netdev_tx_sent_queue(netif_txq, pkt_len);
796 
797 	cppi5_hdesc_set_pktlen(first_desc, pkt_len);
798 	desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc);
799 	/* cppi5_desc_dump(first_desc, 64); */
800 
801 	skb_tx_timestamp(skb);  /* SW timestamp if SKBTX_IN_PROGRESS not set */
802 	ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma);
803 	if (ret) {
804 		netdev_err(ndev, "tx: push failed: %d\n", ret);
805 		goto drop_free_descs;
806 	}
807 
808 	if (in_tx_ts)
809 		atomic_inc(&emac->tx_ts_pending);
810 
811 	if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) {
812 		netif_tx_stop_queue(netif_txq);
813 		/* Barrier, so that stop_queue visible to other cpus */
814 		smp_mb__after_atomic();
815 
816 		if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >=
817 		    MAX_SKB_FRAGS)
818 			netif_tx_wake_queue(netif_txq);
819 	}
820 
821 	return NETDEV_TX_OK;
822 
823 cleanup_tx_ts:
824 	if (in_tx_ts) {
825 		dev_kfree_skb_any(emac->tx_ts_skb[tx_ts_cookie]);
826 		emac->tx_ts_skb[tx_ts_cookie] = NULL;
827 	}
828 
829 drop_free_descs:
830 	prueth_xmit_free(tx_chn, first_desc);
831 
832 drop_free_skb:
833 	dev_kfree_skb_any(skb);
834 
835 	/* error */
836 	ndev->stats.tx_dropped++;
837 	netdev_err(ndev, "tx: error: %d\n", ret);
838 
839 	return ret;
840 
841 free_desc_stop_q_busy_cleanup_tx_ts:
842 	if (in_tx_ts) {
843 		dev_kfree_skb_any(emac->tx_ts_skb[tx_ts_cookie]);
844 		emac->tx_ts_skb[tx_ts_cookie] = NULL;
845 	}
846 	prueth_xmit_free(tx_chn, first_desc);
847 
848 drop_stop_q_busy:
849 	netif_tx_stop_queue(netif_txq);
850 	return NETDEV_TX_BUSY;
851 }
852 
853 static void prueth_tx_cleanup(void *data, dma_addr_t desc_dma)
854 {
855 	struct prueth_tx_chn *tx_chn = data;
856 	struct cppi5_host_desc_t *desc_tx;
857 	struct sk_buff *skb;
858 	void **swdata;
859 
860 	desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma);
861 	swdata = cppi5_hdesc_get_swdata(desc_tx);
862 	skb = *(swdata);
863 	prueth_xmit_free(tx_chn, desc_tx);
864 
865 	dev_kfree_skb_any(skb);
866 }
867 
868 static irqreturn_t prueth_tx_ts_irq(int irq, void *dev_id)
869 {
870 	struct prueth_emac *emac = dev_id;
871 
872 	/* currently only TX timestamp is being returned */
873 	tx_ts_work(emac);
874 
875 	return IRQ_HANDLED;
876 }
877 
878 static irqreturn_t prueth_rx_irq(int irq, void *dev_id)
879 {
880 	struct prueth_emac *emac = dev_id;
881 
882 	disable_irq_nosync(irq);
883 	napi_schedule(&emac->napi_rx);
884 
885 	return IRQ_HANDLED;
886 }
887 
888 struct icssg_firmwares {
889 	char *pru;
890 	char *rtu;
891 	char *txpru;
892 };
893 
894 static struct icssg_firmwares icssg_emac_firmwares[] = {
895 	{
896 		.pru = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
897 		.rtu = "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
898 		.txpru = "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
899 	},
900 	{
901 		.pru = "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
902 		.rtu = "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
903 		.txpru = "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf",
904 	}
905 };
906 
907 static int prueth_emac_start(struct prueth *prueth, struct prueth_emac *emac)
908 {
909 	struct icssg_firmwares *firmwares;
910 	struct device *dev = prueth->dev;
911 	int slice, ret;
912 
913 	firmwares = icssg_emac_firmwares;
914 
915 	slice = prueth_emac_slice(emac);
916 	if (slice < 0) {
917 		netdev_err(emac->ndev, "invalid port\n");
918 		return -EINVAL;
919 	}
920 
921 	ret = icssg_config(prueth, emac, slice);
922 	if (ret)
923 		return ret;
924 
925 	ret = rproc_set_firmware(prueth->pru[slice], firmwares[slice].pru);
926 	ret = rproc_boot(prueth->pru[slice]);
927 	if (ret) {
928 		dev_err(dev, "failed to boot PRU%d: %d\n", slice, ret);
929 		return -EINVAL;
930 	}
931 
932 	ret = rproc_set_firmware(prueth->rtu[slice], firmwares[slice].rtu);
933 	ret = rproc_boot(prueth->rtu[slice]);
934 	if (ret) {
935 		dev_err(dev, "failed to boot RTU%d: %d\n", slice, ret);
936 		goto halt_pru;
937 	}
938 
939 	ret = rproc_set_firmware(prueth->txpru[slice], firmwares[slice].txpru);
940 	ret = rproc_boot(prueth->txpru[slice]);
941 	if (ret) {
942 		dev_err(dev, "failed to boot TX_PRU%d: %d\n", slice, ret);
943 		goto halt_rtu;
944 	}
945 
946 	emac->fw_running = 1;
947 	return 0;
948 
949 halt_rtu:
950 	rproc_shutdown(prueth->rtu[slice]);
951 
952 halt_pru:
953 	rproc_shutdown(prueth->pru[slice]);
954 
955 	return ret;
956 }
957 
958 static void prueth_emac_stop(struct prueth_emac *emac)
959 {
960 	struct prueth *prueth = emac->prueth;
961 	int slice;
962 
963 	switch (emac->port_id) {
964 	case PRUETH_PORT_MII0:
965 		slice = ICSS_SLICE0;
966 		break;
967 	case PRUETH_PORT_MII1:
968 		slice = ICSS_SLICE1;
969 		break;
970 	default:
971 		netdev_err(emac->ndev, "invalid port\n");
972 		return;
973 	}
974 
975 	emac->fw_running = 0;
976 	rproc_shutdown(prueth->txpru[slice]);
977 	rproc_shutdown(prueth->rtu[slice]);
978 	rproc_shutdown(prueth->pru[slice]);
979 }
980 
981 static void prueth_cleanup_tx_ts(struct prueth_emac *emac)
982 {
983 	int i;
984 
985 	for (i = 0; i < PRUETH_MAX_TX_TS_REQUESTS; i++) {
986 		if (emac->tx_ts_skb[i]) {
987 			dev_kfree_skb_any(emac->tx_ts_skb[i]);
988 			emac->tx_ts_skb[i] = NULL;
989 		}
990 	}
991 }
992 
993 /* called back by PHY layer if there is change in link state of hw port*/
994 static void emac_adjust_link(struct net_device *ndev)
995 {
996 	struct prueth_emac *emac = netdev_priv(ndev);
997 	struct phy_device *phydev = ndev->phydev;
998 	struct prueth *prueth = emac->prueth;
999 	bool new_state = false;
1000 	unsigned long flags;
1001 
1002 	if (phydev->link) {
1003 		/* check the mode of operation - full/half duplex */
1004 		if (phydev->duplex != emac->duplex) {
1005 			new_state = true;
1006 			emac->duplex = phydev->duplex;
1007 		}
1008 		if (phydev->speed != emac->speed) {
1009 			new_state = true;
1010 			emac->speed = phydev->speed;
1011 		}
1012 		if (!emac->link) {
1013 			new_state = true;
1014 			emac->link = 1;
1015 		}
1016 	} else if (emac->link) {
1017 		new_state = true;
1018 		emac->link = 0;
1019 
1020 		/* f/w should support 100 & 1000 */
1021 		emac->speed = SPEED_1000;
1022 
1023 		/* half duplex may not be supported by f/w */
1024 		emac->duplex = DUPLEX_FULL;
1025 	}
1026 
1027 	if (new_state) {
1028 		phy_print_status(phydev);
1029 
1030 		/* update RGMII and MII configuration based on PHY negotiated
1031 		 * values
1032 		 */
1033 		if (emac->link) {
1034 			/* Set the RGMII cfg for gig en and full duplex */
1035 			icssg_update_rgmii_cfg(prueth->miig_rt, emac);
1036 
1037 			/* update the Tx IPG based on 100M/1G speed */
1038 			spin_lock_irqsave(&emac->lock, flags);
1039 			icssg_config_ipg(emac);
1040 			spin_unlock_irqrestore(&emac->lock, flags);
1041 			icssg_config_set_speed(emac);
1042 			emac_set_port_state(emac, ICSSG_EMAC_PORT_FORWARD);
1043 
1044 		} else {
1045 			emac_set_port_state(emac, ICSSG_EMAC_PORT_DISABLE);
1046 		}
1047 	}
1048 
1049 	if (emac->link) {
1050 		/* reactivate the transmit queue */
1051 		netif_tx_wake_all_queues(ndev);
1052 	} else {
1053 		netif_tx_stop_all_queues(ndev);
1054 		prueth_cleanup_tx_ts(emac);
1055 	}
1056 }
1057 
1058 static int emac_napi_rx_poll(struct napi_struct *napi_rx, int budget)
1059 {
1060 	struct prueth_emac *emac = prueth_napi_to_emac(napi_rx);
1061 	int rx_flow = PRUETH_RX_FLOW_DATA;
1062 	int flow = PRUETH_MAX_RX_FLOWS;
1063 	int num_rx = 0;
1064 	int cur_budget;
1065 	int ret;
1066 
1067 	while (flow--) {
1068 		cur_budget = budget - num_rx;
1069 
1070 		while (cur_budget--) {
1071 			ret = emac_rx_packet(emac, flow);
1072 			if (ret)
1073 				break;
1074 			num_rx++;
1075 		}
1076 
1077 		if (num_rx >= budget)
1078 			break;
1079 	}
1080 
1081 	if (num_rx < budget && napi_complete_done(napi_rx, num_rx))
1082 		enable_irq(emac->rx_chns.irq[rx_flow]);
1083 
1084 	return num_rx;
1085 }
1086 
1087 static int prueth_prepare_rx_chan(struct prueth_emac *emac,
1088 				  struct prueth_rx_chn *chn,
1089 				  int buf_size)
1090 {
1091 	struct sk_buff *skb;
1092 	int i, ret;
1093 
1094 	for (i = 0; i < chn->descs_num; i++) {
1095 		skb = __netdev_alloc_skb_ip_align(NULL, buf_size, GFP_KERNEL);
1096 		if (!skb)
1097 			return -ENOMEM;
1098 
1099 		ret = prueth_dma_rx_push(emac, skb, chn);
1100 		if (ret < 0) {
1101 			netdev_err(emac->ndev,
1102 				   "cannot submit skb for rx chan %s ret %d\n",
1103 				   chn->name, ret);
1104 			kfree_skb(skb);
1105 			return ret;
1106 		}
1107 	}
1108 
1109 	return 0;
1110 }
1111 
1112 static void prueth_reset_tx_chan(struct prueth_emac *emac, int ch_num,
1113 				 bool free_skb)
1114 {
1115 	int i;
1116 
1117 	for (i = 0; i < ch_num; i++) {
1118 		if (free_skb)
1119 			k3_udma_glue_reset_tx_chn(emac->tx_chns[i].tx_chn,
1120 						  &emac->tx_chns[i],
1121 						  prueth_tx_cleanup);
1122 		k3_udma_glue_disable_tx_chn(emac->tx_chns[i].tx_chn);
1123 	}
1124 }
1125 
1126 static void prueth_reset_rx_chan(struct prueth_rx_chn *chn,
1127 				 int num_flows, bool disable)
1128 {
1129 	int i;
1130 
1131 	for (i = 0; i < num_flows; i++)
1132 		k3_udma_glue_reset_rx_chn(chn->rx_chn, i, chn,
1133 					  prueth_rx_cleanup, !!i);
1134 	if (disable)
1135 		k3_udma_glue_disable_rx_chn(chn->rx_chn);
1136 }
1137 
1138 static int emac_phy_connect(struct prueth_emac *emac)
1139 {
1140 	struct prueth *prueth = emac->prueth;
1141 	struct net_device *ndev = emac->ndev;
1142 	/* connect PHY */
1143 	ndev->phydev = of_phy_connect(emac->ndev, emac->phy_node,
1144 				      &emac_adjust_link, 0,
1145 				      emac->phy_if);
1146 	if (!ndev->phydev) {
1147 		dev_err(prueth->dev, "couldn't connect to phy %s\n",
1148 			emac->phy_node->full_name);
1149 		return -ENODEV;
1150 	}
1151 
1152 	/* remove unsupported modes */
1153 	phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
1154 	phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
1155 	phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1156 	phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_Pause_BIT);
1157 	phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT);
1158 
1159 	if (emac->phy_if == PHY_INTERFACE_MODE_MII)
1160 		phy_set_max_speed(ndev->phydev, SPEED_100);
1161 
1162 	return 0;
1163 }
1164 
1165 static u64 prueth_iep_gettime(void *clockops_data, struct ptp_system_timestamp *sts)
1166 {
1167 	u32 hi_rollover_count, hi_rollover_count_r;
1168 	struct prueth_emac *emac = clockops_data;
1169 	struct prueth *prueth = emac->prueth;
1170 	void __iomem *fw_hi_r_count_addr;
1171 	void __iomem *fw_count_hi_addr;
1172 	u32 iepcount_hi, iepcount_hi_r;
1173 	unsigned long flags;
1174 	u32 iepcount_lo;
1175 	u64 ts = 0;
1176 
1177 	fw_count_hi_addr = prueth->shram.va + TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET;
1178 	fw_hi_r_count_addr = prueth->shram.va + TIMESYNC_FW_WC_HI_ROLLOVER_COUNT_OFFSET;
1179 
1180 	local_irq_save(flags);
1181 	do {
1182 		iepcount_hi = icss_iep_get_count_hi(emac->iep);
1183 		iepcount_hi += readl(fw_count_hi_addr);
1184 		hi_rollover_count = readl(fw_hi_r_count_addr);
1185 		ptp_read_system_prets(sts);
1186 		iepcount_lo = icss_iep_get_count_low(emac->iep);
1187 		ptp_read_system_postts(sts);
1188 
1189 		iepcount_hi_r = icss_iep_get_count_hi(emac->iep);
1190 		iepcount_hi_r += readl(fw_count_hi_addr);
1191 		hi_rollover_count_r = readl(fw_hi_r_count_addr);
1192 	} while ((iepcount_hi_r != iepcount_hi) ||
1193 		 (hi_rollover_count != hi_rollover_count_r));
1194 	local_irq_restore(flags);
1195 
1196 	ts = ((u64)hi_rollover_count) << 23 | iepcount_hi;
1197 	ts = ts * (u64)IEP_DEFAULT_CYCLE_TIME_NS + iepcount_lo;
1198 
1199 	return ts;
1200 }
1201 
1202 static void prueth_iep_settime(void *clockops_data, u64 ns)
1203 {
1204 	struct icssg_setclock_desc __iomem *sc_descp;
1205 	struct prueth_emac *emac = clockops_data;
1206 	struct icssg_setclock_desc sc_desc;
1207 	u64 cyclecount;
1208 	u32 cycletime;
1209 	int timeout;
1210 
1211 	if (!emac->fw_running)
1212 		return;
1213 
1214 	sc_descp = emac->prueth->shram.va + TIMESYNC_FW_WC_SETCLOCK_DESC_OFFSET;
1215 
1216 	cycletime = IEP_DEFAULT_CYCLE_TIME_NS;
1217 	cyclecount = ns / cycletime;
1218 
1219 	memset(&sc_desc, 0, sizeof(sc_desc));
1220 	sc_desc.margin = cycletime - 1000;
1221 	sc_desc.cyclecounter0_set = cyclecount & GENMASK(31, 0);
1222 	sc_desc.cyclecounter1_set = (cyclecount & GENMASK(63, 32)) >> 32;
1223 	sc_desc.iepcount_set = ns % cycletime;
1224 	sc_desc.CMP0_current = cycletime - 4; //Count from 0 to (cycle time)-4
1225 
1226 	memcpy_toio(sc_descp, &sc_desc, sizeof(sc_desc));
1227 
1228 	writeb(1, &sc_descp->request);
1229 
1230 	timeout = 5;	/* fw should take 2-3 ms */
1231 	while (timeout--) {
1232 		if (readb(&sc_descp->acknowledgment))
1233 			return;
1234 
1235 		usleep_range(500, 1000);
1236 	}
1237 
1238 	dev_err(emac->prueth->dev, "settime timeout\n");
1239 }
1240 
1241 static int prueth_perout_enable(void *clockops_data,
1242 				struct ptp_perout_request *req, int on,
1243 				u64 *cmp)
1244 {
1245 	struct prueth_emac *emac = clockops_data;
1246 	u32 reduction_factor = 0, offset = 0;
1247 	struct timespec64 ts;
1248 	u64 ns_period;
1249 
1250 	if (!on)
1251 		return 0;
1252 
1253 	/* Any firmware specific stuff for PPS/PEROUT handling */
1254 	ts.tv_sec = req->period.sec;
1255 	ts.tv_nsec = req->period.nsec;
1256 	ns_period = timespec64_to_ns(&ts);
1257 
1258 	/* f/w doesn't support period less than cycle time */
1259 	if (ns_period < IEP_DEFAULT_CYCLE_TIME_NS)
1260 		return -ENXIO;
1261 
1262 	reduction_factor = ns_period / IEP_DEFAULT_CYCLE_TIME_NS;
1263 	offset = ns_period % IEP_DEFAULT_CYCLE_TIME_NS;
1264 
1265 	/* f/w requires at least 1uS within a cycle so CMP
1266 	 * can trigger after SYNC is enabled
1267 	 */
1268 	if (offset < 5 * NSEC_PER_USEC)
1269 		offset = 5 * NSEC_PER_USEC;
1270 
1271 	/* if offset is close to cycle time then we will miss
1272 	 * the CMP event for last tick when IEP rolls over.
1273 	 * In normal mode, IEP tick is 4ns.
1274 	 * In slow compensation it could be 0ns or 8ns at
1275 	 * every slow compensation cycle.
1276 	 */
1277 	if (offset > IEP_DEFAULT_CYCLE_TIME_NS - 8)
1278 		offset = IEP_DEFAULT_CYCLE_TIME_NS - 8;
1279 
1280 	/* we're in shadow mode so need to set upper 32-bits */
1281 	*cmp = (u64)offset << 32;
1282 
1283 	writel(reduction_factor, emac->prueth->shram.va +
1284 		TIMESYNC_FW_WC_SYNCOUT_REDUCTION_FACTOR_OFFSET);
1285 
1286 	writel(0, emac->prueth->shram.va +
1287 		TIMESYNC_FW_WC_SYNCOUT_START_TIME_CYCLECOUNT_OFFSET);
1288 
1289 	return 0;
1290 }
1291 
1292 const struct icss_iep_clockops prueth_iep_clockops = {
1293 	.settime = prueth_iep_settime,
1294 	.gettime = prueth_iep_gettime,
1295 	.perout_enable = prueth_perout_enable,
1296 };
1297 
1298 /**
1299  * emac_ndo_open - EMAC device open
1300  * @ndev: network adapter device
1301  *
1302  * Called when system wants to start the interface.
1303  *
1304  * Return: 0 for a successful open, or appropriate error code
1305  */
1306 static int emac_ndo_open(struct net_device *ndev)
1307 {
1308 	struct prueth_emac *emac = netdev_priv(ndev);
1309 	int ret, i, num_data_chn = emac->tx_ch_num;
1310 	struct prueth *prueth = emac->prueth;
1311 	int slice = prueth_emac_slice(emac);
1312 	struct device *dev = prueth->dev;
1313 	int max_rx_flows;
1314 	int rx_flow;
1315 
1316 	/* clear SMEM and MSMC settings for all slices */
1317 	if (!prueth->emacs_initialized) {
1318 		memset_io(prueth->msmcram.va, 0, prueth->msmcram.size);
1319 		memset_io(prueth->shram.va, 0, ICSSG_CONFIG_OFFSET_SLICE1 * PRUETH_NUM_MACS);
1320 	}
1321 
1322 	/* set h/w MAC as user might have re-configured */
1323 	ether_addr_copy(emac->mac_addr, ndev->dev_addr);
1324 
1325 	icssg_class_set_mac_addr(prueth->miig_rt, slice, emac->mac_addr);
1326 	icssg_ft1_set_mac_addr(prueth->miig_rt, slice, emac->mac_addr);
1327 
1328 	icssg_class_default(prueth->miig_rt, slice, 0);
1329 
1330 	/* Notify the stack of the actual queue counts. */
1331 	ret = netif_set_real_num_tx_queues(ndev, num_data_chn);
1332 	if (ret) {
1333 		dev_err(dev, "cannot set real number of tx queues\n");
1334 		return ret;
1335 	}
1336 
1337 	init_completion(&emac->cmd_complete);
1338 	ret = prueth_init_tx_chns(emac);
1339 	if (ret) {
1340 		dev_err(dev, "failed to init tx channel: %d\n", ret);
1341 		return ret;
1342 	}
1343 
1344 	max_rx_flows = PRUETH_MAX_RX_FLOWS;
1345 	ret = prueth_init_rx_chns(emac, &emac->rx_chns, "rx",
1346 				  max_rx_flows, PRUETH_MAX_RX_DESC);
1347 	if (ret) {
1348 		dev_err(dev, "failed to init rx channel: %d\n", ret);
1349 		goto cleanup_tx;
1350 	}
1351 
1352 	ret = prueth_ndev_add_tx_napi(emac);
1353 	if (ret)
1354 		goto cleanup_rx;
1355 
1356 	/* we use only the highest priority flow for now i.e. @irq[3] */
1357 	rx_flow = PRUETH_RX_FLOW_DATA;
1358 	ret = request_irq(emac->rx_chns.irq[rx_flow], prueth_rx_irq,
1359 			  IRQF_TRIGGER_HIGH, dev_name(dev), emac);
1360 	if (ret) {
1361 		dev_err(dev, "unable to request RX IRQ\n");
1362 		goto cleanup_napi;
1363 	}
1364 
1365 	/* reset and start PRU firmware */
1366 	ret = prueth_emac_start(prueth, emac);
1367 	if (ret)
1368 		goto free_rx_irq;
1369 
1370 	icssg_mii_update_mtu(prueth->mii_rt, slice, ndev->max_mtu);
1371 
1372 	if (!prueth->emacs_initialized) {
1373 		ret = icss_iep_init(emac->iep, &prueth_iep_clockops,
1374 				    emac, IEP_DEFAULT_CYCLE_TIME_NS);
1375 	}
1376 
1377 	ret = request_threaded_irq(emac->tx_ts_irq, NULL, prueth_tx_ts_irq,
1378 				   IRQF_ONESHOT, dev_name(dev), emac);
1379 	if (ret)
1380 		goto stop;
1381 
1382 	/* Prepare RX */
1383 	ret = prueth_prepare_rx_chan(emac, &emac->rx_chns, PRUETH_MAX_PKT_SIZE);
1384 	if (ret)
1385 		goto free_tx_ts_irq;
1386 
1387 	ret = k3_udma_glue_enable_rx_chn(emac->rx_chns.rx_chn);
1388 	if (ret)
1389 		goto reset_rx_chn;
1390 
1391 	for (i = 0; i < emac->tx_ch_num; i++) {
1392 		ret = k3_udma_glue_enable_tx_chn(emac->tx_chns[i].tx_chn);
1393 		if (ret)
1394 			goto reset_tx_chan;
1395 	}
1396 
1397 	/* Enable NAPI in Tx and Rx direction */
1398 	for (i = 0; i < emac->tx_ch_num; i++)
1399 		napi_enable(&emac->tx_chns[i].napi_tx);
1400 	napi_enable(&emac->napi_rx);
1401 
1402 	/* start PHY */
1403 	phy_start(ndev->phydev);
1404 
1405 	prueth->emacs_initialized++;
1406 
1407 	queue_work(system_long_wq, &emac->stats_work.work);
1408 
1409 	return 0;
1410 
1411 reset_tx_chan:
1412 	/* Since interface is not yet up, there is wouldn't be
1413 	 * any SKB for completion. So set false to free_skb
1414 	 */
1415 	prueth_reset_tx_chan(emac, i, false);
1416 reset_rx_chn:
1417 	prueth_reset_rx_chan(&emac->rx_chns, max_rx_flows, false);
1418 free_tx_ts_irq:
1419 	free_irq(emac->tx_ts_irq, emac);
1420 stop:
1421 	prueth_emac_stop(emac);
1422 free_rx_irq:
1423 	free_irq(emac->rx_chns.irq[rx_flow], emac);
1424 cleanup_napi:
1425 	prueth_ndev_del_tx_napi(emac, emac->tx_ch_num);
1426 cleanup_rx:
1427 	prueth_cleanup_rx_chns(emac, &emac->rx_chns, max_rx_flows);
1428 cleanup_tx:
1429 	prueth_cleanup_tx_chns(emac);
1430 
1431 	return ret;
1432 }
1433 
1434 /**
1435  * emac_ndo_stop - EMAC device stop
1436  * @ndev: network adapter device
1437  *
1438  * Called when system wants to stop or down the interface.
1439  *
1440  * Return: Always 0 (Success)
1441  */
1442 static int emac_ndo_stop(struct net_device *ndev)
1443 {
1444 	struct prueth_emac *emac = netdev_priv(ndev);
1445 	struct prueth *prueth = emac->prueth;
1446 	int rx_flow = PRUETH_RX_FLOW_DATA;
1447 	int max_rx_flows;
1448 	int ret, i;
1449 
1450 	/* inform the upper layers. */
1451 	netif_tx_stop_all_queues(ndev);
1452 
1453 	/* block packets from wire */
1454 	if (ndev->phydev)
1455 		phy_stop(ndev->phydev);
1456 
1457 	icssg_class_disable(prueth->miig_rt, prueth_emac_slice(emac));
1458 
1459 	atomic_set(&emac->tdown_cnt, emac->tx_ch_num);
1460 	/* ensure new tdown_cnt value is visible */
1461 	smp_mb__after_atomic();
1462 	/* tear down and disable UDMA channels */
1463 	reinit_completion(&emac->tdown_complete);
1464 	for (i = 0; i < emac->tx_ch_num; i++)
1465 		k3_udma_glue_tdown_tx_chn(emac->tx_chns[i].tx_chn, false);
1466 
1467 	ret = wait_for_completion_timeout(&emac->tdown_complete,
1468 					  msecs_to_jiffies(1000));
1469 	if (!ret)
1470 		netdev_err(ndev, "tx teardown timeout\n");
1471 
1472 	prueth_reset_tx_chan(emac, emac->tx_ch_num, true);
1473 	for (i = 0; i < emac->tx_ch_num; i++)
1474 		napi_disable(&emac->tx_chns[i].napi_tx);
1475 
1476 	max_rx_flows = PRUETH_MAX_RX_FLOWS;
1477 	k3_udma_glue_tdown_rx_chn(emac->rx_chns.rx_chn, true);
1478 
1479 	prueth_reset_rx_chan(&emac->rx_chns, max_rx_flows, true);
1480 
1481 	napi_disable(&emac->napi_rx);
1482 
1483 	cancel_work_sync(&emac->rx_mode_work);
1484 
1485 	/* Destroying the queued work in ndo_stop() */
1486 	cancel_delayed_work_sync(&emac->stats_work);
1487 
1488 	/* stop PRUs */
1489 	prueth_emac_stop(emac);
1490 
1491 	if (prueth->emacs_initialized == 1)
1492 		icss_iep_exit(emac->iep);
1493 
1494 	/* stop PRUs */
1495 	prueth_emac_stop(emac);
1496 
1497 	free_irq(emac->tx_ts_irq, emac);
1498 
1499 	free_irq(emac->rx_chns.irq[rx_flow], emac);
1500 	prueth_ndev_del_tx_napi(emac, emac->tx_ch_num);
1501 	prueth_cleanup_tx_chns(emac);
1502 
1503 	prueth_cleanup_rx_chns(emac, &emac->rx_chns, max_rx_flows);
1504 	prueth_cleanup_tx_chns(emac);
1505 
1506 	prueth->emacs_initialized--;
1507 
1508 	return 0;
1509 }
1510 
1511 static void emac_ndo_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1512 {
1513 	ndev->stats.tx_errors++;
1514 }
1515 
1516 static void emac_ndo_set_rx_mode_work(struct work_struct *work)
1517 {
1518 	struct prueth_emac *emac = container_of(work, struct prueth_emac, rx_mode_work);
1519 	struct net_device *ndev = emac->ndev;
1520 	bool promisc, allmulti;
1521 
1522 	if (!netif_running(ndev))
1523 		return;
1524 
1525 	promisc = ndev->flags & IFF_PROMISC;
1526 	allmulti = ndev->flags & IFF_ALLMULTI;
1527 	emac_set_port_state(emac, ICSSG_EMAC_PORT_UC_FLOODING_DISABLE);
1528 	emac_set_port_state(emac, ICSSG_EMAC_PORT_MC_FLOODING_DISABLE);
1529 
1530 	if (promisc) {
1531 		emac_set_port_state(emac, ICSSG_EMAC_PORT_UC_FLOODING_ENABLE);
1532 		emac_set_port_state(emac, ICSSG_EMAC_PORT_MC_FLOODING_ENABLE);
1533 		return;
1534 	}
1535 
1536 	if (allmulti) {
1537 		emac_set_port_state(emac, ICSSG_EMAC_PORT_MC_FLOODING_ENABLE);
1538 		return;
1539 	}
1540 
1541 	if (!netdev_mc_empty(ndev)) {
1542 		emac_set_port_state(emac, ICSSG_EMAC_PORT_MC_FLOODING_ENABLE);
1543 		return;
1544 	}
1545 }
1546 
1547 /**
1548  * emac_ndo_set_rx_mode - EMAC set receive mode function
1549  * @ndev: The EMAC network adapter
1550  *
1551  * Called when system wants to set the receive mode of the device.
1552  *
1553  */
1554 static void emac_ndo_set_rx_mode(struct net_device *ndev)
1555 {
1556 	struct prueth_emac *emac = netdev_priv(ndev);
1557 
1558 	queue_work(emac->cmd_wq, &emac->rx_mode_work);
1559 }
1560 
1561 static int emac_set_ts_config(struct net_device *ndev, struct ifreq *ifr)
1562 {
1563 	struct prueth_emac *emac = netdev_priv(ndev);
1564 	struct hwtstamp_config config;
1565 
1566 	if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1567 		return -EFAULT;
1568 
1569 	switch (config.tx_type) {
1570 	case HWTSTAMP_TX_OFF:
1571 		emac->tx_ts_enabled = 0;
1572 		break;
1573 	case HWTSTAMP_TX_ON:
1574 		emac->tx_ts_enabled = 1;
1575 		break;
1576 	default:
1577 		return -ERANGE;
1578 	}
1579 
1580 	switch (config.rx_filter) {
1581 	case HWTSTAMP_FILTER_NONE:
1582 		emac->rx_ts_enabled = 0;
1583 		break;
1584 	case HWTSTAMP_FILTER_ALL:
1585 	case HWTSTAMP_FILTER_SOME:
1586 	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1587 	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1588 	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1589 	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1590 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1591 	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1592 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1593 	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1594 	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1595 	case HWTSTAMP_FILTER_PTP_V2_EVENT:
1596 	case HWTSTAMP_FILTER_PTP_V2_SYNC:
1597 	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1598 	case HWTSTAMP_FILTER_NTP_ALL:
1599 		emac->rx_ts_enabled = 1;
1600 		config.rx_filter = HWTSTAMP_FILTER_ALL;
1601 		break;
1602 	default:
1603 		return -ERANGE;
1604 	}
1605 
1606 	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1607 		-EFAULT : 0;
1608 }
1609 
1610 static int emac_get_ts_config(struct net_device *ndev, struct ifreq *ifr)
1611 {
1612 	struct prueth_emac *emac = netdev_priv(ndev);
1613 	struct hwtstamp_config config;
1614 
1615 	config.flags = 0;
1616 	config.tx_type = emac->tx_ts_enabled ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1617 	config.rx_filter = emac->rx_ts_enabled ? HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE;
1618 
1619 	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1620 			    -EFAULT : 0;
1621 }
1622 
1623 static int emac_ndo_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
1624 {
1625 	switch (cmd) {
1626 	case SIOCGHWTSTAMP:
1627 		return emac_get_ts_config(ndev, ifr);
1628 	case SIOCSHWTSTAMP:
1629 		return emac_set_ts_config(ndev, ifr);
1630 	default:
1631 		break;
1632 	}
1633 
1634 	return phy_do_ioctl(ndev, ifr, cmd);
1635 }
1636 
1637 static void emac_ndo_get_stats64(struct net_device *ndev,
1638 				 struct rtnl_link_stats64 *stats)
1639 {
1640 	struct prueth_emac *emac = netdev_priv(ndev);
1641 
1642 	emac_update_hardware_stats(emac);
1643 
1644 	stats->rx_packets     = emac_get_stat_by_name(emac, "rx_packets");
1645 	stats->rx_bytes       = emac_get_stat_by_name(emac, "rx_bytes");
1646 	stats->tx_packets     = emac_get_stat_by_name(emac, "tx_packets");
1647 	stats->tx_bytes       = emac_get_stat_by_name(emac, "tx_bytes");
1648 	stats->rx_crc_errors  = emac_get_stat_by_name(emac, "rx_crc_errors");
1649 	stats->rx_over_errors = emac_get_stat_by_name(emac, "rx_over_errors");
1650 	stats->multicast      = emac_get_stat_by_name(emac, "rx_multicast_frames");
1651 
1652 	stats->rx_errors  = ndev->stats.rx_errors;
1653 	stats->rx_dropped = ndev->stats.rx_dropped;
1654 	stats->tx_errors  = ndev->stats.tx_errors;
1655 	stats->tx_dropped = ndev->stats.tx_dropped;
1656 }
1657 
1658 static const struct net_device_ops emac_netdev_ops = {
1659 	.ndo_open = emac_ndo_open,
1660 	.ndo_stop = emac_ndo_stop,
1661 	.ndo_start_xmit = emac_ndo_start_xmit,
1662 	.ndo_set_mac_address = eth_mac_addr,
1663 	.ndo_validate_addr = eth_validate_addr,
1664 	.ndo_tx_timeout = emac_ndo_tx_timeout,
1665 	.ndo_set_rx_mode = emac_ndo_set_rx_mode,
1666 	.ndo_eth_ioctl = emac_ndo_ioctl,
1667 	.ndo_get_stats64 = emac_ndo_get_stats64,
1668 };
1669 
1670 /* get emac_port corresponding to eth_node name */
1671 static int prueth_node_port(struct device_node *eth_node)
1672 {
1673 	u32 port_id;
1674 	int ret;
1675 
1676 	ret = of_property_read_u32(eth_node, "reg", &port_id);
1677 	if (ret)
1678 		return ret;
1679 
1680 	if (port_id == 0)
1681 		return PRUETH_PORT_MII0;
1682 	else if (port_id == 1)
1683 		return PRUETH_PORT_MII1;
1684 	else
1685 		return PRUETH_PORT_INVALID;
1686 }
1687 
1688 /* get MAC instance corresponding to eth_node name */
1689 static int prueth_node_mac(struct device_node *eth_node)
1690 {
1691 	u32 port_id;
1692 	int ret;
1693 
1694 	ret = of_property_read_u32(eth_node, "reg", &port_id);
1695 	if (ret)
1696 		return ret;
1697 
1698 	if (port_id == 0)
1699 		return PRUETH_MAC0;
1700 	else if (port_id == 1)
1701 		return PRUETH_MAC1;
1702 	else
1703 		return PRUETH_MAC_INVALID;
1704 }
1705 
1706 static int prueth_netdev_init(struct prueth *prueth,
1707 			      struct device_node *eth_node)
1708 {
1709 	int ret, num_tx_chn = PRUETH_MAX_TX_QUEUES;
1710 	struct prueth_emac *emac;
1711 	struct net_device *ndev;
1712 	enum prueth_port port;
1713 	const char *irq_name;
1714 	enum prueth_mac mac;
1715 
1716 	port = prueth_node_port(eth_node);
1717 	if (port == PRUETH_PORT_INVALID)
1718 		return -EINVAL;
1719 
1720 	mac = prueth_node_mac(eth_node);
1721 	if (mac == PRUETH_MAC_INVALID)
1722 		return -EINVAL;
1723 
1724 	ndev = alloc_etherdev_mq(sizeof(*emac), num_tx_chn);
1725 	if (!ndev)
1726 		return -ENOMEM;
1727 
1728 	emac = netdev_priv(ndev);
1729 	emac->prueth = prueth;
1730 	emac->ndev = ndev;
1731 	emac->port_id = port;
1732 	emac->cmd_wq = create_singlethread_workqueue("icssg_cmd_wq");
1733 	if (!emac->cmd_wq) {
1734 		ret = -ENOMEM;
1735 		goto free_ndev;
1736 	}
1737 	INIT_WORK(&emac->rx_mode_work, emac_ndo_set_rx_mode_work);
1738 
1739 	INIT_DELAYED_WORK(&emac->stats_work, emac_stats_work_handler);
1740 
1741 	ret = pruss_request_mem_region(prueth->pruss,
1742 				       port == PRUETH_PORT_MII0 ?
1743 				       PRUSS_MEM_DRAM0 : PRUSS_MEM_DRAM1,
1744 				       &emac->dram);
1745 	if (ret) {
1746 		dev_err(prueth->dev, "unable to get DRAM: %d\n", ret);
1747 		ret = -ENOMEM;
1748 		goto free_wq;
1749 	}
1750 
1751 	emac->tx_ch_num = 1;
1752 
1753 	irq_name = "tx_ts0";
1754 	if (emac->port_id == PRUETH_PORT_MII1)
1755 		irq_name = "tx_ts1";
1756 	emac->tx_ts_irq = platform_get_irq_byname_optional(prueth->pdev, irq_name);
1757 	if (emac->tx_ts_irq < 0) {
1758 		ret = dev_err_probe(prueth->dev, emac->tx_ts_irq, "could not get tx_ts_irq\n");
1759 		goto free;
1760 	}
1761 
1762 	SET_NETDEV_DEV(ndev, prueth->dev);
1763 	spin_lock_init(&emac->lock);
1764 	mutex_init(&emac->cmd_lock);
1765 
1766 	emac->phy_node = of_parse_phandle(eth_node, "phy-handle", 0);
1767 	if (!emac->phy_node && !of_phy_is_fixed_link(eth_node)) {
1768 		dev_err(prueth->dev, "couldn't find phy-handle\n");
1769 		ret = -ENODEV;
1770 		goto free;
1771 	} else if (of_phy_is_fixed_link(eth_node)) {
1772 		ret = of_phy_register_fixed_link(eth_node);
1773 		if (ret) {
1774 			ret = dev_err_probe(prueth->dev, ret,
1775 					    "failed to register fixed-link phy\n");
1776 			goto free;
1777 		}
1778 
1779 		emac->phy_node = eth_node;
1780 	}
1781 
1782 	ret = of_get_phy_mode(eth_node, &emac->phy_if);
1783 	if (ret) {
1784 		dev_err(prueth->dev, "could not get phy-mode property\n");
1785 		goto free;
1786 	}
1787 
1788 	if (emac->phy_if != PHY_INTERFACE_MODE_MII &&
1789 	    !phy_interface_mode_is_rgmii(emac->phy_if)) {
1790 		dev_err(prueth->dev, "PHY mode unsupported %s\n", phy_modes(emac->phy_if));
1791 		ret = -EINVAL;
1792 		goto free;
1793 	}
1794 
1795 	/* AM65 SR2.0 has TX Internal delay always enabled by hardware
1796 	 * and it is not possible to disable TX Internal delay. The below
1797 	 * switch case block describes how we handle different phy modes
1798 	 * based on hardware restriction.
1799 	 */
1800 	switch (emac->phy_if) {
1801 	case PHY_INTERFACE_MODE_RGMII_ID:
1802 		emac->phy_if = PHY_INTERFACE_MODE_RGMII_RXID;
1803 		break;
1804 	case PHY_INTERFACE_MODE_RGMII_TXID:
1805 		emac->phy_if = PHY_INTERFACE_MODE_RGMII;
1806 		break;
1807 	case PHY_INTERFACE_MODE_RGMII:
1808 	case PHY_INTERFACE_MODE_RGMII_RXID:
1809 		dev_err(prueth->dev, "RGMII mode without TX delay is not supported");
1810 		ret = -EINVAL;
1811 		goto free;
1812 	default:
1813 		break;
1814 	}
1815 
1816 	/* get mac address from DT and set private and netdev addr */
1817 	ret = of_get_ethdev_address(eth_node, ndev);
1818 	if (!is_valid_ether_addr(ndev->dev_addr)) {
1819 		eth_hw_addr_random(ndev);
1820 		dev_warn(prueth->dev, "port %d: using random MAC addr: %pM\n",
1821 			 port, ndev->dev_addr);
1822 	}
1823 	ether_addr_copy(emac->mac_addr, ndev->dev_addr);
1824 
1825 	ndev->min_mtu = PRUETH_MIN_PKT_SIZE;
1826 	ndev->max_mtu = PRUETH_MAX_MTU;
1827 	ndev->netdev_ops = &emac_netdev_ops;
1828 	ndev->ethtool_ops = &icssg_ethtool_ops;
1829 	ndev->hw_features = NETIF_F_SG;
1830 	ndev->features = ndev->hw_features;
1831 
1832 	netif_napi_add(ndev, &emac->napi_rx, emac_napi_rx_poll);
1833 	prueth->emac[mac] = emac;
1834 
1835 	return 0;
1836 
1837 free:
1838 	pruss_release_mem_region(prueth->pruss, &emac->dram);
1839 free_wq:
1840 	destroy_workqueue(emac->cmd_wq);
1841 free_ndev:
1842 	emac->ndev = NULL;
1843 	prueth->emac[mac] = NULL;
1844 	free_netdev(ndev);
1845 
1846 	return ret;
1847 }
1848 
1849 static void prueth_netdev_exit(struct prueth *prueth,
1850 			       struct device_node *eth_node)
1851 {
1852 	struct prueth_emac *emac;
1853 	enum prueth_mac mac;
1854 
1855 	mac = prueth_node_mac(eth_node);
1856 	if (mac == PRUETH_MAC_INVALID)
1857 		return;
1858 
1859 	emac = prueth->emac[mac];
1860 	if (!emac)
1861 		return;
1862 
1863 	if (of_phy_is_fixed_link(emac->phy_node))
1864 		of_phy_deregister_fixed_link(emac->phy_node);
1865 
1866 	netif_napi_del(&emac->napi_rx);
1867 
1868 	pruss_release_mem_region(prueth->pruss, &emac->dram);
1869 	destroy_workqueue(emac->cmd_wq);
1870 	free_netdev(emac->ndev);
1871 	prueth->emac[mac] = NULL;
1872 }
1873 
1874 static int prueth_get_cores(struct prueth *prueth, int slice)
1875 {
1876 	struct device *dev = prueth->dev;
1877 	enum pruss_pru_id pruss_id;
1878 	struct device_node *np;
1879 	int idx = -1, ret;
1880 
1881 	np = dev->of_node;
1882 
1883 	switch (slice) {
1884 	case ICSS_SLICE0:
1885 		idx = 0;
1886 		break;
1887 	case ICSS_SLICE1:
1888 		idx = 3;
1889 		break;
1890 	default:
1891 		return -EINVAL;
1892 	}
1893 
1894 	prueth->pru[slice] = pru_rproc_get(np, idx, &pruss_id);
1895 	if (IS_ERR(prueth->pru[slice])) {
1896 		ret = PTR_ERR(prueth->pru[slice]);
1897 		prueth->pru[slice] = NULL;
1898 		return dev_err_probe(dev, ret, "unable to get PRU%d\n", slice);
1899 	}
1900 	prueth->pru_id[slice] = pruss_id;
1901 
1902 	idx++;
1903 	prueth->rtu[slice] = pru_rproc_get(np, idx, NULL);
1904 	if (IS_ERR(prueth->rtu[slice])) {
1905 		ret = PTR_ERR(prueth->rtu[slice]);
1906 		prueth->rtu[slice] = NULL;
1907 		return dev_err_probe(dev, ret, "unable to get RTU%d\n", slice);
1908 	}
1909 
1910 	idx++;
1911 	prueth->txpru[slice] = pru_rproc_get(np, idx, NULL);
1912 	if (IS_ERR(prueth->txpru[slice])) {
1913 		ret = PTR_ERR(prueth->txpru[slice]);
1914 		prueth->txpru[slice] = NULL;
1915 		return dev_err_probe(dev, ret, "unable to get TX_PRU%d\n", slice);
1916 	}
1917 
1918 	return 0;
1919 }
1920 
1921 static void prueth_put_cores(struct prueth *prueth, int slice)
1922 {
1923 	if (prueth->txpru[slice])
1924 		pru_rproc_put(prueth->txpru[slice]);
1925 
1926 	if (prueth->rtu[slice])
1927 		pru_rproc_put(prueth->rtu[slice]);
1928 
1929 	if (prueth->pru[slice])
1930 		pru_rproc_put(prueth->pru[slice]);
1931 }
1932 
1933 static const struct of_device_id prueth_dt_match[];
1934 
1935 static int prueth_probe(struct platform_device *pdev)
1936 {
1937 	struct device_node *eth_node, *eth_ports_node;
1938 	struct device_node  *eth0_node = NULL;
1939 	struct device_node  *eth1_node = NULL;
1940 	struct genpool_data_align gp_data = {
1941 		.align = SZ_64K,
1942 	};
1943 	const struct of_device_id *match;
1944 	struct device *dev = &pdev->dev;
1945 	struct device_node *np;
1946 	struct prueth *prueth;
1947 	struct pruss *pruss;
1948 	u32 msmc_ram_size;
1949 	int i, ret;
1950 
1951 	np = dev->of_node;
1952 
1953 	match = of_match_device(prueth_dt_match, dev);
1954 	if (!match)
1955 		return -ENODEV;
1956 
1957 	prueth = devm_kzalloc(dev, sizeof(*prueth), GFP_KERNEL);
1958 	if (!prueth)
1959 		return -ENOMEM;
1960 
1961 	dev_set_drvdata(dev, prueth);
1962 	prueth->pdev = pdev;
1963 	prueth->pdata = *(const struct prueth_pdata *)match->data;
1964 
1965 	prueth->dev = dev;
1966 	eth_ports_node = of_get_child_by_name(np, "ethernet-ports");
1967 	if (!eth_ports_node)
1968 		return -ENOENT;
1969 
1970 	for_each_child_of_node(eth_ports_node, eth_node) {
1971 		u32 reg;
1972 
1973 		if (strcmp(eth_node->name, "port"))
1974 			continue;
1975 		ret = of_property_read_u32(eth_node, "reg", &reg);
1976 		if (ret < 0) {
1977 			dev_err(dev, "%pOF error reading port_id %d\n",
1978 				eth_node, ret);
1979 		}
1980 
1981 		of_node_get(eth_node);
1982 
1983 		if (reg == 0) {
1984 			eth0_node = eth_node;
1985 			if (!of_device_is_available(eth0_node)) {
1986 				of_node_put(eth0_node);
1987 				eth0_node = NULL;
1988 			}
1989 		} else if (reg == 1) {
1990 			eth1_node = eth_node;
1991 			if (!of_device_is_available(eth1_node)) {
1992 				of_node_put(eth1_node);
1993 				eth1_node = NULL;
1994 			}
1995 		} else {
1996 			dev_err(dev, "port reg should be 0 or 1\n");
1997 		}
1998 	}
1999 
2000 	of_node_put(eth_ports_node);
2001 
2002 	/* At least one node must be present and available else we fail */
2003 	if (!eth0_node && !eth1_node) {
2004 		dev_err(dev, "neither port0 nor port1 node available\n");
2005 		return -ENODEV;
2006 	}
2007 
2008 	if (eth0_node == eth1_node) {
2009 		dev_err(dev, "port0 and port1 can't have same reg\n");
2010 		of_node_put(eth0_node);
2011 		return -ENODEV;
2012 	}
2013 
2014 	prueth->eth_node[PRUETH_MAC0] = eth0_node;
2015 	prueth->eth_node[PRUETH_MAC1] = eth1_node;
2016 
2017 	prueth->miig_rt = syscon_regmap_lookup_by_phandle(np, "ti,mii-g-rt");
2018 	if (IS_ERR(prueth->miig_rt)) {
2019 		dev_err(dev, "couldn't get ti,mii-g-rt syscon regmap\n");
2020 		return -ENODEV;
2021 	}
2022 
2023 	prueth->mii_rt = syscon_regmap_lookup_by_phandle(np, "ti,mii-rt");
2024 	if (IS_ERR(prueth->mii_rt)) {
2025 		dev_err(dev, "couldn't get ti,mii-rt syscon regmap\n");
2026 		return -ENODEV;
2027 	}
2028 
2029 	if (eth0_node) {
2030 		ret = prueth_get_cores(prueth, ICSS_SLICE0);
2031 		if (ret)
2032 			goto put_cores;
2033 	}
2034 
2035 	if (eth1_node) {
2036 		ret = prueth_get_cores(prueth, ICSS_SLICE1);
2037 		if (ret)
2038 			goto put_cores;
2039 	}
2040 
2041 	pruss = pruss_get(eth0_node ?
2042 			  prueth->pru[ICSS_SLICE0] : prueth->pru[ICSS_SLICE1]);
2043 	if (IS_ERR(pruss)) {
2044 		ret = PTR_ERR(pruss);
2045 		dev_err(dev, "unable to get pruss handle\n");
2046 		goto put_cores;
2047 	}
2048 
2049 	prueth->pruss = pruss;
2050 
2051 	ret = pruss_request_mem_region(pruss, PRUSS_MEM_SHRD_RAM2,
2052 				       &prueth->shram);
2053 	if (ret) {
2054 		dev_err(dev, "unable to get PRUSS SHRD RAM2: %d\n", ret);
2055 		goto put_pruss;
2056 	}
2057 
2058 	prueth->sram_pool = of_gen_pool_get(np, "sram", 0);
2059 	if (!prueth->sram_pool) {
2060 		dev_err(dev, "unable to get SRAM pool\n");
2061 		ret = -ENODEV;
2062 
2063 		goto put_mem;
2064 	}
2065 
2066 	msmc_ram_size = MSMC_RAM_SIZE;
2067 
2068 	/* NOTE: FW bug needs buffer base to be 64KB aligned */
2069 	prueth->msmcram.va =
2070 		(void __iomem *)gen_pool_alloc_algo(prueth->sram_pool,
2071 						    msmc_ram_size,
2072 						    gen_pool_first_fit_align,
2073 						    &gp_data);
2074 
2075 	if (!prueth->msmcram.va) {
2076 		ret = -ENOMEM;
2077 		dev_err(dev, "unable to allocate MSMC resource\n");
2078 		goto put_mem;
2079 	}
2080 	prueth->msmcram.pa = gen_pool_virt_to_phys(prueth->sram_pool,
2081 						   (unsigned long)prueth->msmcram.va);
2082 	prueth->msmcram.size = msmc_ram_size;
2083 	memset_io(prueth->msmcram.va, 0, msmc_ram_size);
2084 	dev_dbg(dev, "sram: pa %llx va %p size %zx\n", prueth->msmcram.pa,
2085 		prueth->msmcram.va, prueth->msmcram.size);
2086 
2087 	prueth->iep0 = icss_iep_get_idx(np, 0);
2088 	if (IS_ERR(prueth->iep0)) {
2089 		ret = dev_err_probe(dev, PTR_ERR(prueth->iep0), "iep0 get failed\n");
2090 		prueth->iep0 = NULL;
2091 		goto free_pool;
2092 	}
2093 
2094 	prueth->iep1 = icss_iep_get_idx(np, 1);
2095 	if (IS_ERR(prueth->iep1)) {
2096 		ret = dev_err_probe(dev, PTR_ERR(prueth->iep1), "iep1 get failed\n");
2097 		goto put_iep0;
2098 	}
2099 
2100 	if (prueth->pdata.quirk_10m_link_issue) {
2101 		/* Enable IEP1 for FW in 64bit mode as W/A for 10M FD link detect issue under TX
2102 		 * traffic.
2103 		 */
2104 		icss_iep_init_fw(prueth->iep1);
2105 	}
2106 
2107 	/* setup netdev interfaces */
2108 	if (eth0_node) {
2109 		ret = prueth_netdev_init(prueth, eth0_node);
2110 		if (ret) {
2111 			dev_err_probe(dev, ret, "netdev init %s failed\n",
2112 				      eth0_node->name);
2113 			goto exit_iep;
2114 		}
2115 		prueth->emac[PRUETH_MAC0]->iep = prueth->iep0;
2116 	}
2117 
2118 	if (eth1_node) {
2119 		ret = prueth_netdev_init(prueth, eth1_node);
2120 		if (ret) {
2121 			dev_err_probe(dev, ret, "netdev init %s failed\n",
2122 				      eth1_node->name);
2123 			goto netdev_exit;
2124 		}
2125 
2126 		prueth->emac[PRUETH_MAC1]->iep = prueth->iep0;
2127 	}
2128 
2129 	/* register the network devices */
2130 	if (eth0_node) {
2131 		ret = register_netdev(prueth->emac[PRUETH_MAC0]->ndev);
2132 		if (ret) {
2133 			dev_err(dev, "can't register netdev for port MII0");
2134 			goto netdev_exit;
2135 		}
2136 
2137 		prueth->registered_netdevs[PRUETH_MAC0] = prueth->emac[PRUETH_MAC0]->ndev;
2138 
2139 		ret = emac_phy_connect(prueth->emac[PRUETH_MAC0]);
2140 		if (ret) {
2141 			dev_err(dev,
2142 				"can't connect to MII0 PHY, error -%d", ret);
2143 			goto netdev_unregister;
2144 		}
2145 		phy_attached_info(prueth->emac[PRUETH_MAC0]->ndev->phydev);
2146 	}
2147 
2148 	if (eth1_node) {
2149 		ret = register_netdev(prueth->emac[PRUETH_MAC1]->ndev);
2150 		if (ret) {
2151 			dev_err(dev, "can't register netdev for port MII1");
2152 			goto netdev_unregister;
2153 		}
2154 
2155 		prueth->registered_netdevs[PRUETH_MAC1] = prueth->emac[PRUETH_MAC1]->ndev;
2156 		ret = emac_phy_connect(prueth->emac[PRUETH_MAC1]);
2157 		if (ret) {
2158 			dev_err(dev,
2159 				"can't connect to MII1 PHY, error %d", ret);
2160 			goto netdev_unregister;
2161 		}
2162 		phy_attached_info(prueth->emac[PRUETH_MAC1]->ndev->phydev);
2163 	}
2164 
2165 	dev_info(dev, "TI PRU ethernet driver initialized: %s EMAC mode\n",
2166 		 (!eth0_node || !eth1_node) ? "single" : "dual");
2167 
2168 	if (eth1_node)
2169 		of_node_put(eth1_node);
2170 	if (eth0_node)
2171 		of_node_put(eth0_node);
2172 	return 0;
2173 
2174 netdev_unregister:
2175 	for (i = 0; i < PRUETH_NUM_MACS; i++) {
2176 		if (!prueth->registered_netdevs[i])
2177 			continue;
2178 		if (prueth->emac[i]->ndev->phydev) {
2179 			phy_disconnect(prueth->emac[i]->ndev->phydev);
2180 			prueth->emac[i]->ndev->phydev = NULL;
2181 		}
2182 		unregister_netdev(prueth->registered_netdevs[i]);
2183 	}
2184 
2185 netdev_exit:
2186 	for (i = 0; i < PRUETH_NUM_MACS; i++) {
2187 		eth_node = prueth->eth_node[i];
2188 		if (!eth_node)
2189 			continue;
2190 
2191 		prueth_netdev_exit(prueth, eth_node);
2192 	}
2193 
2194 exit_iep:
2195 	if (prueth->pdata.quirk_10m_link_issue)
2196 		icss_iep_exit_fw(prueth->iep1);
2197 	icss_iep_put(prueth->iep1);
2198 
2199 put_iep0:
2200 	icss_iep_put(prueth->iep0);
2201 	prueth->iep0 = NULL;
2202 	prueth->iep1 = NULL;
2203 
2204 free_pool:
2205 	gen_pool_free(prueth->sram_pool,
2206 		      (unsigned long)prueth->msmcram.va, msmc_ram_size);
2207 
2208 put_mem:
2209 	pruss_release_mem_region(prueth->pruss, &prueth->shram);
2210 
2211 put_pruss:
2212 	pruss_put(prueth->pruss);
2213 
2214 put_cores:
2215 	if (eth1_node) {
2216 		prueth_put_cores(prueth, ICSS_SLICE1);
2217 		of_node_put(eth1_node);
2218 	}
2219 
2220 	if (eth0_node) {
2221 		prueth_put_cores(prueth, ICSS_SLICE0);
2222 		of_node_put(eth0_node);
2223 	}
2224 
2225 	return ret;
2226 }
2227 
2228 static void prueth_remove(struct platform_device *pdev)
2229 {
2230 	struct prueth *prueth = platform_get_drvdata(pdev);
2231 	struct device_node *eth_node;
2232 	int i;
2233 
2234 	for (i = 0; i < PRUETH_NUM_MACS; i++) {
2235 		if (!prueth->registered_netdevs[i])
2236 			continue;
2237 		phy_stop(prueth->emac[i]->ndev->phydev);
2238 		phy_disconnect(prueth->emac[i]->ndev->phydev);
2239 		prueth->emac[i]->ndev->phydev = NULL;
2240 		unregister_netdev(prueth->registered_netdevs[i]);
2241 	}
2242 
2243 	for (i = 0; i < PRUETH_NUM_MACS; i++) {
2244 		eth_node = prueth->eth_node[i];
2245 		if (!eth_node)
2246 			continue;
2247 
2248 		prueth_netdev_exit(prueth, eth_node);
2249 	}
2250 
2251 	if (prueth->pdata.quirk_10m_link_issue)
2252 		icss_iep_exit_fw(prueth->iep1);
2253 
2254 	icss_iep_put(prueth->iep1);
2255 	icss_iep_put(prueth->iep0);
2256 
2257 	gen_pool_free(prueth->sram_pool,
2258 		      (unsigned long)prueth->msmcram.va,
2259 		      MSMC_RAM_SIZE);
2260 
2261 	pruss_release_mem_region(prueth->pruss, &prueth->shram);
2262 
2263 	pruss_put(prueth->pruss);
2264 
2265 	if (prueth->eth_node[PRUETH_MAC1])
2266 		prueth_put_cores(prueth, ICSS_SLICE1);
2267 
2268 	if (prueth->eth_node[PRUETH_MAC0])
2269 		prueth_put_cores(prueth, ICSS_SLICE0);
2270 }
2271 
2272 #ifdef CONFIG_PM_SLEEP
2273 static int prueth_suspend(struct device *dev)
2274 {
2275 	struct prueth *prueth = dev_get_drvdata(dev);
2276 	struct net_device *ndev;
2277 	int i, ret;
2278 
2279 	for (i = 0; i < PRUETH_NUM_MACS; i++) {
2280 		ndev = prueth->registered_netdevs[i];
2281 
2282 		if (!ndev)
2283 			continue;
2284 
2285 		if (netif_running(ndev)) {
2286 			netif_device_detach(ndev);
2287 			ret = emac_ndo_stop(ndev);
2288 			if (ret < 0) {
2289 				netdev_err(ndev, "failed to stop: %d", ret);
2290 				return ret;
2291 			}
2292 		}
2293 	}
2294 
2295 	return 0;
2296 }
2297 
2298 static int prueth_resume(struct device *dev)
2299 {
2300 	struct prueth *prueth = dev_get_drvdata(dev);
2301 	struct net_device *ndev;
2302 	int i, ret;
2303 
2304 	for (i = 0; i < PRUETH_NUM_MACS; i++) {
2305 		ndev = prueth->registered_netdevs[i];
2306 
2307 		if (!ndev)
2308 			continue;
2309 
2310 		if (netif_running(ndev)) {
2311 			ret = emac_ndo_open(ndev);
2312 			if (ret < 0) {
2313 				netdev_err(ndev, "failed to start: %d", ret);
2314 				return ret;
2315 			}
2316 			netif_device_attach(ndev);
2317 		}
2318 	}
2319 
2320 	return 0;
2321 }
2322 #endif /* CONFIG_PM_SLEEP */
2323 
2324 static const struct dev_pm_ops prueth_dev_pm_ops = {
2325 	SET_SYSTEM_SLEEP_PM_OPS(prueth_suspend, prueth_resume)
2326 };
2327 
2328 static const struct prueth_pdata am654_icssg_pdata = {
2329 	.fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE,
2330 	.quirk_10m_link_issue = 1,
2331 };
2332 
2333 static const struct of_device_id prueth_dt_match[] = {
2334 	{ .compatible = "ti,am654-icssg-prueth", .data = &am654_icssg_pdata },
2335 	{ /* sentinel */ }
2336 };
2337 MODULE_DEVICE_TABLE(of, prueth_dt_match);
2338 
2339 static struct platform_driver prueth_driver = {
2340 	.probe = prueth_probe,
2341 	.remove_new = prueth_remove,
2342 	.driver = {
2343 		.name = "icssg-prueth",
2344 		.of_match_table = prueth_dt_match,
2345 		.pm = &prueth_dev_pm_ops,
2346 	},
2347 };
2348 module_platform_driver(prueth_driver);
2349 
2350 MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>");
2351 MODULE_AUTHOR("Md Danish Anwar <danishanwar@ti.com>");
2352 MODULE_DESCRIPTION("PRUSS ICSSG Ethernet Driver");
2353 MODULE_LICENSE("GPL");
2354