1 /*
2  * DaVinci MDIO Module driver
3  *
4  * Copyright (C) 2010 Texas Instruments.
5  *
6  * Shamelessly ripped out of davinci_emac.c, original copyrights follow:
7  *
8  * Copyright (C) 2009 Texas Instruments.
9  *
10  * ---------------------------------------------------------------------------
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License as published by
14  * the Free Software Foundation; either version 2 of the License, or
15  * (at your option) any later version.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25  * ---------------------------------------------------------------------------
26  */
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/platform_device.h>
30 #include <linux/delay.h>
31 #include <linux/sched.h>
32 #include <linux/slab.h>
33 #include <linux/phy.h>
34 #include <linux/clk.h>
35 #include <linux/err.h>
36 #include <linux/io.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/davinci_emac.h>
39 #include <linux/of.h>
40 #include <linux/of_device.h>
41 #include <linux/pinctrl/consumer.h>
42 
43 /*
44  * This timeout definition is a worst-case ultra defensive measure against
45  * unexpected controller lock ups.  Ideally, we should never ever hit this
46  * scenario in practice.
47  */
48 #define MDIO_TIMEOUT		100 /* msecs */
49 
50 #define PHY_REG_MASK		0x1f
51 #define PHY_ID_MASK		0x1f
52 
53 #define DEF_OUT_FREQ		2200000		/* 2.2 MHz */
54 
55 struct davinci_mdio_regs {
56 	u32	version;
57 	u32	control;
58 #define CONTROL_IDLE		BIT(31)
59 #define CONTROL_ENABLE		BIT(30)
60 #define CONTROL_MAX_DIV		(0xffff)
61 
62 	u32	alive;
63 	u32	link;
64 	u32	linkintraw;
65 	u32	linkintmasked;
66 	u32	__reserved_0[2];
67 	u32	userintraw;
68 	u32	userintmasked;
69 	u32	userintmaskset;
70 	u32	userintmaskclr;
71 	u32	__reserved_1[20];
72 
73 	struct {
74 		u32	access;
75 #define USERACCESS_GO		BIT(31)
76 #define USERACCESS_WRITE	BIT(30)
77 #define USERACCESS_ACK		BIT(29)
78 #define USERACCESS_READ		(0)
79 #define USERACCESS_DATA		(0xffff)
80 
81 		u32	physel;
82 	}	user[0];
83 };
84 
85 struct mdio_platform_data default_pdata = {
86 	.bus_freq = DEF_OUT_FREQ,
87 };
88 
89 struct davinci_mdio_data {
90 	struct mdio_platform_data pdata;
91 	struct davinci_mdio_regs __iomem *regs;
92 	spinlock_t	lock;
93 	struct clk	*clk;
94 	struct device	*dev;
95 	struct mii_bus	*bus;
96 	bool		suspended;
97 	unsigned long	access_time; /* jiffies */
98 };
99 
100 static void __davinci_mdio_reset(struct davinci_mdio_data *data)
101 {
102 	u32 mdio_in, div, mdio_out_khz, access_time;
103 
104 	mdio_in = clk_get_rate(data->clk);
105 	div = (mdio_in / data->pdata.bus_freq) - 1;
106 	if (div > CONTROL_MAX_DIV)
107 		div = CONTROL_MAX_DIV;
108 
109 	/* set enable and clock divider */
110 	__raw_writel(div | CONTROL_ENABLE, &data->regs->control);
111 
112 	/*
113 	 * One mdio transaction consists of:
114 	 *	32 bits of preamble
115 	 *	32 bits of transferred data
116 	 *	24 bits of bus yield (not needed unless shared?)
117 	 */
118 	mdio_out_khz = mdio_in / (1000 * (div + 1));
119 	access_time  = (88 * 1000) / mdio_out_khz;
120 
121 	/*
122 	 * In the worst case, we could be kicking off a user-access immediately
123 	 * after the mdio bus scan state-machine triggered its own read.  If
124 	 * so, our request could get deferred by one access cycle.  We
125 	 * defensively allow for 4 access cycles.
126 	 */
127 	data->access_time = usecs_to_jiffies(access_time * 4);
128 	if (!data->access_time)
129 		data->access_time = 1;
130 }
131 
132 static int davinci_mdio_reset(struct mii_bus *bus)
133 {
134 	struct davinci_mdio_data *data = bus->priv;
135 	u32 phy_mask, ver;
136 
137 	__davinci_mdio_reset(data);
138 
139 	/* wait for scan logic to settle */
140 	msleep(PHY_MAX_ADDR * data->access_time);
141 
142 	/* dump hardware version info */
143 	ver = __raw_readl(&data->regs->version);
144 	dev_info(data->dev, "davinci mdio revision %d.%d\n",
145 		 (ver >> 8) & 0xff, ver & 0xff);
146 
147 	/* get phy mask from the alive register */
148 	phy_mask = __raw_readl(&data->regs->alive);
149 	if (phy_mask) {
150 		/* restrict mdio bus to live phys only */
151 		dev_info(data->dev, "detected phy mask %x\n", ~phy_mask);
152 		phy_mask = ~phy_mask;
153 	} else {
154 		/* desperately scan all phys */
155 		dev_warn(data->dev, "no live phy, scanning all\n");
156 		phy_mask = 0;
157 	}
158 	data->bus->phy_mask = phy_mask;
159 
160 	return 0;
161 }
162 
163 /* wait until hardware is ready for another user access */
164 static inline int wait_for_user_access(struct davinci_mdio_data *data)
165 {
166 	struct davinci_mdio_regs __iomem *regs = data->regs;
167 	unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
168 	u32 reg;
169 
170 	while (time_after(timeout, jiffies)) {
171 		reg = __raw_readl(&regs->user[0].access);
172 		if ((reg & USERACCESS_GO) == 0)
173 			return 0;
174 
175 		reg = __raw_readl(&regs->control);
176 		if ((reg & CONTROL_IDLE) == 0)
177 			continue;
178 
179 		/*
180 		 * An emac soft_reset may have clobbered the mdio controller's
181 		 * state machine.  We need to reset and retry the current
182 		 * operation
183 		 */
184 		dev_warn(data->dev, "resetting idled controller\n");
185 		__davinci_mdio_reset(data);
186 		return -EAGAIN;
187 	}
188 
189 	reg = __raw_readl(&regs->user[0].access);
190 	if ((reg & USERACCESS_GO) == 0)
191 		return 0;
192 
193 	dev_err(data->dev, "timed out waiting for user access\n");
194 	return -ETIMEDOUT;
195 }
196 
197 /* wait until hardware state machine is idle */
198 static inline int wait_for_idle(struct davinci_mdio_data *data)
199 {
200 	struct davinci_mdio_regs __iomem *regs = data->regs;
201 	unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
202 
203 	while (time_after(timeout, jiffies)) {
204 		if (__raw_readl(&regs->control) & CONTROL_IDLE)
205 			return 0;
206 	}
207 	dev_err(data->dev, "timed out waiting for idle\n");
208 	return -ETIMEDOUT;
209 }
210 
211 static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
212 {
213 	struct davinci_mdio_data *data = bus->priv;
214 	u32 reg;
215 	int ret;
216 
217 	if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
218 		return -EINVAL;
219 
220 	spin_lock(&data->lock);
221 
222 	if (data->suspended) {
223 		spin_unlock(&data->lock);
224 		return -ENODEV;
225 	}
226 
227 	reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
228 	       (phy_id << 16));
229 
230 	while (1) {
231 		ret = wait_for_user_access(data);
232 		if (ret == -EAGAIN)
233 			continue;
234 		if (ret < 0)
235 			break;
236 
237 		__raw_writel(reg, &data->regs->user[0].access);
238 
239 		ret = wait_for_user_access(data);
240 		if (ret == -EAGAIN)
241 			continue;
242 		if (ret < 0)
243 			break;
244 
245 		reg = __raw_readl(&data->regs->user[0].access);
246 		ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO;
247 		break;
248 	}
249 
250 	spin_unlock(&data->lock);
251 
252 	return ret;
253 }
254 
255 static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
256 			      int phy_reg, u16 phy_data)
257 {
258 	struct davinci_mdio_data *data = bus->priv;
259 	u32 reg;
260 	int ret;
261 
262 	if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
263 		return -EINVAL;
264 
265 	spin_lock(&data->lock);
266 
267 	if (data->suspended) {
268 		spin_unlock(&data->lock);
269 		return -ENODEV;
270 	}
271 
272 	reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
273 		   (phy_id << 16) | (phy_data & USERACCESS_DATA));
274 
275 	while (1) {
276 		ret = wait_for_user_access(data);
277 		if (ret == -EAGAIN)
278 			continue;
279 		if (ret < 0)
280 			break;
281 
282 		__raw_writel(reg, &data->regs->user[0].access);
283 
284 		ret = wait_for_user_access(data);
285 		if (ret == -EAGAIN)
286 			continue;
287 		break;
288 	}
289 
290 	spin_unlock(&data->lock);
291 
292 	return 0;
293 }
294 
295 static int davinci_mdio_probe_dt(struct mdio_platform_data *data,
296 			 struct platform_device *pdev)
297 {
298 	struct device_node *node = pdev->dev.of_node;
299 	u32 prop;
300 
301 	if (!node)
302 		return -EINVAL;
303 
304 	if (of_property_read_u32(node, "bus_freq", &prop)) {
305 		pr_err("Missing bus_freq property in the DT.\n");
306 		return -EINVAL;
307 	}
308 	data->bus_freq = prop;
309 
310 	return 0;
311 }
312 
313 
314 static int davinci_mdio_probe(struct platform_device *pdev)
315 {
316 	struct mdio_platform_data *pdata = pdev->dev.platform_data;
317 	struct device *dev = &pdev->dev;
318 	struct davinci_mdio_data *data;
319 	struct resource *res;
320 	struct phy_device *phy;
321 	int ret, addr;
322 
323 	data = kzalloc(sizeof(*data), GFP_KERNEL);
324 	if (!data)
325 		return -ENOMEM;
326 
327 	data->bus = mdiobus_alloc();
328 	if (!data->bus) {
329 		dev_err(dev, "failed to alloc mii bus\n");
330 		ret = -ENOMEM;
331 		goto bail_out;
332 	}
333 
334 	if (dev->of_node) {
335 		if (davinci_mdio_probe_dt(&data->pdata, pdev))
336 			data->pdata = default_pdata;
337 		snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
338 	} else {
339 		data->pdata = pdata ? (*pdata) : default_pdata;
340 		snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x",
341 			 pdev->name, pdev->id);
342 	}
343 
344 	data->bus->name		= dev_name(dev);
345 	data->bus->read		= davinci_mdio_read,
346 	data->bus->write	= davinci_mdio_write,
347 	data->bus->reset	= davinci_mdio_reset,
348 	data->bus->parent	= dev;
349 	data->bus->priv		= data;
350 
351 	/* Select default pin state */
352 	pinctrl_pm_select_default_state(&pdev->dev);
353 
354 	pm_runtime_enable(&pdev->dev);
355 	pm_runtime_get_sync(&pdev->dev);
356 	data->clk = clk_get(&pdev->dev, "fck");
357 	if (IS_ERR(data->clk)) {
358 		dev_err(dev, "failed to get device clock\n");
359 		ret = PTR_ERR(data->clk);
360 		data->clk = NULL;
361 		goto bail_out;
362 	}
363 
364 	dev_set_drvdata(dev, data);
365 	data->dev = dev;
366 	spin_lock_init(&data->lock);
367 
368 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
369 	if (!res) {
370 		dev_err(dev, "could not find register map resource\n");
371 		ret = -ENOENT;
372 		goto bail_out;
373 	}
374 
375 	res = devm_request_mem_region(dev, res->start, resource_size(res),
376 					    dev_name(dev));
377 	if (!res) {
378 		dev_err(dev, "could not allocate register map resource\n");
379 		ret = -ENXIO;
380 		goto bail_out;
381 	}
382 
383 	data->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
384 	if (!data->regs) {
385 		dev_err(dev, "could not map mdio registers\n");
386 		ret = -ENOMEM;
387 		goto bail_out;
388 	}
389 
390 	/* register the mii bus */
391 	ret = mdiobus_register(data->bus);
392 	if (ret)
393 		goto bail_out;
394 
395 	/* scan and dump the bus */
396 	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
397 		phy = data->bus->phy_map[addr];
398 		if (phy) {
399 			dev_info(dev, "phy[%d]: device %s, driver %s\n",
400 				 phy->addr, dev_name(&phy->dev),
401 				 phy->drv ? phy->drv->name : "unknown");
402 		}
403 	}
404 
405 	return 0;
406 
407 bail_out:
408 	if (data->bus)
409 		mdiobus_free(data->bus);
410 
411 	if (data->clk)
412 		clk_put(data->clk);
413 	pm_runtime_put_sync(&pdev->dev);
414 	pm_runtime_disable(&pdev->dev);
415 
416 	kfree(data);
417 
418 	return ret;
419 }
420 
421 static int davinci_mdio_remove(struct platform_device *pdev)
422 {
423 	struct device *dev = &pdev->dev;
424 	struct davinci_mdio_data *data = dev_get_drvdata(dev);
425 
426 	if (data->bus) {
427 		mdiobus_unregister(data->bus);
428 		mdiobus_free(data->bus);
429 	}
430 
431 	if (data->clk)
432 		clk_put(data->clk);
433 	pm_runtime_put_sync(&pdev->dev);
434 	pm_runtime_disable(&pdev->dev);
435 
436 	dev_set_drvdata(dev, NULL);
437 
438 	kfree(data);
439 
440 	return 0;
441 }
442 
443 static int davinci_mdio_suspend(struct device *dev)
444 {
445 	struct davinci_mdio_data *data = dev_get_drvdata(dev);
446 	u32 ctrl;
447 
448 	spin_lock(&data->lock);
449 
450 	/* shutdown the scan state machine */
451 	ctrl = __raw_readl(&data->regs->control);
452 	ctrl &= ~CONTROL_ENABLE;
453 	__raw_writel(ctrl, &data->regs->control);
454 	wait_for_idle(data);
455 
456 	data->suspended = true;
457 	spin_unlock(&data->lock);
458 	pm_runtime_put_sync(data->dev);
459 
460 	/* Select sleep pin state */
461 	pinctrl_pm_select_sleep_state(dev);
462 
463 	return 0;
464 }
465 
466 static int davinci_mdio_resume(struct device *dev)
467 {
468 	struct davinci_mdio_data *data = dev_get_drvdata(dev);
469 
470 	/* Select default pin state */
471 	pinctrl_pm_select_default_state(dev);
472 
473 	pm_runtime_get_sync(data->dev);
474 
475 	spin_lock(&data->lock);
476 	/* restart the scan state machine */
477 	__davinci_mdio_reset(data);
478 
479 	data->suspended = false;
480 	spin_unlock(&data->lock);
481 
482 	return 0;
483 }
484 
485 static const struct dev_pm_ops davinci_mdio_pm_ops = {
486 	.suspend_late	= davinci_mdio_suspend,
487 	.resume_early	= davinci_mdio_resume,
488 };
489 
490 static const struct of_device_id davinci_mdio_of_mtable[] = {
491 	{ .compatible = "ti,davinci_mdio", },
492 	{ /* sentinel */ },
493 };
494 MODULE_DEVICE_TABLE(of, davinci_mdio_of_mtable);
495 
496 static struct platform_driver davinci_mdio_driver = {
497 	.driver = {
498 		.name	 = "davinci_mdio",
499 		.owner	 = THIS_MODULE,
500 		.pm	 = &davinci_mdio_pm_ops,
501 		.of_match_table = of_match_ptr(davinci_mdio_of_mtable),
502 	},
503 	.probe = davinci_mdio_probe,
504 	.remove = davinci_mdio_remove,
505 };
506 
507 static int __init davinci_mdio_init(void)
508 {
509 	return platform_driver_register(&davinci_mdio_driver);
510 }
511 device_initcall(davinci_mdio_init);
512 
513 static void __exit davinci_mdio_exit(void)
514 {
515 	platform_driver_unregister(&davinci_mdio_driver);
516 }
517 module_exit(davinci_mdio_exit);
518 
519 MODULE_LICENSE("GPL");
520 MODULE_DESCRIPTION("DaVinci MDIO driver");
521