1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * DaVinci Ethernet Medium Access Controller
4  *
5  * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
6  *
7  * Copyright (C) 2009 Texas Instruments.
8  *
9  * ---------------------------------------------------------------------------
10  * History:
11  * 0-5 A number of folks worked on this driver in bits and pieces but the major
12  *     contribution came from Suraj Iyer and Anant Gole
13  * 6.0 Anant Gole - rewrote the driver as per Linux conventions
14  * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
15  *     PHY layer usage
16  */
17 
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/sched.h>
21 #include <linux/string.h>
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/in.h>
25 #include <linux/ioport.h>
26 #include <linux/slab.h>
27 #include <linux/mm.h>
28 #include <linux/interrupt.h>
29 #include <linux/init.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/highmem.h>
35 #include <linux/proc_fs.h>
36 #include <linux/ctype.h>
37 #include <linux/spinlock.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/clk.h>
40 #include <linux/platform_device.h>
41 #include <linux/regmap.h>
42 #include <linux/semaphore.h>
43 #include <linux/phy.h>
44 #include <linux/bitops.h>
45 #include <linux/io.h>
46 #include <linux/uaccess.h>
47 #include <linux/pm_runtime.h>
48 #include <linux/davinci_emac.h>
49 #include <linux/of.h>
50 #include <linux/of_address.h>
51 #include <linux/of_device.h>
52 #include <linux/of_mdio.h>
53 #include <linux/of_irq.h>
54 #include <linux/of_net.h>
55 #include <linux/mfd/syscon.h>
56 
57 #include <asm/irq.h>
58 #include <asm/page.h>
59 
60 #include "cpsw.h"
61 #include "davinci_cpdma.h"
62 
63 static int debug_level;
64 module_param(debug_level, int, 0);
65 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
66 
67 /* Netif debug messages possible */
68 #define DAVINCI_EMAC_DEBUG	(NETIF_MSG_DRV | \
69 				NETIF_MSG_PROBE | \
70 				NETIF_MSG_LINK | \
71 				NETIF_MSG_TIMER | \
72 				NETIF_MSG_IFDOWN | \
73 				NETIF_MSG_IFUP | \
74 				NETIF_MSG_RX_ERR | \
75 				NETIF_MSG_TX_ERR | \
76 				NETIF_MSG_TX_QUEUED | \
77 				NETIF_MSG_INTR | \
78 				NETIF_MSG_TX_DONE | \
79 				NETIF_MSG_RX_STATUS | \
80 				NETIF_MSG_PKTDATA | \
81 				NETIF_MSG_HW | \
82 				NETIF_MSG_WOL)
83 
84 /* version info */
85 #define EMAC_MAJOR_VERSION	6
86 #define EMAC_MINOR_VERSION	1
87 #define EMAC_MODULE_VERSION	"6.1"
88 MODULE_VERSION(EMAC_MODULE_VERSION);
89 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
90 
91 /* Configuration items */
92 #define EMAC_DEF_PASS_CRC		(0) /* Do not pass CRC up to frames */
93 #define EMAC_DEF_QOS_EN			(0) /* EMAC proprietary QoS disabled */
94 #define EMAC_DEF_NO_BUFF_CHAIN		(0) /* No buffer chain */
95 #define EMAC_DEF_MACCTRL_FRAME_EN	(0) /* Discard Maccontrol frames */
96 #define EMAC_DEF_SHORT_FRAME_EN		(0) /* Discard short frames */
97 #define EMAC_DEF_ERROR_FRAME_EN		(0) /* Discard error frames */
98 #define EMAC_DEF_PROM_EN		(0) /* Promiscuous disabled */
99 #define EMAC_DEF_PROM_CH		(0) /* Promiscuous channel is 0 */
100 #define EMAC_DEF_BCAST_EN		(1) /* Broadcast enabled */
101 #define EMAC_DEF_BCAST_CH		(0) /* Broadcast channel is 0 */
102 #define EMAC_DEF_MCAST_EN		(1) /* Multicast enabled */
103 #define EMAC_DEF_MCAST_CH		(0) /* Multicast channel is 0 */
104 
105 #define EMAC_DEF_TXPRIO_FIXED		(1) /* TX Priority is fixed */
106 #define EMAC_DEF_TXPACING_EN		(0) /* TX pacing NOT supported*/
107 
108 #define EMAC_DEF_BUFFER_OFFSET		(0) /* Buffer offset to DMA (future) */
109 #define EMAC_DEF_MIN_ETHPKTSIZE		(60) /* Minimum ethernet pkt size */
110 #define EMAC_DEF_MAX_FRAME_SIZE		(1500 + 14 + 4 + 4)
111 #define EMAC_DEF_TX_CH			(0) /* Default 0th channel */
112 #define EMAC_DEF_RX_CH			(0) /* Default 0th channel */
113 #define EMAC_DEF_RX_NUM_DESC		(128)
114 #define EMAC_DEF_MAX_TX_CH		(1) /* Max TX channels configured */
115 #define EMAC_DEF_MAX_RX_CH		(1) /* Max RX channels configured */
116 #define EMAC_POLL_WEIGHT		(64) /* Default NAPI poll weight */
117 
118 /* Buffer descriptor parameters */
119 #define EMAC_DEF_TX_MAX_SERVICE		(32) /* TX max service BD's */
120 #define EMAC_DEF_RX_MAX_SERVICE		(64) /* should = netdev->weight */
121 
122 /* EMAC register related defines */
123 #define EMAC_ALL_MULTI_REG_VALUE	(0xFFFFFFFF)
124 #define EMAC_NUM_MULTICAST_BITS		(64)
125 #define EMAC_TX_CONTROL_TX_ENABLE_VAL	(0x1)
126 #define EMAC_RX_CONTROL_RX_ENABLE_VAL	(0x1)
127 #define EMAC_MAC_HOST_ERR_INTMASK_VAL	(0x2)
128 #define EMAC_RX_UNICAST_CLEAR_ALL	(0xFF)
129 #define EMAC_INT_MASK_CLEAR		(0xFF)
130 
131 /* RX MBP register bit positions */
132 #define EMAC_RXMBP_PASSCRC_MASK		BIT(30)
133 #define EMAC_RXMBP_QOSEN_MASK		BIT(29)
134 #define EMAC_RXMBP_NOCHAIN_MASK		BIT(28)
135 #define EMAC_RXMBP_CMFEN_MASK		BIT(24)
136 #define EMAC_RXMBP_CSFEN_MASK		BIT(23)
137 #define EMAC_RXMBP_CEFEN_MASK		BIT(22)
138 #define EMAC_RXMBP_CAFEN_MASK		BIT(21)
139 #define EMAC_RXMBP_PROMCH_SHIFT		(16)
140 #define EMAC_RXMBP_PROMCH_MASK		(0x7 << 16)
141 #define EMAC_RXMBP_BROADEN_MASK		BIT(13)
142 #define EMAC_RXMBP_BROADCH_SHIFT	(8)
143 #define EMAC_RXMBP_BROADCH_MASK		(0x7 << 8)
144 #define EMAC_RXMBP_MULTIEN_MASK		BIT(5)
145 #define EMAC_RXMBP_MULTICH_SHIFT	(0)
146 #define EMAC_RXMBP_MULTICH_MASK		(0x7)
147 #define EMAC_RXMBP_CHMASK		(0x7)
148 
149 /* EMAC register definitions/bit maps used */
150 # define EMAC_MBP_RXPROMISC		(0x00200000)
151 # define EMAC_MBP_PROMISCCH(ch)		(((ch) & 0x7) << 16)
152 # define EMAC_MBP_RXBCAST		(0x00002000)
153 # define EMAC_MBP_BCASTCHAN(ch)		(((ch) & 0x7) << 8)
154 # define EMAC_MBP_RXMCAST		(0x00000020)
155 # define EMAC_MBP_MCASTCHAN(ch)		((ch) & 0x7)
156 
157 /* EMAC mac_control register */
158 #define EMAC_MACCONTROL_TXPTYPE		BIT(9)
159 #define EMAC_MACCONTROL_TXPACEEN	BIT(6)
160 #define EMAC_MACCONTROL_GMIIEN		BIT(5)
161 #define EMAC_MACCONTROL_GIGABITEN	BIT(7)
162 #define EMAC_MACCONTROL_FULLDUPLEXEN	BIT(0)
163 #define EMAC_MACCONTROL_RMIISPEED_MASK	BIT(15)
164 
165 /* GIGABIT MODE related bits */
166 #define EMAC_DM646X_MACCONTORL_GIG	BIT(7)
167 #define EMAC_DM646X_MACCONTORL_GIGFORCE	BIT(17)
168 
169 /* EMAC mac_status register */
170 #define EMAC_MACSTATUS_TXERRCODE_MASK	(0xF00000)
171 #define EMAC_MACSTATUS_TXERRCODE_SHIFT	(20)
172 #define EMAC_MACSTATUS_TXERRCH_MASK	(0x7)
173 #define EMAC_MACSTATUS_TXERRCH_SHIFT	(16)
174 #define EMAC_MACSTATUS_RXERRCODE_MASK	(0xF000)
175 #define EMAC_MACSTATUS_RXERRCODE_SHIFT	(12)
176 #define EMAC_MACSTATUS_RXERRCH_MASK	(0x7)
177 #define EMAC_MACSTATUS_RXERRCH_SHIFT	(8)
178 
179 /* EMAC RX register masks */
180 #define EMAC_RX_MAX_LEN_MASK		(0xFFFF)
181 #define EMAC_RX_BUFFER_OFFSET_MASK	(0xFFFF)
182 
183 /* MAC_IN_VECTOR (0x180) register bit fields */
184 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT	BIT(17)
185 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT	BIT(16)
186 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC	BIT(8)
187 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC	BIT(0)
188 
189 /** NOTE:: For DM646x the IN_VECTOR has changed */
190 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC	BIT(EMAC_DEF_RX_CH)
191 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC	BIT(16 + EMAC_DEF_TX_CH)
192 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT	BIT(26)
193 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT	BIT(27)
194 
195 /* CPPI bit positions */
196 #define EMAC_CPPI_SOP_BIT		BIT(31)
197 #define EMAC_CPPI_EOP_BIT		BIT(30)
198 #define EMAC_CPPI_OWNERSHIP_BIT		BIT(29)
199 #define EMAC_CPPI_EOQ_BIT		BIT(28)
200 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
201 #define EMAC_CPPI_PASS_CRC_BIT		BIT(26)
202 #define EMAC_RX_BD_BUF_SIZE		(0xFFFF)
203 #define EMAC_BD_LENGTH_FOR_CACHE	(16) /* only CPPI bytes */
204 #define EMAC_RX_BD_PKT_LENGTH_MASK	(0xFFFF)
205 
206 /* Max hardware defines */
207 #define EMAC_MAX_TXRX_CHANNELS		 (8)  /* Max hardware channels */
208 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
209 
210 /* EMAC Peripheral Device Register Memory Layout structure */
211 #define EMAC_MACINVECTOR	0x90
212 
213 #define EMAC_DM646X_MACEOIVECTOR	0x94
214 
215 #define EMAC_MACINTSTATRAW	0xB0
216 #define EMAC_MACINTSTATMASKED	0xB4
217 #define EMAC_MACINTMASKSET	0xB8
218 #define EMAC_MACINTMASKCLEAR	0xBC
219 
220 #define EMAC_RXMBPENABLE	0x100
221 #define EMAC_RXUNICASTSET	0x104
222 #define EMAC_RXUNICASTCLEAR	0x108
223 #define EMAC_RXMAXLEN		0x10C
224 #define EMAC_RXBUFFEROFFSET	0x110
225 #define EMAC_RXFILTERLOWTHRESH	0x114
226 
227 #define EMAC_MACCONTROL		0x160
228 #define EMAC_MACSTATUS		0x164
229 #define EMAC_EMCONTROL		0x168
230 #define EMAC_FIFOCONTROL	0x16C
231 #define EMAC_MACCONFIG		0x170
232 #define EMAC_SOFTRESET		0x174
233 #define EMAC_MACSRCADDRLO	0x1D0
234 #define EMAC_MACSRCADDRHI	0x1D4
235 #define EMAC_MACHASH1		0x1D8
236 #define EMAC_MACHASH2		0x1DC
237 #define EMAC_MACADDRLO		0x500
238 #define EMAC_MACADDRHI		0x504
239 #define EMAC_MACINDEX		0x508
240 
241 /* EMAC statistics registers */
242 #define EMAC_RXGOODFRAMES	0x200
243 #define EMAC_RXBCASTFRAMES	0x204
244 #define EMAC_RXMCASTFRAMES	0x208
245 #define EMAC_RXPAUSEFRAMES	0x20C
246 #define EMAC_RXCRCERRORS	0x210
247 #define EMAC_RXALIGNCODEERRORS	0x214
248 #define EMAC_RXOVERSIZED	0x218
249 #define EMAC_RXJABBER		0x21C
250 #define EMAC_RXUNDERSIZED	0x220
251 #define EMAC_RXFRAGMENTS	0x224
252 #define EMAC_RXFILTERED		0x228
253 #define EMAC_RXQOSFILTERED	0x22C
254 #define EMAC_RXOCTETS		0x230
255 #define EMAC_TXGOODFRAMES	0x234
256 #define EMAC_TXBCASTFRAMES	0x238
257 #define EMAC_TXMCASTFRAMES	0x23C
258 #define EMAC_TXPAUSEFRAMES	0x240
259 #define EMAC_TXDEFERRED		0x244
260 #define EMAC_TXCOLLISION	0x248
261 #define EMAC_TXSINGLECOLL	0x24C
262 #define EMAC_TXMULTICOLL	0x250
263 #define EMAC_TXEXCESSIVECOLL	0x254
264 #define EMAC_TXLATECOLL		0x258
265 #define EMAC_TXUNDERRUN		0x25C
266 #define EMAC_TXCARRIERSENSE	0x260
267 #define EMAC_TXOCTETS		0x264
268 #define EMAC_NETOCTETS		0x280
269 #define EMAC_RXSOFOVERRUNS	0x284
270 #define EMAC_RXMOFOVERRUNS	0x288
271 #define EMAC_RXDMAOVERRUNS	0x28C
272 
273 /* EMAC DM644x control registers */
274 #define EMAC_CTRL_EWCTL		(0x4)
275 #define EMAC_CTRL_EWINTTCNT	(0x8)
276 
277 /* EMAC DM644x control module masks */
278 #define EMAC_DM644X_EWINTCNT_MASK	0x1FFFF
279 #define EMAC_DM644X_INTMIN_INTVL	0x1
280 #define EMAC_DM644X_INTMAX_INTVL	(EMAC_DM644X_EWINTCNT_MASK)
281 
282 /* EMAC DM646X control module registers */
283 #define EMAC_DM646X_CMINTCTRL	0x0C
284 #define EMAC_DM646X_CMRXINTEN	0x14
285 #define EMAC_DM646X_CMTXINTEN	0x18
286 #define EMAC_DM646X_CMRXINTMAX	0x70
287 #define EMAC_DM646X_CMTXINTMAX	0x74
288 
289 /* EMAC DM646X control module masks */
290 #define EMAC_DM646X_INTPACEEN		(0x3 << 16)
291 #define EMAC_DM646X_INTPRESCALE_MASK	(0x7FF << 0)
292 #define EMAC_DM646X_CMINTMAX_CNT	63
293 #define EMAC_DM646X_CMINTMIN_CNT	2
294 #define EMAC_DM646X_CMINTMAX_INTVL	(1000 / EMAC_DM646X_CMINTMIN_CNT)
295 #define EMAC_DM646X_CMINTMIN_INTVL	((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
296 
297 
298 /* EMAC EOI codes for C0 */
299 #define EMAC_DM646X_MAC_EOI_C0_RXEN	(0x01)
300 #define EMAC_DM646X_MAC_EOI_C0_TXEN	(0x02)
301 
302 /* EMAC Stats Clear Mask */
303 #define EMAC_STATS_CLR_MASK    (0xFFFFFFFF)
304 
305 /* emac_priv: EMAC private data structure
306  *
307  * EMAC adapter private data structure
308  */
309 struct emac_priv {
310 	u32 msg_enable;
311 	struct net_device *ndev;
312 	struct platform_device *pdev;
313 	struct napi_struct napi;
314 	char mac_addr[6];
315 	void __iomem *remap_addr;
316 	u32 emac_base_phys;
317 	void __iomem *emac_base;
318 	void __iomem *ctrl_base;
319 	struct cpdma_ctlr *dma;
320 	struct cpdma_chan *txchan;
321 	struct cpdma_chan *rxchan;
322 	u32 link; /* 1=link on, 0=link off */
323 	u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
324 	u32 duplex; /* Link duplex: 0=Half, 1=Full */
325 	u32 rx_buf_size;
326 	u32 isr_count;
327 	u32 coal_intvl;
328 	u32 bus_freq_mhz;
329 	u8 rmii_en;
330 	u8 version;
331 	u32 mac_hash1;
332 	u32 mac_hash2;
333 	u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
334 	u32 rx_addr_type;
335 	const char *phy_id;
336 	struct device_node *phy_node;
337 	spinlock_t lock;
338 	/*platform specific members*/
339 	void (*int_enable) (void);
340 	void (*int_disable) (void);
341 };
342 
343 /* EMAC TX Host Error description strings */
344 static char *emac_txhost_errcodes[16] = {
345 	"No error", "SOP error", "Ownership bit not set in SOP buffer",
346 	"Zero Next Buffer Descriptor Pointer Without EOP",
347 	"Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
348 	"Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
349 	"Reserved", "Reserved", "Reserved", "Reserved"
350 };
351 
352 /* EMAC RX Host Error description strings */
353 static char *emac_rxhost_errcodes[16] = {
354 	"No error", "Reserved", "Ownership bit not set in input buffer",
355 	"Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
356 	"Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
357 	"Reserved", "Reserved", "Reserved", "Reserved"
358 };
359 
360 /* Helper macros */
361 #define emac_read(reg)		  ioread32(priv->emac_base + (reg))
362 #define emac_write(reg, val)      iowrite32(val, priv->emac_base + (reg))
363 
364 #define emac_ctrl_read(reg)	  ioread32((priv->ctrl_base + (reg)))
365 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
366 
367 /**
368  * emac_get_drvinfo - Get EMAC driver information
369  * @ndev: The DaVinci EMAC network adapter
370  * @info: ethtool info structure containing name and version
371  *
372  * Returns EMAC driver information (name and version)
373  *
374  */
375 static void emac_get_drvinfo(struct net_device *ndev,
376 			     struct ethtool_drvinfo *info)
377 {
378 	strlcpy(info->driver, emac_version_string, sizeof(info->driver));
379 	strlcpy(info->version, EMAC_MODULE_VERSION, sizeof(info->version));
380 }
381 
382 /**
383  * emac_get_coalesce - Get interrupt coalesce settings for this device
384  * @ndev : The DaVinci EMAC network adapter
385  * @coal : ethtool coalesce settings structure
386  *
387  * Fetch the current interrupt coalesce settings
388  *
389  */
390 static int emac_get_coalesce(struct net_device *ndev,
391 				struct ethtool_coalesce *coal)
392 {
393 	struct emac_priv *priv = netdev_priv(ndev);
394 
395 	coal->rx_coalesce_usecs = priv->coal_intvl;
396 	return 0;
397 
398 }
399 
400 /**
401  * emac_set_coalesce - Set interrupt coalesce settings for this device
402  * @ndev : The DaVinci EMAC network adapter
403  * @coal : ethtool coalesce settings structure
404  *
405  * Set interrupt coalesce parameters
406  *
407  */
408 static int emac_set_coalesce(struct net_device *ndev,
409 				struct ethtool_coalesce *coal)
410 {
411 	struct emac_priv *priv = netdev_priv(ndev);
412 	u32 int_ctrl, num_interrupts = 0;
413 	u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;
414 
415 	if (!coal->rx_coalesce_usecs)
416 		return -EINVAL;
417 
418 	coal_intvl = coal->rx_coalesce_usecs;
419 
420 	switch (priv->version) {
421 	case EMAC_VERSION_2:
422 		int_ctrl =  emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
423 		prescale = priv->bus_freq_mhz * 4;
424 
425 		if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
426 			coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;
427 
428 		if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
429 			/*
430 			 * Interrupt pacer works with 4us Pulse, we can
431 			 * throttle further by dilating the 4us pulse.
432 			 */
433 			addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;
434 
435 			if (addnl_dvdr > 1) {
436 				prescale *= addnl_dvdr;
437 				if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
438 							* addnl_dvdr))
439 					coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
440 							* addnl_dvdr);
441 			} else {
442 				addnl_dvdr = 1;
443 				coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
444 			}
445 		}
446 
447 		num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
448 
449 		int_ctrl |= EMAC_DM646X_INTPACEEN;
450 		int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
451 		int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
452 		emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);
453 
454 		emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
455 		emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);
456 
457 		break;
458 	default:
459 		int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
460 		int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
461 		prescale = coal_intvl * priv->bus_freq_mhz;
462 		if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
463 			prescale = EMAC_DM644X_EWINTCNT_MASK;
464 			coal_intvl = prescale / priv->bus_freq_mhz;
465 		}
466 		emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));
467 
468 		break;
469 	}
470 
471 	printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
472 	priv->coal_intvl = coal_intvl;
473 
474 	return 0;
475 
476 }
477 
478 
479 /* ethtool_ops: DaVinci EMAC Ethtool structure
480  *
481  * Ethtool support for EMAC adapter
482  */
483 static const struct ethtool_ops ethtool_ops = {
484 	.supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS,
485 	.get_drvinfo = emac_get_drvinfo,
486 	.get_link = ethtool_op_get_link,
487 	.get_coalesce = emac_get_coalesce,
488 	.set_coalesce =  emac_set_coalesce,
489 	.get_ts_info = ethtool_op_get_ts_info,
490 	.get_link_ksettings = phy_ethtool_get_link_ksettings,
491 	.set_link_ksettings = phy_ethtool_set_link_ksettings,
492 };
493 
494 /**
495  * emac_update_phystatus - Update Phy status
496  * @priv: The DaVinci EMAC private adapter structure
497  *
498  * Updates phy status and takes action for network queue if required
499  * based upon link status
500  *
501  */
502 static void emac_update_phystatus(struct emac_priv *priv)
503 {
504 	u32 mac_control;
505 	u32 new_duplex;
506 	u32 cur_duplex;
507 	struct net_device *ndev = priv->ndev;
508 
509 	mac_control = emac_read(EMAC_MACCONTROL);
510 	cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
511 			DUPLEX_FULL : DUPLEX_HALF;
512 	if (ndev->phydev)
513 		new_duplex = ndev->phydev->duplex;
514 	else
515 		new_duplex = DUPLEX_FULL;
516 
517 	/* We get called only if link has changed (speed/duplex/status) */
518 	if ((priv->link) && (new_duplex != cur_duplex)) {
519 		priv->duplex = new_duplex;
520 		if (DUPLEX_FULL == priv->duplex)
521 			mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
522 		else
523 			mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
524 	}
525 
526 	if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
527 		mac_control = emac_read(EMAC_MACCONTROL);
528 		mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
529 				EMAC_DM646X_MACCONTORL_GIGFORCE);
530 	} else {
531 		/* Clear the GIG bit and GIGFORCE bit */
532 		mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
533 					EMAC_DM646X_MACCONTORL_GIG);
534 
535 		if (priv->rmii_en && (priv->speed == SPEED_100))
536 			mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
537 		else
538 			mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
539 	}
540 
541 	/* Update mac_control if changed */
542 	emac_write(EMAC_MACCONTROL, mac_control);
543 
544 	if (priv->link) {
545 		/* link ON */
546 		if (!netif_carrier_ok(ndev))
547 			netif_carrier_on(ndev);
548 	/* reactivate the transmit queue if it is stopped */
549 		if (netif_running(ndev) && netif_queue_stopped(ndev))
550 			netif_wake_queue(ndev);
551 	} else {
552 		/* link OFF */
553 		if (netif_carrier_ok(ndev))
554 			netif_carrier_off(ndev);
555 		if (!netif_queue_stopped(ndev))
556 			netif_stop_queue(ndev);
557 	}
558 }
559 
560 /**
561  * hash_get - Calculate hash value from mac address
562  * @addr: mac address to delete from hash table
563  *
564  * Calculates hash value from mac address
565  *
566  */
567 static u32 hash_get(u8 *addr)
568 {
569 	u32 hash;
570 	u8 tmpval;
571 	int cnt;
572 	hash = 0;
573 
574 	for (cnt = 0; cnt < 2; cnt++) {
575 		tmpval = *addr++;
576 		hash ^= (tmpval >> 2) ^ (tmpval << 4);
577 		tmpval = *addr++;
578 		hash ^= (tmpval >> 4) ^ (tmpval << 2);
579 		tmpval = *addr++;
580 		hash ^= (tmpval >> 6) ^ (tmpval);
581 	}
582 
583 	return hash & 0x3F;
584 }
585 
586 /**
587  * emac_hash_add - Hash function to add mac addr from hash table
588  * @priv: The DaVinci EMAC private adapter structure
589  * @mac_addr: mac address to delete from hash table
590  *
591  * Adds mac address to the internal hash table
592  *
593  */
594 static int emac_hash_add(struct emac_priv *priv, u8 *mac_addr)
595 {
596 	struct device *emac_dev = &priv->ndev->dev;
597 	u32 rc = 0;
598 	u32 hash_bit;
599 	u32 hash_value = hash_get(mac_addr);
600 
601 	if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
602 		if (netif_msg_drv(priv)) {
603 			dev_err(emac_dev, "DaVinci EMAC: emac_hash_add(): Invalid "\
604 				"Hash %08x, should not be greater than %08x",
605 				hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
606 		}
607 		return -1;
608 	}
609 
610 	/* set the hash bit only if not previously set */
611 	if (priv->multicast_hash_cnt[hash_value] == 0) {
612 		rc = 1; /* hash value changed */
613 		if (hash_value < 32) {
614 			hash_bit = BIT(hash_value);
615 			priv->mac_hash1 |= hash_bit;
616 		} else {
617 			hash_bit = BIT((hash_value - 32));
618 			priv->mac_hash2 |= hash_bit;
619 		}
620 	}
621 
622 	/* incr counter for num of mcast addr's mapped to "this" hash bit */
623 	++priv->multicast_hash_cnt[hash_value];
624 
625 	return rc;
626 }
627 
628 /**
629  * emac_hash_del - Hash function to delete mac addr from hash table
630  * @priv: The DaVinci EMAC private adapter structure
631  * @mac_addr: mac address to delete from hash table
632  *
633  * Removes mac address from the internal hash table
634  *
635  */
636 static int emac_hash_del(struct emac_priv *priv, u8 *mac_addr)
637 {
638 	u32 hash_value;
639 	u32 hash_bit;
640 
641 	hash_value = hash_get(mac_addr);
642 	if (priv->multicast_hash_cnt[hash_value] > 0) {
643 		/* dec cntr for num of mcast addr's mapped to this hash bit */
644 		--priv->multicast_hash_cnt[hash_value];
645 	}
646 
647 	/* if counter still > 0, at least one multicast address refers
648 	 * to this hash bit. so return 0 */
649 	if (priv->multicast_hash_cnt[hash_value] > 0)
650 		return 0;
651 
652 	if (hash_value < 32) {
653 		hash_bit = BIT(hash_value);
654 		priv->mac_hash1 &= ~hash_bit;
655 	} else {
656 		hash_bit = BIT((hash_value - 32));
657 		priv->mac_hash2 &= ~hash_bit;
658 	}
659 
660 	/* return 1 to indicate change in mac_hash registers reqd */
661 	return 1;
662 }
663 
664 /* EMAC multicast operation */
665 #define EMAC_MULTICAST_ADD	0
666 #define EMAC_MULTICAST_DEL	1
667 #define EMAC_ALL_MULTI_SET	2
668 #define EMAC_ALL_MULTI_CLR	3
669 
670 /**
671  * emac_add_mcast - Set multicast address in the EMAC adapter (Internal)
672  * @priv: The DaVinci EMAC private adapter structure
673  * @action: multicast operation to perform
674  * mac_addr: mac address to set
675  *
676  * Set multicast addresses in EMAC adapter - internal function
677  *
678  */
679 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
680 {
681 	struct device *emac_dev = &priv->ndev->dev;
682 	int update = -1;
683 
684 	switch (action) {
685 	case EMAC_MULTICAST_ADD:
686 		update = emac_hash_add(priv, mac_addr);
687 		break;
688 	case EMAC_MULTICAST_DEL:
689 		update = emac_hash_del(priv, mac_addr);
690 		break;
691 	case EMAC_ALL_MULTI_SET:
692 		update = 1;
693 		priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
694 		priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
695 		break;
696 	case EMAC_ALL_MULTI_CLR:
697 		update = 1;
698 		priv->mac_hash1 = 0;
699 		priv->mac_hash2 = 0;
700 		memset(&(priv->multicast_hash_cnt[0]), 0,
701 		sizeof(priv->multicast_hash_cnt[0]) *
702 		       EMAC_NUM_MULTICAST_BITS);
703 		break;
704 	default:
705 		if (netif_msg_drv(priv))
706 			dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
707 				": bad operation %d", action);
708 		break;
709 	}
710 
711 	/* write to the hardware only if the register status chances */
712 	if (update > 0) {
713 		emac_write(EMAC_MACHASH1, priv->mac_hash1);
714 		emac_write(EMAC_MACHASH2, priv->mac_hash2);
715 	}
716 }
717 
718 /**
719  * emac_dev_mcast_set - Set multicast address in the EMAC adapter
720  * @ndev: The DaVinci EMAC network adapter
721  *
722  * Set multicast addresses in EMAC adapter
723  *
724  */
725 static void emac_dev_mcast_set(struct net_device *ndev)
726 {
727 	u32 mbp_enable;
728 	struct emac_priv *priv = netdev_priv(ndev);
729 
730 	mbp_enable = emac_read(EMAC_RXMBPENABLE);
731 	if (ndev->flags & IFF_PROMISC) {
732 		mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
733 		mbp_enable |= (EMAC_MBP_RXPROMISC);
734 	} else {
735 		mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
736 		if ((ndev->flags & IFF_ALLMULTI) ||
737 		    netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
738 			mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
739 			emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
740 		} else if (!netdev_mc_empty(ndev)) {
741 			struct netdev_hw_addr *ha;
742 
743 			mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
744 			emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
745 			/* program multicast address list into EMAC hardware */
746 			netdev_for_each_mc_addr(ha, ndev) {
747 				emac_add_mcast(priv, EMAC_MULTICAST_ADD,
748 					       (u8 *) ha->addr);
749 			}
750 		} else {
751 			mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
752 			emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
753 		}
754 	}
755 	/* Set mbp config register */
756 	emac_write(EMAC_RXMBPENABLE, mbp_enable);
757 }
758 
759 /*************************************************************************
760  *  EMAC Hardware manipulation
761  *************************************************************************/
762 
763 /**
764  * emac_int_disable - Disable EMAC module interrupt (from adapter)
765  * @priv: The DaVinci EMAC private adapter structure
766  *
767  * Disable EMAC interrupt on the adapter
768  *
769  */
770 static void emac_int_disable(struct emac_priv *priv)
771 {
772 	if (priv->version == EMAC_VERSION_2) {
773 		unsigned long flags;
774 
775 		local_irq_save(flags);
776 
777 		/* Program C0_Int_En to zero to turn off
778 		* interrupts to the CPU */
779 		emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
780 		emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
781 		/* NOTE: Rx Threshold and Misc interrupts are not disabled */
782 		if (priv->int_disable)
783 			priv->int_disable();
784 
785 		/* NOTE: Rx Threshold and Misc interrupts are not enabled */
786 
787 		/* ack rxen only then a new pulse will be generated */
788 		emac_write(EMAC_DM646X_MACEOIVECTOR,
789 			EMAC_DM646X_MAC_EOI_C0_RXEN);
790 
791 		/* ack txen- only then a new pulse will be generated */
792 		emac_write(EMAC_DM646X_MACEOIVECTOR,
793 			EMAC_DM646X_MAC_EOI_C0_TXEN);
794 
795 		local_irq_restore(flags);
796 
797 	} else {
798 		/* Set DM644x control registers for interrupt control */
799 		emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
800 	}
801 }
802 
803 /**
804  * emac_int_enable - Enable EMAC module interrupt (from adapter)
805  * @priv: The DaVinci EMAC private adapter structure
806  *
807  * Enable EMAC interrupt on the adapter
808  *
809  */
810 static void emac_int_enable(struct emac_priv *priv)
811 {
812 	if (priv->version == EMAC_VERSION_2) {
813 		if (priv->int_enable)
814 			priv->int_enable();
815 
816 		emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
817 		emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
818 
819 		/* In addition to turning on interrupt Enable, we need
820 		 * ack by writing appropriate values to the EOI
821 		 * register */
822 
823 		/* NOTE: Rx Threshold and Misc interrupts are not enabled */
824 	} else {
825 		/* Set DM644x control registers for interrupt control */
826 		emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
827 	}
828 }
829 
830 /**
831  * emac_irq - EMAC interrupt handler
832  * @irq: interrupt number
833  * @dev_id: EMAC network adapter data structure ptr
834  *
835  * EMAC Interrupt handler - we only schedule NAPI and not process any packets
836  * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
837  *
838  * Returns interrupt handled condition
839  */
840 static irqreturn_t emac_irq(int irq, void *dev_id)
841 {
842 	struct net_device *ndev = (struct net_device *)dev_id;
843 	struct emac_priv *priv = netdev_priv(ndev);
844 
845 	++priv->isr_count;
846 	if (likely(netif_running(priv->ndev))) {
847 		emac_int_disable(priv);
848 		napi_schedule(&priv->napi);
849 	} else {
850 		/* we are closing down, so dont process anything */
851 	}
852 	return IRQ_HANDLED;
853 }
854 
855 static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
856 {
857 	struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size);
858 	if (WARN_ON(!skb))
859 		return NULL;
860 	skb_reserve(skb, NET_IP_ALIGN);
861 	return skb;
862 }
863 
864 static void emac_rx_handler(void *token, int len, int status)
865 {
866 	struct sk_buff		*skb = token;
867 	struct net_device	*ndev = skb->dev;
868 	struct emac_priv	*priv = netdev_priv(ndev);
869 	struct device		*emac_dev = &ndev->dev;
870 	int			ret;
871 
872 	/* free and bail if we are shutting down */
873 	if (unlikely(!netif_running(ndev))) {
874 		dev_kfree_skb_any(skb);
875 		return;
876 	}
877 
878 	/* recycle on receive error */
879 	if (status < 0) {
880 		ndev->stats.rx_errors++;
881 		goto recycle;
882 	}
883 
884 	/* feed received packet up the stack */
885 	skb_put(skb, len);
886 	skb->protocol = eth_type_trans(skb, ndev);
887 	netif_receive_skb(skb);
888 	ndev->stats.rx_bytes += len;
889 	ndev->stats.rx_packets++;
890 
891 	/* alloc a new packet for receive */
892 	skb = emac_rx_alloc(priv);
893 	if (!skb) {
894 		if (netif_msg_rx_err(priv) && net_ratelimit())
895 			dev_err(emac_dev, "failed rx buffer alloc\n");
896 		return;
897 	}
898 
899 recycle:
900 	ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
901 			skb_tailroom(skb), 0);
902 
903 	WARN_ON(ret == -ENOMEM);
904 	if (unlikely(ret < 0))
905 		dev_kfree_skb_any(skb);
906 }
907 
908 static void emac_tx_handler(void *token, int len, int status)
909 {
910 	struct sk_buff		*skb = token;
911 	struct net_device	*ndev = skb->dev;
912 
913 	/* Check whether the queue is stopped due to stalled tx dma, if the
914 	 * queue is stopped then start the queue as we have free desc for tx
915 	 */
916 	if (unlikely(netif_queue_stopped(ndev)))
917 		netif_wake_queue(ndev);
918 	ndev->stats.tx_packets++;
919 	ndev->stats.tx_bytes += len;
920 	dev_kfree_skb_any(skb);
921 }
922 
923 /**
924  * emac_dev_xmit - EMAC Transmit function
925  * @skb: SKB pointer
926  * @ndev: The DaVinci EMAC network adapter
927  *
928  * Called by the system to transmit a packet  - we queue the packet in
929  * EMAC hardware transmit queue
930  *
931  * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
932  */
933 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
934 {
935 	struct device *emac_dev = &ndev->dev;
936 	int ret_code;
937 	struct emac_priv *priv = netdev_priv(ndev);
938 
939 	/* If no link, return */
940 	if (unlikely(!priv->link)) {
941 		if (netif_msg_tx_err(priv) && net_ratelimit())
942 			dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
943 		goto fail_tx;
944 	}
945 
946 	ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
947 	if (unlikely(ret_code < 0)) {
948 		if (netif_msg_tx_err(priv) && net_ratelimit())
949 			dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
950 		goto fail_tx;
951 	}
952 
953 	skb_tx_timestamp(skb);
954 
955 	ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
956 				     0);
957 	if (unlikely(ret_code != 0)) {
958 		if (netif_msg_tx_err(priv) && net_ratelimit())
959 			dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
960 		goto fail_tx;
961 	}
962 
963 	/* If there is no more tx desc left free then we need to
964 	 * tell the kernel to stop sending us tx frames.
965 	 */
966 	if (unlikely(!cpdma_check_free_tx_desc(priv->txchan)))
967 		netif_stop_queue(ndev);
968 
969 	return NETDEV_TX_OK;
970 
971 fail_tx:
972 	ndev->stats.tx_dropped++;
973 	netif_stop_queue(ndev);
974 	return NETDEV_TX_BUSY;
975 }
976 
977 /**
978  * emac_dev_tx_timeout - EMAC Transmit timeout function
979  * @ndev: The DaVinci EMAC network adapter
980  *
981  * Called when system detects that a skb timeout period has expired
982  * potentially due to a fault in the adapter in not being able to send
983  * it out on the wire. We teardown the TX channel assuming a hardware
984  * error and re-initialize the TX channel for hardware operation
985  *
986  */
987 static void emac_dev_tx_timeout(struct net_device *ndev, unsigned int txqueue)
988 {
989 	struct emac_priv *priv = netdev_priv(ndev);
990 	struct device *emac_dev = &ndev->dev;
991 
992 	if (netif_msg_tx_err(priv))
993 		dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
994 
995 	ndev->stats.tx_errors++;
996 	emac_int_disable(priv);
997 	cpdma_chan_stop(priv->txchan);
998 	cpdma_chan_start(priv->txchan);
999 	emac_int_enable(priv);
1000 }
1001 
1002 /**
1003  * emac_set_type0addr - Set EMAC Type0 mac address
1004  * @priv: The DaVinci EMAC private adapter structure
1005  * @ch: RX channel number
1006  * @mac_addr: MAC address to set in device
1007  *
1008  * Called internally to set Type0 mac address of the adapter (Device)
1009  *
1010  * Returns success (0) or appropriate error code (none as of now)
1011  */
1012 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1013 {
1014 	u32 val;
1015 	val = ((mac_addr[5] << 8) | (mac_addr[4]));
1016 	emac_write(EMAC_MACSRCADDRLO, val);
1017 
1018 	val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1019 	       (mac_addr[1] << 8) | (mac_addr[0]));
1020 	emac_write(EMAC_MACSRCADDRHI, val);
1021 	val = emac_read(EMAC_RXUNICASTSET);
1022 	val |= BIT(ch);
1023 	emac_write(EMAC_RXUNICASTSET, val);
1024 	val = emac_read(EMAC_RXUNICASTCLEAR);
1025 	val &= ~BIT(ch);
1026 	emac_write(EMAC_RXUNICASTCLEAR, val);
1027 }
1028 
1029 /**
1030  * emac_set_type1addr - Set EMAC Type1 mac address
1031  * @priv: The DaVinci EMAC private adapter structure
1032  * @ch: RX channel number
1033  * @mac_addr: MAC address to set in device
1034  *
1035  * Called internally to set Type1 mac address of the adapter (Device)
1036  *
1037  * Returns success (0) or appropriate error code (none as of now)
1038  */
1039 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1040 {
1041 	u32 val;
1042 	emac_write(EMAC_MACINDEX, ch);
1043 	val = ((mac_addr[5] << 8) | mac_addr[4]);
1044 	emac_write(EMAC_MACADDRLO, val);
1045 	val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1046 	       (mac_addr[1] << 8) | (mac_addr[0]));
1047 	emac_write(EMAC_MACADDRHI, val);
1048 	emac_set_type0addr(priv, ch, mac_addr);
1049 }
1050 
1051 /**
1052  * emac_set_type2addr - Set EMAC Type2 mac address
1053  * @priv: The DaVinci EMAC private adapter structure
1054  * @ch: RX channel number
1055  * @mac_addr: MAC address to set in device
1056  * @index: index into RX address entries
1057  * @match: match parameter for RX address matching logic
1058  *
1059  * Called internally to set Type2 mac address of the adapter (Device)
1060  *
1061  * Returns success (0) or appropriate error code (none as of now)
1062  */
1063 static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1064 			       char *mac_addr, int index, int match)
1065 {
1066 	u32 val;
1067 	emac_write(EMAC_MACINDEX, index);
1068 	val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1069 	       (mac_addr[1] << 8) | (mac_addr[0]));
1070 	emac_write(EMAC_MACADDRHI, val);
1071 	val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1072 	       (match << 19) | BIT(20));
1073 	emac_write(EMAC_MACADDRLO, val);
1074 	emac_set_type0addr(priv, ch, mac_addr);
1075 }
1076 
1077 /**
1078  * emac_setmac - Set mac address in the adapter (internal function)
1079  * @priv: The DaVinci EMAC private adapter structure
1080  * @ch: RX channel number
1081  * @mac_addr: MAC address to set in device
1082  *
1083  * Called internally to set the mac address of the adapter (Device)
1084  *
1085  * Returns success (0) or appropriate error code (none as of now)
1086  */
1087 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1088 {
1089 	struct device *emac_dev = &priv->ndev->dev;
1090 
1091 	if (priv->rx_addr_type == 0) {
1092 		emac_set_type0addr(priv, ch, mac_addr);
1093 	} else if (priv->rx_addr_type == 1) {
1094 		u32 cnt;
1095 		for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1096 			emac_set_type1addr(priv, ch, mac_addr);
1097 	} else if (priv->rx_addr_type == 2) {
1098 		emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1099 		emac_set_type0addr(priv, ch, mac_addr);
1100 	} else {
1101 		if (netif_msg_drv(priv))
1102 			dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1103 	}
1104 }
1105 
1106 /**
1107  * emac_dev_setmac_addr - Set mac address in the adapter
1108  * @ndev: The DaVinci EMAC network adapter
1109  * @addr: MAC address to set in device
1110  *
1111  * Called by the system to set the mac address of the adapter (Device)
1112  *
1113  * Returns success (0) or appropriate error code (none as of now)
1114  */
1115 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1116 {
1117 	struct emac_priv *priv = netdev_priv(ndev);
1118 	struct device *emac_dev = &priv->ndev->dev;
1119 	struct sockaddr *sa = addr;
1120 
1121 	if (!is_valid_ether_addr(sa->sa_data))
1122 		return -EADDRNOTAVAIL;
1123 
1124 	/* Store mac addr in priv and rx channel and set it in EMAC hw */
1125 	memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1126 	memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1127 
1128 	/* MAC address is configured only after the interface is enabled. */
1129 	if (netif_running(ndev)) {
1130 		emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1131 	}
1132 
1133 	if (netif_msg_drv(priv))
1134 		dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1135 					priv->mac_addr);
1136 
1137 	return 0;
1138 }
1139 
1140 /**
1141  * emac_hw_enable - Enable EMAC hardware for packet transmission/reception
1142  * @priv: The DaVinci EMAC private adapter structure
1143  *
1144  * Enables EMAC hardware for packet processing - enables PHY, enables RX
1145  * for packet reception and enables device interrupts and then NAPI
1146  *
1147  * Returns success (0) or appropriate error code (none right now)
1148  */
1149 static int emac_hw_enable(struct emac_priv *priv)
1150 {
1151 	u32 val, mbp_enable, mac_control;
1152 
1153 	/* Soft reset */
1154 	emac_write(EMAC_SOFTRESET, 1);
1155 	while (emac_read(EMAC_SOFTRESET))
1156 		cpu_relax();
1157 
1158 	/* Disable interrupt & Set pacing for more interrupts initially */
1159 	emac_int_disable(priv);
1160 
1161 	/* Full duplex enable bit set when auto negotiation happens */
1162 	mac_control =
1163 		(((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
1164 		((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
1165 		((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
1166 		((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
1167 	emac_write(EMAC_MACCONTROL, mac_control);
1168 
1169 	mbp_enable =
1170 		(((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
1171 		((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
1172 		 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
1173 		 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
1174 		 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
1175 		 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
1176 		 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
1177 		 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
1178 			EMAC_RXMBP_PROMCH_SHIFT) |
1179 		 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
1180 		 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
1181 			EMAC_RXMBP_BROADCH_SHIFT) |
1182 		 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
1183 		 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
1184 			EMAC_RXMBP_MULTICH_SHIFT));
1185 	emac_write(EMAC_RXMBPENABLE, mbp_enable);
1186 	emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
1187 				   EMAC_RX_MAX_LEN_MASK));
1188 	emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
1189 					 EMAC_RX_BUFFER_OFFSET_MASK));
1190 	emac_write(EMAC_RXFILTERLOWTHRESH, 0);
1191 	emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
1192 	priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
1193 
1194 	emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
1195 
1196 	emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1197 
1198 	/* Enable MII */
1199 	val = emac_read(EMAC_MACCONTROL);
1200 	val |= (EMAC_MACCONTROL_GMIIEN);
1201 	emac_write(EMAC_MACCONTROL, val);
1202 
1203 	/* Enable NAPI and interrupts */
1204 	napi_enable(&priv->napi);
1205 	emac_int_enable(priv);
1206 	return 0;
1207 
1208 }
1209 
1210 /**
1211  * emac_poll - EMAC NAPI Poll function
1212  * @ndev: The DaVinci EMAC network adapter
1213  * @budget: Number of receive packets to process (as told by NAPI layer)
1214  *
1215  * NAPI Poll function implemented to process packets as per budget. We check
1216  * the type of interrupt on the device and accordingly call the TX or RX
1217  * packet processing functions. We follow the budget for RX processing and
1218  * also put a cap on number of TX pkts processed through config param. The
1219  * NAPI schedule function is called if more packets pending.
1220  *
1221  * Returns number of packets received (in most cases; else TX pkts - rarely)
1222  */
1223 static int emac_poll(struct napi_struct *napi, int budget)
1224 {
1225 	unsigned int mask;
1226 	struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
1227 	struct net_device *ndev = priv->ndev;
1228 	struct device *emac_dev = &ndev->dev;
1229 	u32 status = 0;
1230 	u32 num_tx_pkts = 0, num_rx_pkts = 0;
1231 
1232 	/* Check interrupt vectors and call packet processing */
1233 	status = emac_read(EMAC_MACINVECTOR);
1234 
1235 	mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
1236 
1237 	if (priv->version == EMAC_VERSION_2)
1238 		mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
1239 
1240 	if (status & mask) {
1241 		num_tx_pkts = cpdma_chan_process(priv->txchan,
1242 					      EMAC_DEF_TX_MAX_SERVICE);
1243 	} /* TX processing */
1244 
1245 	mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
1246 
1247 	if (priv->version == EMAC_VERSION_2)
1248 		mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
1249 
1250 	if (status & mask) {
1251 		num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
1252 	} /* RX processing */
1253 
1254 	mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
1255 	if (priv->version == EMAC_VERSION_2)
1256 		mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
1257 
1258 	if (unlikely(status & mask)) {
1259 		u32 ch, cause;
1260 		dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
1261 		netif_stop_queue(ndev);
1262 		napi_disable(&priv->napi);
1263 
1264 		status = emac_read(EMAC_MACSTATUS);
1265 		cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
1266 			 EMAC_MACSTATUS_TXERRCODE_SHIFT);
1267 		if (cause) {
1268 			ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
1269 			      EMAC_MACSTATUS_TXERRCH_SHIFT);
1270 			if (net_ratelimit()) {
1271 				dev_err(emac_dev, "TX Host error %s on ch=%d\n",
1272 					&emac_txhost_errcodes[cause][0], ch);
1273 			}
1274 		}
1275 		cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
1276 			 EMAC_MACSTATUS_RXERRCODE_SHIFT);
1277 		if (cause) {
1278 			ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
1279 			      EMAC_MACSTATUS_RXERRCH_SHIFT);
1280 			if (netif_msg_hw(priv) && net_ratelimit())
1281 				dev_err(emac_dev, "RX Host error %s on ch=%d\n",
1282 					&emac_rxhost_errcodes[cause][0], ch);
1283 		}
1284 	} else if (num_rx_pkts < budget) {
1285 		napi_complete_done(napi, num_rx_pkts);
1286 		emac_int_enable(priv);
1287 	}
1288 
1289 	return num_rx_pkts;
1290 }
1291 
1292 #ifdef CONFIG_NET_POLL_CONTROLLER
1293 /**
1294  * emac_poll_controller - EMAC Poll controller function
1295  * @ndev: The DaVinci EMAC network adapter
1296  *
1297  * Polled functionality used by netconsole and others in non interrupt mode
1298  *
1299  */
1300 static void emac_poll_controller(struct net_device *ndev)
1301 {
1302 	struct emac_priv *priv = netdev_priv(ndev);
1303 
1304 	emac_int_disable(priv);
1305 	emac_irq(ndev->irq, ndev);
1306 	emac_int_enable(priv);
1307 }
1308 #endif
1309 
1310 static void emac_adjust_link(struct net_device *ndev)
1311 {
1312 	struct emac_priv *priv = netdev_priv(ndev);
1313 	struct phy_device *phydev = ndev->phydev;
1314 	unsigned long flags;
1315 	int new_state = 0;
1316 
1317 	spin_lock_irqsave(&priv->lock, flags);
1318 
1319 	if (phydev->link) {
1320 		/* check the mode of operation - full/half duplex */
1321 		if (phydev->duplex != priv->duplex) {
1322 			new_state = 1;
1323 			priv->duplex = phydev->duplex;
1324 		}
1325 		if (phydev->speed != priv->speed) {
1326 			new_state = 1;
1327 			priv->speed = phydev->speed;
1328 		}
1329 		if (!priv->link) {
1330 			new_state = 1;
1331 			priv->link = 1;
1332 		}
1333 
1334 	} else if (priv->link) {
1335 		new_state = 1;
1336 		priv->link = 0;
1337 		priv->speed = 0;
1338 		priv->duplex = ~0;
1339 	}
1340 	if (new_state) {
1341 		emac_update_phystatus(priv);
1342 		phy_print_status(ndev->phydev);
1343 	}
1344 
1345 	spin_unlock_irqrestore(&priv->lock, flags);
1346 }
1347 
1348 /*************************************************************************
1349  *  Linux Driver Model
1350  *************************************************************************/
1351 
1352 /**
1353  * emac_devioctl - EMAC adapter ioctl
1354  * @ndev: The DaVinci EMAC network adapter
1355  * @ifrq: request parameter
1356  * @cmd: command parameter
1357  *
1358  * EMAC driver ioctl function
1359  *
1360  * Returns success(0) or appropriate error code
1361  */
1362 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
1363 {
1364 	if (!(netif_running(ndev)))
1365 		return -EINVAL;
1366 
1367 	/* TODO: Add phy read and write and private statistics get feature */
1368 
1369 	if (ndev->phydev)
1370 		return phy_mii_ioctl(ndev->phydev, ifrq, cmd);
1371 	else
1372 		return -EOPNOTSUPP;
1373 }
1374 
1375 static int match_first_device(struct device *dev, const void *data)
1376 {
1377 	if (dev->parent && dev->parent->of_node)
1378 		return of_device_is_compatible(dev->parent->of_node,
1379 					       "ti,davinci_mdio");
1380 
1381 	return !strncmp(dev_name(dev), "davinci_mdio", 12);
1382 }
1383 
1384 /**
1385  * emac_dev_open - EMAC device open
1386  * @ndev: The DaVinci EMAC network adapter
1387  *
1388  * Called when system wants to start the interface. We init TX/RX channels
1389  * and enable the hardware for packet reception/transmission and start the
1390  * network queue.
1391  *
1392  * Returns 0 for a successful open, or appropriate error code
1393  */
1394 static int emac_dev_open(struct net_device *ndev)
1395 {
1396 	struct device *emac_dev = &ndev->dev;
1397 	u32 cnt;
1398 	struct resource *res;
1399 	int q, m, ret;
1400 	int res_num = 0, irq_num = 0;
1401 	int i = 0;
1402 	struct emac_priv *priv = netdev_priv(ndev);
1403 	struct phy_device *phydev = NULL;
1404 	struct device *phy = NULL;
1405 
1406 	ret = pm_runtime_get_sync(&priv->pdev->dev);
1407 	if (ret < 0) {
1408 		pm_runtime_put_noidle(&priv->pdev->dev);
1409 		dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
1410 			__func__, ret);
1411 		return ret;
1412 	}
1413 
1414 	netif_carrier_off(ndev);
1415 	for (cnt = 0; cnt < ETH_ALEN; cnt++)
1416 		ndev->dev_addr[cnt] = priv->mac_addr[cnt];
1417 
1418 	/* Configuration items */
1419 	priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
1420 
1421 	priv->mac_hash1 = 0;
1422 	priv->mac_hash2 = 0;
1423 	emac_write(EMAC_MACHASH1, 0);
1424 	emac_write(EMAC_MACHASH2, 0);
1425 
1426 	for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
1427 		struct sk_buff *skb = emac_rx_alloc(priv);
1428 
1429 		if (!skb)
1430 			break;
1431 
1432 		ret = cpdma_chan_idle_submit(priv->rxchan, skb, skb->data,
1433 					     skb_tailroom(skb), 0);
1434 		if (WARN_ON(ret < 0))
1435 			break;
1436 	}
1437 
1438 	/* Request IRQ */
1439 	while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ,
1440 					    res_num))) {
1441 		for (irq_num = res->start; irq_num <= res->end; irq_num++) {
1442 			if (request_irq(irq_num, emac_irq, 0, ndev->name,
1443 					ndev)) {
1444 				dev_err(emac_dev,
1445 					"DaVinci EMAC: request_irq() failed\n");
1446 				ret = -EBUSY;
1447 
1448 				goto rollback;
1449 			}
1450 		}
1451 		res_num++;
1452 	}
1453 	/* prepare counters for rollback in case of an error */
1454 	res_num--;
1455 	irq_num--;
1456 
1457 	/* Start/Enable EMAC hardware */
1458 	emac_hw_enable(priv);
1459 
1460 	/* Enable Interrupt pacing if configured */
1461 	if (priv->coal_intvl != 0) {
1462 		struct ethtool_coalesce coal;
1463 
1464 		coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1465 		emac_set_coalesce(ndev, &coal);
1466 	}
1467 
1468 	cpdma_ctlr_start(priv->dma);
1469 
1470 	if (priv->phy_node) {
1471 		phydev = of_phy_connect(ndev, priv->phy_node,
1472 					&emac_adjust_link, 0, 0);
1473 		if (!phydev) {
1474 			dev_err(emac_dev, "could not connect to phy %pOF\n",
1475 				priv->phy_node);
1476 			ret = -ENODEV;
1477 			goto err;
1478 		}
1479 	}
1480 
1481 	/* use the first phy on the bus if pdata did not give us a phy id */
1482 	if (!phydev && !priv->phy_id) {
1483 		/* NOTE: we can't use bus_find_device_by_name() here because
1484 		 * the device name is not guaranteed to be 'davinci_mdio'. On
1485 		 * some systems it can be 'davinci_mdio.0' so we need to use
1486 		 * strncmp() against the first part of the string to correctly
1487 		 * match it.
1488 		 */
1489 		phy = bus_find_device(&mdio_bus_type, NULL, NULL,
1490 				      match_first_device);
1491 		if (phy) {
1492 			priv->phy_id = dev_name(phy);
1493 			if (!priv->phy_id || !*priv->phy_id)
1494 				put_device(phy);
1495 		}
1496 	}
1497 
1498 	if (!phydev && priv->phy_id && *priv->phy_id) {
1499 		phydev = phy_connect(ndev, priv->phy_id,
1500 				     &emac_adjust_link,
1501 				     PHY_INTERFACE_MODE_MII);
1502 		put_device(phy);	/* reference taken by bus_find_device */
1503 		if (IS_ERR(phydev)) {
1504 			dev_err(emac_dev, "could not connect to phy %s\n",
1505 				priv->phy_id);
1506 			ret = PTR_ERR(phydev);
1507 			goto err;
1508 		}
1509 
1510 		priv->link = 0;
1511 		priv->speed = 0;
1512 		priv->duplex = ~0;
1513 
1514 		phy_attached_info(phydev);
1515 	}
1516 
1517 	if (!phydev) {
1518 		/* No PHY , fix the link, speed and duplex settings */
1519 		dev_notice(emac_dev, "no phy, defaulting to 100/full\n");
1520 		priv->link = 1;
1521 		priv->speed = SPEED_100;
1522 		priv->duplex = DUPLEX_FULL;
1523 		emac_update_phystatus(priv);
1524 	}
1525 
1526 	if (netif_msg_drv(priv))
1527 		dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
1528 
1529 	if (phydev)
1530 		phy_start(phydev);
1531 
1532 	return 0;
1533 
1534 err:
1535 	emac_int_disable(priv);
1536 	napi_disable(&priv->napi);
1537 
1538 rollback:
1539 	for (q = res_num; q >= 0; q--) {
1540 		res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, q);
1541 		/* at the first iteration, irq_num is already set to the
1542 		 * right value
1543 		 */
1544 		if (q != res_num)
1545 			irq_num = res->end;
1546 
1547 		for (m = irq_num; m >= res->start; m--)
1548 			free_irq(m, ndev);
1549 	}
1550 	cpdma_ctlr_stop(priv->dma);
1551 	pm_runtime_put(&priv->pdev->dev);
1552 	return ret;
1553 }
1554 
1555 /**
1556  * emac_dev_stop - EMAC device stop
1557  * @ndev: The DaVinci EMAC network adapter
1558  *
1559  * Called when system wants to stop or down the interface. We stop the network
1560  * queue, disable interrupts and cleanup TX/RX channels.
1561  *
1562  * We return the statistics in net_device_stats structure pulled from emac
1563  */
1564 static int emac_dev_stop(struct net_device *ndev)
1565 {
1566 	struct resource *res;
1567 	int i = 0;
1568 	int irq_num;
1569 	struct emac_priv *priv = netdev_priv(ndev);
1570 	struct device *emac_dev = &ndev->dev;
1571 
1572 	/* inform the upper layers. */
1573 	netif_stop_queue(ndev);
1574 	napi_disable(&priv->napi);
1575 
1576 	netif_carrier_off(ndev);
1577 	emac_int_disable(priv);
1578 	cpdma_ctlr_stop(priv->dma);
1579 	emac_write(EMAC_SOFTRESET, 1);
1580 
1581 	if (ndev->phydev)
1582 		phy_disconnect(ndev->phydev);
1583 
1584 	/* Free IRQ */
1585 	while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
1586 		for (irq_num = res->start; irq_num <= res->end; irq_num++)
1587 			free_irq(irq_num, priv->ndev);
1588 		i++;
1589 	}
1590 
1591 	if (netif_msg_drv(priv))
1592 		dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
1593 
1594 	pm_runtime_put(&priv->pdev->dev);
1595 	return 0;
1596 }
1597 
1598 /**
1599  * emac_dev_getnetstats - EMAC get statistics function
1600  * @ndev: The DaVinci EMAC network adapter
1601  *
1602  * Called when system wants to get statistics from the device.
1603  *
1604  * We return the statistics in net_device_stats structure pulled from emac
1605  */
1606 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
1607 {
1608 	struct emac_priv *priv = netdev_priv(ndev);
1609 	u32 mac_control;
1610 	u32 stats_clear_mask;
1611 	int err;
1612 
1613 	err = pm_runtime_get_sync(&priv->pdev->dev);
1614 	if (err < 0) {
1615 		pm_runtime_put_noidle(&priv->pdev->dev);
1616 		dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
1617 			__func__, err);
1618 		return &ndev->stats;
1619 	}
1620 
1621 	/* update emac hardware stats and reset the registers*/
1622 
1623 	mac_control = emac_read(EMAC_MACCONTROL);
1624 
1625 	if (mac_control & EMAC_MACCONTROL_GMIIEN)
1626 		stats_clear_mask = EMAC_STATS_CLR_MASK;
1627 	else
1628 		stats_clear_mask = 0;
1629 
1630 	ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
1631 	emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
1632 
1633 	ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
1634 					   emac_read(EMAC_TXSINGLECOLL) +
1635 					   emac_read(EMAC_TXMULTICOLL));
1636 	emac_write(EMAC_TXCOLLISION, stats_clear_mask);
1637 	emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
1638 	emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
1639 
1640 	ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
1641 						emac_read(EMAC_RXJABBER) +
1642 						emac_read(EMAC_RXUNDERSIZED));
1643 	emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
1644 	emac_write(EMAC_RXJABBER, stats_clear_mask);
1645 	emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
1646 
1647 	ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
1648 					       emac_read(EMAC_RXMOFOVERRUNS));
1649 	emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
1650 	emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
1651 
1652 	ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
1653 	emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
1654 
1655 	ndev->stats.tx_carrier_errors +=
1656 		emac_read(EMAC_TXCARRIERSENSE);
1657 	emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
1658 
1659 	ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN);
1660 	emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
1661 
1662 	pm_runtime_put(&priv->pdev->dev);
1663 
1664 	return &ndev->stats;
1665 }
1666 
1667 static const struct net_device_ops emac_netdev_ops = {
1668 	.ndo_open		= emac_dev_open,
1669 	.ndo_stop		= emac_dev_stop,
1670 	.ndo_start_xmit		= emac_dev_xmit,
1671 	.ndo_set_rx_mode	= emac_dev_mcast_set,
1672 	.ndo_set_mac_address	= emac_dev_setmac_addr,
1673 	.ndo_do_ioctl		= emac_devioctl,
1674 	.ndo_tx_timeout		= emac_dev_tx_timeout,
1675 	.ndo_get_stats		= emac_dev_getnetstats,
1676 #ifdef CONFIG_NET_POLL_CONTROLLER
1677 	.ndo_poll_controller	= emac_poll_controller,
1678 #endif
1679 };
1680 
1681 static const struct of_device_id davinci_emac_of_match[];
1682 
1683 static struct emac_platform_data *
1684 davinci_emac_of_get_pdata(struct platform_device *pdev, struct emac_priv *priv)
1685 {
1686 	struct device_node *np;
1687 	const struct of_device_id *match;
1688 	const struct emac_platform_data *auxdata;
1689 	struct emac_platform_data *pdata = NULL;
1690 	const u8 *mac_addr;
1691 
1692 	if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
1693 		return dev_get_platdata(&pdev->dev);
1694 
1695 	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1696 	if (!pdata)
1697 		return NULL;
1698 
1699 	np = pdev->dev.of_node;
1700 	pdata->version = EMAC_VERSION_2;
1701 
1702 	if (!is_valid_ether_addr(pdata->mac_addr)) {
1703 		mac_addr = of_get_mac_address(np);
1704 		if (!IS_ERR(mac_addr))
1705 			ether_addr_copy(pdata->mac_addr, mac_addr);
1706 	}
1707 
1708 	of_property_read_u32(np, "ti,davinci-ctrl-reg-offset",
1709 			     &pdata->ctrl_reg_offset);
1710 
1711 	of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset",
1712 			     &pdata->ctrl_mod_reg_offset);
1713 
1714 	of_property_read_u32(np, "ti,davinci-ctrl-ram-offset",
1715 			     &pdata->ctrl_ram_offset);
1716 
1717 	of_property_read_u32(np, "ti,davinci-ctrl-ram-size",
1718 			     &pdata->ctrl_ram_size);
1719 
1720 	of_property_read_u8(np, "ti,davinci-rmii-en", &pdata->rmii_en);
1721 
1722 	pdata->no_bd_ram = of_property_read_bool(np, "ti,davinci-no-bd-ram");
1723 
1724 	priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
1725 	if (!priv->phy_node) {
1726 		if (!of_phy_is_fixed_link(np))
1727 			pdata->phy_id = NULL;
1728 		else if (of_phy_register_fixed_link(np) >= 0)
1729 			priv->phy_node = of_node_get(np);
1730 	}
1731 
1732 	auxdata = pdev->dev.platform_data;
1733 	if (auxdata) {
1734 		pdata->interrupt_enable = auxdata->interrupt_enable;
1735 		pdata->interrupt_disable = auxdata->interrupt_disable;
1736 	}
1737 
1738 	match = of_match_device(davinci_emac_of_match, &pdev->dev);
1739 	if (match && match->data) {
1740 		auxdata = match->data;
1741 		pdata->version = auxdata->version;
1742 		pdata->hw_ram_addr = auxdata->hw_ram_addr;
1743 	}
1744 
1745 	return  pdata;
1746 }
1747 
1748 static int davinci_emac_try_get_mac(struct platform_device *pdev,
1749 				    int instance, u8 *mac_addr)
1750 {
1751 	if (!pdev->dev.of_node)
1752 		return -EINVAL;
1753 
1754 	return ti_cm_get_macid(&pdev->dev, instance, mac_addr);
1755 }
1756 
1757 /**
1758  * davinci_emac_probe - EMAC device probe
1759  * @pdev: The DaVinci EMAC device that we are removing
1760  *
1761  * Called when probing for emac devicesr. We get details of instances and
1762  * resource information from platform init and register a network device
1763  * and allocate resources necessary for driver to perform
1764  */
1765 static int davinci_emac_probe(struct platform_device *pdev)
1766 {
1767 	struct device_node *np = pdev->dev.of_node;
1768 	int rc = 0;
1769 	struct resource *res, *res_ctrl;
1770 	struct net_device *ndev;
1771 	struct emac_priv *priv;
1772 	unsigned long hw_ram_addr;
1773 	struct emac_platform_data *pdata;
1774 	struct cpdma_params dma_params;
1775 	struct clk *emac_clk;
1776 	unsigned long emac_bus_frequency;
1777 
1778 
1779 	/* obtain emac clock from kernel */
1780 	emac_clk = devm_clk_get(&pdev->dev, NULL);
1781 	if (IS_ERR(emac_clk)) {
1782 		dev_err(&pdev->dev, "failed to get EMAC clock\n");
1783 		return -EBUSY;
1784 	}
1785 	emac_bus_frequency = clk_get_rate(emac_clk);
1786 	devm_clk_put(&pdev->dev, emac_clk);
1787 
1788 	/* TODO: Probe PHY here if possible */
1789 
1790 	ndev = alloc_etherdev(sizeof(struct emac_priv));
1791 	if (!ndev)
1792 		return -ENOMEM;
1793 
1794 	platform_set_drvdata(pdev, ndev);
1795 	priv = netdev_priv(ndev);
1796 	priv->pdev = pdev;
1797 	priv->ndev = ndev;
1798 	priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
1799 
1800 	spin_lock_init(&priv->lock);
1801 
1802 	pdata = davinci_emac_of_get_pdata(pdev, priv);
1803 	if (!pdata) {
1804 		dev_err(&pdev->dev, "no platform data\n");
1805 		rc = -ENODEV;
1806 		goto err_free_netdev;
1807 	}
1808 
1809 	/* MAC addr and PHY mask , RMII enable info from platform_data */
1810 	memcpy(priv->mac_addr, pdata->mac_addr, ETH_ALEN);
1811 	priv->phy_id = pdata->phy_id;
1812 	priv->rmii_en = pdata->rmii_en;
1813 	priv->version = pdata->version;
1814 	priv->int_enable = pdata->interrupt_enable;
1815 	priv->int_disable = pdata->interrupt_disable;
1816 
1817 	priv->coal_intvl = 0;
1818 	priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);
1819 
1820 	/* Get EMAC platform data */
1821 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1822 	priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
1823 	priv->remap_addr = devm_ioremap_resource(&pdev->dev, res);
1824 	if (IS_ERR(priv->remap_addr)) {
1825 		rc = PTR_ERR(priv->remap_addr);
1826 		goto no_pdata;
1827 	}
1828 
1829 	res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1830 	if (res_ctrl) {
1831 		priv->ctrl_base =
1832 			devm_ioremap_resource(&pdev->dev, res_ctrl);
1833 		if (IS_ERR(priv->ctrl_base)) {
1834 			rc = PTR_ERR(priv->ctrl_base);
1835 			goto no_pdata;
1836 		}
1837 	} else {
1838 		priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
1839 	}
1840 
1841 	priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
1842 	ndev->base_addr = (unsigned long)priv->remap_addr;
1843 
1844 	hw_ram_addr = pdata->hw_ram_addr;
1845 	if (!hw_ram_addr)
1846 		hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
1847 
1848 	memset(&dma_params, 0, sizeof(dma_params));
1849 	dma_params.dev			= &pdev->dev;
1850 	dma_params.dmaregs		= priv->emac_base;
1851 	dma_params.rxthresh		= priv->emac_base + 0x120;
1852 	dma_params.rxfree		= priv->emac_base + 0x140;
1853 	dma_params.txhdp		= priv->emac_base + 0x600;
1854 	dma_params.rxhdp		= priv->emac_base + 0x620;
1855 	dma_params.txcp			= priv->emac_base + 0x640;
1856 	dma_params.rxcp			= priv->emac_base + 0x660;
1857 	dma_params.num_chan		= EMAC_MAX_TXRX_CHANNELS;
1858 	dma_params.min_packet_size	= EMAC_DEF_MIN_ETHPKTSIZE;
1859 	dma_params.desc_hw_addr		= hw_ram_addr;
1860 	dma_params.desc_mem_size	= pdata->ctrl_ram_size;
1861 	dma_params.desc_align		= 16;
1862 
1863 	dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :
1864 			(u32 __force)res->start + pdata->ctrl_ram_offset;
1865 
1866 	priv->dma = cpdma_ctlr_create(&dma_params);
1867 	if (!priv->dma) {
1868 		dev_err(&pdev->dev, "error initializing DMA\n");
1869 		rc = -ENOMEM;
1870 		goto no_pdata;
1871 	}
1872 
1873 	priv->txchan = cpdma_chan_create(priv->dma, EMAC_DEF_TX_CH,
1874 					 emac_tx_handler, 0);
1875 	if (IS_ERR(priv->txchan)) {
1876 		dev_err(&pdev->dev, "error initializing tx dma channel\n");
1877 		rc = PTR_ERR(priv->txchan);
1878 		goto err_free_dma;
1879 	}
1880 
1881 	priv->rxchan = cpdma_chan_create(priv->dma, EMAC_DEF_RX_CH,
1882 					 emac_rx_handler, 1);
1883 	if (IS_ERR(priv->rxchan)) {
1884 		dev_err(&pdev->dev, "error initializing rx dma channel\n");
1885 		rc = PTR_ERR(priv->rxchan);
1886 		goto err_free_txchan;
1887 	}
1888 
1889 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1890 	if (!res) {
1891 		dev_err(&pdev->dev, "error getting irq res\n");
1892 		rc = -ENOENT;
1893 		goto err_free_rxchan;
1894 	}
1895 	ndev->irq = res->start;
1896 
1897 	rc = davinci_emac_try_get_mac(pdev, res_ctrl ? 0 : 1, priv->mac_addr);
1898 	if (!rc)
1899 		ether_addr_copy(ndev->dev_addr, priv->mac_addr);
1900 
1901 	if (!is_valid_ether_addr(priv->mac_addr)) {
1902 		/* Use random MAC if still none obtained. */
1903 		eth_hw_addr_random(ndev);
1904 		memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len);
1905 		dev_warn(&pdev->dev, "using random MAC addr: %pM\n",
1906 			 priv->mac_addr);
1907 	}
1908 
1909 	ndev->netdev_ops = &emac_netdev_ops;
1910 	ndev->ethtool_ops = &ethtool_ops;
1911 	netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
1912 
1913 	pm_runtime_enable(&pdev->dev);
1914 	rc = pm_runtime_get_sync(&pdev->dev);
1915 	if (rc < 0) {
1916 		pm_runtime_put_noidle(&pdev->dev);
1917 		dev_err(&pdev->dev, "%s: failed to get_sync(%d)\n",
1918 			__func__, rc);
1919 		goto err_napi_del;
1920 	}
1921 
1922 	/* register the network device */
1923 	SET_NETDEV_DEV(ndev, &pdev->dev);
1924 	rc = register_netdev(ndev);
1925 	if (rc) {
1926 		dev_err(&pdev->dev, "error in register_netdev\n");
1927 		rc = -ENODEV;
1928 		pm_runtime_put(&pdev->dev);
1929 		goto err_napi_del;
1930 	}
1931 
1932 
1933 	if (netif_msg_probe(priv)) {
1934 		dev_notice(&pdev->dev, "DaVinci EMAC Probe found device "
1935 			   "(regs: %pa, irq: %d)\n",
1936 			   &priv->emac_base_phys, ndev->irq);
1937 	}
1938 	pm_runtime_put(&pdev->dev);
1939 
1940 	return 0;
1941 
1942 err_napi_del:
1943 	netif_napi_del(&priv->napi);
1944 err_free_rxchan:
1945 	cpdma_chan_destroy(priv->rxchan);
1946 err_free_txchan:
1947 	cpdma_chan_destroy(priv->txchan);
1948 err_free_dma:
1949 	cpdma_ctlr_destroy(priv->dma);
1950 no_pdata:
1951 	if (of_phy_is_fixed_link(np))
1952 		of_phy_deregister_fixed_link(np);
1953 	of_node_put(priv->phy_node);
1954 err_free_netdev:
1955 	free_netdev(ndev);
1956 	return rc;
1957 }
1958 
1959 /**
1960  * davinci_emac_remove - EMAC device remove
1961  * @pdev: The DaVinci EMAC device that we are removing
1962  *
1963  * Called when removing the device driver. We disable clock usage and release
1964  * the resources taken up by the driver and unregister network device
1965  */
1966 static int davinci_emac_remove(struct platform_device *pdev)
1967 {
1968 	struct net_device *ndev = platform_get_drvdata(pdev);
1969 	struct emac_priv *priv = netdev_priv(ndev);
1970 	struct device_node *np = pdev->dev.of_node;
1971 
1972 	dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
1973 
1974 	if (priv->txchan)
1975 		cpdma_chan_destroy(priv->txchan);
1976 	if (priv->rxchan)
1977 		cpdma_chan_destroy(priv->rxchan);
1978 	cpdma_ctlr_destroy(priv->dma);
1979 
1980 	unregister_netdev(ndev);
1981 	of_node_put(priv->phy_node);
1982 	pm_runtime_disable(&pdev->dev);
1983 	if (of_phy_is_fixed_link(np))
1984 		of_phy_deregister_fixed_link(np);
1985 	free_netdev(ndev);
1986 
1987 	return 0;
1988 }
1989 
1990 static int davinci_emac_suspend(struct device *dev)
1991 {
1992 	struct net_device *ndev = dev_get_drvdata(dev);
1993 
1994 	if (netif_running(ndev))
1995 		emac_dev_stop(ndev);
1996 
1997 	return 0;
1998 }
1999 
2000 static int davinci_emac_resume(struct device *dev)
2001 {
2002 	struct net_device *ndev = dev_get_drvdata(dev);
2003 
2004 	if (netif_running(ndev))
2005 		emac_dev_open(ndev);
2006 
2007 	return 0;
2008 }
2009 
2010 static const struct dev_pm_ops davinci_emac_pm_ops = {
2011 	.suspend	= davinci_emac_suspend,
2012 	.resume		= davinci_emac_resume,
2013 };
2014 
2015 static const struct emac_platform_data am3517_emac_data = {
2016 	.version		= EMAC_VERSION_2,
2017 	.hw_ram_addr		= 0x01e20000,
2018 };
2019 
2020 static const struct emac_platform_data dm816_emac_data = {
2021 	.version		= EMAC_VERSION_2,
2022 };
2023 
2024 static const struct of_device_id davinci_emac_of_match[] = {
2025 	{.compatible = "ti,davinci-dm6467-emac", },
2026 	{.compatible = "ti,am3517-emac", .data = &am3517_emac_data, },
2027 	{.compatible = "ti,dm816-emac", .data = &dm816_emac_data, },
2028 	{},
2029 };
2030 MODULE_DEVICE_TABLE(of, davinci_emac_of_match);
2031 
2032 /* davinci_emac_driver: EMAC platform driver structure */
2033 static struct platform_driver davinci_emac_driver = {
2034 	.driver = {
2035 		.name	 = "davinci_emac",
2036 		.pm	 = &davinci_emac_pm_ops,
2037 		.of_match_table = davinci_emac_of_match,
2038 	},
2039 	.probe = davinci_emac_probe,
2040 	.remove = davinci_emac_remove,
2041 };
2042 
2043 /**
2044  * davinci_emac_init - EMAC driver module init
2045  *
2046  * Called when initializing the driver. We register the driver with
2047  * the platform.
2048  */
2049 static int __init davinci_emac_init(void)
2050 {
2051 	return platform_driver_register(&davinci_emac_driver);
2052 }
2053 late_initcall(davinci_emac_init);
2054 
2055 /**
2056  * davinci_emac_exit - EMAC driver module exit
2057  *
2058  * Called when exiting the driver completely. We unregister the driver with
2059  * the platform and exit
2060  */
2061 static void __exit davinci_emac_exit(void)
2062 {
2063 	platform_driver_unregister(&davinci_emac_driver);
2064 }
2065 module_exit(davinci_emac_exit);
2066 
2067 MODULE_LICENSE("GPL");
2068 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2069 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2070 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");
2071