1 /* 2 * DaVinci Ethernet Medium Access Controller 3 * 4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine 5 * 6 * Copyright (C) 2009 Texas Instruments. 7 * 8 * --------------------------------------------------------------------------- 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 * --------------------------------------------------------------------------- 24 * History: 25 * 0-5 A number of folks worked on this driver in bits and pieces but the major 26 * contribution came from Suraj Iyer and Anant Gole 27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions 28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features, 29 * PHY layer usage 30 */ 31 32 #include <linux/module.h> 33 #include <linux/kernel.h> 34 #include <linux/sched.h> 35 #include <linux/string.h> 36 #include <linux/timer.h> 37 #include <linux/errno.h> 38 #include <linux/in.h> 39 #include <linux/ioport.h> 40 #include <linux/slab.h> 41 #include <linux/mm.h> 42 #include <linux/interrupt.h> 43 #include <linux/init.h> 44 #include <linux/netdevice.h> 45 #include <linux/etherdevice.h> 46 #include <linux/skbuff.h> 47 #include <linux/ethtool.h> 48 #include <linux/highmem.h> 49 #include <linux/proc_fs.h> 50 #include <linux/ctype.h> 51 #include <linux/spinlock.h> 52 #include <linux/dma-mapping.h> 53 #include <linux/clk.h> 54 #include <linux/platform_device.h> 55 #include <linux/semaphore.h> 56 #include <linux/phy.h> 57 #include <linux/bitops.h> 58 #include <linux/io.h> 59 #include <linux/uaccess.h> 60 #include <linux/pm_runtime.h> 61 #include <linux/davinci_emac.h> 62 #include <linux/of.h> 63 #include <linux/of_address.h> 64 #include <linux/of_irq.h> 65 #include <linux/of_net.h> 66 67 #include <asm/irq.h> 68 #include <asm/page.h> 69 70 #include "davinci_cpdma.h" 71 72 static int debug_level; 73 module_param(debug_level, int, 0); 74 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)"); 75 76 /* Netif debug messages possible */ 77 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \ 78 NETIF_MSG_PROBE | \ 79 NETIF_MSG_LINK | \ 80 NETIF_MSG_TIMER | \ 81 NETIF_MSG_IFDOWN | \ 82 NETIF_MSG_IFUP | \ 83 NETIF_MSG_RX_ERR | \ 84 NETIF_MSG_TX_ERR | \ 85 NETIF_MSG_TX_QUEUED | \ 86 NETIF_MSG_INTR | \ 87 NETIF_MSG_TX_DONE | \ 88 NETIF_MSG_RX_STATUS | \ 89 NETIF_MSG_PKTDATA | \ 90 NETIF_MSG_HW | \ 91 NETIF_MSG_WOL) 92 93 /* version info */ 94 #define EMAC_MAJOR_VERSION 6 95 #define EMAC_MINOR_VERSION 1 96 #define EMAC_MODULE_VERSION "6.1" 97 MODULE_VERSION(EMAC_MODULE_VERSION); 98 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1"; 99 100 /* Configuration items */ 101 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */ 102 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */ 103 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */ 104 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */ 105 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */ 106 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */ 107 #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */ 108 #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */ 109 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */ 110 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */ 111 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */ 112 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */ 113 114 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */ 115 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/ 116 117 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */ 118 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */ 119 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4) 120 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */ 121 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */ 122 #define EMAC_DEF_RX_NUM_DESC (128) 123 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */ 124 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */ 125 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */ 126 127 /* Buffer descriptor parameters */ 128 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */ 129 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */ 130 131 /* EMAC register related defines */ 132 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF) 133 #define EMAC_NUM_MULTICAST_BITS (64) 134 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1) 135 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1) 136 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2) 137 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF) 138 #define EMAC_INT_MASK_CLEAR (0xFF) 139 140 /* RX MBP register bit positions */ 141 #define EMAC_RXMBP_PASSCRC_MASK BIT(30) 142 #define EMAC_RXMBP_QOSEN_MASK BIT(29) 143 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28) 144 #define EMAC_RXMBP_CMFEN_MASK BIT(24) 145 #define EMAC_RXMBP_CSFEN_MASK BIT(23) 146 #define EMAC_RXMBP_CEFEN_MASK BIT(22) 147 #define EMAC_RXMBP_CAFEN_MASK BIT(21) 148 #define EMAC_RXMBP_PROMCH_SHIFT (16) 149 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16) 150 #define EMAC_RXMBP_BROADEN_MASK BIT(13) 151 #define EMAC_RXMBP_BROADCH_SHIFT (8) 152 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8) 153 #define EMAC_RXMBP_MULTIEN_MASK BIT(5) 154 #define EMAC_RXMBP_MULTICH_SHIFT (0) 155 #define EMAC_RXMBP_MULTICH_MASK (0x7) 156 #define EMAC_RXMBP_CHMASK (0x7) 157 158 /* EMAC register definitions/bit maps used */ 159 # define EMAC_MBP_RXPROMISC (0x00200000) 160 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16) 161 # define EMAC_MBP_RXBCAST (0x00002000) 162 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8) 163 # define EMAC_MBP_RXMCAST (0x00000020) 164 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7) 165 166 /* EMAC mac_control register */ 167 #define EMAC_MACCONTROL_TXPTYPE BIT(9) 168 #define EMAC_MACCONTROL_TXPACEEN BIT(6) 169 #define EMAC_MACCONTROL_GMIIEN BIT(5) 170 #define EMAC_MACCONTROL_GIGABITEN BIT(7) 171 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0) 172 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15) 173 174 /* GIGABIT MODE related bits */ 175 #define EMAC_DM646X_MACCONTORL_GIG BIT(7) 176 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17) 177 178 /* EMAC mac_status register */ 179 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000) 180 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20) 181 #define EMAC_MACSTATUS_TXERRCH_MASK (0x7) 182 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16) 183 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000) 184 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12) 185 #define EMAC_MACSTATUS_RXERRCH_MASK (0x7) 186 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8) 187 188 /* EMAC RX register masks */ 189 #define EMAC_RX_MAX_LEN_MASK (0xFFFF) 190 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF) 191 192 /* MAC_IN_VECTOR (0x180) register bit fields */ 193 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17) 194 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16) 195 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8) 196 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0) 197 198 /** NOTE:: For DM646x the IN_VECTOR has changed */ 199 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH) 200 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH) 201 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26) 202 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27) 203 204 /* CPPI bit positions */ 205 #define EMAC_CPPI_SOP_BIT BIT(31) 206 #define EMAC_CPPI_EOP_BIT BIT(30) 207 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29) 208 #define EMAC_CPPI_EOQ_BIT BIT(28) 209 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27) 210 #define EMAC_CPPI_PASS_CRC_BIT BIT(26) 211 #define EMAC_RX_BD_BUF_SIZE (0xFFFF) 212 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */ 213 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF) 214 215 /* Max hardware defines */ 216 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */ 217 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */ 218 219 /* EMAC Peripheral Device Register Memory Layout structure */ 220 #define EMAC_MACINVECTOR 0x90 221 222 #define EMAC_DM646X_MACEOIVECTOR 0x94 223 224 #define EMAC_MACINTSTATRAW 0xB0 225 #define EMAC_MACINTSTATMASKED 0xB4 226 #define EMAC_MACINTMASKSET 0xB8 227 #define EMAC_MACINTMASKCLEAR 0xBC 228 229 #define EMAC_RXMBPENABLE 0x100 230 #define EMAC_RXUNICASTSET 0x104 231 #define EMAC_RXUNICASTCLEAR 0x108 232 #define EMAC_RXMAXLEN 0x10C 233 #define EMAC_RXBUFFEROFFSET 0x110 234 #define EMAC_RXFILTERLOWTHRESH 0x114 235 236 #define EMAC_MACCONTROL 0x160 237 #define EMAC_MACSTATUS 0x164 238 #define EMAC_EMCONTROL 0x168 239 #define EMAC_FIFOCONTROL 0x16C 240 #define EMAC_MACCONFIG 0x170 241 #define EMAC_SOFTRESET 0x174 242 #define EMAC_MACSRCADDRLO 0x1D0 243 #define EMAC_MACSRCADDRHI 0x1D4 244 #define EMAC_MACHASH1 0x1D8 245 #define EMAC_MACHASH2 0x1DC 246 #define EMAC_MACADDRLO 0x500 247 #define EMAC_MACADDRHI 0x504 248 #define EMAC_MACINDEX 0x508 249 250 /* EMAC statistics registers */ 251 #define EMAC_RXGOODFRAMES 0x200 252 #define EMAC_RXBCASTFRAMES 0x204 253 #define EMAC_RXMCASTFRAMES 0x208 254 #define EMAC_RXPAUSEFRAMES 0x20C 255 #define EMAC_RXCRCERRORS 0x210 256 #define EMAC_RXALIGNCODEERRORS 0x214 257 #define EMAC_RXOVERSIZED 0x218 258 #define EMAC_RXJABBER 0x21C 259 #define EMAC_RXUNDERSIZED 0x220 260 #define EMAC_RXFRAGMENTS 0x224 261 #define EMAC_RXFILTERED 0x228 262 #define EMAC_RXQOSFILTERED 0x22C 263 #define EMAC_RXOCTETS 0x230 264 #define EMAC_TXGOODFRAMES 0x234 265 #define EMAC_TXBCASTFRAMES 0x238 266 #define EMAC_TXMCASTFRAMES 0x23C 267 #define EMAC_TXPAUSEFRAMES 0x240 268 #define EMAC_TXDEFERRED 0x244 269 #define EMAC_TXCOLLISION 0x248 270 #define EMAC_TXSINGLECOLL 0x24C 271 #define EMAC_TXMULTICOLL 0x250 272 #define EMAC_TXEXCESSIVECOLL 0x254 273 #define EMAC_TXLATECOLL 0x258 274 #define EMAC_TXUNDERRUN 0x25C 275 #define EMAC_TXCARRIERSENSE 0x260 276 #define EMAC_TXOCTETS 0x264 277 #define EMAC_NETOCTETS 0x280 278 #define EMAC_RXSOFOVERRUNS 0x284 279 #define EMAC_RXMOFOVERRUNS 0x288 280 #define EMAC_RXDMAOVERRUNS 0x28C 281 282 /* EMAC DM644x control registers */ 283 #define EMAC_CTRL_EWCTL (0x4) 284 #define EMAC_CTRL_EWINTTCNT (0x8) 285 286 /* EMAC DM644x control module masks */ 287 #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF 288 #define EMAC_DM644X_INTMIN_INTVL 0x1 289 #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK) 290 291 /* EMAC DM646X control module registers */ 292 #define EMAC_DM646X_CMINTCTRL 0x0C 293 #define EMAC_DM646X_CMRXINTEN 0x14 294 #define EMAC_DM646X_CMTXINTEN 0x18 295 #define EMAC_DM646X_CMRXINTMAX 0x70 296 #define EMAC_DM646X_CMTXINTMAX 0x74 297 298 /* EMAC DM646X control module masks */ 299 #define EMAC_DM646X_INTPACEEN (0x3 << 16) 300 #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0) 301 #define EMAC_DM646X_CMINTMAX_CNT 63 302 #define EMAC_DM646X_CMINTMIN_CNT 2 303 #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT) 304 #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1) 305 306 307 /* EMAC EOI codes for C0 */ 308 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01) 309 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02) 310 311 /* EMAC Stats Clear Mask */ 312 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF) 313 314 /* emac_priv: EMAC private data structure 315 * 316 * EMAC adapter private data structure 317 */ 318 struct emac_priv { 319 u32 msg_enable; 320 struct net_device *ndev; 321 struct platform_device *pdev; 322 struct napi_struct napi; 323 char mac_addr[6]; 324 void __iomem *remap_addr; 325 u32 emac_base_phys; 326 void __iomem *emac_base; 327 void __iomem *ctrl_base; 328 struct cpdma_ctlr *dma; 329 struct cpdma_chan *txchan; 330 struct cpdma_chan *rxchan; 331 u32 link; /* 1=link on, 0=link off */ 332 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */ 333 u32 duplex; /* Link duplex: 0=Half, 1=Full */ 334 u32 rx_buf_size; 335 u32 isr_count; 336 u32 coal_intvl; 337 u32 bus_freq_mhz; 338 u8 rmii_en; 339 u8 version; 340 u32 mac_hash1; 341 u32 mac_hash2; 342 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS]; 343 u32 rx_addr_type; 344 const char *phy_id; 345 #ifdef CONFIG_OF 346 struct device_node *phy_node; 347 #endif 348 struct phy_device *phydev; 349 spinlock_t lock; 350 /*platform specific members*/ 351 void (*int_enable) (void); 352 void (*int_disable) (void); 353 }; 354 355 /* EMAC TX Host Error description strings */ 356 static char *emac_txhost_errcodes[16] = { 357 "No error", "SOP error", "Ownership bit not set in SOP buffer", 358 "Zero Next Buffer Descriptor Pointer Without EOP", 359 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error", 360 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", 361 "Reserved", "Reserved", "Reserved", "Reserved" 362 }; 363 364 /* EMAC RX Host Error description strings */ 365 static char *emac_rxhost_errcodes[16] = { 366 "No error", "Reserved", "Ownership bit not set in input buffer", 367 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved", 368 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", 369 "Reserved", "Reserved", "Reserved", "Reserved" 370 }; 371 372 /* Helper macros */ 373 #define emac_read(reg) ioread32(priv->emac_base + (reg)) 374 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg)) 375 376 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg))) 377 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg))) 378 379 /** 380 * emac_dump_regs - Dump important EMAC registers to debug terminal 381 * @priv: The DaVinci EMAC private adapter structure 382 * 383 * Executes ethtool set cmd & sets phy mode 384 * 385 */ 386 static void emac_dump_regs(struct emac_priv *priv) 387 { 388 struct device *emac_dev = &priv->ndev->dev; 389 390 /* Print important registers in EMAC */ 391 dev_info(emac_dev, "EMAC Basic registers\n"); 392 if (priv->version == EMAC_VERSION_1) { 393 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n", 394 emac_ctrl_read(EMAC_CTRL_EWCTL), 395 emac_ctrl_read(EMAC_CTRL_EWINTTCNT)); 396 } 397 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n", 398 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL)); 399 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\ 400 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE), 401 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN)); 402 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\ 403 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL), 404 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG)); 405 dev_info(emac_dev, "EMAC Statistics\n"); 406 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n", 407 emac_read(EMAC_RXGOODFRAMES)); 408 dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n", 409 emac_read(EMAC_RXBCASTFRAMES)); 410 dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n", 411 emac_read(EMAC_RXMCASTFRAMES)); 412 dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n", 413 emac_read(EMAC_RXPAUSEFRAMES)); 414 dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n", 415 emac_read(EMAC_RXCRCERRORS)); 416 dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n", 417 emac_read(EMAC_RXALIGNCODEERRORS)); 418 dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n", 419 emac_read(EMAC_RXOVERSIZED)); 420 dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n", 421 emac_read(EMAC_RXJABBER)); 422 dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n", 423 emac_read(EMAC_RXUNDERSIZED)); 424 dev_info(emac_dev, "EMAC: rx_fragments:%d\n", 425 emac_read(EMAC_RXFRAGMENTS)); 426 dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n", 427 emac_read(EMAC_RXFILTERED)); 428 dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n", 429 emac_read(EMAC_RXQOSFILTERED)); 430 dev_info(emac_dev, "EMAC: rx_octets:%d\n", 431 emac_read(EMAC_RXOCTETS)); 432 dev_info(emac_dev, "EMAC: tx_goodframes:%d\n", 433 emac_read(EMAC_TXGOODFRAMES)); 434 dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n", 435 emac_read(EMAC_TXBCASTFRAMES)); 436 dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n", 437 emac_read(EMAC_TXMCASTFRAMES)); 438 dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n", 439 emac_read(EMAC_TXPAUSEFRAMES)); 440 dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n", 441 emac_read(EMAC_TXDEFERRED)); 442 dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n", 443 emac_read(EMAC_TXCOLLISION)); 444 dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n", 445 emac_read(EMAC_TXSINGLECOLL)); 446 dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n", 447 emac_read(EMAC_TXMULTICOLL)); 448 dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n", 449 emac_read(EMAC_TXEXCESSIVECOLL)); 450 dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n", 451 emac_read(EMAC_TXLATECOLL)); 452 dev_info(emac_dev, "EMAC: tx_underrun:%d\n", 453 emac_read(EMAC_TXUNDERRUN)); 454 dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n", 455 emac_read(EMAC_TXCARRIERSENSE)); 456 dev_info(emac_dev, "EMAC: tx_octets:%d\n", 457 emac_read(EMAC_TXOCTETS)); 458 dev_info(emac_dev, "EMAC: net_octets:%d\n", 459 emac_read(EMAC_NETOCTETS)); 460 dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n", 461 emac_read(EMAC_RXSOFOVERRUNS)); 462 dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n", 463 emac_read(EMAC_RXMOFOVERRUNS)); 464 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n", 465 emac_read(EMAC_RXDMAOVERRUNS)); 466 467 cpdma_ctlr_dump(priv->dma); 468 } 469 470 /** 471 * emac_get_drvinfo - Get EMAC driver information 472 * @ndev: The DaVinci EMAC network adapter 473 * @info: ethtool info structure containing name and version 474 * 475 * Returns EMAC driver information (name and version) 476 * 477 */ 478 static void emac_get_drvinfo(struct net_device *ndev, 479 struct ethtool_drvinfo *info) 480 { 481 strlcpy(info->driver, emac_version_string, sizeof(info->driver)); 482 strlcpy(info->version, EMAC_MODULE_VERSION, sizeof(info->version)); 483 } 484 485 /** 486 * emac_get_settings - Get EMAC settings 487 * @ndev: The DaVinci EMAC network adapter 488 * @ecmd: ethtool command 489 * 490 * Executes ethool get command 491 * 492 */ 493 static int emac_get_settings(struct net_device *ndev, 494 struct ethtool_cmd *ecmd) 495 { 496 struct emac_priv *priv = netdev_priv(ndev); 497 if (priv->phydev) 498 return phy_ethtool_gset(priv->phydev, ecmd); 499 else 500 return -EOPNOTSUPP; 501 502 } 503 504 /** 505 * emac_set_settings - Set EMAC settings 506 * @ndev: The DaVinci EMAC network adapter 507 * @ecmd: ethtool command 508 * 509 * Executes ethool set command 510 * 511 */ 512 static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 513 { 514 struct emac_priv *priv = netdev_priv(ndev); 515 if (priv->phydev) 516 return phy_ethtool_sset(priv->phydev, ecmd); 517 else 518 return -EOPNOTSUPP; 519 520 } 521 522 /** 523 * emac_get_coalesce - Get interrupt coalesce settings for this device 524 * @ndev : The DaVinci EMAC network adapter 525 * @coal : ethtool coalesce settings structure 526 * 527 * Fetch the current interrupt coalesce settings 528 * 529 */ 530 static int emac_get_coalesce(struct net_device *ndev, 531 struct ethtool_coalesce *coal) 532 { 533 struct emac_priv *priv = netdev_priv(ndev); 534 535 coal->rx_coalesce_usecs = priv->coal_intvl; 536 return 0; 537 538 } 539 540 /** 541 * emac_set_coalesce - Set interrupt coalesce settings for this device 542 * @ndev : The DaVinci EMAC network adapter 543 * @coal : ethtool coalesce settings structure 544 * 545 * Set interrupt coalesce parameters 546 * 547 */ 548 static int emac_set_coalesce(struct net_device *ndev, 549 struct ethtool_coalesce *coal) 550 { 551 struct emac_priv *priv = netdev_priv(ndev); 552 u32 int_ctrl, num_interrupts = 0; 553 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0; 554 555 if (!coal->rx_coalesce_usecs) 556 return -EINVAL; 557 558 coal_intvl = coal->rx_coalesce_usecs; 559 560 switch (priv->version) { 561 case EMAC_VERSION_2: 562 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL); 563 prescale = priv->bus_freq_mhz * 4; 564 565 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL) 566 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL; 567 568 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) { 569 /* 570 * Interrupt pacer works with 4us Pulse, we can 571 * throttle further by dilating the 4us pulse. 572 */ 573 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale; 574 575 if (addnl_dvdr > 1) { 576 prescale *= addnl_dvdr; 577 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL 578 * addnl_dvdr)) 579 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL 580 * addnl_dvdr); 581 } else { 582 addnl_dvdr = 1; 583 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL; 584 } 585 } 586 587 num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 588 589 int_ctrl |= EMAC_DM646X_INTPACEEN; 590 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK); 591 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK); 592 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl); 593 594 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts); 595 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts); 596 597 break; 598 default: 599 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT); 600 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK); 601 prescale = coal_intvl * priv->bus_freq_mhz; 602 if (prescale > EMAC_DM644X_EWINTCNT_MASK) { 603 prescale = EMAC_DM644X_EWINTCNT_MASK; 604 coal_intvl = prescale / priv->bus_freq_mhz; 605 } 606 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale)); 607 608 break; 609 } 610 611 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl); 612 priv->coal_intvl = coal_intvl; 613 614 return 0; 615 616 } 617 618 619 /* ethtool_ops: DaVinci EMAC Ethtool structure 620 * 621 * Ethtool support for EMAC adapter 622 */ 623 static const struct ethtool_ops ethtool_ops = { 624 .get_drvinfo = emac_get_drvinfo, 625 .get_settings = emac_get_settings, 626 .set_settings = emac_set_settings, 627 .get_link = ethtool_op_get_link, 628 .get_coalesce = emac_get_coalesce, 629 .set_coalesce = emac_set_coalesce, 630 .get_ts_info = ethtool_op_get_ts_info, 631 }; 632 633 /** 634 * emac_update_phystatus - Update Phy status 635 * @priv: The DaVinci EMAC private adapter structure 636 * 637 * Updates phy status and takes action for network queue if required 638 * based upon link status 639 * 640 */ 641 static void emac_update_phystatus(struct emac_priv *priv) 642 { 643 u32 mac_control; 644 u32 new_duplex; 645 u32 cur_duplex; 646 struct net_device *ndev = priv->ndev; 647 648 mac_control = emac_read(EMAC_MACCONTROL); 649 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ? 650 DUPLEX_FULL : DUPLEX_HALF; 651 if (priv->phydev) 652 new_duplex = priv->phydev->duplex; 653 else 654 new_duplex = DUPLEX_FULL; 655 656 /* We get called only if link has changed (speed/duplex/status) */ 657 if ((priv->link) && (new_duplex != cur_duplex)) { 658 priv->duplex = new_duplex; 659 if (DUPLEX_FULL == priv->duplex) 660 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN); 661 else 662 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN); 663 } 664 665 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) { 666 mac_control = emac_read(EMAC_MACCONTROL); 667 mac_control |= (EMAC_DM646X_MACCONTORL_GIG | 668 EMAC_DM646X_MACCONTORL_GIGFORCE); 669 } else { 670 /* Clear the GIG bit and GIGFORCE bit */ 671 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE | 672 EMAC_DM646X_MACCONTORL_GIG); 673 674 if (priv->rmii_en && (priv->speed == SPEED_100)) 675 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK; 676 else 677 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK; 678 } 679 680 /* Update mac_control if changed */ 681 emac_write(EMAC_MACCONTROL, mac_control); 682 683 if (priv->link) { 684 /* link ON */ 685 if (!netif_carrier_ok(ndev)) 686 netif_carrier_on(ndev); 687 /* reactivate the transmit queue if it is stopped */ 688 if (netif_running(ndev) && netif_queue_stopped(ndev)) 689 netif_wake_queue(ndev); 690 } else { 691 /* link OFF */ 692 if (netif_carrier_ok(ndev)) 693 netif_carrier_off(ndev); 694 if (!netif_queue_stopped(ndev)) 695 netif_stop_queue(ndev); 696 } 697 } 698 699 /** 700 * hash_get - Calculate hash value from mac address 701 * @addr: mac address to delete from hash table 702 * 703 * Calculates hash value from mac address 704 * 705 */ 706 static u32 hash_get(u8 *addr) 707 { 708 u32 hash; 709 u8 tmpval; 710 int cnt; 711 hash = 0; 712 713 for (cnt = 0; cnt < 2; cnt++) { 714 tmpval = *addr++; 715 hash ^= (tmpval >> 2) ^ (tmpval << 4); 716 tmpval = *addr++; 717 hash ^= (tmpval >> 4) ^ (tmpval << 2); 718 tmpval = *addr++; 719 hash ^= (tmpval >> 6) ^ (tmpval); 720 } 721 722 return hash & 0x3F; 723 } 724 725 /** 726 * hash_add - Hash function to add mac addr from hash table 727 * @priv: The DaVinci EMAC private adapter structure 728 * @mac_addr: mac address to delete from hash table 729 * 730 * Adds mac address to the internal hash table 731 * 732 */ 733 static int hash_add(struct emac_priv *priv, u8 *mac_addr) 734 { 735 struct device *emac_dev = &priv->ndev->dev; 736 u32 rc = 0; 737 u32 hash_bit; 738 u32 hash_value = hash_get(mac_addr); 739 740 if (hash_value >= EMAC_NUM_MULTICAST_BITS) { 741 if (netif_msg_drv(priv)) { 742 dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\ 743 "Hash %08x, should not be greater than %08x", 744 hash_value, (EMAC_NUM_MULTICAST_BITS - 1)); 745 } 746 return -1; 747 } 748 749 /* set the hash bit only if not previously set */ 750 if (priv->multicast_hash_cnt[hash_value] == 0) { 751 rc = 1; /* hash value changed */ 752 if (hash_value < 32) { 753 hash_bit = BIT(hash_value); 754 priv->mac_hash1 |= hash_bit; 755 } else { 756 hash_bit = BIT((hash_value - 32)); 757 priv->mac_hash2 |= hash_bit; 758 } 759 } 760 761 /* incr counter for num of mcast addr's mapped to "this" hash bit */ 762 ++priv->multicast_hash_cnt[hash_value]; 763 764 return rc; 765 } 766 767 /** 768 * hash_del - Hash function to delete mac addr from hash table 769 * @priv: The DaVinci EMAC private adapter structure 770 * @mac_addr: mac address to delete from hash table 771 * 772 * Removes mac address from the internal hash table 773 * 774 */ 775 static int hash_del(struct emac_priv *priv, u8 *mac_addr) 776 { 777 u32 hash_value; 778 u32 hash_bit; 779 780 hash_value = hash_get(mac_addr); 781 if (priv->multicast_hash_cnt[hash_value] > 0) { 782 /* dec cntr for num of mcast addr's mapped to this hash bit */ 783 --priv->multicast_hash_cnt[hash_value]; 784 } 785 786 /* if counter still > 0, at least one multicast address refers 787 * to this hash bit. so return 0 */ 788 if (priv->multicast_hash_cnt[hash_value] > 0) 789 return 0; 790 791 if (hash_value < 32) { 792 hash_bit = BIT(hash_value); 793 priv->mac_hash1 &= ~hash_bit; 794 } else { 795 hash_bit = BIT((hash_value - 32)); 796 priv->mac_hash2 &= ~hash_bit; 797 } 798 799 /* return 1 to indicate change in mac_hash registers reqd */ 800 return 1; 801 } 802 803 /* EMAC multicast operation */ 804 #define EMAC_MULTICAST_ADD 0 805 #define EMAC_MULTICAST_DEL 1 806 #define EMAC_ALL_MULTI_SET 2 807 #define EMAC_ALL_MULTI_CLR 3 808 809 /** 810 * emac_add_mcast - Set multicast address in the EMAC adapter (Internal) 811 * @priv: The DaVinci EMAC private adapter structure 812 * @action: multicast operation to perform 813 * mac_addr: mac address to set 814 * 815 * Set multicast addresses in EMAC adapter - internal function 816 * 817 */ 818 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr) 819 { 820 struct device *emac_dev = &priv->ndev->dev; 821 int update = -1; 822 823 switch (action) { 824 case EMAC_MULTICAST_ADD: 825 update = hash_add(priv, mac_addr); 826 break; 827 case EMAC_MULTICAST_DEL: 828 update = hash_del(priv, mac_addr); 829 break; 830 case EMAC_ALL_MULTI_SET: 831 update = 1; 832 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE; 833 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE; 834 break; 835 case EMAC_ALL_MULTI_CLR: 836 update = 1; 837 priv->mac_hash1 = 0; 838 priv->mac_hash2 = 0; 839 memset(&(priv->multicast_hash_cnt[0]), 0, 840 sizeof(priv->multicast_hash_cnt[0]) * 841 EMAC_NUM_MULTICAST_BITS); 842 break; 843 default: 844 if (netif_msg_drv(priv)) 845 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\ 846 ": bad operation %d", action); 847 break; 848 } 849 850 /* write to the hardware only if the register status chances */ 851 if (update > 0) { 852 emac_write(EMAC_MACHASH1, priv->mac_hash1); 853 emac_write(EMAC_MACHASH2, priv->mac_hash2); 854 } 855 } 856 857 /** 858 * emac_dev_mcast_set - Set multicast address in the EMAC adapter 859 * @ndev: The DaVinci EMAC network adapter 860 * 861 * Set multicast addresses in EMAC adapter 862 * 863 */ 864 static void emac_dev_mcast_set(struct net_device *ndev) 865 { 866 u32 mbp_enable; 867 struct emac_priv *priv = netdev_priv(ndev); 868 869 mbp_enable = emac_read(EMAC_RXMBPENABLE); 870 if (ndev->flags & IFF_PROMISC) { 871 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH)); 872 mbp_enable |= (EMAC_MBP_RXPROMISC); 873 } else { 874 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC); 875 if ((ndev->flags & IFF_ALLMULTI) || 876 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) { 877 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST); 878 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL); 879 } else if (!netdev_mc_empty(ndev)) { 880 struct netdev_hw_addr *ha; 881 882 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST); 883 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL); 884 /* program multicast address list into EMAC hardware */ 885 netdev_for_each_mc_addr(ha, ndev) { 886 emac_add_mcast(priv, EMAC_MULTICAST_ADD, 887 (u8 *) ha->addr); 888 } 889 } else { 890 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST); 891 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL); 892 } 893 } 894 /* Set mbp config register */ 895 emac_write(EMAC_RXMBPENABLE, mbp_enable); 896 } 897 898 /************************************************************************* 899 * EMAC Hardware manipulation 900 *************************************************************************/ 901 902 /** 903 * emac_int_disable - Disable EMAC module interrupt (from adapter) 904 * @priv: The DaVinci EMAC private adapter structure 905 * 906 * Disable EMAC interrupt on the adapter 907 * 908 */ 909 static void emac_int_disable(struct emac_priv *priv) 910 { 911 if (priv->version == EMAC_VERSION_2) { 912 unsigned long flags; 913 914 local_irq_save(flags); 915 916 /* Program C0_Int_En to zero to turn off 917 * interrupts to the CPU */ 918 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0); 919 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0); 920 /* NOTE: Rx Threshold and Misc interrupts are not disabled */ 921 if (priv->int_disable) 922 priv->int_disable(); 923 924 local_irq_restore(flags); 925 926 } else { 927 /* Set DM644x control registers for interrupt control */ 928 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0); 929 } 930 } 931 932 /** 933 * emac_int_enable - Enable EMAC module interrupt (from adapter) 934 * @priv: The DaVinci EMAC private adapter structure 935 * 936 * Enable EMAC interrupt on the adapter 937 * 938 */ 939 static void emac_int_enable(struct emac_priv *priv) 940 { 941 if (priv->version == EMAC_VERSION_2) { 942 if (priv->int_enable) 943 priv->int_enable(); 944 945 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff); 946 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff); 947 948 /* In addition to turning on interrupt Enable, we need 949 * ack by writing appropriate values to the EOI 950 * register */ 951 952 /* NOTE: Rx Threshold and Misc interrupts are not enabled */ 953 954 /* ack rxen only then a new pulse will be generated */ 955 emac_write(EMAC_DM646X_MACEOIVECTOR, 956 EMAC_DM646X_MAC_EOI_C0_RXEN); 957 958 /* ack txen- only then a new pulse will be generated */ 959 emac_write(EMAC_DM646X_MACEOIVECTOR, 960 EMAC_DM646X_MAC_EOI_C0_TXEN); 961 962 } else { 963 /* Set DM644x control registers for interrupt control */ 964 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1); 965 } 966 } 967 968 /** 969 * emac_irq - EMAC interrupt handler 970 * @irq: interrupt number 971 * @dev_id: EMAC network adapter data structure ptr 972 * 973 * EMAC Interrupt handler - we only schedule NAPI and not process any packets 974 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function 975 * 976 * Returns interrupt handled condition 977 */ 978 static irqreturn_t emac_irq(int irq, void *dev_id) 979 { 980 struct net_device *ndev = (struct net_device *)dev_id; 981 struct emac_priv *priv = netdev_priv(ndev); 982 983 ++priv->isr_count; 984 if (likely(netif_running(priv->ndev))) { 985 emac_int_disable(priv); 986 napi_schedule(&priv->napi); 987 } else { 988 /* we are closing down, so dont process anything */ 989 } 990 return IRQ_HANDLED; 991 } 992 993 static struct sk_buff *emac_rx_alloc(struct emac_priv *priv) 994 { 995 struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size); 996 if (WARN_ON(!skb)) 997 return NULL; 998 skb_reserve(skb, NET_IP_ALIGN); 999 return skb; 1000 } 1001 1002 static void emac_rx_handler(void *token, int len, int status) 1003 { 1004 struct sk_buff *skb = token; 1005 struct net_device *ndev = skb->dev; 1006 struct emac_priv *priv = netdev_priv(ndev); 1007 struct device *emac_dev = &ndev->dev; 1008 int ret; 1009 1010 /* free and bail if we are shutting down */ 1011 if (unlikely(!netif_running(ndev))) { 1012 dev_kfree_skb_any(skb); 1013 return; 1014 } 1015 1016 /* recycle on receive error */ 1017 if (status < 0) { 1018 ndev->stats.rx_errors++; 1019 goto recycle; 1020 } 1021 1022 /* feed received packet up the stack */ 1023 skb_put(skb, len); 1024 skb->protocol = eth_type_trans(skb, ndev); 1025 netif_receive_skb(skb); 1026 ndev->stats.rx_bytes += len; 1027 ndev->stats.rx_packets++; 1028 1029 /* alloc a new packet for receive */ 1030 skb = emac_rx_alloc(priv); 1031 if (!skb) { 1032 if (netif_msg_rx_err(priv) && net_ratelimit()) 1033 dev_err(emac_dev, "failed rx buffer alloc\n"); 1034 return; 1035 } 1036 1037 recycle: 1038 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data, 1039 skb_tailroom(skb), 0); 1040 1041 WARN_ON(ret == -ENOMEM); 1042 if (unlikely(ret < 0)) 1043 dev_kfree_skb_any(skb); 1044 } 1045 1046 static void emac_tx_handler(void *token, int len, int status) 1047 { 1048 struct sk_buff *skb = token; 1049 struct net_device *ndev = skb->dev; 1050 1051 /* Check whether the queue is stopped due to stalled tx dma, if the 1052 * queue is stopped then start the queue as we have free desc for tx 1053 */ 1054 if (unlikely(netif_queue_stopped(ndev))) 1055 netif_wake_queue(ndev); 1056 ndev->stats.tx_packets++; 1057 ndev->stats.tx_bytes += len; 1058 dev_kfree_skb_any(skb); 1059 } 1060 1061 /** 1062 * emac_dev_xmit - EMAC Transmit function 1063 * @skb: SKB pointer 1064 * @ndev: The DaVinci EMAC network adapter 1065 * 1066 * Called by the system to transmit a packet - we queue the packet in 1067 * EMAC hardware transmit queue 1068 * 1069 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's) 1070 */ 1071 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev) 1072 { 1073 struct device *emac_dev = &ndev->dev; 1074 int ret_code; 1075 struct emac_priv *priv = netdev_priv(ndev); 1076 1077 /* If no link, return */ 1078 if (unlikely(!priv->link)) { 1079 if (netif_msg_tx_err(priv) && net_ratelimit()) 1080 dev_err(emac_dev, "DaVinci EMAC: No link to transmit"); 1081 goto fail_tx; 1082 } 1083 1084 ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE); 1085 if (unlikely(ret_code < 0)) { 1086 if (netif_msg_tx_err(priv) && net_ratelimit()) 1087 dev_err(emac_dev, "DaVinci EMAC: packet pad failed"); 1088 goto fail_tx; 1089 } 1090 1091 skb_tx_timestamp(skb); 1092 1093 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len, 1094 0); 1095 if (unlikely(ret_code != 0)) { 1096 if (netif_msg_tx_err(priv) && net_ratelimit()) 1097 dev_err(emac_dev, "DaVinci EMAC: desc submit failed"); 1098 goto fail_tx; 1099 } 1100 1101 /* If there is no more tx desc left free then we need to 1102 * tell the kernel to stop sending us tx frames. 1103 */ 1104 if (unlikely(!cpdma_check_free_tx_desc(priv->txchan))) 1105 netif_stop_queue(ndev); 1106 1107 return NETDEV_TX_OK; 1108 1109 fail_tx: 1110 ndev->stats.tx_dropped++; 1111 netif_stop_queue(ndev); 1112 return NETDEV_TX_BUSY; 1113 } 1114 1115 /** 1116 * emac_dev_tx_timeout - EMAC Transmit timeout function 1117 * @ndev: The DaVinci EMAC network adapter 1118 * 1119 * Called when system detects that a skb timeout period has expired 1120 * potentially due to a fault in the adapter in not being able to send 1121 * it out on the wire. We teardown the TX channel assuming a hardware 1122 * error and re-initialize the TX channel for hardware operation 1123 * 1124 */ 1125 static void emac_dev_tx_timeout(struct net_device *ndev) 1126 { 1127 struct emac_priv *priv = netdev_priv(ndev); 1128 struct device *emac_dev = &ndev->dev; 1129 1130 if (netif_msg_tx_err(priv)) 1131 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX"); 1132 1133 emac_dump_regs(priv); 1134 1135 ndev->stats.tx_errors++; 1136 emac_int_disable(priv); 1137 cpdma_chan_stop(priv->txchan); 1138 cpdma_chan_start(priv->txchan); 1139 emac_int_enable(priv); 1140 } 1141 1142 /** 1143 * emac_set_type0addr - Set EMAC Type0 mac address 1144 * @priv: The DaVinci EMAC private adapter structure 1145 * @ch: RX channel number 1146 * @mac_addr: MAC address to set in device 1147 * 1148 * Called internally to set Type0 mac address of the adapter (Device) 1149 * 1150 * Returns success (0) or appropriate error code (none as of now) 1151 */ 1152 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr) 1153 { 1154 u32 val; 1155 val = ((mac_addr[5] << 8) | (mac_addr[4])); 1156 emac_write(EMAC_MACSRCADDRLO, val); 1157 1158 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 1159 (mac_addr[1] << 8) | (mac_addr[0])); 1160 emac_write(EMAC_MACSRCADDRHI, val); 1161 val = emac_read(EMAC_RXUNICASTSET); 1162 val |= BIT(ch); 1163 emac_write(EMAC_RXUNICASTSET, val); 1164 val = emac_read(EMAC_RXUNICASTCLEAR); 1165 val &= ~BIT(ch); 1166 emac_write(EMAC_RXUNICASTCLEAR, val); 1167 } 1168 1169 /** 1170 * emac_set_type1addr - Set EMAC Type1 mac address 1171 * @priv: The DaVinci EMAC private adapter structure 1172 * @ch: RX channel number 1173 * @mac_addr: MAC address to set in device 1174 * 1175 * Called internally to set Type1 mac address of the adapter (Device) 1176 * 1177 * Returns success (0) or appropriate error code (none as of now) 1178 */ 1179 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr) 1180 { 1181 u32 val; 1182 emac_write(EMAC_MACINDEX, ch); 1183 val = ((mac_addr[5] << 8) | mac_addr[4]); 1184 emac_write(EMAC_MACADDRLO, val); 1185 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 1186 (mac_addr[1] << 8) | (mac_addr[0])); 1187 emac_write(EMAC_MACADDRHI, val); 1188 emac_set_type0addr(priv, ch, mac_addr); 1189 } 1190 1191 /** 1192 * emac_set_type2addr - Set EMAC Type2 mac address 1193 * @priv: The DaVinci EMAC private adapter structure 1194 * @ch: RX channel number 1195 * @mac_addr: MAC address to set in device 1196 * @index: index into RX address entries 1197 * @match: match parameter for RX address matching logic 1198 * 1199 * Called internally to set Type2 mac address of the adapter (Device) 1200 * 1201 * Returns success (0) or appropriate error code (none as of now) 1202 */ 1203 static void emac_set_type2addr(struct emac_priv *priv, u32 ch, 1204 char *mac_addr, int index, int match) 1205 { 1206 u32 val; 1207 emac_write(EMAC_MACINDEX, index); 1208 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 1209 (mac_addr[1] << 8) | (mac_addr[0])); 1210 emac_write(EMAC_MACADDRHI, val); 1211 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \ 1212 (match << 19) | BIT(20)); 1213 emac_write(EMAC_MACADDRLO, val); 1214 emac_set_type0addr(priv, ch, mac_addr); 1215 } 1216 1217 /** 1218 * emac_setmac - Set mac address in the adapter (internal function) 1219 * @priv: The DaVinci EMAC private adapter structure 1220 * @ch: RX channel number 1221 * @mac_addr: MAC address to set in device 1222 * 1223 * Called internally to set the mac address of the adapter (Device) 1224 * 1225 * Returns success (0) or appropriate error code (none as of now) 1226 */ 1227 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr) 1228 { 1229 struct device *emac_dev = &priv->ndev->dev; 1230 1231 if (priv->rx_addr_type == 0) { 1232 emac_set_type0addr(priv, ch, mac_addr); 1233 } else if (priv->rx_addr_type == 1) { 1234 u32 cnt; 1235 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++) 1236 emac_set_type1addr(priv, ch, mac_addr); 1237 } else if (priv->rx_addr_type == 2) { 1238 emac_set_type2addr(priv, ch, mac_addr, ch, 1); 1239 emac_set_type0addr(priv, ch, mac_addr); 1240 } else { 1241 if (netif_msg_drv(priv)) 1242 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n"); 1243 } 1244 } 1245 1246 /** 1247 * emac_dev_setmac_addr - Set mac address in the adapter 1248 * @ndev: The DaVinci EMAC network adapter 1249 * @addr: MAC address to set in device 1250 * 1251 * Called by the system to set the mac address of the adapter (Device) 1252 * 1253 * Returns success (0) or appropriate error code (none as of now) 1254 */ 1255 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr) 1256 { 1257 struct emac_priv *priv = netdev_priv(ndev); 1258 struct device *emac_dev = &priv->ndev->dev; 1259 struct sockaddr *sa = addr; 1260 1261 if (!is_valid_ether_addr(sa->sa_data)) 1262 return -EADDRNOTAVAIL; 1263 1264 /* Store mac addr in priv and rx channel and set it in EMAC hw */ 1265 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len); 1266 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len); 1267 1268 /* MAC address is configured only after the interface is enabled. */ 1269 if (netif_running(ndev)) { 1270 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr); 1271 } 1272 1273 if (netif_msg_drv(priv)) 1274 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n", 1275 priv->mac_addr); 1276 1277 return 0; 1278 } 1279 1280 /** 1281 * emac_hw_enable - Enable EMAC hardware for packet transmission/reception 1282 * @priv: The DaVinci EMAC private adapter structure 1283 * 1284 * Enables EMAC hardware for packet processing - enables PHY, enables RX 1285 * for packet reception and enables device interrupts and then NAPI 1286 * 1287 * Returns success (0) or appropriate error code (none right now) 1288 */ 1289 static int emac_hw_enable(struct emac_priv *priv) 1290 { 1291 u32 val, mbp_enable, mac_control; 1292 1293 /* Soft reset */ 1294 emac_write(EMAC_SOFTRESET, 1); 1295 while (emac_read(EMAC_SOFTRESET)) 1296 cpu_relax(); 1297 1298 /* Disable interrupt & Set pacing for more interrupts initially */ 1299 emac_int_disable(priv); 1300 1301 /* Full duplex enable bit set when auto negotiation happens */ 1302 mac_control = 1303 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) | 1304 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) | 1305 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) | 1306 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0)); 1307 emac_write(EMAC_MACCONTROL, mac_control); 1308 1309 mbp_enable = 1310 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) | 1311 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) | 1312 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) | 1313 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) | 1314 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) | 1315 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) | 1316 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) | 1317 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \ 1318 EMAC_RXMBP_PROMCH_SHIFT) | 1319 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) | 1320 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \ 1321 EMAC_RXMBP_BROADCH_SHIFT) | 1322 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) | 1323 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \ 1324 EMAC_RXMBP_MULTICH_SHIFT)); 1325 emac_write(EMAC_RXMBPENABLE, mbp_enable); 1326 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE & 1327 EMAC_RX_MAX_LEN_MASK)); 1328 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET & 1329 EMAC_RX_BUFFER_OFFSET_MASK)); 1330 emac_write(EMAC_RXFILTERLOWTHRESH, 0); 1331 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL); 1332 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF; 1333 1334 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL); 1335 1336 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr); 1337 1338 /* Enable MII */ 1339 val = emac_read(EMAC_MACCONTROL); 1340 val |= (EMAC_MACCONTROL_GMIIEN); 1341 emac_write(EMAC_MACCONTROL, val); 1342 1343 /* Enable NAPI and interrupts */ 1344 napi_enable(&priv->napi); 1345 emac_int_enable(priv); 1346 return 0; 1347 1348 } 1349 1350 /** 1351 * emac_poll - EMAC NAPI Poll function 1352 * @ndev: The DaVinci EMAC network adapter 1353 * @budget: Number of receive packets to process (as told by NAPI layer) 1354 * 1355 * NAPI Poll function implemented to process packets as per budget. We check 1356 * the type of interrupt on the device and accordingly call the TX or RX 1357 * packet processing functions. We follow the budget for RX processing and 1358 * also put a cap on number of TX pkts processed through config param. The 1359 * NAPI schedule function is called if more packets pending. 1360 * 1361 * Returns number of packets received (in most cases; else TX pkts - rarely) 1362 */ 1363 static int emac_poll(struct napi_struct *napi, int budget) 1364 { 1365 unsigned int mask; 1366 struct emac_priv *priv = container_of(napi, struct emac_priv, napi); 1367 struct net_device *ndev = priv->ndev; 1368 struct device *emac_dev = &ndev->dev; 1369 u32 status = 0; 1370 u32 num_tx_pkts = 0, num_rx_pkts = 0; 1371 1372 /* Check interrupt vectors and call packet processing */ 1373 status = emac_read(EMAC_MACINVECTOR); 1374 1375 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC; 1376 1377 if (priv->version == EMAC_VERSION_2) 1378 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC; 1379 1380 if (status & mask) { 1381 num_tx_pkts = cpdma_chan_process(priv->txchan, 1382 EMAC_DEF_TX_MAX_SERVICE); 1383 } /* TX processing */ 1384 1385 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC; 1386 1387 if (priv->version == EMAC_VERSION_2) 1388 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC; 1389 1390 if (status & mask) { 1391 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget); 1392 } /* RX processing */ 1393 1394 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT; 1395 if (priv->version == EMAC_VERSION_2) 1396 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT; 1397 1398 if (unlikely(status & mask)) { 1399 u32 ch, cause; 1400 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n"); 1401 netif_stop_queue(ndev); 1402 napi_disable(&priv->napi); 1403 1404 status = emac_read(EMAC_MACSTATUS); 1405 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >> 1406 EMAC_MACSTATUS_TXERRCODE_SHIFT); 1407 if (cause) { 1408 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >> 1409 EMAC_MACSTATUS_TXERRCH_SHIFT); 1410 if (net_ratelimit()) { 1411 dev_err(emac_dev, "TX Host error %s on ch=%d\n", 1412 &emac_txhost_errcodes[cause][0], ch); 1413 } 1414 } 1415 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >> 1416 EMAC_MACSTATUS_RXERRCODE_SHIFT); 1417 if (cause) { 1418 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >> 1419 EMAC_MACSTATUS_RXERRCH_SHIFT); 1420 if (netif_msg_hw(priv) && net_ratelimit()) 1421 dev_err(emac_dev, "RX Host error %s on ch=%d\n", 1422 &emac_rxhost_errcodes[cause][0], ch); 1423 } 1424 } else if (num_rx_pkts < budget) { 1425 napi_complete(napi); 1426 emac_int_enable(priv); 1427 } 1428 1429 return num_rx_pkts; 1430 } 1431 1432 #ifdef CONFIG_NET_POLL_CONTROLLER 1433 /** 1434 * emac_poll_controller - EMAC Poll controller function 1435 * @ndev: The DaVinci EMAC network adapter 1436 * 1437 * Polled functionality used by netconsole and others in non interrupt mode 1438 * 1439 */ 1440 static void emac_poll_controller(struct net_device *ndev) 1441 { 1442 struct emac_priv *priv = netdev_priv(ndev); 1443 1444 emac_int_disable(priv); 1445 emac_irq(ndev->irq, ndev); 1446 emac_int_enable(priv); 1447 } 1448 #endif 1449 1450 static void emac_adjust_link(struct net_device *ndev) 1451 { 1452 struct emac_priv *priv = netdev_priv(ndev); 1453 struct phy_device *phydev = priv->phydev; 1454 unsigned long flags; 1455 int new_state = 0; 1456 1457 spin_lock_irqsave(&priv->lock, flags); 1458 1459 if (phydev->link) { 1460 /* check the mode of operation - full/half duplex */ 1461 if (phydev->duplex != priv->duplex) { 1462 new_state = 1; 1463 priv->duplex = phydev->duplex; 1464 } 1465 if (phydev->speed != priv->speed) { 1466 new_state = 1; 1467 priv->speed = phydev->speed; 1468 } 1469 if (!priv->link) { 1470 new_state = 1; 1471 priv->link = 1; 1472 } 1473 1474 } else if (priv->link) { 1475 new_state = 1; 1476 priv->link = 0; 1477 priv->speed = 0; 1478 priv->duplex = ~0; 1479 } 1480 if (new_state) { 1481 emac_update_phystatus(priv); 1482 phy_print_status(priv->phydev); 1483 } 1484 1485 spin_unlock_irqrestore(&priv->lock, flags); 1486 } 1487 1488 /************************************************************************* 1489 * Linux Driver Model 1490 *************************************************************************/ 1491 1492 /** 1493 * emac_devioctl - EMAC adapter ioctl 1494 * @ndev: The DaVinci EMAC network adapter 1495 * @ifrq: request parameter 1496 * @cmd: command parameter 1497 * 1498 * EMAC driver ioctl function 1499 * 1500 * Returns success(0) or appropriate error code 1501 */ 1502 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd) 1503 { 1504 struct emac_priv *priv = netdev_priv(ndev); 1505 1506 if (!(netif_running(ndev))) 1507 return -EINVAL; 1508 1509 /* TODO: Add phy read and write and private statistics get feature */ 1510 1511 return phy_mii_ioctl(priv->phydev, ifrq, cmd); 1512 } 1513 1514 static int match_first_device(struct device *dev, void *data) 1515 { 1516 return !strncmp(dev_name(dev), "davinci_mdio", 12); 1517 } 1518 1519 /** 1520 * emac_dev_open - EMAC device open 1521 * @ndev: The DaVinci EMAC network adapter 1522 * 1523 * Called when system wants to start the interface. We init TX/RX channels 1524 * and enable the hardware for packet reception/transmission and start the 1525 * network queue. 1526 * 1527 * Returns 0 for a successful open, or appropriate error code 1528 */ 1529 static int emac_dev_open(struct net_device *ndev) 1530 { 1531 struct device *emac_dev = &ndev->dev; 1532 u32 cnt; 1533 struct resource *res; 1534 int ret; 1535 int i = 0; 1536 int k = 0; 1537 struct emac_priv *priv = netdev_priv(ndev); 1538 1539 pm_runtime_get(&priv->pdev->dev); 1540 1541 netif_carrier_off(ndev); 1542 for (cnt = 0; cnt < ETH_ALEN; cnt++) 1543 ndev->dev_addr[cnt] = priv->mac_addr[cnt]; 1544 1545 /* Configuration items */ 1546 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN; 1547 1548 priv->mac_hash1 = 0; 1549 priv->mac_hash2 = 0; 1550 emac_write(EMAC_MACHASH1, 0); 1551 emac_write(EMAC_MACHASH2, 0); 1552 1553 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) { 1554 struct sk_buff *skb = emac_rx_alloc(priv); 1555 1556 if (!skb) 1557 break; 1558 1559 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data, 1560 skb_tailroom(skb), 0); 1561 if (WARN_ON(ret < 0)) 1562 break; 1563 } 1564 1565 /* Request IRQ */ 1566 1567 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { 1568 for (i = res->start; i <= res->end; i++) { 1569 if (devm_request_irq(&priv->pdev->dev, i, emac_irq, 1570 0, ndev->name, ndev)) 1571 goto rollback; 1572 } 1573 k++; 1574 } 1575 1576 /* Start/Enable EMAC hardware */ 1577 emac_hw_enable(priv); 1578 1579 /* Enable Interrupt pacing if configured */ 1580 if (priv->coal_intvl != 0) { 1581 struct ethtool_coalesce coal; 1582 1583 coal.rx_coalesce_usecs = (priv->coal_intvl << 4); 1584 emac_set_coalesce(ndev, &coal); 1585 } 1586 1587 cpdma_ctlr_start(priv->dma); 1588 1589 priv->phydev = NULL; 1590 /* use the first phy on the bus if pdata did not give us a phy id */ 1591 if (!priv->phy_id) { 1592 struct device *phy; 1593 1594 phy = bus_find_device(&mdio_bus_type, NULL, NULL, 1595 match_first_device); 1596 if (phy) 1597 priv->phy_id = dev_name(phy); 1598 } 1599 1600 if (priv->phy_id && *priv->phy_id) { 1601 priv->phydev = phy_connect(ndev, priv->phy_id, 1602 &emac_adjust_link, 1603 PHY_INTERFACE_MODE_MII); 1604 1605 if (IS_ERR(priv->phydev)) { 1606 dev_err(emac_dev, "could not connect to phy %s\n", 1607 priv->phy_id); 1608 ret = PTR_ERR(priv->phydev); 1609 priv->phydev = NULL; 1610 goto err; 1611 } 1612 1613 priv->link = 0; 1614 priv->speed = 0; 1615 priv->duplex = ~0; 1616 1617 dev_info(emac_dev, "attached PHY driver [%s] " 1618 "(mii_bus:phy_addr=%s, id=%x)\n", 1619 priv->phydev->drv->name, dev_name(&priv->phydev->dev), 1620 priv->phydev->phy_id); 1621 } else { 1622 /* No PHY , fix the link, speed and duplex settings */ 1623 dev_notice(emac_dev, "no phy, defaulting to 100/full\n"); 1624 priv->link = 1; 1625 priv->speed = SPEED_100; 1626 priv->duplex = DUPLEX_FULL; 1627 emac_update_phystatus(priv); 1628 } 1629 1630 if (!netif_running(ndev)) /* debug only - to avoid compiler warning */ 1631 emac_dump_regs(priv); 1632 1633 if (netif_msg_drv(priv)) 1634 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name); 1635 1636 if (priv->phydev) 1637 phy_start(priv->phydev); 1638 1639 return 0; 1640 1641 rollback: 1642 1643 dev_err(emac_dev, "DaVinci EMAC: devm_request_irq() failed"); 1644 ret = -EBUSY; 1645 err: 1646 pm_runtime_put(&priv->pdev->dev); 1647 return ret; 1648 } 1649 1650 /** 1651 * emac_dev_stop - EMAC device stop 1652 * @ndev: The DaVinci EMAC network adapter 1653 * 1654 * Called when system wants to stop or down the interface. We stop the network 1655 * queue, disable interrupts and cleanup TX/RX channels. 1656 * 1657 * We return the statistics in net_device_stats structure pulled from emac 1658 */ 1659 static int emac_dev_stop(struct net_device *ndev) 1660 { 1661 struct emac_priv *priv = netdev_priv(ndev); 1662 struct device *emac_dev = &ndev->dev; 1663 1664 /* inform the upper layers. */ 1665 netif_stop_queue(ndev); 1666 napi_disable(&priv->napi); 1667 1668 netif_carrier_off(ndev); 1669 emac_int_disable(priv); 1670 cpdma_ctlr_stop(priv->dma); 1671 emac_write(EMAC_SOFTRESET, 1); 1672 1673 if (priv->phydev) 1674 phy_disconnect(priv->phydev); 1675 1676 if (netif_msg_drv(priv)) 1677 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name); 1678 1679 pm_runtime_put(&priv->pdev->dev); 1680 return 0; 1681 } 1682 1683 /** 1684 * emac_dev_getnetstats - EMAC get statistics function 1685 * @ndev: The DaVinci EMAC network adapter 1686 * 1687 * Called when system wants to get statistics from the device. 1688 * 1689 * We return the statistics in net_device_stats structure pulled from emac 1690 */ 1691 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev) 1692 { 1693 struct emac_priv *priv = netdev_priv(ndev); 1694 u32 mac_control; 1695 u32 stats_clear_mask; 1696 1697 /* update emac hardware stats and reset the registers*/ 1698 1699 mac_control = emac_read(EMAC_MACCONTROL); 1700 1701 if (mac_control & EMAC_MACCONTROL_GMIIEN) 1702 stats_clear_mask = EMAC_STATS_CLR_MASK; 1703 else 1704 stats_clear_mask = 0; 1705 1706 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES); 1707 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask); 1708 1709 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) + 1710 emac_read(EMAC_TXSINGLECOLL) + 1711 emac_read(EMAC_TXMULTICOLL)); 1712 emac_write(EMAC_TXCOLLISION, stats_clear_mask); 1713 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask); 1714 emac_write(EMAC_TXMULTICOLL, stats_clear_mask); 1715 1716 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) + 1717 emac_read(EMAC_RXJABBER) + 1718 emac_read(EMAC_RXUNDERSIZED)); 1719 emac_write(EMAC_RXOVERSIZED, stats_clear_mask); 1720 emac_write(EMAC_RXJABBER, stats_clear_mask); 1721 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask); 1722 1723 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) + 1724 emac_read(EMAC_RXMOFOVERRUNS)); 1725 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask); 1726 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask); 1727 1728 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS); 1729 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask); 1730 1731 ndev->stats.tx_carrier_errors += 1732 emac_read(EMAC_TXCARRIERSENSE); 1733 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask); 1734 1735 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN); 1736 emac_write(EMAC_TXUNDERRUN, stats_clear_mask); 1737 1738 return &ndev->stats; 1739 } 1740 1741 static const struct net_device_ops emac_netdev_ops = { 1742 .ndo_open = emac_dev_open, 1743 .ndo_stop = emac_dev_stop, 1744 .ndo_start_xmit = emac_dev_xmit, 1745 .ndo_set_rx_mode = emac_dev_mcast_set, 1746 .ndo_set_mac_address = emac_dev_setmac_addr, 1747 .ndo_do_ioctl = emac_devioctl, 1748 .ndo_tx_timeout = emac_dev_tx_timeout, 1749 .ndo_get_stats = emac_dev_getnetstats, 1750 #ifdef CONFIG_NET_POLL_CONTROLLER 1751 .ndo_poll_controller = emac_poll_controller, 1752 #endif 1753 }; 1754 1755 static struct emac_platform_data * 1756 davinci_emac_of_get_pdata(struct platform_device *pdev, struct emac_priv *priv) 1757 { 1758 struct device_node *np; 1759 struct emac_platform_data *pdata = NULL; 1760 const u8 *mac_addr; 1761 1762 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) 1763 return dev_get_platdata(&pdev->dev); 1764 1765 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1766 if (!pdata) 1767 return NULL; 1768 1769 np = pdev->dev.of_node; 1770 pdata->version = EMAC_VERSION_2; 1771 1772 if (!is_valid_ether_addr(pdata->mac_addr)) { 1773 mac_addr = of_get_mac_address(np); 1774 if (mac_addr) 1775 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN); 1776 } 1777 1778 of_property_read_u32(np, "ti,davinci-ctrl-reg-offset", 1779 &pdata->ctrl_reg_offset); 1780 1781 of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset", 1782 &pdata->ctrl_mod_reg_offset); 1783 1784 of_property_read_u32(np, "ti,davinci-ctrl-ram-offset", 1785 &pdata->ctrl_ram_offset); 1786 1787 of_property_read_u32(np, "ti,davinci-ctrl-ram-size", 1788 &pdata->ctrl_ram_size); 1789 1790 of_property_read_u8(np, "ti,davinci-rmii-en", &pdata->rmii_en); 1791 1792 pdata->no_bd_ram = of_property_read_bool(np, "ti,davinci-no-bd-ram"); 1793 1794 priv->phy_node = of_parse_phandle(np, "phy-handle", 0); 1795 if (!priv->phy_node) 1796 pdata->phy_id = ""; 1797 1798 pdev->dev.platform_data = pdata; 1799 1800 return pdata; 1801 } 1802 1803 /** 1804 * davinci_emac_probe - EMAC device probe 1805 * @pdev: The DaVinci EMAC device that we are removing 1806 * 1807 * Called when probing for emac devicesr. We get details of instances and 1808 * resource information from platform init and register a network device 1809 * and allocate resources necessary for driver to perform 1810 */ 1811 static int davinci_emac_probe(struct platform_device *pdev) 1812 { 1813 int rc = 0; 1814 struct resource *res; 1815 struct net_device *ndev; 1816 struct emac_priv *priv; 1817 unsigned long hw_ram_addr; 1818 struct emac_platform_data *pdata; 1819 struct device *emac_dev; 1820 struct cpdma_params dma_params; 1821 struct clk *emac_clk; 1822 unsigned long emac_bus_frequency; 1823 1824 1825 /* obtain emac clock from kernel */ 1826 emac_clk = devm_clk_get(&pdev->dev, NULL); 1827 if (IS_ERR(emac_clk)) { 1828 dev_err(&pdev->dev, "failed to get EMAC clock\n"); 1829 return -EBUSY; 1830 } 1831 emac_bus_frequency = clk_get_rate(emac_clk); 1832 1833 /* TODO: Probe PHY here if possible */ 1834 1835 ndev = alloc_etherdev(sizeof(struct emac_priv)); 1836 if (!ndev) 1837 return -ENOMEM; 1838 1839 platform_set_drvdata(pdev, ndev); 1840 priv = netdev_priv(ndev); 1841 priv->pdev = pdev; 1842 priv->ndev = ndev; 1843 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG); 1844 1845 spin_lock_init(&priv->lock); 1846 1847 pdata = davinci_emac_of_get_pdata(pdev, priv); 1848 if (!pdata) { 1849 dev_err(&pdev->dev, "no platform data\n"); 1850 rc = -ENODEV; 1851 goto no_pdata; 1852 } 1853 1854 /* MAC addr and PHY mask , RMII enable info from platform_data */ 1855 memcpy(priv->mac_addr, pdata->mac_addr, 6); 1856 priv->phy_id = pdata->phy_id; 1857 priv->rmii_en = pdata->rmii_en; 1858 priv->version = pdata->version; 1859 priv->int_enable = pdata->interrupt_enable; 1860 priv->int_disable = pdata->interrupt_disable; 1861 1862 priv->coal_intvl = 0; 1863 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000); 1864 1865 emac_dev = &ndev->dev; 1866 /* Get EMAC platform data */ 1867 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1868 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset; 1869 priv->remap_addr = devm_ioremap_resource(&pdev->dev, res); 1870 if (IS_ERR(priv->remap_addr)) { 1871 rc = PTR_ERR(priv->remap_addr); 1872 goto no_pdata; 1873 } 1874 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset; 1875 ndev->base_addr = (unsigned long)priv->remap_addr; 1876 1877 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset; 1878 1879 hw_ram_addr = pdata->hw_ram_addr; 1880 if (!hw_ram_addr) 1881 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset; 1882 1883 memset(&dma_params, 0, sizeof(dma_params)); 1884 dma_params.dev = emac_dev; 1885 dma_params.dmaregs = priv->emac_base; 1886 dma_params.rxthresh = priv->emac_base + 0x120; 1887 dma_params.rxfree = priv->emac_base + 0x140; 1888 dma_params.txhdp = priv->emac_base + 0x600; 1889 dma_params.rxhdp = priv->emac_base + 0x620; 1890 dma_params.txcp = priv->emac_base + 0x640; 1891 dma_params.rxcp = priv->emac_base + 0x660; 1892 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS; 1893 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE; 1894 dma_params.desc_hw_addr = hw_ram_addr; 1895 dma_params.desc_mem_size = pdata->ctrl_ram_size; 1896 dma_params.desc_align = 16; 1897 1898 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 : 1899 (u32 __force)res->start + pdata->ctrl_ram_offset; 1900 1901 priv->dma = cpdma_ctlr_create(&dma_params); 1902 if (!priv->dma) { 1903 dev_err(&pdev->dev, "error initializing DMA\n"); 1904 rc = -ENOMEM; 1905 goto no_pdata; 1906 } 1907 1908 priv->txchan = cpdma_chan_create(priv->dma, tx_chan_num(EMAC_DEF_TX_CH), 1909 emac_tx_handler); 1910 priv->rxchan = cpdma_chan_create(priv->dma, rx_chan_num(EMAC_DEF_RX_CH), 1911 emac_rx_handler); 1912 if (WARN_ON(!priv->txchan || !priv->rxchan)) { 1913 rc = -ENOMEM; 1914 goto no_cpdma_chan; 1915 } 1916 1917 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1918 if (!res) { 1919 dev_err(&pdev->dev, "error getting irq res\n"); 1920 rc = -ENOENT; 1921 goto no_cpdma_chan; 1922 } 1923 ndev->irq = res->start; 1924 1925 if (!is_valid_ether_addr(priv->mac_addr)) { 1926 /* Use random MAC if none passed */ 1927 eth_hw_addr_random(ndev); 1928 memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len); 1929 dev_warn(&pdev->dev, "using random MAC addr: %pM\n", 1930 priv->mac_addr); 1931 } 1932 1933 ndev->netdev_ops = &emac_netdev_ops; 1934 SET_ETHTOOL_OPS(ndev, ðtool_ops); 1935 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT); 1936 1937 /* register the network device */ 1938 SET_NETDEV_DEV(ndev, &pdev->dev); 1939 rc = register_netdev(ndev); 1940 if (rc) { 1941 dev_err(&pdev->dev, "error in register_netdev\n"); 1942 rc = -ENODEV; 1943 goto no_cpdma_chan; 1944 } 1945 1946 1947 if (netif_msg_probe(priv)) { 1948 dev_notice(emac_dev, "DaVinci EMAC Probe found device "\ 1949 "(regs: %p, irq: %d)\n", 1950 (void *)priv->emac_base_phys, ndev->irq); 1951 } 1952 1953 pm_runtime_enable(&pdev->dev); 1954 pm_runtime_resume(&pdev->dev); 1955 1956 return 0; 1957 1958 no_cpdma_chan: 1959 if (priv->txchan) 1960 cpdma_chan_destroy(priv->txchan); 1961 if (priv->rxchan) 1962 cpdma_chan_destroy(priv->rxchan); 1963 cpdma_ctlr_destroy(priv->dma); 1964 no_pdata: 1965 free_netdev(ndev); 1966 return rc; 1967 } 1968 1969 /** 1970 * davinci_emac_remove - EMAC device remove 1971 * @pdev: The DaVinci EMAC device that we are removing 1972 * 1973 * Called when removing the device driver. We disable clock usage and release 1974 * the resources taken up by the driver and unregister network device 1975 */ 1976 static int davinci_emac_remove(struct platform_device *pdev) 1977 { 1978 struct net_device *ndev = platform_get_drvdata(pdev); 1979 struct emac_priv *priv = netdev_priv(ndev); 1980 1981 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n"); 1982 1983 if (priv->txchan) 1984 cpdma_chan_destroy(priv->txchan); 1985 if (priv->rxchan) 1986 cpdma_chan_destroy(priv->rxchan); 1987 cpdma_ctlr_destroy(priv->dma); 1988 1989 unregister_netdev(ndev); 1990 free_netdev(ndev); 1991 1992 return 0; 1993 } 1994 1995 static int davinci_emac_suspend(struct device *dev) 1996 { 1997 struct platform_device *pdev = to_platform_device(dev); 1998 struct net_device *ndev = platform_get_drvdata(pdev); 1999 2000 if (netif_running(ndev)) 2001 emac_dev_stop(ndev); 2002 2003 return 0; 2004 } 2005 2006 static int davinci_emac_resume(struct device *dev) 2007 { 2008 struct platform_device *pdev = to_platform_device(dev); 2009 struct net_device *ndev = platform_get_drvdata(pdev); 2010 2011 if (netif_running(ndev)) 2012 emac_dev_open(ndev); 2013 2014 return 0; 2015 } 2016 2017 static const struct dev_pm_ops davinci_emac_pm_ops = { 2018 .suspend = davinci_emac_suspend, 2019 .resume = davinci_emac_resume, 2020 }; 2021 2022 #if IS_ENABLED(CONFIG_OF) 2023 static const struct of_device_id davinci_emac_of_match[] = { 2024 {.compatible = "ti,davinci-dm6467-emac", }, 2025 {}, 2026 }; 2027 MODULE_DEVICE_TABLE(of, davinci_emac_of_match); 2028 #endif 2029 2030 /* davinci_emac_driver: EMAC platform driver structure */ 2031 static struct platform_driver davinci_emac_driver = { 2032 .driver = { 2033 .name = "davinci_emac", 2034 .owner = THIS_MODULE, 2035 .pm = &davinci_emac_pm_ops, 2036 .of_match_table = of_match_ptr(davinci_emac_of_match), 2037 }, 2038 .probe = davinci_emac_probe, 2039 .remove = davinci_emac_remove, 2040 }; 2041 2042 /** 2043 * davinci_emac_init - EMAC driver module init 2044 * 2045 * Called when initializing the driver. We register the driver with 2046 * the platform. 2047 */ 2048 static int __init davinci_emac_init(void) 2049 { 2050 return platform_driver_register(&davinci_emac_driver); 2051 } 2052 late_initcall(davinci_emac_init); 2053 2054 /** 2055 * davinci_emac_exit - EMAC driver module exit 2056 * 2057 * Called when exiting the driver completely. We unregister the driver with 2058 * the platform and exit 2059 */ 2060 static void __exit davinci_emac_exit(void) 2061 { 2062 platform_driver_unregister(&davinci_emac_driver); 2063 } 2064 module_exit(davinci_emac_exit); 2065 2066 MODULE_LICENSE("GPL"); 2067 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>"); 2068 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>"); 2069 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver"); 2070