1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * DaVinci Ethernet Medium Access Controller
4 *
5 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
6 *
7 * Copyright (C) 2009 Texas Instruments.
8 *
9 * ---------------------------------------------------------------------------
10 * History:
11 * 0-5 A number of folks worked on this driver in bits and pieces but the major
12 * contribution came from Suraj Iyer and Anant Gole
13 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
14 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
15 * PHY layer usage
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/sched.h>
21 #include <linux/string.h>
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/in.h>
25 #include <linux/ioport.h>
26 #include <linux/slab.h>
27 #include <linux/mm.h>
28 #include <linux/interrupt.h>
29 #include <linux/init.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/highmem.h>
35 #include <linux/proc_fs.h>
36 #include <linux/ctype.h>
37 #include <linux/spinlock.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/clk.h>
40 #include <linux/platform_device.h>
41 #include <linux/regmap.h>
42 #include <linux/semaphore.h>
43 #include <linux/phy.h>
44 #include <linux/bitops.h>
45 #include <linux/io.h>
46 #include <linux/uaccess.h>
47 #include <linux/pm_runtime.h>
48 #include <linux/davinci_emac.h>
49 #include <linux/of.h>
50 #include <linux/of_address.h>
51 #include <linux/of_device.h>
52 #include <linux/of_mdio.h>
53 #include <linux/of_irq.h>
54 #include <linux/of_net.h>
55 #include <linux/mfd/syscon.h>
56
57 #include <asm/irq.h>
58 #include <asm/page.h>
59
60 #include "cpsw.h"
61 #include "davinci_cpdma.h"
62
63 static int debug_level;
64 module_param(debug_level, int, 0);
65 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
66
67 /* Netif debug messages possible */
68 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
69 NETIF_MSG_PROBE | \
70 NETIF_MSG_LINK | \
71 NETIF_MSG_TIMER | \
72 NETIF_MSG_IFDOWN | \
73 NETIF_MSG_IFUP | \
74 NETIF_MSG_RX_ERR | \
75 NETIF_MSG_TX_ERR | \
76 NETIF_MSG_TX_QUEUED | \
77 NETIF_MSG_INTR | \
78 NETIF_MSG_TX_DONE | \
79 NETIF_MSG_RX_STATUS | \
80 NETIF_MSG_PKTDATA | \
81 NETIF_MSG_HW | \
82 NETIF_MSG_WOL)
83
84 /* version info */
85 #define EMAC_MAJOR_VERSION 6
86 #define EMAC_MINOR_VERSION 1
87 #define EMAC_MODULE_VERSION "6.1"
88 MODULE_VERSION(EMAC_MODULE_VERSION);
89 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
90
91 /* Configuration items */
92 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */
93 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
94 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
95 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
96 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
97 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
98 #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */
99 #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */
100 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
101 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
102 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
103 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
104
105 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
106 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
107
108 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
109 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
110 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
111 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
112 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
113 #define EMAC_DEF_RX_NUM_DESC (128)
114 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
115 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
116
117 /* Buffer descriptor parameters */
118 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
119 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
120
121 /* EMAC register related defines */
122 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
123 #define EMAC_NUM_MULTICAST_BITS (64)
124 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
125 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
126 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
127 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
128 #define EMAC_INT_MASK_CLEAR (0xFF)
129
130 /* RX MBP register bit positions */
131 #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
132 #define EMAC_RXMBP_QOSEN_MASK BIT(29)
133 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
134 #define EMAC_RXMBP_CMFEN_MASK BIT(24)
135 #define EMAC_RXMBP_CSFEN_MASK BIT(23)
136 #define EMAC_RXMBP_CEFEN_MASK BIT(22)
137 #define EMAC_RXMBP_CAFEN_MASK BIT(21)
138 #define EMAC_RXMBP_PROMCH_SHIFT (16)
139 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
140 #define EMAC_RXMBP_BROADEN_MASK BIT(13)
141 #define EMAC_RXMBP_BROADCH_SHIFT (8)
142 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
143 #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
144 #define EMAC_RXMBP_MULTICH_SHIFT (0)
145 #define EMAC_RXMBP_MULTICH_MASK (0x7)
146 #define EMAC_RXMBP_CHMASK (0x7)
147
148 /* EMAC register definitions/bit maps used */
149 # define EMAC_MBP_RXPROMISC (0x00200000)
150 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
151 # define EMAC_MBP_RXBCAST (0x00002000)
152 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
153 # define EMAC_MBP_RXMCAST (0x00000020)
154 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
155
156 /* EMAC mac_control register */
157 #define EMAC_MACCONTROL_TXPTYPE BIT(9)
158 #define EMAC_MACCONTROL_TXPACEEN BIT(6)
159 #define EMAC_MACCONTROL_GMIIEN BIT(5)
160 #define EMAC_MACCONTROL_GIGABITEN BIT(7)
161 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
162 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
163
164 /* GIGABIT MODE related bits */
165 #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
166 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
167
168 /* EMAC mac_status register */
169 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
170 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
171 #define EMAC_MACSTATUS_TXERRCH_MASK (0x70000)
172 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
173 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
174 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
175 #define EMAC_MACSTATUS_RXERRCH_MASK (0x700)
176 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
177
178 /* EMAC RX register masks */
179 #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
180 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
181
182 /* MAC_IN_VECTOR (0x180) register bit fields */
183 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
184 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
185 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
186 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
187
188 /** NOTE:: For DM646x the IN_VECTOR has changed */
189 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
190 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
191 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
192 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
193
194 /* CPPI bit positions */
195 #define EMAC_CPPI_SOP_BIT BIT(31)
196 #define EMAC_CPPI_EOP_BIT BIT(30)
197 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
198 #define EMAC_CPPI_EOQ_BIT BIT(28)
199 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
200 #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
201 #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
202 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
203 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
204
205 /* Max hardware defines */
206 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
207 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
208
209 /* EMAC Peripheral Device Register Memory Layout structure */
210 #define EMAC_MACINVECTOR 0x90
211
212 #define EMAC_DM646X_MACEOIVECTOR 0x94
213
214 #define EMAC_MACINTSTATRAW 0xB0
215 #define EMAC_MACINTSTATMASKED 0xB4
216 #define EMAC_MACINTMASKSET 0xB8
217 #define EMAC_MACINTMASKCLEAR 0xBC
218
219 #define EMAC_RXMBPENABLE 0x100
220 #define EMAC_RXUNICASTSET 0x104
221 #define EMAC_RXUNICASTCLEAR 0x108
222 #define EMAC_RXMAXLEN 0x10C
223 #define EMAC_RXBUFFEROFFSET 0x110
224 #define EMAC_RXFILTERLOWTHRESH 0x114
225
226 #define EMAC_MACCONTROL 0x160
227 #define EMAC_MACSTATUS 0x164
228 #define EMAC_EMCONTROL 0x168
229 #define EMAC_FIFOCONTROL 0x16C
230 #define EMAC_MACCONFIG 0x170
231 #define EMAC_SOFTRESET 0x174
232 #define EMAC_MACSRCADDRLO 0x1D0
233 #define EMAC_MACSRCADDRHI 0x1D4
234 #define EMAC_MACHASH1 0x1D8
235 #define EMAC_MACHASH2 0x1DC
236 #define EMAC_MACADDRLO 0x500
237 #define EMAC_MACADDRHI 0x504
238 #define EMAC_MACINDEX 0x508
239
240 /* EMAC statistics registers */
241 #define EMAC_RXGOODFRAMES 0x200
242 #define EMAC_RXBCASTFRAMES 0x204
243 #define EMAC_RXMCASTFRAMES 0x208
244 #define EMAC_RXPAUSEFRAMES 0x20C
245 #define EMAC_RXCRCERRORS 0x210
246 #define EMAC_RXALIGNCODEERRORS 0x214
247 #define EMAC_RXOVERSIZED 0x218
248 #define EMAC_RXJABBER 0x21C
249 #define EMAC_RXUNDERSIZED 0x220
250 #define EMAC_RXFRAGMENTS 0x224
251 #define EMAC_RXFILTERED 0x228
252 #define EMAC_RXQOSFILTERED 0x22C
253 #define EMAC_RXOCTETS 0x230
254 #define EMAC_TXGOODFRAMES 0x234
255 #define EMAC_TXBCASTFRAMES 0x238
256 #define EMAC_TXMCASTFRAMES 0x23C
257 #define EMAC_TXPAUSEFRAMES 0x240
258 #define EMAC_TXDEFERRED 0x244
259 #define EMAC_TXCOLLISION 0x248
260 #define EMAC_TXSINGLECOLL 0x24C
261 #define EMAC_TXMULTICOLL 0x250
262 #define EMAC_TXEXCESSIVECOLL 0x254
263 #define EMAC_TXLATECOLL 0x258
264 #define EMAC_TXUNDERRUN 0x25C
265 #define EMAC_TXCARRIERSENSE 0x260
266 #define EMAC_TXOCTETS 0x264
267 #define EMAC_NETOCTETS 0x280
268 #define EMAC_RXSOFOVERRUNS 0x284
269 #define EMAC_RXMOFOVERRUNS 0x288
270 #define EMAC_RXDMAOVERRUNS 0x28C
271
272 /* EMAC DM644x control registers */
273 #define EMAC_CTRL_EWCTL (0x4)
274 #define EMAC_CTRL_EWINTTCNT (0x8)
275
276 /* EMAC DM644x control module masks */
277 #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF
278 #define EMAC_DM644X_INTMIN_INTVL 0x1
279 #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
280
281 /* EMAC DM646X control module registers */
282 #define EMAC_DM646X_CMINTCTRL 0x0C
283 #define EMAC_DM646X_CMRXINTEN 0x14
284 #define EMAC_DM646X_CMTXINTEN 0x18
285 #define EMAC_DM646X_CMRXINTMAX 0x70
286 #define EMAC_DM646X_CMTXINTMAX 0x74
287
288 /* EMAC DM646X control module masks */
289 #define EMAC_DM646X_INTPACEEN (0x3 << 16)
290 #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0)
291 #define EMAC_DM646X_CMINTMAX_CNT 63
292 #define EMAC_DM646X_CMINTMIN_CNT 2
293 #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT)
294 #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
295
296
297 /* EMAC EOI codes for C0 */
298 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
299 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
300
301 /* EMAC Stats Clear Mask */
302 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
303
304 /* emac_priv: EMAC private data structure
305 *
306 * EMAC adapter private data structure
307 */
308 struct emac_priv {
309 u32 msg_enable;
310 struct net_device *ndev;
311 struct platform_device *pdev;
312 struct napi_struct napi;
313 char mac_addr[6];
314 void __iomem *remap_addr;
315 u32 emac_base_phys;
316 void __iomem *emac_base;
317 void __iomem *ctrl_base;
318 struct cpdma_ctlr *dma;
319 struct cpdma_chan *txchan;
320 struct cpdma_chan *rxchan;
321 u32 link; /* 1=link on, 0=link off */
322 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
323 u32 duplex; /* Link duplex: 0=Half, 1=Full */
324 u32 rx_buf_size;
325 u32 isr_count;
326 u32 coal_intvl;
327 u32 bus_freq_mhz;
328 u8 rmii_en;
329 u8 version;
330 u32 mac_hash1;
331 u32 mac_hash2;
332 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
333 u32 rx_addr_type;
334 const char *phy_id;
335 struct device_node *phy_node;
336 spinlock_t lock;
337 /*platform specific members*/
338 void (*int_enable) (void);
339 void (*int_disable) (void);
340 };
341
342 /* EMAC TX Host Error description strings */
343 static char *emac_txhost_errcodes[16] = {
344 "No error", "SOP error", "Ownership bit not set in SOP buffer",
345 "Zero Next Buffer Descriptor Pointer Without EOP",
346 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
347 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
348 "Reserved", "Reserved", "Reserved", "Reserved"
349 };
350
351 /* EMAC RX Host Error description strings */
352 static char *emac_rxhost_errcodes[16] = {
353 "No error", "Reserved", "Ownership bit not set in input buffer",
354 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
355 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
356 "Reserved", "Reserved", "Reserved", "Reserved"
357 };
358
359 /* Helper macros */
360 #define emac_read(reg) ioread32(priv->emac_base + (reg))
361 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
362
363 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
364 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
365
366 /**
367 * emac_get_drvinfo - Get EMAC driver information
368 * @ndev: The DaVinci EMAC network adapter
369 * @info: ethtool info structure containing name and version
370 *
371 * Returns EMAC driver information (name and version)
372 *
373 */
emac_get_drvinfo(struct net_device * ndev,struct ethtool_drvinfo * info)374 static void emac_get_drvinfo(struct net_device *ndev,
375 struct ethtool_drvinfo *info)
376 {
377 strscpy(info->driver, emac_version_string, sizeof(info->driver));
378 strscpy(info->version, EMAC_MODULE_VERSION, sizeof(info->version));
379 }
380
381 /**
382 * emac_get_coalesce - Get interrupt coalesce settings for this device
383 * @ndev : The DaVinci EMAC network adapter
384 * @coal : ethtool coalesce settings structure
385 * @kernel_coal: ethtool CQE mode setting structure
386 * @extack: extack for reporting error messages
387 *
388 * Fetch the current interrupt coalesce settings
389 *
390 */
emac_get_coalesce(struct net_device * ndev,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)391 static int emac_get_coalesce(struct net_device *ndev,
392 struct ethtool_coalesce *coal,
393 struct kernel_ethtool_coalesce *kernel_coal,
394 struct netlink_ext_ack *extack)
395 {
396 struct emac_priv *priv = netdev_priv(ndev);
397
398 coal->rx_coalesce_usecs = priv->coal_intvl;
399 return 0;
400
401 }
402
403 /**
404 * emac_set_coalesce - Set interrupt coalesce settings for this device
405 * @ndev : The DaVinci EMAC network adapter
406 * @coal : ethtool coalesce settings structure
407 * @kernel_coal: ethtool CQE mode setting structure
408 * @extack: extack for reporting error messages
409 *
410 * Set interrupt coalesce parameters
411 *
412 */
emac_set_coalesce(struct net_device * ndev,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)413 static int emac_set_coalesce(struct net_device *ndev,
414 struct ethtool_coalesce *coal,
415 struct kernel_ethtool_coalesce *kernel_coal,
416 struct netlink_ext_ack *extack)
417 {
418 struct emac_priv *priv = netdev_priv(ndev);
419 u32 int_ctrl, num_interrupts = 0;
420 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;
421
422 if (!coal->rx_coalesce_usecs) {
423 priv->coal_intvl = 0;
424
425 switch (priv->version) {
426 case EMAC_VERSION_2:
427 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, 0);
428 break;
429 default:
430 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, 0);
431 break;
432 }
433
434 return 0;
435 }
436
437 coal_intvl = coal->rx_coalesce_usecs;
438
439 switch (priv->version) {
440 case EMAC_VERSION_2:
441 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
442 prescale = priv->bus_freq_mhz * 4;
443
444 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
445 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;
446
447 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
448 /*
449 * Interrupt pacer works with 4us Pulse, we can
450 * throttle further by dilating the 4us pulse.
451 */
452 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;
453
454 if (addnl_dvdr > 1) {
455 prescale *= addnl_dvdr;
456 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
457 * addnl_dvdr))
458 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
459 * addnl_dvdr);
460 } else {
461 addnl_dvdr = 1;
462 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
463 }
464 }
465
466 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
467
468 int_ctrl |= EMAC_DM646X_INTPACEEN;
469 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
470 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
471 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);
472
473 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
474 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);
475
476 break;
477 default:
478 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
479 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
480 prescale = coal_intvl * priv->bus_freq_mhz;
481 if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
482 prescale = EMAC_DM644X_EWINTCNT_MASK;
483 coal_intvl = prescale / priv->bus_freq_mhz;
484 }
485 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));
486
487 break;
488 }
489
490 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
491 priv->coal_intvl = coal_intvl;
492
493 return 0;
494
495 }
496
497
498 /* ethtool_ops: DaVinci EMAC Ethtool structure
499 *
500 * Ethtool support for EMAC adapter
501 */
502 static const struct ethtool_ops ethtool_ops = {
503 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS,
504 .get_drvinfo = emac_get_drvinfo,
505 .get_link = ethtool_op_get_link,
506 .get_coalesce = emac_get_coalesce,
507 .set_coalesce = emac_set_coalesce,
508 .get_ts_info = ethtool_op_get_ts_info,
509 .get_link_ksettings = phy_ethtool_get_link_ksettings,
510 .set_link_ksettings = phy_ethtool_set_link_ksettings,
511 };
512
513 /**
514 * emac_update_phystatus - Update Phy status
515 * @priv: The DaVinci EMAC private adapter structure
516 *
517 * Updates phy status and takes action for network queue if required
518 * based upon link status
519 *
520 */
emac_update_phystatus(struct emac_priv * priv)521 static void emac_update_phystatus(struct emac_priv *priv)
522 {
523 u32 mac_control;
524 u32 new_duplex;
525 u32 cur_duplex;
526 struct net_device *ndev = priv->ndev;
527
528 mac_control = emac_read(EMAC_MACCONTROL);
529 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
530 DUPLEX_FULL : DUPLEX_HALF;
531 if (ndev->phydev)
532 new_duplex = ndev->phydev->duplex;
533 else
534 new_duplex = DUPLEX_FULL;
535
536 /* We get called only if link has changed (speed/duplex/status) */
537 if ((priv->link) && (new_duplex != cur_duplex)) {
538 priv->duplex = new_duplex;
539 if (DUPLEX_FULL == priv->duplex)
540 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
541 else
542 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
543 }
544
545 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
546 mac_control = emac_read(EMAC_MACCONTROL);
547 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
548 EMAC_DM646X_MACCONTORL_GIGFORCE);
549 } else {
550 /* Clear the GIG bit and GIGFORCE bit */
551 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
552 EMAC_DM646X_MACCONTORL_GIG);
553
554 if (priv->rmii_en && (priv->speed == SPEED_100))
555 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
556 else
557 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
558 }
559
560 /* Update mac_control if changed */
561 emac_write(EMAC_MACCONTROL, mac_control);
562
563 if (priv->link) {
564 /* link ON */
565 if (!netif_carrier_ok(ndev))
566 netif_carrier_on(ndev);
567 /* reactivate the transmit queue if it is stopped */
568 if (netif_running(ndev) && netif_queue_stopped(ndev))
569 netif_wake_queue(ndev);
570 } else {
571 /* link OFF */
572 if (netif_carrier_ok(ndev))
573 netif_carrier_off(ndev);
574 if (!netif_queue_stopped(ndev))
575 netif_stop_queue(ndev);
576 }
577 }
578
579 /**
580 * hash_get - Calculate hash value from mac address
581 * @addr: mac address to delete from hash table
582 *
583 * Calculates hash value from mac address
584 *
585 */
hash_get(u8 * addr)586 static u32 hash_get(u8 *addr)
587 {
588 u32 hash;
589 u8 tmpval;
590 int cnt;
591 hash = 0;
592
593 for (cnt = 0; cnt < 2; cnt++) {
594 tmpval = *addr++;
595 hash ^= (tmpval >> 2) ^ (tmpval << 4);
596 tmpval = *addr++;
597 hash ^= (tmpval >> 4) ^ (tmpval << 2);
598 tmpval = *addr++;
599 hash ^= (tmpval >> 6) ^ (tmpval);
600 }
601
602 return hash & 0x3F;
603 }
604
605 /**
606 * emac_hash_add - Hash function to add mac addr from hash table
607 * @priv: The DaVinci EMAC private adapter structure
608 * @mac_addr: mac address to delete from hash table
609 *
610 * Adds mac address to the internal hash table
611 *
612 */
emac_hash_add(struct emac_priv * priv,u8 * mac_addr)613 static int emac_hash_add(struct emac_priv *priv, u8 *mac_addr)
614 {
615 struct device *emac_dev = &priv->ndev->dev;
616 u32 rc = 0;
617 u32 hash_bit;
618 u32 hash_value = hash_get(mac_addr);
619
620 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
621 if (netif_msg_drv(priv)) {
622 dev_err(emac_dev, "DaVinci EMAC: emac_hash_add(): Invalid "\
623 "Hash %08x, should not be greater than %08x",
624 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
625 }
626 return -1;
627 }
628
629 /* set the hash bit only if not previously set */
630 if (priv->multicast_hash_cnt[hash_value] == 0) {
631 rc = 1; /* hash value changed */
632 if (hash_value < 32) {
633 hash_bit = BIT(hash_value);
634 priv->mac_hash1 |= hash_bit;
635 } else {
636 hash_bit = BIT((hash_value - 32));
637 priv->mac_hash2 |= hash_bit;
638 }
639 }
640
641 /* incr counter for num of mcast addr's mapped to "this" hash bit */
642 ++priv->multicast_hash_cnt[hash_value];
643
644 return rc;
645 }
646
647 /**
648 * emac_hash_del - Hash function to delete mac addr from hash table
649 * @priv: The DaVinci EMAC private adapter structure
650 * @mac_addr: mac address to delete from hash table
651 *
652 * Removes mac address from the internal hash table
653 *
654 */
emac_hash_del(struct emac_priv * priv,u8 * mac_addr)655 static int emac_hash_del(struct emac_priv *priv, u8 *mac_addr)
656 {
657 u32 hash_value;
658 u32 hash_bit;
659
660 hash_value = hash_get(mac_addr);
661 if (priv->multicast_hash_cnt[hash_value] > 0) {
662 /* dec cntr for num of mcast addr's mapped to this hash bit */
663 --priv->multicast_hash_cnt[hash_value];
664 }
665
666 /* if counter still > 0, at least one multicast address refers
667 * to this hash bit. so return 0 */
668 if (priv->multicast_hash_cnt[hash_value] > 0)
669 return 0;
670
671 if (hash_value < 32) {
672 hash_bit = BIT(hash_value);
673 priv->mac_hash1 &= ~hash_bit;
674 } else {
675 hash_bit = BIT((hash_value - 32));
676 priv->mac_hash2 &= ~hash_bit;
677 }
678
679 /* return 1 to indicate change in mac_hash registers reqd */
680 return 1;
681 }
682
683 /* EMAC multicast operation */
684 #define EMAC_MULTICAST_ADD 0
685 #define EMAC_MULTICAST_DEL 1
686 #define EMAC_ALL_MULTI_SET 2
687 #define EMAC_ALL_MULTI_CLR 3
688
689 /**
690 * emac_add_mcast - Set multicast address in the EMAC adapter (Internal)
691 * @priv: The DaVinci EMAC private adapter structure
692 * @action: multicast operation to perform
693 * @mac_addr: mac address to set
694 *
695 * Set multicast addresses in EMAC adapter - internal function
696 *
697 */
emac_add_mcast(struct emac_priv * priv,u32 action,u8 * mac_addr)698 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
699 {
700 struct device *emac_dev = &priv->ndev->dev;
701 int update = -1;
702
703 switch (action) {
704 case EMAC_MULTICAST_ADD:
705 update = emac_hash_add(priv, mac_addr);
706 break;
707 case EMAC_MULTICAST_DEL:
708 update = emac_hash_del(priv, mac_addr);
709 break;
710 case EMAC_ALL_MULTI_SET:
711 update = 1;
712 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
713 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
714 break;
715 case EMAC_ALL_MULTI_CLR:
716 update = 1;
717 priv->mac_hash1 = 0;
718 priv->mac_hash2 = 0;
719 memset(&(priv->multicast_hash_cnt[0]), 0,
720 sizeof(priv->multicast_hash_cnt[0]) *
721 EMAC_NUM_MULTICAST_BITS);
722 break;
723 default:
724 if (netif_msg_drv(priv))
725 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
726 ": bad operation %d", action);
727 break;
728 }
729
730 /* write to the hardware only if the register status chances */
731 if (update > 0) {
732 emac_write(EMAC_MACHASH1, priv->mac_hash1);
733 emac_write(EMAC_MACHASH2, priv->mac_hash2);
734 }
735 }
736
737 /**
738 * emac_dev_mcast_set - Set multicast address in the EMAC adapter
739 * @ndev: The DaVinci EMAC network adapter
740 *
741 * Set multicast addresses in EMAC adapter
742 *
743 */
emac_dev_mcast_set(struct net_device * ndev)744 static void emac_dev_mcast_set(struct net_device *ndev)
745 {
746 u32 mbp_enable;
747 struct emac_priv *priv = netdev_priv(ndev);
748
749 mbp_enable = emac_read(EMAC_RXMBPENABLE);
750 if (ndev->flags & IFF_PROMISC) {
751 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
752 mbp_enable |= (EMAC_MBP_RXPROMISC);
753 } else {
754 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
755 if ((ndev->flags & IFF_ALLMULTI) ||
756 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
757 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
758 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
759 } else if (!netdev_mc_empty(ndev)) {
760 struct netdev_hw_addr *ha;
761
762 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
763 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
764 /* program multicast address list into EMAC hardware */
765 netdev_for_each_mc_addr(ha, ndev) {
766 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
767 (u8 *) ha->addr);
768 }
769 } else {
770 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
771 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
772 }
773 }
774 /* Set mbp config register */
775 emac_write(EMAC_RXMBPENABLE, mbp_enable);
776 }
777
778 /*************************************************************************
779 * EMAC Hardware manipulation
780 *************************************************************************/
781
782 /**
783 * emac_int_disable - Disable EMAC module interrupt (from adapter)
784 * @priv: The DaVinci EMAC private adapter structure
785 *
786 * Disable EMAC interrupt on the adapter
787 *
788 */
emac_int_disable(struct emac_priv * priv)789 static void emac_int_disable(struct emac_priv *priv)
790 {
791 if (priv->version == EMAC_VERSION_2) {
792 unsigned long flags;
793
794 local_irq_save(flags);
795
796 /* Program C0_Int_En to zero to turn off
797 * interrupts to the CPU */
798 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
799 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
800 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
801 if (priv->int_disable)
802 priv->int_disable();
803
804 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
805
806 /* ack rxen only then a new pulse will be generated */
807 emac_write(EMAC_DM646X_MACEOIVECTOR,
808 EMAC_DM646X_MAC_EOI_C0_RXEN);
809
810 /* ack txen- only then a new pulse will be generated */
811 emac_write(EMAC_DM646X_MACEOIVECTOR,
812 EMAC_DM646X_MAC_EOI_C0_TXEN);
813
814 local_irq_restore(flags);
815
816 } else {
817 /* Set DM644x control registers for interrupt control */
818 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
819 }
820 }
821
822 /**
823 * emac_int_enable - Enable EMAC module interrupt (from adapter)
824 * @priv: The DaVinci EMAC private adapter structure
825 *
826 * Enable EMAC interrupt on the adapter
827 *
828 */
emac_int_enable(struct emac_priv * priv)829 static void emac_int_enable(struct emac_priv *priv)
830 {
831 if (priv->version == EMAC_VERSION_2) {
832 if (priv->int_enable)
833 priv->int_enable();
834
835 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
836 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
837
838 /* In addition to turning on interrupt Enable, we need
839 * ack by writing appropriate values to the EOI
840 * register */
841
842 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
843 } else {
844 /* Set DM644x control registers for interrupt control */
845 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
846 }
847 }
848
849 /**
850 * emac_irq - EMAC interrupt handler
851 * @irq: interrupt number
852 * @dev_id: EMAC network adapter data structure ptr
853 *
854 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
855 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
856 *
857 * Returns interrupt handled condition
858 */
emac_irq(int irq,void * dev_id)859 static irqreturn_t emac_irq(int irq, void *dev_id)
860 {
861 struct net_device *ndev = (struct net_device *)dev_id;
862 struct emac_priv *priv = netdev_priv(ndev);
863
864 ++priv->isr_count;
865 if (likely(netif_running(priv->ndev))) {
866 emac_int_disable(priv);
867 napi_schedule(&priv->napi);
868 } else {
869 /* we are closing down, so dont process anything */
870 }
871 return IRQ_HANDLED;
872 }
873
emac_rx_alloc(struct emac_priv * priv)874 static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
875 {
876 struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size);
877 if (WARN_ON(!skb))
878 return NULL;
879 skb_reserve(skb, NET_IP_ALIGN);
880 return skb;
881 }
882
emac_rx_handler(void * token,int len,int status)883 static void emac_rx_handler(void *token, int len, int status)
884 {
885 struct sk_buff *skb = token;
886 struct net_device *ndev = skb->dev;
887 struct emac_priv *priv = netdev_priv(ndev);
888 struct device *emac_dev = &ndev->dev;
889 int ret;
890
891 /* free and bail if we are shutting down */
892 if (unlikely(!netif_running(ndev))) {
893 dev_kfree_skb_any(skb);
894 return;
895 }
896
897 /* recycle on receive error */
898 if (status < 0) {
899 ndev->stats.rx_errors++;
900 goto recycle;
901 }
902
903 /* feed received packet up the stack */
904 skb_put(skb, len);
905 skb->protocol = eth_type_trans(skb, ndev);
906 netif_receive_skb(skb);
907 ndev->stats.rx_bytes += len;
908 ndev->stats.rx_packets++;
909
910 /* alloc a new packet for receive */
911 skb = emac_rx_alloc(priv);
912 if (!skb) {
913 if (netif_msg_rx_err(priv) && net_ratelimit())
914 dev_err(emac_dev, "failed rx buffer alloc\n");
915 return;
916 }
917
918 recycle:
919 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
920 skb_tailroom(skb), 0);
921
922 WARN_ON(ret == -ENOMEM);
923 if (unlikely(ret < 0))
924 dev_kfree_skb_any(skb);
925 }
926
emac_tx_handler(void * token,int len,int status)927 static void emac_tx_handler(void *token, int len, int status)
928 {
929 struct sk_buff *skb = token;
930 struct net_device *ndev = skb->dev;
931
932 /* Check whether the queue is stopped due to stalled tx dma, if the
933 * queue is stopped then start the queue as we have free desc for tx
934 */
935 if (unlikely(netif_queue_stopped(ndev)))
936 netif_wake_queue(ndev);
937 ndev->stats.tx_packets++;
938 ndev->stats.tx_bytes += len;
939 dev_kfree_skb_any(skb);
940 }
941
942 /**
943 * emac_dev_xmit - EMAC Transmit function
944 * @skb: SKB pointer
945 * @ndev: The DaVinci EMAC network adapter
946 *
947 * Called by the system to transmit a packet - we queue the packet in
948 * EMAC hardware transmit queue
949 *
950 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
951 */
emac_dev_xmit(struct sk_buff * skb,struct net_device * ndev)952 static netdev_tx_t emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
953 {
954 struct device *emac_dev = &ndev->dev;
955 int ret_code;
956 struct emac_priv *priv = netdev_priv(ndev);
957
958 /* If no link, return */
959 if (unlikely(!priv->link)) {
960 if (netif_msg_tx_err(priv) && net_ratelimit())
961 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
962 goto fail_tx;
963 }
964
965 ret_code = skb_put_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
966 if (unlikely(ret_code < 0)) {
967 if (netif_msg_tx_err(priv) && net_ratelimit())
968 dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
969 goto fail_tx;
970 }
971
972 skb_tx_timestamp(skb);
973
974 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
975 0);
976 if (unlikely(ret_code != 0)) {
977 if (netif_msg_tx_err(priv) && net_ratelimit())
978 dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
979 goto fail_tx;
980 }
981
982 /* If there is no more tx desc left free then we need to
983 * tell the kernel to stop sending us tx frames.
984 */
985 if (unlikely(!cpdma_check_free_tx_desc(priv->txchan)))
986 netif_stop_queue(ndev);
987
988 return NETDEV_TX_OK;
989
990 fail_tx:
991 ndev->stats.tx_dropped++;
992 netif_stop_queue(ndev);
993 return NETDEV_TX_BUSY;
994 }
995
996 /**
997 * emac_dev_tx_timeout - EMAC Transmit timeout function
998 * @ndev: The DaVinci EMAC network adapter
999 * @txqueue: the index of the hung transmit queue
1000 *
1001 * Called when system detects that a skb timeout period has expired
1002 * potentially due to a fault in the adapter in not being able to send
1003 * it out on the wire. We teardown the TX channel assuming a hardware
1004 * error and re-initialize the TX channel for hardware operation
1005 *
1006 */
emac_dev_tx_timeout(struct net_device * ndev,unsigned int txqueue)1007 static void emac_dev_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1008 {
1009 struct emac_priv *priv = netdev_priv(ndev);
1010 struct device *emac_dev = &ndev->dev;
1011
1012 if (netif_msg_tx_err(priv))
1013 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1014
1015 ndev->stats.tx_errors++;
1016 emac_int_disable(priv);
1017 cpdma_chan_stop(priv->txchan);
1018 cpdma_chan_start(priv->txchan);
1019 emac_int_enable(priv);
1020 }
1021
1022 /**
1023 * emac_set_type0addr - Set EMAC Type0 mac address
1024 * @priv: The DaVinci EMAC private adapter structure
1025 * @ch: RX channel number
1026 * @mac_addr: MAC address to set in device
1027 *
1028 * Called internally to set Type0 mac address of the adapter (Device)
1029 *
1030 * Returns success (0) or appropriate error code (none as of now)
1031 */
emac_set_type0addr(struct emac_priv * priv,u32 ch,char * mac_addr)1032 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1033 {
1034 u32 val;
1035 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1036 emac_write(EMAC_MACSRCADDRLO, val);
1037
1038 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1039 (mac_addr[1] << 8) | (mac_addr[0]));
1040 emac_write(EMAC_MACSRCADDRHI, val);
1041 val = emac_read(EMAC_RXUNICASTSET);
1042 val |= BIT(ch);
1043 emac_write(EMAC_RXUNICASTSET, val);
1044 val = emac_read(EMAC_RXUNICASTCLEAR);
1045 val &= ~BIT(ch);
1046 emac_write(EMAC_RXUNICASTCLEAR, val);
1047 }
1048
1049 /**
1050 * emac_set_type1addr - Set EMAC Type1 mac address
1051 * @priv: The DaVinci EMAC private adapter structure
1052 * @ch: RX channel number
1053 * @mac_addr: MAC address to set in device
1054 *
1055 * Called internally to set Type1 mac address of the adapter (Device)
1056 *
1057 * Returns success (0) or appropriate error code (none as of now)
1058 */
emac_set_type1addr(struct emac_priv * priv,u32 ch,char * mac_addr)1059 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1060 {
1061 u32 val;
1062 emac_write(EMAC_MACINDEX, ch);
1063 val = ((mac_addr[5] << 8) | mac_addr[4]);
1064 emac_write(EMAC_MACADDRLO, val);
1065 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1066 (mac_addr[1] << 8) | (mac_addr[0]));
1067 emac_write(EMAC_MACADDRHI, val);
1068 emac_set_type0addr(priv, ch, mac_addr);
1069 }
1070
1071 /**
1072 * emac_set_type2addr - Set EMAC Type2 mac address
1073 * @priv: The DaVinci EMAC private adapter structure
1074 * @ch: RX channel number
1075 * @mac_addr: MAC address to set in device
1076 * @index: index into RX address entries
1077 * @match: match parameter for RX address matching logic
1078 *
1079 * Called internally to set Type2 mac address of the adapter (Device)
1080 *
1081 * Returns success (0) or appropriate error code (none as of now)
1082 */
emac_set_type2addr(struct emac_priv * priv,u32 ch,char * mac_addr,int index,int match)1083 static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1084 char *mac_addr, int index, int match)
1085 {
1086 u32 val;
1087 emac_write(EMAC_MACINDEX, index);
1088 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1089 (mac_addr[1] << 8) | (mac_addr[0]));
1090 emac_write(EMAC_MACADDRHI, val);
1091 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1092 (match << 19) | BIT(20));
1093 emac_write(EMAC_MACADDRLO, val);
1094 emac_set_type0addr(priv, ch, mac_addr);
1095 }
1096
1097 /**
1098 * emac_setmac - Set mac address in the adapter (internal function)
1099 * @priv: The DaVinci EMAC private adapter structure
1100 * @ch: RX channel number
1101 * @mac_addr: MAC address to set in device
1102 *
1103 * Called internally to set the mac address of the adapter (Device)
1104 *
1105 * Returns success (0) or appropriate error code (none as of now)
1106 */
emac_setmac(struct emac_priv * priv,u32 ch,char * mac_addr)1107 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1108 {
1109 struct device *emac_dev = &priv->ndev->dev;
1110
1111 if (priv->rx_addr_type == 0) {
1112 emac_set_type0addr(priv, ch, mac_addr);
1113 } else if (priv->rx_addr_type == 1) {
1114 u32 cnt;
1115 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1116 emac_set_type1addr(priv, ch, mac_addr);
1117 } else if (priv->rx_addr_type == 2) {
1118 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1119 emac_set_type0addr(priv, ch, mac_addr);
1120 } else {
1121 if (netif_msg_drv(priv))
1122 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1123 }
1124 }
1125
1126 /**
1127 * emac_dev_setmac_addr - Set mac address in the adapter
1128 * @ndev: The DaVinci EMAC network adapter
1129 * @addr: MAC address to set in device
1130 *
1131 * Called by the system to set the mac address of the adapter (Device)
1132 *
1133 * Returns success (0) or appropriate error code (none as of now)
1134 */
emac_dev_setmac_addr(struct net_device * ndev,void * addr)1135 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1136 {
1137 struct emac_priv *priv = netdev_priv(ndev);
1138 struct device *emac_dev = &priv->ndev->dev;
1139 struct sockaddr *sa = addr;
1140
1141 if (!is_valid_ether_addr(sa->sa_data))
1142 return -EADDRNOTAVAIL;
1143
1144 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1145 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1146 eth_hw_addr_set(ndev, sa->sa_data);
1147
1148 /* MAC address is configured only after the interface is enabled. */
1149 if (netif_running(ndev)) {
1150 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1151 }
1152
1153 if (netif_msg_drv(priv))
1154 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1155 priv->mac_addr);
1156
1157 return 0;
1158 }
1159
1160 /**
1161 * emac_hw_enable - Enable EMAC hardware for packet transmission/reception
1162 * @priv: The DaVinci EMAC private adapter structure
1163 *
1164 * Enables EMAC hardware for packet processing - enables PHY, enables RX
1165 * for packet reception and enables device interrupts and then NAPI
1166 *
1167 * Returns success (0) or appropriate error code (none right now)
1168 */
emac_hw_enable(struct emac_priv * priv)1169 static int emac_hw_enable(struct emac_priv *priv)
1170 {
1171 u32 val, mbp_enable, mac_control;
1172
1173 /* Soft reset */
1174 emac_write(EMAC_SOFTRESET, 1);
1175 while (emac_read(EMAC_SOFTRESET))
1176 cpu_relax();
1177
1178 /* Disable interrupt & Set pacing for more interrupts initially */
1179 emac_int_disable(priv);
1180
1181 /* Full duplex enable bit set when auto negotiation happens */
1182 mac_control =
1183 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
1184 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
1185 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
1186 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
1187 emac_write(EMAC_MACCONTROL, mac_control);
1188
1189 mbp_enable =
1190 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
1191 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
1192 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
1193 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
1194 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
1195 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
1196 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
1197 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
1198 EMAC_RXMBP_PROMCH_SHIFT) |
1199 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
1200 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
1201 EMAC_RXMBP_BROADCH_SHIFT) |
1202 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
1203 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
1204 EMAC_RXMBP_MULTICH_SHIFT));
1205 emac_write(EMAC_RXMBPENABLE, mbp_enable);
1206 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
1207 EMAC_RX_MAX_LEN_MASK));
1208 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
1209 EMAC_RX_BUFFER_OFFSET_MASK));
1210 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
1211 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
1212 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
1213
1214 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
1215
1216 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1217
1218 /* Enable MII */
1219 val = emac_read(EMAC_MACCONTROL);
1220 val |= (EMAC_MACCONTROL_GMIIEN);
1221 emac_write(EMAC_MACCONTROL, val);
1222
1223 /* Enable NAPI and interrupts */
1224 napi_enable(&priv->napi);
1225 emac_int_enable(priv);
1226 return 0;
1227
1228 }
1229
1230 /**
1231 * emac_poll - EMAC NAPI Poll function
1232 * @napi: pointer to the napi_struct containing The DaVinci EMAC network adapter
1233 * @budget: Number of receive packets to process (as told by NAPI layer)
1234 *
1235 * NAPI Poll function implemented to process packets as per budget. We check
1236 * the type of interrupt on the device and accordingly call the TX or RX
1237 * packet processing functions. We follow the budget for RX processing and
1238 * also put a cap on number of TX pkts processed through config param. The
1239 * NAPI schedule function is called if more packets pending.
1240 *
1241 * Returns number of packets received (in most cases; else TX pkts - rarely)
1242 */
emac_poll(struct napi_struct * napi,int budget)1243 static int emac_poll(struct napi_struct *napi, int budget)
1244 {
1245 unsigned int mask;
1246 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
1247 struct net_device *ndev = priv->ndev;
1248 struct device *emac_dev = &ndev->dev;
1249 u32 status = 0;
1250 u32 num_rx_pkts = 0;
1251
1252 /* Check interrupt vectors and call packet processing */
1253 status = emac_read(EMAC_MACINVECTOR);
1254
1255 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
1256
1257 if (priv->version == EMAC_VERSION_2)
1258 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
1259
1260 if (status & mask) {
1261 cpdma_chan_process(priv->txchan, EMAC_DEF_TX_MAX_SERVICE);
1262 } /* TX processing */
1263
1264 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
1265
1266 if (priv->version == EMAC_VERSION_2)
1267 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
1268
1269 if (status & mask) {
1270 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
1271 } /* RX processing */
1272
1273 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
1274 if (priv->version == EMAC_VERSION_2)
1275 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
1276
1277 if (unlikely(status & mask)) {
1278 u32 ch, cause;
1279 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
1280 netif_stop_queue(ndev);
1281 napi_disable(&priv->napi);
1282
1283 status = emac_read(EMAC_MACSTATUS);
1284 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
1285 EMAC_MACSTATUS_TXERRCODE_SHIFT);
1286 if (cause) {
1287 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
1288 EMAC_MACSTATUS_TXERRCH_SHIFT);
1289 if (net_ratelimit()) {
1290 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
1291 &emac_txhost_errcodes[cause][0], ch);
1292 }
1293 }
1294 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
1295 EMAC_MACSTATUS_RXERRCODE_SHIFT);
1296 if (cause) {
1297 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
1298 EMAC_MACSTATUS_RXERRCH_SHIFT);
1299 if (netif_msg_hw(priv) && net_ratelimit())
1300 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
1301 &emac_rxhost_errcodes[cause][0], ch);
1302 }
1303 } else if (num_rx_pkts < budget) {
1304 napi_complete_done(napi, num_rx_pkts);
1305 emac_int_enable(priv);
1306 }
1307
1308 return num_rx_pkts;
1309 }
1310
1311 #ifdef CONFIG_NET_POLL_CONTROLLER
1312 /**
1313 * emac_poll_controller - EMAC Poll controller function
1314 * @ndev: The DaVinci EMAC network adapter
1315 *
1316 * Polled functionality used by netconsole and others in non interrupt mode
1317 *
1318 */
emac_poll_controller(struct net_device * ndev)1319 static void emac_poll_controller(struct net_device *ndev)
1320 {
1321 struct emac_priv *priv = netdev_priv(ndev);
1322
1323 emac_int_disable(priv);
1324 emac_irq(ndev->irq, ndev);
1325 emac_int_enable(priv);
1326 }
1327 #endif
1328
emac_adjust_link(struct net_device * ndev)1329 static void emac_adjust_link(struct net_device *ndev)
1330 {
1331 struct emac_priv *priv = netdev_priv(ndev);
1332 struct phy_device *phydev = ndev->phydev;
1333 unsigned long flags;
1334 int new_state = 0;
1335
1336 spin_lock_irqsave(&priv->lock, flags);
1337
1338 if (phydev->link) {
1339 /* check the mode of operation - full/half duplex */
1340 if (phydev->duplex != priv->duplex) {
1341 new_state = 1;
1342 priv->duplex = phydev->duplex;
1343 }
1344 if (phydev->speed != priv->speed) {
1345 new_state = 1;
1346 priv->speed = phydev->speed;
1347 }
1348 if (!priv->link) {
1349 new_state = 1;
1350 priv->link = 1;
1351 }
1352
1353 } else if (priv->link) {
1354 new_state = 1;
1355 priv->link = 0;
1356 priv->speed = 0;
1357 priv->duplex = ~0;
1358 }
1359 if (new_state) {
1360 emac_update_phystatus(priv);
1361 phy_print_status(ndev->phydev);
1362 }
1363
1364 spin_unlock_irqrestore(&priv->lock, flags);
1365 }
1366
1367 /*************************************************************************
1368 * Linux Driver Model
1369 *************************************************************************/
1370
1371 /**
1372 * emac_devioctl - EMAC adapter ioctl
1373 * @ndev: The DaVinci EMAC network adapter
1374 * @ifrq: request parameter
1375 * @cmd: command parameter
1376 *
1377 * EMAC driver ioctl function
1378 *
1379 * Returns success(0) or appropriate error code
1380 */
emac_devioctl(struct net_device * ndev,struct ifreq * ifrq,int cmd)1381 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
1382 {
1383 if (!(netif_running(ndev)))
1384 return -EINVAL;
1385
1386 /* TODO: Add phy read and write and private statistics get feature */
1387
1388 if (ndev->phydev)
1389 return phy_mii_ioctl(ndev->phydev, ifrq, cmd);
1390 else
1391 return -EOPNOTSUPP;
1392 }
1393
match_first_device(struct device * dev,const void * data)1394 static int match_first_device(struct device *dev, const void *data)
1395 {
1396 if (dev->parent && dev->parent->of_node)
1397 return of_device_is_compatible(dev->parent->of_node,
1398 "ti,davinci_mdio");
1399
1400 return !strncmp(dev_name(dev), "davinci_mdio", 12);
1401 }
1402
1403 /**
1404 * emac_dev_open - EMAC device open
1405 * @ndev: The DaVinci EMAC network adapter
1406 *
1407 * Called when system wants to start the interface. We init TX/RX channels
1408 * and enable the hardware for packet reception/transmission and start the
1409 * network queue.
1410 *
1411 * Returns 0 for a successful open, or appropriate error code
1412 */
emac_dev_open(struct net_device * ndev)1413 static int emac_dev_open(struct net_device *ndev)
1414 {
1415 struct device *emac_dev = &ndev->dev;
1416 struct resource *res;
1417 int q, m, ret;
1418 int res_num = 0, irq_num = 0;
1419 int i = 0;
1420 struct emac_priv *priv = netdev_priv(ndev);
1421 struct phy_device *phydev = NULL;
1422 struct device *phy = NULL;
1423
1424 ret = pm_runtime_resume_and_get(&priv->pdev->dev);
1425 if (ret < 0) {
1426 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
1427 __func__, ret);
1428 return ret;
1429 }
1430
1431 netif_carrier_off(ndev);
1432 eth_hw_addr_set(ndev, priv->mac_addr);
1433
1434 /* Configuration items */
1435 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
1436
1437 priv->mac_hash1 = 0;
1438 priv->mac_hash2 = 0;
1439 emac_write(EMAC_MACHASH1, 0);
1440 emac_write(EMAC_MACHASH2, 0);
1441
1442 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
1443 struct sk_buff *skb = emac_rx_alloc(priv);
1444
1445 if (!skb)
1446 break;
1447
1448 ret = cpdma_chan_idle_submit(priv->rxchan, skb, skb->data,
1449 skb_tailroom(skb), 0);
1450 if (WARN_ON(ret < 0))
1451 break;
1452 }
1453
1454 /* Request IRQ */
1455 if (dev_of_node(&priv->pdev->dev)) {
1456 while ((ret = platform_get_irq_optional(priv->pdev, res_num)) != -ENXIO) {
1457 if (ret < 0)
1458 goto rollback;
1459
1460 ret = request_irq(ret, emac_irq, 0, ndev->name, ndev);
1461 if (ret) {
1462 dev_err(emac_dev, "DaVinci EMAC: request_irq() failed\n");
1463 goto rollback;
1464 }
1465 res_num++;
1466 }
1467 } else {
1468 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, res_num))) {
1469 for (irq_num = res->start; irq_num <= res->end; irq_num++) {
1470 ret = request_irq(irq_num, emac_irq, 0, ndev->name, ndev);
1471 if (ret) {
1472 dev_err(emac_dev, "DaVinci EMAC: request_irq() failed\n");
1473 goto rollback;
1474 }
1475 }
1476 res_num++;
1477 }
1478 /* prepare counters for rollback in case of an error */
1479 res_num--;
1480 irq_num--;
1481 }
1482
1483 /* Start/Enable EMAC hardware */
1484 emac_hw_enable(priv);
1485
1486 /* Enable Interrupt pacing if configured */
1487 if (priv->coal_intvl != 0) {
1488 struct ethtool_coalesce coal;
1489
1490 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1491 emac_set_coalesce(ndev, &coal, NULL, NULL);
1492 }
1493
1494 cpdma_ctlr_start(priv->dma);
1495
1496 if (priv->phy_node) {
1497 phydev = of_phy_connect(ndev, priv->phy_node,
1498 &emac_adjust_link, 0, 0);
1499 if (!phydev) {
1500 dev_err(emac_dev, "could not connect to phy %pOF\n",
1501 priv->phy_node);
1502 ret = -ENODEV;
1503 goto err;
1504 }
1505 }
1506
1507 /* use the first phy on the bus if pdata did not give us a phy id */
1508 if (!phydev && !priv->phy_id) {
1509 /* NOTE: we can't use bus_find_device_by_name() here because
1510 * the device name is not guaranteed to be 'davinci_mdio'. On
1511 * some systems it can be 'davinci_mdio.0' so we need to use
1512 * strncmp() against the first part of the string to correctly
1513 * match it.
1514 */
1515 phy = bus_find_device(&mdio_bus_type, NULL, NULL,
1516 match_first_device);
1517 if (phy) {
1518 priv->phy_id = dev_name(phy);
1519 if (!priv->phy_id || !*priv->phy_id)
1520 put_device(phy);
1521 }
1522 }
1523
1524 if (!phydev && priv->phy_id && *priv->phy_id) {
1525 phydev = phy_connect(ndev, priv->phy_id,
1526 &emac_adjust_link,
1527 PHY_INTERFACE_MODE_MII);
1528 put_device(phy); /* reference taken by bus_find_device */
1529 if (IS_ERR(phydev)) {
1530 dev_err(emac_dev, "could not connect to phy %s\n",
1531 priv->phy_id);
1532 ret = PTR_ERR(phydev);
1533 goto err;
1534 }
1535
1536 priv->link = 0;
1537 priv->speed = 0;
1538 priv->duplex = ~0;
1539
1540 phy_attached_info(phydev);
1541 }
1542
1543 if (!phydev) {
1544 /* No PHY , fix the link, speed and duplex settings */
1545 dev_notice(emac_dev, "no phy, defaulting to 100/full\n");
1546 priv->link = 1;
1547 priv->speed = SPEED_100;
1548 priv->duplex = DUPLEX_FULL;
1549 emac_update_phystatus(priv);
1550 }
1551
1552 if (netif_msg_drv(priv))
1553 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
1554
1555 if (phydev)
1556 phy_start(phydev);
1557
1558 return 0;
1559
1560 err:
1561 emac_int_disable(priv);
1562 napi_disable(&priv->napi);
1563
1564 rollback:
1565 if (dev_of_node(&priv->pdev->dev)) {
1566 for (q = res_num - 1; q >= 0; q--) {
1567 irq_num = platform_get_irq(priv->pdev, q);
1568 if (irq_num > 0)
1569 free_irq(irq_num, ndev);
1570 }
1571 } else {
1572 for (q = res_num; q >= 0; q--) {
1573 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, q);
1574 /* at the first iteration, irq_num is already set to the
1575 * right value
1576 */
1577 if (q != res_num)
1578 irq_num = res->end;
1579
1580 for (m = irq_num; m >= res->start; m--)
1581 free_irq(m, ndev);
1582 }
1583 }
1584 cpdma_ctlr_stop(priv->dma);
1585 pm_runtime_put(&priv->pdev->dev);
1586 return ret;
1587 }
1588
1589 /**
1590 * emac_dev_stop - EMAC device stop
1591 * @ndev: The DaVinci EMAC network adapter
1592 *
1593 * Called when system wants to stop or down the interface. We stop the network
1594 * queue, disable interrupts and cleanup TX/RX channels.
1595 *
1596 * We return the statistics in net_device_stats structure pulled from emac
1597 */
emac_dev_stop(struct net_device * ndev)1598 static int emac_dev_stop(struct net_device *ndev)
1599 {
1600 struct resource *res;
1601 int i = 0;
1602 int irq_num;
1603 struct emac_priv *priv = netdev_priv(ndev);
1604 struct device *emac_dev = &ndev->dev;
1605 int ret = 0;
1606
1607 /* inform the upper layers. */
1608 netif_stop_queue(ndev);
1609 napi_disable(&priv->napi);
1610
1611 netif_carrier_off(ndev);
1612 emac_int_disable(priv);
1613 cpdma_ctlr_stop(priv->dma);
1614 emac_write(EMAC_SOFTRESET, 1);
1615
1616 if (ndev->phydev)
1617 phy_disconnect(ndev->phydev);
1618
1619 /* Free IRQ */
1620 if (dev_of_node(&priv->pdev->dev)) {
1621 do {
1622 ret = platform_get_irq_optional(priv->pdev, i);
1623 if (ret < 0 && ret != -ENXIO)
1624 break;
1625 if (ret > 0) {
1626 free_irq(ret, priv->ndev);
1627 } else {
1628 ret = 0;
1629 break;
1630 }
1631 } while (++i);
1632 } else {
1633 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
1634 for (irq_num = res->start; irq_num <= res->end; irq_num++)
1635 free_irq(irq_num, priv->ndev);
1636 i++;
1637 }
1638 }
1639
1640 if (netif_msg_drv(priv))
1641 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
1642
1643 pm_runtime_put(&priv->pdev->dev);
1644 return ret;
1645 }
1646
1647 /**
1648 * emac_dev_getnetstats - EMAC get statistics function
1649 * @ndev: The DaVinci EMAC network adapter
1650 *
1651 * Called when system wants to get statistics from the device.
1652 *
1653 * We return the statistics in net_device_stats structure pulled from emac
1654 */
emac_dev_getnetstats(struct net_device * ndev)1655 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
1656 {
1657 struct emac_priv *priv = netdev_priv(ndev);
1658 u32 mac_control;
1659 u32 stats_clear_mask;
1660 int err;
1661
1662 err = pm_runtime_resume_and_get(&priv->pdev->dev);
1663 if (err < 0) {
1664 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
1665 __func__, err);
1666 return &ndev->stats;
1667 }
1668
1669 /* update emac hardware stats and reset the registers*/
1670
1671 mac_control = emac_read(EMAC_MACCONTROL);
1672
1673 if (mac_control & EMAC_MACCONTROL_GMIIEN)
1674 stats_clear_mask = EMAC_STATS_CLR_MASK;
1675 else
1676 stats_clear_mask = 0;
1677
1678 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
1679 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
1680
1681 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
1682 emac_read(EMAC_TXSINGLECOLL) +
1683 emac_read(EMAC_TXMULTICOLL));
1684 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
1685 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
1686 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
1687
1688 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
1689 emac_read(EMAC_RXJABBER) +
1690 emac_read(EMAC_RXUNDERSIZED));
1691 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
1692 emac_write(EMAC_RXJABBER, stats_clear_mask);
1693 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
1694
1695 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
1696 emac_read(EMAC_RXMOFOVERRUNS));
1697 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
1698 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
1699
1700 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
1701 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
1702
1703 ndev->stats.tx_carrier_errors +=
1704 emac_read(EMAC_TXCARRIERSENSE);
1705 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
1706
1707 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN);
1708 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
1709
1710 pm_runtime_put(&priv->pdev->dev);
1711
1712 return &ndev->stats;
1713 }
1714
1715 static const struct net_device_ops emac_netdev_ops = {
1716 .ndo_open = emac_dev_open,
1717 .ndo_stop = emac_dev_stop,
1718 .ndo_start_xmit = emac_dev_xmit,
1719 .ndo_set_rx_mode = emac_dev_mcast_set,
1720 .ndo_set_mac_address = emac_dev_setmac_addr,
1721 .ndo_eth_ioctl = emac_devioctl,
1722 .ndo_tx_timeout = emac_dev_tx_timeout,
1723 .ndo_get_stats = emac_dev_getnetstats,
1724 #ifdef CONFIG_NET_POLL_CONTROLLER
1725 .ndo_poll_controller = emac_poll_controller,
1726 #endif
1727 };
1728
1729 static const struct of_device_id davinci_emac_of_match[];
1730
1731 static struct emac_platform_data *
davinci_emac_of_get_pdata(struct platform_device * pdev,struct emac_priv * priv)1732 davinci_emac_of_get_pdata(struct platform_device *pdev, struct emac_priv *priv)
1733 {
1734 struct device_node *np;
1735 const struct of_device_id *match;
1736 const struct emac_platform_data *auxdata;
1737 struct emac_platform_data *pdata = NULL;
1738
1739 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
1740 return dev_get_platdata(&pdev->dev);
1741
1742 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1743 if (!pdata)
1744 return NULL;
1745
1746 np = pdev->dev.of_node;
1747 pdata->version = EMAC_VERSION_2;
1748
1749 if (!is_valid_ether_addr(pdata->mac_addr))
1750 of_get_mac_address(np, pdata->mac_addr);
1751
1752 of_property_read_u32(np, "ti,davinci-ctrl-reg-offset",
1753 &pdata->ctrl_reg_offset);
1754
1755 of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset",
1756 &pdata->ctrl_mod_reg_offset);
1757
1758 of_property_read_u32(np, "ti,davinci-ctrl-ram-offset",
1759 &pdata->ctrl_ram_offset);
1760
1761 of_property_read_u32(np, "ti,davinci-ctrl-ram-size",
1762 &pdata->ctrl_ram_size);
1763
1764 of_property_read_u8(np, "ti,davinci-rmii-en", &pdata->rmii_en);
1765
1766 pdata->no_bd_ram = of_property_read_bool(np, "ti,davinci-no-bd-ram");
1767
1768 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
1769 if (!priv->phy_node) {
1770 if (!of_phy_is_fixed_link(np))
1771 pdata->phy_id = NULL;
1772 else if (of_phy_register_fixed_link(np) >= 0)
1773 priv->phy_node = of_node_get(np);
1774 }
1775
1776 auxdata = pdev->dev.platform_data;
1777 if (auxdata) {
1778 pdata->interrupt_enable = auxdata->interrupt_enable;
1779 pdata->interrupt_disable = auxdata->interrupt_disable;
1780 }
1781
1782 match = of_match_device(davinci_emac_of_match, &pdev->dev);
1783 if (match && match->data) {
1784 auxdata = match->data;
1785 pdata->version = auxdata->version;
1786 pdata->hw_ram_addr = auxdata->hw_ram_addr;
1787 }
1788
1789 return pdata;
1790 }
1791
davinci_emac_try_get_mac(struct platform_device * pdev,int instance,u8 * mac_addr)1792 static int davinci_emac_try_get_mac(struct platform_device *pdev,
1793 int instance, u8 *mac_addr)
1794 {
1795 if (!pdev->dev.of_node)
1796 return -EINVAL;
1797
1798 return ti_cm_get_macid(&pdev->dev, instance, mac_addr);
1799 }
1800
1801 /**
1802 * davinci_emac_probe - EMAC device probe
1803 * @pdev: The DaVinci EMAC device that we are removing
1804 *
1805 * Called when probing for emac devicesr. We get details of instances and
1806 * resource information from platform init and register a network device
1807 * and allocate resources necessary for driver to perform
1808 */
davinci_emac_probe(struct platform_device * pdev)1809 static int davinci_emac_probe(struct platform_device *pdev)
1810 {
1811 struct device_node *np = pdev->dev.of_node;
1812 int rc = 0;
1813 struct resource *res, *res_ctrl;
1814 struct net_device *ndev;
1815 struct emac_priv *priv;
1816 unsigned long hw_ram_addr;
1817 struct emac_platform_data *pdata;
1818 struct cpdma_params dma_params;
1819 struct clk *emac_clk;
1820 unsigned long emac_bus_frequency;
1821
1822
1823 /* obtain emac clock from kernel */
1824 emac_clk = devm_clk_get(&pdev->dev, NULL);
1825 if (IS_ERR(emac_clk)) {
1826 dev_err(&pdev->dev, "failed to get EMAC clock\n");
1827 return -EBUSY;
1828 }
1829 emac_bus_frequency = clk_get_rate(emac_clk);
1830 devm_clk_put(&pdev->dev, emac_clk);
1831
1832 /* TODO: Probe PHY here if possible */
1833
1834 ndev = alloc_etherdev(sizeof(struct emac_priv));
1835 if (!ndev)
1836 return -ENOMEM;
1837
1838 platform_set_drvdata(pdev, ndev);
1839 priv = netdev_priv(ndev);
1840 priv->pdev = pdev;
1841 priv->ndev = ndev;
1842 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
1843
1844 spin_lock_init(&priv->lock);
1845
1846 pdata = davinci_emac_of_get_pdata(pdev, priv);
1847 if (!pdata) {
1848 dev_err(&pdev->dev, "no platform data\n");
1849 rc = -ENODEV;
1850 goto err_free_netdev;
1851 }
1852
1853 /* MAC addr and PHY mask , RMII enable info from platform_data */
1854 memcpy(priv->mac_addr, pdata->mac_addr, ETH_ALEN);
1855 priv->phy_id = pdata->phy_id;
1856 priv->rmii_en = pdata->rmii_en;
1857 priv->version = pdata->version;
1858 priv->int_enable = pdata->interrupt_enable;
1859 priv->int_disable = pdata->interrupt_disable;
1860
1861 priv->coal_intvl = 0;
1862 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);
1863
1864 /* Get EMAC platform data */
1865 priv->remap_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1866 if (IS_ERR(priv->remap_addr)) {
1867 rc = PTR_ERR(priv->remap_addr);
1868 goto no_pdata;
1869 }
1870 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
1871
1872 res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1873 if (res_ctrl) {
1874 priv->ctrl_base =
1875 devm_ioremap_resource(&pdev->dev, res_ctrl);
1876 if (IS_ERR(priv->ctrl_base)) {
1877 rc = PTR_ERR(priv->ctrl_base);
1878 goto no_pdata;
1879 }
1880 } else {
1881 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
1882 }
1883
1884 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
1885 ndev->base_addr = (unsigned long)priv->remap_addr;
1886
1887 hw_ram_addr = pdata->hw_ram_addr;
1888 if (!hw_ram_addr)
1889 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
1890
1891 memset(&dma_params, 0, sizeof(dma_params));
1892 dma_params.dev = &pdev->dev;
1893 dma_params.dmaregs = priv->emac_base;
1894 dma_params.rxthresh = priv->emac_base + 0x120;
1895 dma_params.rxfree = priv->emac_base + 0x140;
1896 dma_params.txhdp = priv->emac_base + 0x600;
1897 dma_params.rxhdp = priv->emac_base + 0x620;
1898 dma_params.txcp = priv->emac_base + 0x640;
1899 dma_params.rxcp = priv->emac_base + 0x660;
1900 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS;
1901 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE;
1902 dma_params.desc_hw_addr = hw_ram_addr;
1903 dma_params.desc_mem_size = pdata->ctrl_ram_size;
1904 dma_params.desc_align = 16;
1905
1906 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :
1907 (u32 __force)res->start + pdata->ctrl_ram_offset;
1908
1909 priv->dma = cpdma_ctlr_create(&dma_params);
1910 if (!priv->dma) {
1911 dev_err(&pdev->dev, "error initializing DMA\n");
1912 rc = -ENOMEM;
1913 goto no_pdata;
1914 }
1915
1916 priv->txchan = cpdma_chan_create(priv->dma, EMAC_DEF_TX_CH,
1917 emac_tx_handler, 0);
1918 if (IS_ERR(priv->txchan)) {
1919 dev_err(&pdev->dev, "error initializing tx dma channel\n");
1920 rc = PTR_ERR(priv->txchan);
1921 goto err_free_dma;
1922 }
1923
1924 priv->rxchan = cpdma_chan_create(priv->dma, EMAC_DEF_RX_CH,
1925 emac_rx_handler, 1);
1926 if (IS_ERR(priv->rxchan)) {
1927 dev_err(&pdev->dev, "error initializing rx dma channel\n");
1928 rc = PTR_ERR(priv->rxchan);
1929 goto err_free_txchan;
1930 }
1931
1932 rc = platform_get_irq(pdev, 0);
1933 if (rc < 0)
1934 goto err_free_rxchan;
1935 ndev->irq = rc;
1936
1937 rc = davinci_emac_try_get_mac(pdev, res_ctrl ? 0 : 1, priv->mac_addr);
1938 if (!rc)
1939 eth_hw_addr_set(ndev, priv->mac_addr);
1940
1941 if (!is_valid_ether_addr(priv->mac_addr)) {
1942 /* Use random MAC if still none obtained. */
1943 eth_hw_addr_random(ndev);
1944 memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len);
1945 dev_warn(&pdev->dev, "using random MAC addr: %pM\n",
1946 priv->mac_addr);
1947 }
1948
1949 ndev->netdev_ops = &emac_netdev_ops;
1950 ndev->ethtool_ops = ðtool_ops;
1951 netif_napi_add(ndev, &priv->napi, emac_poll);
1952
1953 pm_runtime_enable(&pdev->dev);
1954 rc = pm_runtime_resume_and_get(&pdev->dev);
1955 if (rc < 0) {
1956 dev_err(&pdev->dev, "%s: failed to get_sync(%d)\n",
1957 __func__, rc);
1958 goto err_napi_del;
1959 }
1960
1961 /* register the network device */
1962 SET_NETDEV_DEV(ndev, &pdev->dev);
1963 rc = register_netdev(ndev);
1964 if (rc) {
1965 dev_err(&pdev->dev, "error in register_netdev\n");
1966 rc = -ENODEV;
1967 pm_runtime_put(&pdev->dev);
1968 goto err_napi_del;
1969 }
1970
1971
1972 if (netif_msg_probe(priv)) {
1973 dev_notice(&pdev->dev, "DaVinci EMAC Probe found device "
1974 "(regs: %pa, irq: %d)\n",
1975 &priv->emac_base_phys, ndev->irq);
1976 }
1977 pm_runtime_put(&pdev->dev);
1978
1979 return 0;
1980
1981 err_napi_del:
1982 netif_napi_del(&priv->napi);
1983 err_free_rxchan:
1984 cpdma_chan_destroy(priv->rxchan);
1985 err_free_txchan:
1986 cpdma_chan_destroy(priv->txchan);
1987 err_free_dma:
1988 cpdma_ctlr_destroy(priv->dma);
1989 no_pdata:
1990 if (of_phy_is_fixed_link(np))
1991 of_phy_deregister_fixed_link(np);
1992 of_node_put(priv->phy_node);
1993 err_free_netdev:
1994 free_netdev(ndev);
1995 return rc;
1996 }
1997
1998 /**
1999 * davinci_emac_remove - EMAC device remove
2000 * @pdev: The DaVinci EMAC device that we are removing
2001 *
2002 * Called when removing the device driver. We disable clock usage and release
2003 * the resources taken up by the driver and unregister network device
2004 */
davinci_emac_remove(struct platform_device * pdev)2005 static int davinci_emac_remove(struct platform_device *pdev)
2006 {
2007 struct net_device *ndev = platform_get_drvdata(pdev);
2008 struct emac_priv *priv = netdev_priv(ndev);
2009 struct device_node *np = pdev->dev.of_node;
2010
2011 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
2012
2013 if (priv->txchan)
2014 cpdma_chan_destroy(priv->txchan);
2015 if (priv->rxchan)
2016 cpdma_chan_destroy(priv->rxchan);
2017 cpdma_ctlr_destroy(priv->dma);
2018
2019 unregister_netdev(ndev);
2020 of_node_put(priv->phy_node);
2021 pm_runtime_disable(&pdev->dev);
2022 if (of_phy_is_fixed_link(np))
2023 of_phy_deregister_fixed_link(np);
2024 free_netdev(ndev);
2025
2026 return 0;
2027 }
2028
davinci_emac_suspend(struct device * dev)2029 static int davinci_emac_suspend(struct device *dev)
2030 {
2031 struct net_device *ndev = dev_get_drvdata(dev);
2032
2033 if (netif_running(ndev))
2034 emac_dev_stop(ndev);
2035
2036 return 0;
2037 }
2038
davinci_emac_resume(struct device * dev)2039 static int davinci_emac_resume(struct device *dev)
2040 {
2041 struct net_device *ndev = dev_get_drvdata(dev);
2042
2043 if (netif_running(ndev))
2044 emac_dev_open(ndev);
2045
2046 return 0;
2047 }
2048
2049 static const struct dev_pm_ops davinci_emac_pm_ops = {
2050 .suspend = davinci_emac_suspend,
2051 .resume = davinci_emac_resume,
2052 };
2053
2054 static const struct emac_platform_data am3517_emac_data = {
2055 .version = EMAC_VERSION_2,
2056 .hw_ram_addr = 0x01e20000,
2057 };
2058
2059 static const struct emac_platform_data dm816_emac_data = {
2060 .version = EMAC_VERSION_2,
2061 };
2062
2063 static const struct of_device_id davinci_emac_of_match[] = {
2064 {.compatible = "ti,davinci-dm6467-emac", },
2065 {.compatible = "ti,am3517-emac", .data = &am3517_emac_data, },
2066 {.compatible = "ti,dm816-emac", .data = &dm816_emac_data, },
2067 {},
2068 };
2069 MODULE_DEVICE_TABLE(of, davinci_emac_of_match);
2070
2071 /* davinci_emac_driver: EMAC platform driver structure */
2072 static struct platform_driver davinci_emac_driver = {
2073 .driver = {
2074 .name = "davinci_emac",
2075 .pm = &davinci_emac_pm_ops,
2076 .of_match_table = davinci_emac_of_match,
2077 },
2078 .probe = davinci_emac_probe,
2079 .remove = davinci_emac_remove,
2080 };
2081
2082 /**
2083 * davinci_emac_init - EMAC driver module init
2084 *
2085 * Called when initializing the driver. We register the driver with
2086 * the platform.
2087 */
davinci_emac_init(void)2088 static int __init davinci_emac_init(void)
2089 {
2090 return platform_driver_register(&davinci_emac_driver);
2091 }
2092 late_initcall(davinci_emac_init);
2093
2094 /**
2095 * davinci_emac_exit - EMAC driver module exit
2096 *
2097 * Called when exiting the driver completely. We unregister the driver with
2098 * the platform and exit
2099 */
davinci_emac_exit(void)2100 static void __exit davinci_emac_exit(void)
2101 {
2102 platform_driver_unregister(&davinci_emac_driver);
2103 }
2104 module_exit(davinci_emac_exit);
2105
2106 MODULE_LICENSE("GPL");
2107 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2108 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2109 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");
2110