1 /* 2 * Texas Instruments CPDMA Driver 3 * 4 * Copyright (C) 2010 Texas Instruments 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 #ifndef __DAVINCI_CPDMA_H__ 16 #define __DAVINCI_CPDMA_H__ 17 18 #define CPDMA_MAX_CHANNELS BITS_PER_LONG 19 20 #define CPDMA_RX_SOURCE_PORT(__status__) ((__status__ >> 16) & 0x7) 21 22 #define CPDMA_EOI_RX_THRESH 0x0 23 #define CPDMA_EOI_RX 0x1 24 #define CPDMA_EOI_TX 0x2 25 #define CPDMA_EOI_MISC 0x3 26 27 struct cpdma_params { 28 struct device *dev; 29 void __iomem *dmaregs; 30 void __iomem *txhdp, *rxhdp, *txcp, *rxcp; 31 void __iomem *rxthresh, *rxfree; 32 int num_chan; 33 bool has_soft_reset; 34 int min_packet_size; 35 u32 desc_mem_phys; 36 u32 desc_hw_addr; 37 int desc_mem_size; 38 int desc_align; 39 u32 bus_freq_mhz; 40 41 /* 42 * Some instances of embedded cpdma controllers have extra control and 43 * status registers. The following flag enables access to these 44 * "extended" registers. 45 */ 46 bool has_ext_regs; 47 }; 48 49 struct cpdma_chan_stats { 50 u32 head_enqueue; 51 u32 tail_enqueue; 52 u32 pad_enqueue; 53 u32 misqueued; 54 u32 desc_alloc_fail; 55 u32 pad_alloc_fail; 56 u32 runt_receive_buff; 57 u32 runt_transmit_buff; 58 u32 empty_dequeue; 59 u32 busy_dequeue; 60 u32 good_dequeue; 61 u32 requeue; 62 u32 teardown_dequeue; 63 }; 64 65 struct cpdma_ctlr; 66 struct cpdma_chan; 67 68 typedef void (*cpdma_handler_fn)(void *token, int len, int status); 69 70 struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params); 71 int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr); 72 int cpdma_ctlr_start(struct cpdma_ctlr *ctlr); 73 int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr); 74 75 struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num, 76 cpdma_handler_fn handler, int rx_type); 77 int cpdma_chan_get_rx_buf_num(struct cpdma_chan *chan); 78 int cpdma_chan_destroy(struct cpdma_chan *chan); 79 int cpdma_chan_start(struct cpdma_chan *chan); 80 int cpdma_chan_stop(struct cpdma_chan *chan); 81 82 int cpdma_chan_get_stats(struct cpdma_chan *chan, 83 struct cpdma_chan_stats *stats); 84 int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data, 85 int len, int directed); 86 int cpdma_chan_process(struct cpdma_chan *chan, int quota); 87 88 int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable); 89 void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value); 90 int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable); 91 u32 cpdma_ctrl_rxchs_state(struct cpdma_ctlr *ctlr); 92 u32 cpdma_ctrl_txchs_state(struct cpdma_ctlr *ctlr); 93 bool cpdma_check_free_tx_desc(struct cpdma_chan *chan); 94 int cpdma_chan_set_weight(struct cpdma_chan *ch, int weight); 95 int cpdma_chan_set_rate(struct cpdma_chan *ch, u32 rate); 96 u32 cpdma_chan_get_rate(struct cpdma_chan *ch); 97 u32 cpdma_chan_get_min_rate(struct cpdma_ctlr *ctlr); 98 99 enum cpdma_control { 100 CPDMA_TX_RLIM, /* read-write */ 101 CPDMA_CMD_IDLE, /* write-only */ 102 CPDMA_COPY_ERROR_FRAMES, /* read-write */ 103 CPDMA_RX_OFF_LEN_UPDATE, /* read-write */ 104 CPDMA_RX_OWNERSHIP_FLIP, /* read-write */ 105 CPDMA_TX_PRIO_FIXED, /* read-write */ 106 CPDMA_STAT_IDLE, /* read-only */ 107 CPDMA_STAT_TX_ERR_CHAN, /* read-only */ 108 CPDMA_STAT_TX_ERR_CODE, /* read-only */ 109 CPDMA_STAT_RX_ERR_CHAN, /* read-only */ 110 CPDMA_STAT_RX_ERR_CODE, /* read-only */ 111 CPDMA_RX_BUFFER_OFFSET, /* read-write */ 112 }; 113 114 int cpdma_control_get(struct cpdma_ctlr *ctlr, int control); 115 int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value); 116 117 #endif 118