1 /* 2 * Texas Instruments CPDMA Driver 3 * 4 * Copyright (C) 2010 Texas Instruments 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 #include <linux/kernel.h> 16 #include <linux/spinlock.h> 17 #include <linux/device.h> 18 #include <linux/module.h> 19 #include <linux/slab.h> 20 #include <linux/err.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/io.h> 23 #include <linux/delay.h> 24 25 #include "davinci_cpdma.h" 26 27 /* DMA Registers */ 28 #define CPDMA_TXIDVER 0x00 29 #define CPDMA_TXCONTROL 0x04 30 #define CPDMA_TXTEARDOWN 0x08 31 #define CPDMA_RXIDVER 0x10 32 #define CPDMA_RXCONTROL 0x14 33 #define CPDMA_SOFTRESET 0x1c 34 #define CPDMA_RXTEARDOWN 0x18 35 #define CPDMA_TXINTSTATRAW 0x80 36 #define CPDMA_TXINTSTATMASKED 0x84 37 #define CPDMA_TXINTMASKSET 0x88 38 #define CPDMA_TXINTMASKCLEAR 0x8c 39 #define CPDMA_MACINVECTOR 0x90 40 #define CPDMA_MACEOIVECTOR 0x94 41 #define CPDMA_RXINTSTATRAW 0xa0 42 #define CPDMA_RXINTSTATMASKED 0xa4 43 #define CPDMA_RXINTMASKSET 0xa8 44 #define CPDMA_RXINTMASKCLEAR 0xac 45 #define CPDMA_DMAINTSTATRAW 0xb0 46 #define CPDMA_DMAINTSTATMASKED 0xb4 47 #define CPDMA_DMAINTMASKSET 0xb8 48 #define CPDMA_DMAINTMASKCLEAR 0xbc 49 #define CPDMA_DMAINT_HOSTERR BIT(1) 50 51 /* the following exist only if has_ext_regs is set */ 52 #define CPDMA_DMACONTROL 0x20 53 #define CPDMA_DMASTATUS 0x24 54 #define CPDMA_RXBUFFOFS 0x28 55 #define CPDMA_EM_CONTROL 0x2c 56 57 /* Descriptor mode bits */ 58 #define CPDMA_DESC_SOP BIT(31) 59 #define CPDMA_DESC_EOP BIT(30) 60 #define CPDMA_DESC_OWNER BIT(29) 61 #define CPDMA_DESC_EOQ BIT(28) 62 #define CPDMA_DESC_TD_COMPLETE BIT(27) 63 #define CPDMA_DESC_PASS_CRC BIT(26) 64 #define CPDMA_DESC_TO_PORT_EN BIT(20) 65 #define CPDMA_TO_PORT_SHIFT 16 66 #define CPDMA_DESC_PORT_MASK (BIT(18) | BIT(17) | BIT(16)) 67 #define CPDMA_DESC_CRC_LEN 4 68 69 #define CPDMA_TEARDOWN_VALUE 0xfffffffc 70 71 struct cpdma_desc { 72 /* hardware fields */ 73 u32 hw_next; 74 u32 hw_buffer; 75 u32 hw_len; 76 u32 hw_mode; 77 /* software fields */ 78 void *sw_token; 79 u32 sw_buffer; 80 u32 sw_len; 81 }; 82 83 struct cpdma_desc_pool { 84 phys_addr_t phys; 85 dma_addr_t hw_addr; 86 void __iomem *iomap; /* ioremap map */ 87 void *cpumap; /* dma_alloc map */ 88 int desc_size, mem_size; 89 int num_desc, used_desc; 90 unsigned long *bitmap; 91 struct device *dev; 92 spinlock_t lock; 93 }; 94 95 enum cpdma_state { 96 CPDMA_STATE_IDLE, 97 CPDMA_STATE_ACTIVE, 98 CPDMA_STATE_TEARDOWN, 99 }; 100 101 static const char *cpdma_state_str[] = { "idle", "active", "teardown" }; 102 103 struct cpdma_ctlr { 104 enum cpdma_state state; 105 struct cpdma_params params; 106 struct device *dev; 107 struct cpdma_desc_pool *pool; 108 spinlock_t lock; 109 struct cpdma_chan *channels[2 * CPDMA_MAX_CHANNELS]; 110 }; 111 112 struct cpdma_chan { 113 struct cpdma_desc __iomem *head, *tail; 114 void __iomem *hdp, *cp, *rxfree; 115 enum cpdma_state state; 116 struct cpdma_ctlr *ctlr; 117 int chan_num; 118 spinlock_t lock; 119 int count; 120 u32 mask; 121 cpdma_handler_fn handler; 122 enum dma_data_direction dir; 123 struct cpdma_chan_stats stats; 124 /* offsets into dmaregs */ 125 int int_set, int_clear, td; 126 }; 127 128 /* The following make access to common cpdma_ctlr params more readable */ 129 #define dmaregs params.dmaregs 130 #define num_chan params.num_chan 131 132 /* various accessors */ 133 #define dma_reg_read(ctlr, ofs) __raw_readl((ctlr)->dmaregs + (ofs)) 134 #define chan_read(chan, fld) __raw_readl((chan)->fld) 135 #define desc_read(desc, fld) __raw_readl(&(desc)->fld) 136 #define dma_reg_write(ctlr, ofs, v) __raw_writel(v, (ctlr)->dmaregs + (ofs)) 137 #define chan_write(chan, fld, v) __raw_writel(v, (chan)->fld) 138 #define desc_write(desc, fld, v) __raw_writel((u32)(v), &(desc)->fld) 139 140 #define cpdma_desc_to_port(chan, mode, directed) \ 141 do { \ 142 if (!is_rx_chan(chan) && ((directed == 1) || \ 143 (directed == 2))) \ 144 mode |= (CPDMA_DESC_TO_PORT_EN | \ 145 (directed << CPDMA_TO_PORT_SHIFT)); \ 146 } while (0) 147 148 /* 149 * Utility constructs for a cpdma descriptor pool. Some devices (e.g. davinci 150 * emac) have dedicated on-chip memory for these descriptors. Some other 151 * devices (e.g. cpsw switches) use plain old memory. Descriptor pools 152 * abstract out these details 153 */ 154 static struct cpdma_desc_pool * 155 cpdma_desc_pool_create(struct device *dev, u32 phys, dma_addr_t hw_addr, 156 int size, int align) 157 { 158 int bitmap_size; 159 struct cpdma_desc_pool *pool; 160 161 pool = devm_kzalloc(dev, sizeof(*pool), GFP_KERNEL); 162 if (!pool) 163 goto fail; 164 165 spin_lock_init(&pool->lock); 166 167 pool->dev = dev; 168 pool->mem_size = size; 169 pool->desc_size = ALIGN(sizeof(struct cpdma_desc), align); 170 pool->num_desc = size / pool->desc_size; 171 172 bitmap_size = (pool->num_desc / BITS_PER_LONG) * sizeof(long); 173 pool->bitmap = devm_kzalloc(dev, bitmap_size, GFP_KERNEL); 174 if (!pool->bitmap) 175 goto fail; 176 177 if (phys) { 178 pool->phys = phys; 179 pool->iomap = ioremap(phys, size); /* should be memremap? */ 180 pool->hw_addr = hw_addr; 181 } else { 182 pool->cpumap = dma_alloc_coherent(dev, size, &pool->hw_addr, 183 GFP_KERNEL); 184 pool->iomap = (void __iomem __force *)pool->cpumap; 185 pool->phys = pool->hw_addr; /* assumes no IOMMU, don't use this value */ 186 } 187 188 if (pool->iomap) 189 return pool; 190 fail: 191 return NULL; 192 } 193 194 static void cpdma_desc_pool_destroy(struct cpdma_desc_pool *pool) 195 { 196 if (!pool) 197 return; 198 199 WARN_ON(pool->used_desc); 200 if (pool->cpumap) { 201 dma_free_coherent(pool->dev, pool->mem_size, pool->cpumap, 202 pool->phys); 203 } else { 204 iounmap(pool->iomap); 205 } 206 } 207 208 static inline dma_addr_t desc_phys(struct cpdma_desc_pool *pool, 209 struct cpdma_desc __iomem *desc) 210 { 211 if (!desc) 212 return 0; 213 return pool->hw_addr + (__force long)desc - (__force long)pool->iomap; 214 } 215 216 static inline struct cpdma_desc __iomem * 217 desc_from_phys(struct cpdma_desc_pool *pool, dma_addr_t dma) 218 { 219 return dma ? pool->iomap + dma - pool->hw_addr : NULL; 220 } 221 222 static struct cpdma_desc __iomem * 223 cpdma_desc_alloc(struct cpdma_desc_pool *pool, int num_desc, bool is_rx) 224 { 225 unsigned long flags; 226 int index; 227 int desc_start; 228 int desc_end; 229 struct cpdma_desc __iomem *desc = NULL; 230 231 spin_lock_irqsave(&pool->lock, flags); 232 233 if (is_rx) { 234 desc_start = 0; 235 desc_end = pool->num_desc/2; 236 } else { 237 desc_start = pool->num_desc/2; 238 desc_end = pool->num_desc; 239 } 240 241 index = bitmap_find_next_zero_area(pool->bitmap, 242 desc_end, desc_start, num_desc, 0); 243 if (index < desc_end) { 244 bitmap_set(pool->bitmap, index, num_desc); 245 desc = pool->iomap + pool->desc_size * index; 246 pool->used_desc++; 247 } 248 249 spin_unlock_irqrestore(&pool->lock, flags); 250 return desc; 251 } 252 253 static void cpdma_desc_free(struct cpdma_desc_pool *pool, 254 struct cpdma_desc __iomem *desc, int num_desc) 255 { 256 unsigned long flags, index; 257 258 index = ((unsigned long)desc - (unsigned long)pool->iomap) / 259 pool->desc_size; 260 spin_lock_irqsave(&pool->lock, flags); 261 bitmap_clear(pool->bitmap, index, num_desc); 262 pool->used_desc--; 263 spin_unlock_irqrestore(&pool->lock, flags); 264 } 265 266 struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params) 267 { 268 struct cpdma_ctlr *ctlr; 269 270 ctlr = devm_kzalloc(params->dev, sizeof(*ctlr), GFP_KERNEL); 271 if (!ctlr) 272 return NULL; 273 274 ctlr->state = CPDMA_STATE_IDLE; 275 ctlr->params = *params; 276 ctlr->dev = params->dev; 277 spin_lock_init(&ctlr->lock); 278 279 ctlr->pool = cpdma_desc_pool_create(ctlr->dev, 280 ctlr->params.desc_mem_phys, 281 ctlr->params.desc_hw_addr, 282 ctlr->params.desc_mem_size, 283 ctlr->params.desc_align); 284 if (!ctlr->pool) 285 return NULL; 286 287 if (WARN_ON(ctlr->num_chan > CPDMA_MAX_CHANNELS)) 288 ctlr->num_chan = CPDMA_MAX_CHANNELS; 289 return ctlr; 290 } 291 EXPORT_SYMBOL_GPL(cpdma_ctlr_create); 292 293 int cpdma_ctlr_start(struct cpdma_ctlr *ctlr) 294 { 295 unsigned long flags; 296 int i; 297 298 spin_lock_irqsave(&ctlr->lock, flags); 299 if (ctlr->state != CPDMA_STATE_IDLE) { 300 spin_unlock_irqrestore(&ctlr->lock, flags); 301 return -EBUSY; 302 } 303 304 if (ctlr->params.has_soft_reset) { 305 unsigned timeout = 10 * 100; 306 307 dma_reg_write(ctlr, CPDMA_SOFTRESET, 1); 308 while (timeout) { 309 if (dma_reg_read(ctlr, CPDMA_SOFTRESET) == 0) 310 break; 311 udelay(10); 312 timeout--; 313 } 314 WARN_ON(!timeout); 315 } 316 317 for (i = 0; i < ctlr->num_chan; i++) { 318 __raw_writel(0, ctlr->params.txhdp + 4 * i); 319 __raw_writel(0, ctlr->params.rxhdp + 4 * i); 320 __raw_writel(0, ctlr->params.txcp + 4 * i); 321 __raw_writel(0, ctlr->params.rxcp + 4 * i); 322 } 323 324 dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff); 325 dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff); 326 327 dma_reg_write(ctlr, CPDMA_TXCONTROL, 1); 328 dma_reg_write(ctlr, CPDMA_RXCONTROL, 1); 329 330 ctlr->state = CPDMA_STATE_ACTIVE; 331 332 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) { 333 if (ctlr->channels[i]) 334 cpdma_chan_start(ctlr->channels[i]); 335 } 336 spin_unlock_irqrestore(&ctlr->lock, flags); 337 return 0; 338 } 339 EXPORT_SYMBOL_GPL(cpdma_ctlr_start); 340 341 int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr) 342 { 343 unsigned long flags; 344 int i; 345 346 spin_lock_irqsave(&ctlr->lock, flags); 347 if (ctlr->state == CPDMA_STATE_TEARDOWN) { 348 spin_unlock_irqrestore(&ctlr->lock, flags); 349 return -EINVAL; 350 } 351 352 ctlr->state = CPDMA_STATE_TEARDOWN; 353 354 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) { 355 if (ctlr->channels[i]) 356 cpdma_chan_stop(ctlr->channels[i]); 357 } 358 359 dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff); 360 dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff); 361 362 dma_reg_write(ctlr, CPDMA_TXCONTROL, 0); 363 dma_reg_write(ctlr, CPDMA_RXCONTROL, 0); 364 365 ctlr->state = CPDMA_STATE_IDLE; 366 367 spin_unlock_irqrestore(&ctlr->lock, flags); 368 return 0; 369 } 370 EXPORT_SYMBOL_GPL(cpdma_ctlr_stop); 371 372 int cpdma_ctlr_dump(struct cpdma_ctlr *ctlr) 373 { 374 struct device *dev = ctlr->dev; 375 unsigned long flags; 376 int i; 377 378 spin_lock_irqsave(&ctlr->lock, flags); 379 380 dev_info(dev, "CPDMA: state: %s", cpdma_state_str[ctlr->state]); 381 382 dev_info(dev, "CPDMA: txidver: %x", 383 dma_reg_read(ctlr, CPDMA_TXIDVER)); 384 dev_info(dev, "CPDMA: txcontrol: %x", 385 dma_reg_read(ctlr, CPDMA_TXCONTROL)); 386 dev_info(dev, "CPDMA: txteardown: %x", 387 dma_reg_read(ctlr, CPDMA_TXTEARDOWN)); 388 dev_info(dev, "CPDMA: rxidver: %x", 389 dma_reg_read(ctlr, CPDMA_RXIDVER)); 390 dev_info(dev, "CPDMA: rxcontrol: %x", 391 dma_reg_read(ctlr, CPDMA_RXCONTROL)); 392 dev_info(dev, "CPDMA: softreset: %x", 393 dma_reg_read(ctlr, CPDMA_SOFTRESET)); 394 dev_info(dev, "CPDMA: rxteardown: %x", 395 dma_reg_read(ctlr, CPDMA_RXTEARDOWN)); 396 dev_info(dev, "CPDMA: txintstatraw: %x", 397 dma_reg_read(ctlr, CPDMA_TXINTSTATRAW)); 398 dev_info(dev, "CPDMA: txintstatmasked: %x", 399 dma_reg_read(ctlr, CPDMA_TXINTSTATMASKED)); 400 dev_info(dev, "CPDMA: txintmaskset: %x", 401 dma_reg_read(ctlr, CPDMA_TXINTMASKSET)); 402 dev_info(dev, "CPDMA: txintmaskclear: %x", 403 dma_reg_read(ctlr, CPDMA_TXINTMASKCLEAR)); 404 dev_info(dev, "CPDMA: macinvector: %x", 405 dma_reg_read(ctlr, CPDMA_MACINVECTOR)); 406 dev_info(dev, "CPDMA: maceoivector: %x", 407 dma_reg_read(ctlr, CPDMA_MACEOIVECTOR)); 408 dev_info(dev, "CPDMA: rxintstatraw: %x", 409 dma_reg_read(ctlr, CPDMA_RXINTSTATRAW)); 410 dev_info(dev, "CPDMA: rxintstatmasked: %x", 411 dma_reg_read(ctlr, CPDMA_RXINTSTATMASKED)); 412 dev_info(dev, "CPDMA: rxintmaskset: %x", 413 dma_reg_read(ctlr, CPDMA_RXINTMASKSET)); 414 dev_info(dev, "CPDMA: rxintmaskclear: %x", 415 dma_reg_read(ctlr, CPDMA_RXINTMASKCLEAR)); 416 dev_info(dev, "CPDMA: dmaintstatraw: %x", 417 dma_reg_read(ctlr, CPDMA_DMAINTSTATRAW)); 418 dev_info(dev, "CPDMA: dmaintstatmasked: %x", 419 dma_reg_read(ctlr, CPDMA_DMAINTSTATMASKED)); 420 dev_info(dev, "CPDMA: dmaintmaskset: %x", 421 dma_reg_read(ctlr, CPDMA_DMAINTMASKSET)); 422 dev_info(dev, "CPDMA: dmaintmaskclear: %x", 423 dma_reg_read(ctlr, CPDMA_DMAINTMASKCLEAR)); 424 425 if (!ctlr->params.has_ext_regs) { 426 dev_info(dev, "CPDMA: dmacontrol: %x", 427 dma_reg_read(ctlr, CPDMA_DMACONTROL)); 428 dev_info(dev, "CPDMA: dmastatus: %x", 429 dma_reg_read(ctlr, CPDMA_DMASTATUS)); 430 dev_info(dev, "CPDMA: rxbuffofs: %x", 431 dma_reg_read(ctlr, CPDMA_RXBUFFOFS)); 432 } 433 434 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) 435 if (ctlr->channels[i]) 436 cpdma_chan_dump(ctlr->channels[i]); 437 438 spin_unlock_irqrestore(&ctlr->lock, flags); 439 return 0; 440 } 441 EXPORT_SYMBOL_GPL(cpdma_ctlr_dump); 442 443 int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr) 444 { 445 unsigned long flags; 446 int ret = 0, i; 447 448 if (!ctlr) 449 return -EINVAL; 450 451 spin_lock_irqsave(&ctlr->lock, flags); 452 if (ctlr->state != CPDMA_STATE_IDLE) 453 cpdma_ctlr_stop(ctlr); 454 455 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) 456 cpdma_chan_destroy(ctlr->channels[i]); 457 458 cpdma_desc_pool_destroy(ctlr->pool); 459 spin_unlock_irqrestore(&ctlr->lock, flags); 460 return ret; 461 } 462 EXPORT_SYMBOL_GPL(cpdma_ctlr_destroy); 463 464 int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable) 465 { 466 unsigned long flags; 467 int i, reg; 468 469 spin_lock_irqsave(&ctlr->lock, flags); 470 if (ctlr->state != CPDMA_STATE_ACTIVE) { 471 spin_unlock_irqrestore(&ctlr->lock, flags); 472 return -EINVAL; 473 } 474 475 reg = enable ? CPDMA_DMAINTMASKSET : CPDMA_DMAINTMASKCLEAR; 476 dma_reg_write(ctlr, reg, CPDMA_DMAINT_HOSTERR); 477 478 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) { 479 if (ctlr->channels[i]) 480 cpdma_chan_int_ctrl(ctlr->channels[i], enable); 481 } 482 483 spin_unlock_irqrestore(&ctlr->lock, flags); 484 return 0; 485 } 486 EXPORT_SYMBOL_GPL(cpdma_ctlr_int_ctrl); 487 488 void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value) 489 { 490 dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, value); 491 } 492 EXPORT_SYMBOL_GPL(cpdma_ctlr_eoi); 493 494 struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num, 495 cpdma_handler_fn handler) 496 { 497 struct cpdma_chan *chan; 498 int offset = (chan_num % CPDMA_MAX_CHANNELS) * 4; 499 unsigned long flags; 500 501 if (__chan_linear(chan_num) >= ctlr->num_chan) 502 return NULL; 503 504 chan = devm_kzalloc(ctlr->dev, sizeof(*chan), GFP_KERNEL); 505 if (!chan) 506 return ERR_PTR(-ENOMEM); 507 508 spin_lock_irqsave(&ctlr->lock, flags); 509 if (ctlr->channels[chan_num]) { 510 spin_unlock_irqrestore(&ctlr->lock, flags); 511 devm_kfree(ctlr->dev, chan); 512 return ERR_PTR(-EBUSY); 513 } 514 515 chan->ctlr = ctlr; 516 chan->state = CPDMA_STATE_IDLE; 517 chan->chan_num = chan_num; 518 chan->handler = handler; 519 520 if (is_rx_chan(chan)) { 521 chan->hdp = ctlr->params.rxhdp + offset; 522 chan->cp = ctlr->params.rxcp + offset; 523 chan->rxfree = ctlr->params.rxfree + offset; 524 chan->int_set = CPDMA_RXINTMASKSET; 525 chan->int_clear = CPDMA_RXINTMASKCLEAR; 526 chan->td = CPDMA_RXTEARDOWN; 527 chan->dir = DMA_FROM_DEVICE; 528 } else { 529 chan->hdp = ctlr->params.txhdp + offset; 530 chan->cp = ctlr->params.txcp + offset; 531 chan->int_set = CPDMA_TXINTMASKSET; 532 chan->int_clear = CPDMA_TXINTMASKCLEAR; 533 chan->td = CPDMA_TXTEARDOWN; 534 chan->dir = DMA_TO_DEVICE; 535 } 536 chan->mask = BIT(chan_linear(chan)); 537 538 spin_lock_init(&chan->lock); 539 540 ctlr->channels[chan_num] = chan; 541 spin_unlock_irqrestore(&ctlr->lock, flags); 542 return chan; 543 } 544 EXPORT_SYMBOL_GPL(cpdma_chan_create); 545 546 int cpdma_chan_destroy(struct cpdma_chan *chan) 547 { 548 struct cpdma_ctlr *ctlr; 549 unsigned long flags; 550 551 if (!chan) 552 return -EINVAL; 553 ctlr = chan->ctlr; 554 555 spin_lock_irqsave(&ctlr->lock, flags); 556 if (chan->state != CPDMA_STATE_IDLE) 557 cpdma_chan_stop(chan); 558 ctlr->channels[chan->chan_num] = NULL; 559 spin_unlock_irqrestore(&ctlr->lock, flags); 560 return 0; 561 } 562 EXPORT_SYMBOL_GPL(cpdma_chan_destroy); 563 564 int cpdma_chan_get_stats(struct cpdma_chan *chan, 565 struct cpdma_chan_stats *stats) 566 { 567 unsigned long flags; 568 if (!chan) 569 return -EINVAL; 570 spin_lock_irqsave(&chan->lock, flags); 571 memcpy(stats, &chan->stats, sizeof(*stats)); 572 spin_unlock_irqrestore(&chan->lock, flags); 573 return 0; 574 } 575 EXPORT_SYMBOL_GPL(cpdma_chan_get_stats); 576 577 int cpdma_chan_dump(struct cpdma_chan *chan) 578 { 579 unsigned long flags; 580 struct device *dev = chan->ctlr->dev; 581 582 spin_lock_irqsave(&chan->lock, flags); 583 584 dev_info(dev, "channel %d (%s %d) state %s", 585 chan->chan_num, is_rx_chan(chan) ? "rx" : "tx", 586 chan_linear(chan), cpdma_state_str[chan->state]); 587 dev_info(dev, "\thdp: %x\n", chan_read(chan, hdp)); 588 dev_info(dev, "\tcp: %x\n", chan_read(chan, cp)); 589 if (chan->rxfree) { 590 dev_info(dev, "\trxfree: %x\n", 591 chan_read(chan, rxfree)); 592 } 593 594 dev_info(dev, "\tstats head_enqueue: %d\n", 595 chan->stats.head_enqueue); 596 dev_info(dev, "\tstats tail_enqueue: %d\n", 597 chan->stats.tail_enqueue); 598 dev_info(dev, "\tstats pad_enqueue: %d\n", 599 chan->stats.pad_enqueue); 600 dev_info(dev, "\tstats misqueued: %d\n", 601 chan->stats.misqueued); 602 dev_info(dev, "\tstats desc_alloc_fail: %d\n", 603 chan->stats.desc_alloc_fail); 604 dev_info(dev, "\tstats pad_alloc_fail: %d\n", 605 chan->stats.pad_alloc_fail); 606 dev_info(dev, "\tstats runt_receive_buff: %d\n", 607 chan->stats.runt_receive_buff); 608 dev_info(dev, "\tstats runt_transmit_buff: %d\n", 609 chan->stats.runt_transmit_buff); 610 dev_info(dev, "\tstats empty_dequeue: %d\n", 611 chan->stats.empty_dequeue); 612 dev_info(dev, "\tstats busy_dequeue: %d\n", 613 chan->stats.busy_dequeue); 614 dev_info(dev, "\tstats good_dequeue: %d\n", 615 chan->stats.good_dequeue); 616 dev_info(dev, "\tstats requeue: %d\n", 617 chan->stats.requeue); 618 dev_info(dev, "\tstats teardown_dequeue: %d\n", 619 chan->stats.teardown_dequeue); 620 621 spin_unlock_irqrestore(&chan->lock, flags); 622 return 0; 623 } 624 625 static void __cpdma_chan_submit(struct cpdma_chan *chan, 626 struct cpdma_desc __iomem *desc) 627 { 628 struct cpdma_ctlr *ctlr = chan->ctlr; 629 struct cpdma_desc __iomem *prev = chan->tail; 630 struct cpdma_desc_pool *pool = ctlr->pool; 631 dma_addr_t desc_dma; 632 u32 mode; 633 634 desc_dma = desc_phys(pool, desc); 635 636 /* simple case - idle channel */ 637 if (!chan->head) { 638 chan->stats.head_enqueue++; 639 chan->head = desc; 640 chan->tail = desc; 641 if (chan->state == CPDMA_STATE_ACTIVE) 642 chan_write(chan, hdp, desc_dma); 643 return; 644 } 645 646 /* first chain the descriptor at the tail of the list */ 647 desc_write(prev, hw_next, desc_dma); 648 chan->tail = desc; 649 chan->stats.tail_enqueue++; 650 651 /* next check if EOQ has been triggered already */ 652 mode = desc_read(prev, hw_mode); 653 if (((mode & (CPDMA_DESC_EOQ | CPDMA_DESC_OWNER)) == CPDMA_DESC_EOQ) && 654 (chan->state == CPDMA_STATE_ACTIVE)) { 655 desc_write(prev, hw_mode, mode & ~CPDMA_DESC_EOQ); 656 chan_write(chan, hdp, desc_dma); 657 chan->stats.misqueued++; 658 } 659 } 660 661 int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data, 662 int len, int directed) 663 { 664 struct cpdma_ctlr *ctlr = chan->ctlr; 665 struct cpdma_desc __iomem *desc; 666 dma_addr_t buffer; 667 unsigned long flags; 668 u32 mode; 669 int ret = 0; 670 671 spin_lock_irqsave(&chan->lock, flags); 672 673 if (chan->state == CPDMA_STATE_TEARDOWN) { 674 ret = -EINVAL; 675 goto unlock_ret; 676 } 677 678 desc = cpdma_desc_alloc(ctlr->pool, 1, is_rx_chan(chan)); 679 if (!desc) { 680 chan->stats.desc_alloc_fail++; 681 ret = -ENOMEM; 682 goto unlock_ret; 683 } 684 685 if (len < ctlr->params.min_packet_size) { 686 len = ctlr->params.min_packet_size; 687 chan->stats.runt_transmit_buff++; 688 } 689 690 buffer = dma_map_single(ctlr->dev, data, len, chan->dir); 691 ret = dma_mapping_error(ctlr->dev, buffer); 692 if (ret) { 693 cpdma_desc_free(ctlr->pool, desc, 1); 694 ret = -EINVAL; 695 goto unlock_ret; 696 } 697 698 mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP; 699 cpdma_desc_to_port(chan, mode, directed); 700 701 desc_write(desc, hw_next, 0); 702 desc_write(desc, hw_buffer, buffer); 703 desc_write(desc, hw_len, len); 704 desc_write(desc, hw_mode, mode | len); 705 desc_write(desc, sw_token, token); 706 desc_write(desc, sw_buffer, buffer); 707 desc_write(desc, sw_len, len); 708 709 __cpdma_chan_submit(chan, desc); 710 711 if (chan->state == CPDMA_STATE_ACTIVE && chan->rxfree) 712 chan_write(chan, rxfree, 1); 713 714 chan->count++; 715 716 unlock_ret: 717 spin_unlock_irqrestore(&chan->lock, flags); 718 return ret; 719 } 720 EXPORT_SYMBOL_GPL(cpdma_chan_submit); 721 722 bool cpdma_check_free_tx_desc(struct cpdma_chan *chan) 723 { 724 unsigned long flags; 725 int index; 726 bool ret; 727 struct cpdma_ctlr *ctlr = chan->ctlr; 728 struct cpdma_desc_pool *pool = ctlr->pool; 729 730 spin_lock_irqsave(&pool->lock, flags); 731 732 index = bitmap_find_next_zero_area(pool->bitmap, 733 pool->num_desc, pool->num_desc/2, 1, 0); 734 735 if (index < pool->num_desc) 736 ret = true; 737 else 738 ret = false; 739 740 spin_unlock_irqrestore(&pool->lock, flags); 741 return ret; 742 } 743 EXPORT_SYMBOL_GPL(cpdma_check_free_tx_desc); 744 745 static void __cpdma_chan_free(struct cpdma_chan *chan, 746 struct cpdma_desc __iomem *desc, 747 int outlen, int status) 748 { 749 struct cpdma_ctlr *ctlr = chan->ctlr; 750 struct cpdma_desc_pool *pool = ctlr->pool; 751 dma_addr_t buff_dma; 752 int origlen; 753 void *token; 754 755 token = (void *)desc_read(desc, sw_token); 756 buff_dma = desc_read(desc, sw_buffer); 757 origlen = desc_read(desc, sw_len); 758 759 dma_unmap_single(ctlr->dev, buff_dma, origlen, chan->dir); 760 cpdma_desc_free(pool, desc, 1); 761 (*chan->handler)(token, outlen, status); 762 } 763 764 static int __cpdma_chan_process(struct cpdma_chan *chan) 765 { 766 struct cpdma_ctlr *ctlr = chan->ctlr; 767 struct cpdma_desc __iomem *desc; 768 int status, outlen; 769 int cb_status = 0; 770 struct cpdma_desc_pool *pool = ctlr->pool; 771 dma_addr_t desc_dma; 772 unsigned long flags; 773 774 spin_lock_irqsave(&chan->lock, flags); 775 776 desc = chan->head; 777 if (!desc) { 778 chan->stats.empty_dequeue++; 779 status = -ENOENT; 780 goto unlock_ret; 781 } 782 desc_dma = desc_phys(pool, desc); 783 784 status = __raw_readl(&desc->hw_mode); 785 outlen = status & 0x7ff; 786 if (status & CPDMA_DESC_OWNER) { 787 chan->stats.busy_dequeue++; 788 status = -EBUSY; 789 goto unlock_ret; 790 } 791 792 if (status & CPDMA_DESC_PASS_CRC) 793 outlen -= CPDMA_DESC_CRC_LEN; 794 795 status = status & (CPDMA_DESC_EOQ | CPDMA_DESC_TD_COMPLETE | 796 CPDMA_DESC_PORT_MASK); 797 798 chan->head = desc_from_phys(pool, desc_read(desc, hw_next)); 799 chan_write(chan, cp, desc_dma); 800 chan->count--; 801 chan->stats.good_dequeue++; 802 803 if (status & CPDMA_DESC_EOQ) { 804 chan->stats.requeue++; 805 chan_write(chan, hdp, desc_phys(pool, chan->head)); 806 } 807 808 spin_unlock_irqrestore(&chan->lock, flags); 809 if (unlikely(status & CPDMA_DESC_TD_COMPLETE)) 810 cb_status = -ENOSYS; 811 else 812 cb_status = status; 813 814 __cpdma_chan_free(chan, desc, outlen, cb_status); 815 return status; 816 817 unlock_ret: 818 spin_unlock_irqrestore(&chan->lock, flags); 819 return status; 820 } 821 822 int cpdma_chan_process(struct cpdma_chan *chan, int quota) 823 { 824 int used = 0, ret = 0; 825 826 if (chan->state != CPDMA_STATE_ACTIVE) 827 return -EINVAL; 828 829 while (used < quota) { 830 ret = __cpdma_chan_process(chan); 831 if (ret < 0) 832 break; 833 used++; 834 } 835 return used; 836 } 837 EXPORT_SYMBOL_GPL(cpdma_chan_process); 838 839 int cpdma_chan_start(struct cpdma_chan *chan) 840 { 841 struct cpdma_ctlr *ctlr = chan->ctlr; 842 struct cpdma_desc_pool *pool = ctlr->pool; 843 unsigned long flags; 844 845 spin_lock_irqsave(&chan->lock, flags); 846 if (chan->state != CPDMA_STATE_IDLE) { 847 spin_unlock_irqrestore(&chan->lock, flags); 848 return -EBUSY; 849 } 850 if (ctlr->state != CPDMA_STATE_ACTIVE) { 851 spin_unlock_irqrestore(&chan->lock, flags); 852 return -EINVAL; 853 } 854 dma_reg_write(ctlr, chan->int_set, chan->mask); 855 chan->state = CPDMA_STATE_ACTIVE; 856 if (chan->head) { 857 chan_write(chan, hdp, desc_phys(pool, chan->head)); 858 if (chan->rxfree) 859 chan_write(chan, rxfree, chan->count); 860 } 861 862 spin_unlock_irqrestore(&chan->lock, flags); 863 return 0; 864 } 865 EXPORT_SYMBOL_GPL(cpdma_chan_start); 866 867 int cpdma_chan_stop(struct cpdma_chan *chan) 868 { 869 struct cpdma_ctlr *ctlr = chan->ctlr; 870 struct cpdma_desc_pool *pool = ctlr->pool; 871 unsigned long flags; 872 int ret; 873 unsigned timeout; 874 875 spin_lock_irqsave(&chan->lock, flags); 876 if (chan->state == CPDMA_STATE_TEARDOWN) { 877 spin_unlock_irqrestore(&chan->lock, flags); 878 return -EINVAL; 879 } 880 881 chan->state = CPDMA_STATE_TEARDOWN; 882 dma_reg_write(ctlr, chan->int_clear, chan->mask); 883 884 /* trigger teardown */ 885 dma_reg_write(ctlr, chan->td, chan_linear(chan)); 886 887 /* wait for teardown complete */ 888 timeout = 100 * 100; /* 100 ms */ 889 while (timeout) { 890 u32 cp = chan_read(chan, cp); 891 if ((cp & CPDMA_TEARDOWN_VALUE) == CPDMA_TEARDOWN_VALUE) 892 break; 893 udelay(10); 894 timeout--; 895 } 896 WARN_ON(!timeout); 897 chan_write(chan, cp, CPDMA_TEARDOWN_VALUE); 898 899 /* handle completed packets */ 900 spin_unlock_irqrestore(&chan->lock, flags); 901 do { 902 ret = __cpdma_chan_process(chan); 903 if (ret < 0) 904 break; 905 } while ((ret & CPDMA_DESC_TD_COMPLETE) == 0); 906 spin_lock_irqsave(&chan->lock, flags); 907 908 /* remaining packets haven't been tx/rx'ed, clean them up */ 909 while (chan->head) { 910 struct cpdma_desc __iomem *desc = chan->head; 911 dma_addr_t next_dma; 912 913 next_dma = desc_read(desc, hw_next); 914 chan->head = desc_from_phys(pool, next_dma); 915 chan->count--; 916 chan->stats.teardown_dequeue++; 917 918 /* issue callback without locks held */ 919 spin_unlock_irqrestore(&chan->lock, flags); 920 __cpdma_chan_free(chan, desc, 0, -ENOSYS); 921 spin_lock_irqsave(&chan->lock, flags); 922 } 923 924 chan->state = CPDMA_STATE_IDLE; 925 spin_unlock_irqrestore(&chan->lock, flags); 926 return 0; 927 } 928 EXPORT_SYMBOL_GPL(cpdma_chan_stop); 929 930 int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable) 931 { 932 unsigned long flags; 933 934 spin_lock_irqsave(&chan->lock, flags); 935 if (chan->state != CPDMA_STATE_ACTIVE) { 936 spin_unlock_irqrestore(&chan->lock, flags); 937 return -EINVAL; 938 } 939 940 dma_reg_write(chan->ctlr, enable ? chan->int_set : chan->int_clear, 941 chan->mask); 942 spin_unlock_irqrestore(&chan->lock, flags); 943 944 return 0; 945 } 946 947 struct cpdma_control_info { 948 u32 reg; 949 u32 shift, mask; 950 int access; 951 #define ACCESS_RO BIT(0) 952 #define ACCESS_WO BIT(1) 953 #define ACCESS_RW (ACCESS_RO | ACCESS_WO) 954 }; 955 956 static struct cpdma_control_info controls[] = { 957 [CPDMA_CMD_IDLE] = {CPDMA_DMACONTROL, 3, 1, ACCESS_WO}, 958 [CPDMA_COPY_ERROR_FRAMES] = {CPDMA_DMACONTROL, 4, 1, ACCESS_RW}, 959 [CPDMA_RX_OFF_LEN_UPDATE] = {CPDMA_DMACONTROL, 2, 1, ACCESS_RW}, 960 [CPDMA_RX_OWNERSHIP_FLIP] = {CPDMA_DMACONTROL, 1, 1, ACCESS_RW}, 961 [CPDMA_TX_PRIO_FIXED] = {CPDMA_DMACONTROL, 0, 1, ACCESS_RW}, 962 [CPDMA_STAT_IDLE] = {CPDMA_DMASTATUS, 31, 1, ACCESS_RO}, 963 [CPDMA_STAT_TX_ERR_CODE] = {CPDMA_DMASTATUS, 20, 0xf, ACCESS_RW}, 964 [CPDMA_STAT_TX_ERR_CHAN] = {CPDMA_DMASTATUS, 16, 0x7, ACCESS_RW}, 965 [CPDMA_STAT_RX_ERR_CODE] = {CPDMA_DMASTATUS, 12, 0xf, ACCESS_RW}, 966 [CPDMA_STAT_RX_ERR_CHAN] = {CPDMA_DMASTATUS, 8, 0x7, ACCESS_RW}, 967 [CPDMA_RX_BUFFER_OFFSET] = {CPDMA_RXBUFFOFS, 0, 0xffff, ACCESS_RW}, 968 }; 969 970 int cpdma_control_get(struct cpdma_ctlr *ctlr, int control) 971 { 972 unsigned long flags; 973 struct cpdma_control_info *info = &controls[control]; 974 int ret; 975 976 spin_lock_irqsave(&ctlr->lock, flags); 977 978 ret = -ENOTSUPP; 979 if (!ctlr->params.has_ext_regs) 980 goto unlock_ret; 981 982 ret = -EINVAL; 983 if (ctlr->state != CPDMA_STATE_ACTIVE) 984 goto unlock_ret; 985 986 ret = -ENOENT; 987 if (control < 0 || control >= ARRAY_SIZE(controls)) 988 goto unlock_ret; 989 990 ret = -EPERM; 991 if ((info->access & ACCESS_RO) != ACCESS_RO) 992 goto unlock_ret; 993 994 ret = (dma_reg_read(ctlr, info->reg) >> info->shift) & info->mask; 995 996 unlock_ret: 997 spin_unlock_irqrestore(&ctlr->lock, flags); 998 return ret; 999 } 1000 1001 int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value) 1002 { 1003 unsigned long flags; 1004 struct cpdma_control_info *info = &controls[control]; 1005 int ret; 1006 u32 val; 1007 1008 spin_lock_irqsave(&ctlr->lock, flags); 1009 1010 ret = -ENOTSUPP; 1011 if (!ctlr->params.has_ext_regs) 1012 goto unlock_ret; 1013 1014 ret = -EINVAL; 1015 if (ctlr->state != CPDMA_STATE_ACTIVE) 1016 goto unlock_ret; 1017 1018 ret = -ENOENT; 1019 if (control < 0 || control >= ARRAY_SIZE(controls)) 1020 goto unlock_ret; 1021 1022 ret = -EPERM; 1023 if ((info->access & ACCESS_WO) != ACCESS_WO) 1024 goto unlock_ret; 1025 1026 val = dma_reg_read(ctlr, info->reg); 1027 val &= ~(info->mask << info->shift); 1028 val |= (value & info->mask) << info->shift; 1029 dma_reg_write(ctlr, info->reg, val); 1030 ret = 0; 1031 1032 unlock_ret: 1033 spin_unlock_irqrestore(&ctlr->lock, flags); 1034 return ret; 1035 } 1036 EXPORT_SYMBOL_GPL(cpdma_control_set); 1037 1038 MODULE_LICENSE("GPL"); 1039