1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Texas Instruments Ethernet Switch Driver 4 */ 5 6 #ifndef DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_ 7 #define DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_ 8 9 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 10 NETIF_MSG_DRV | NETIF_MSG_LINK | \ 11 NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 12 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 13 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 14 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 15 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 16 NETIF_MSG_RX_STATUS) 17 18 #define cpsw_info(priv, type, format, ...) \ 19 do { \ 20 if (netif_msg_##type(priv) && net_ratelimit()) \ 21 dev_info(priv->dev, format, ## __VA_ARGS__); \ 22 } while (0) 23 24 #define cpsw_err(priv, type, format, ...) \ 25 do { \ 26 if (netif_msg_##type(priv) && net_ratelimit()) \ 27 dev_err(priv->dev, format, ## __VA_ARGS__); \ 28 } while (0) 29 30 #define cpsw_dbg(priv, type, format, ...) \ 31 do { \ 32 if (netif_msg_##type(priv) && net_ratelimit()) \ 33 dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 34 } while (0) 35 36 #define cpsw_notice(priv, type, format, ...) \ 37 do { \ 38 if (netif_msg_##type(priv) && net_ratelimit()) \ 39 dev_notice(priv->dev, format, ## __VA_ARGS__); \ 40 } while (0) 41 42 #define ALE_ALL_PORTS 0x7 43 44 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 45 #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 46 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 47 48 #define CPSW_VERSION_1 0x19010a 49 #define CPSW_VERSION_2 0x19010c 50 #define CPSW_VERSION_3 0x19010f 51 #define CPSW_VERSION_4 0x190112 52 53 #define HOST_PORT_NUM 0 54 #define CPSW_ALE_PORTS_NUM 3 55 #define SLIVER_SIZE 0x40 56 57 #define CPSW1_HOST_PORT_OFFSET 0x028 58 #define CPSW1_SLAVE_OFFSET 0x050 59 #define CPSW1_SLAVE_SIZE 0x040 60 #define CPSW1_CPDMA_OFFSET 0x100 61 #define CPSW1_STATERAM_OFFSET 0x200 62 #define CPSW1_HW_STATS 0x400 63 #define CPSW1_CPTS_OFFSET 0x500 64 #define CPSW1_ALE_OFFSET 0x600 65 #define CPSW1_SLIVER_OFFSET 0x700 66 67 #define CPSW2_HOST_PORT_OFFSET 0x108 68 #define CPSW2_SLAVE_OFFSET 0x200 69 #define CPSW2_SLAVE_SIZE 0x100 70 #define CPSW2_CPDMA_OFFSET 0x800 71 #define CPSW2_HW_STATS 0x900 72 #define CPSW2_STATERAM_OFFSET 0xa00 73 #define CPSW2_CPTS_OFFSET 0xc00 74 #define CPSW2_ALE_OFFSET 0xd00 75 #define CPSW2_SLIVER_OFFSET 0xd80 76 #define CPSW2_BD_OFFSET 0x2000 77 78 #define CPDMA_RXTHRESH 0x0c0 79 #define CPDMA_RXFREE 0x0e0 80 #define CPDMA_TXHDP 0x00 81 #define CPDMA_RXHDP 0x20 82 #define CPDMA_TXCP 0x40 83 #define CPDMA_RXCP 0x60 84 85 #define CPSW_POLL_WEIGHT 64 86 #define CPSW_RX_VLAN_ENCAP_HDR_SIZE 4 87 #define CPSW_MIN_PACKET_SIZE (VLAN_ETH_ZLEN) 88 #define CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN +\ 89 ETH_FCS_LEN +\ 90 CPSW_RX_VLAN_ENCAP_HDR_SIZE) 91 92 #define RX_PRIORITY_MAPPING 0x76543210 93 #define TX_PRIORITY_MAPPING 0x33221100 94 #define CPDMA_TX_PRIORITY_MAP 0x76543210 95 96 #define CPSW_VLAN_AWARE BIT(1) 97 #define CPSW_RX_VLAN_ENCAP BIT(2) 98 #define CPSW_ALE_VLAN_AWARE 1 99 100 #define CPSW_FIFO_NORMAL_MODE (0 << 16) 101 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16) 102 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16) 103 104 #define CPSW_INTPACEEN (0x3f << 16) 105 #define CPSW_INTPRESCALE_MASK (0x7FF << 0) 106 #define CPSW_CMINTMAX_CNT 63 107 #define CPSW_CMINTMIN_CNT 2 108 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) 109 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) 110 111 #define IRQ_NUM 2 112 #define CPSW_MAX_QUEUES 8 113 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256 114 #define CPSW_FIFO_QUEUE_TYPE_SHIFT 16 115 #define CPSW_FIFO_SHAPE_EN_SHIFT 16 116 #define CPSW_FIFO_RATE_EN_SHIFT 20 117 #define CPSW_TC_NUM 4 118 #define CPSW_FIFO_SHAPERS_NUM (CPSW_TC_NUM - 1) 119 #define CPSW_PCT_MASK 0x7f 120 121 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT 29 122 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK GENMASK(2, 0) 123 #define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT 16 124 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT 8 125 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK GENMASK(1, 0) 126 enum { 127 CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0, 128 CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV, 129 CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG, 130 CPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG, 131 }; 132 133 struct cpsw_wr_regs { 134 u32 id_ver; 135 u32 soft_reset; 136 u32 control; 137 u32 int_control; 138 u32 rx_thresh_en; 139 u32 rx_en; 140 u32 tx_en; 141 u32 misc_en; 142 u32 mem_allign1[8]; 143 u32 rx_thresh_stat; 144 u32 rx_stat; 145 u32 tx_stat; 146 u32 misc_stat; 147 u32 mem_allign2[8]; 148 u32 rx_imax; 149 u32 tx_imax; 150 151 }; 152 153 struct cpsw_ss_regs { 154 u32 id_ver; 155 u32 control; 156 u32 soft_reset; 157 u32 stat_port_en; 158 u32 ptype; 159 u32 soft_idle; 160 u32 thru_rate; 161 u32 gap_thresh; 162 u32 tx_start_wds; 163 u32 flow_control; 164 u32 vlan_ltype; 165 u32 ts_ltype; 166 u32 dlr_ltype; 167 }; 168 169 /* CPSW_PORT_V1 */ 170 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 171 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 172 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 173 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 174 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 175 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 176 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 177 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 178 179 /* CPSW_PORT_V2 */ 180 #define CPSW2_CONTROL 0x00 /* Control Register */ 181 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 182 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 183 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 184 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 185 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 186 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 187 188 /* CPSW_PORT_V1 and V2 */ 189 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 190 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 191 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 192 193 /* CPSW_PORT_V2 only */ 194 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 195 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 196 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 197 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 198 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 199 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 200 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 201 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 202 203 /* Bit definitions for the CPSW2_CONTROL register */ 204 #define PASS_PRI_TAGGED BIT(24) /* Pass Priority Tagged */ 205 #define VLAN_LTYPE2_EN BIT(21) /* VLAN LTYPE 2 enable */ 206 #define VLAN_LTYPE1_EN BIT(20) /* VLAN LTYPE 1 enable */ 207 #define DSCP_PRI_EN BIT(16) /* DSCP Priority Enable */ 208 #define TS_107 BIT(15) /* Tyme Sync Dest IP Address 107 */ 209 #define TS_320 BIT(14) /* Time Sync Dest Port 320 enable */ 210 #define TS_319 BIT(13) /* Time Sync Dest Port 319 enable */ 211 #define TS_132 BIT(12) /* Time Sync Dest IP Addr 132 enable */ 212 #define TS_131 BIT(11) /* Time Sync Dest IP Addr 131 enable */ 213 #define TS_130 BIT(10) /* Time Sync Dest IP Addr 130 enable */ 214 #define TS_129 BIT(9) /* Time Sync Dest IP Addr 129 enable */ 215 #define TS_TTL_NONZERO BIT(8) /* Time Sync Time To Live Non-zero enable */ 216 #define TS_ANNEX_F_EN BIT(6) /* Time Sync Annex F enable */ 217 #define TS_ANNEX_D_EN BIT(4) /* Time Sync Annex D enable */ 218 #define TS_LTYPE2_EN BIT(3) /* Time Sync LTYPE 2 enable */ 219 #define TS_LTYPE1_EN BIT(2) /* Time Sync LTYPE 1 enable */ 220 #define TS_TX_EN BIT(1) /* Time Sync Transmit Enable */ 221 #define TS_RX_EN BIT(0) /* Time Sync Receive Enable */ 222 223 #define CTRL_V2_TS_BITS \ 224 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 225 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN | VLAN_LTYPE1_EN) 226 227 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN) 228 #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN) 229 #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN) 230 231 232 #define CTRL_V3_TS_BITS \ 233 (TS_107 | TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 234 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\ 235 TS_LTYPE1_EN | VLAN_LTYPE1_EN) 236 237 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN) 238 #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN) 239 #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN) 240 241 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 242 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 243 #define TS_SEQ_ID_OFFSET_MASK (0x3f) 244 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 245 #define TS_MSG_TYPE_EN_MASK (0xffff) 246 247 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 248 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 249 250 /* Bit definitions for the CPSW1_TS_CTL register */ 251 #define CPSW_V1_TS_RX_EN BIT(0) 252 #define CPSW_V1_TS_TX_EN BIT(4) 253 #define CPSW_V1_MSG_TYPE_OFS 16 254 255 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 256 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 257 258 #define CPSW_MAX_BLKS_TX 15 259 #define CPSW_MAX_BLKS_TX_SHIFT 4 260 #define CPSW_MAX_BLKS_RX 5 261 262 struct cpsw_host_regs { 263 u32 max_blks; 264 u32 blk_cnt; 265 u32 tx_in_ctl; 266 u32 port_vlan; 267 u32 tx_pri_map; 268 u32 cpdma_tx_pri_map; 269 u32 cpdma_rx_chan_map; 270 }; 271 272 struct cpsw_sliver_regs { 273 u32 id_ver; 274 u32 mac_control; 275 u32 mac_status; 276 u32 soft_reset; 277 u32 rx_maxlen; 278 u32 __reserved_0; 279 u32 rx_pause; 280 u32 tx_pause; 281 u32 __reserved_1; 282 u32 rx_pri_map; 283 }; 284 285 struct cpsw_hw_stats { 286 u32 rxgoodframes; 287 u32 rxbroadcastframes; 288 u32 rxmulticastframes; 289 u32 rxpauseframes; 290 u32 rxcrcerrors; 291 u32 rxaligncodeerrors; 292 u32 rxoversizedframes; 293 u32 rxjabberframes; 294 u32 rxundersizedframes; 295 u32 rxfragments; 296 u32 __pad_0[2]; 297 u32 rxoctets; 298 u32 txgoodframes; 299 u32 txbroadcastframes; 300 u32 txmulticastframes; 301 u32 txpauseframes; 302 u32 txdeferredframes; 303 u32 txcollisionframes; 304 u32 txsinglecollframes; 305 u32 txmultcollframes; 306 u32 txexcessivecollisions; 307 u32 txlatecollisions; 308 u32 txunderrun; 309 u32 txcarriersenseerrors; 310 u32 txoctets; 311 u32 octetframes64; 312 u32 octetframes65t127; 313 u32 octetframes128t255; 314 u32 octetframes256t511; 315 u32 octetframes512t1023; 316 u32 octetframes1024tup; 317 u32 netoctets; 318 u32 rxsofoverruns; 319 u32 rxmofoverruns; 320 u32 rxdmaoverruns; 321 }; 322 323 struct cpsw_slave_data { 324 struct device_node *phy_node; 325 char phy_id[MII_BUS_ID_SIZE]; 326 int phy_if; 327 u8 mac_addr[ETH_ALEN]; 328 u16 dual_emac_res_vlan; /* Reserved VLAN for DualEMAC */ 329 struct phy *ifphy; 330 }; 331 332 struct cpsw_platform_data { 333 struct cpsw_slave_data *slave_data; 334 u32 ss_reg_ofs; /* Subsystem control register offset */ 335 u32 channels; /* number of cpdma channels (symmetric) */ 336 u32 slaves; /* number of slave cpgmac ports */ 337 u32 active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */ 338 u32 ale_entries; /* ale table size */ 339 u32 bd_ram_size; /*buffer descriptor ram size */ 340 u32 mac_control; /* Mac control register */ 341 u16 default_vlan; /* Def VLAN for ALE lookup in VLAN aware mode*/ 342 bool dual_emac; /* Enable Dual EMAC mode */ 343 }; 344 345 struct cpsw_slave { 346 void __iomem *regs; 347 struct cpsw_sliver_regs __iomem *sliver; 348 int slave_num; 349 u32 mac_control; 350 struct cpsw_slave_data *data; 351 struct phy_device *phy; 352 struct net_device *ndev; 353 u32 port_vlan; 354 }; 355 356 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 357 { 358 return readl_relaxed(slave->regs + offset); 359 } 360 361 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 362 { 363 writel_relaxed(val, slave->regs + offset); 364 } 365 366 struct cpsw_vector { 367 struct cpdma_chan *ch; 368 int budget; 369 }; 370 371 struct cpsw_common { 372 struct device *dev; 373 struct cpsw_platform_data data; 374 struct napi_struct napi_rx; 375 struct napi_struct napi_tx; 376 struct cpsw_ss_regs __iomem *regs; 377 struct cpsw_wr_regs __iomem *wr_regs; 378 u8 __iomem *hw_stats; 379 struct cpsw_host_regs __iomem *host_port_regs; 380 u32 version; 381 u32 coal_intvl; 382 u32 bus_freq_mhz; 383 int rx_packet_max; 384 struct cpsw_slave *slaves; 385 struct cpdma_ctlr *dma; 386 struct cpsw_vector txv[CPSW_MAX_QUEUES]; 387 struct cpsw_vector rxv[CPSW_MAX_QUEUES]; 388 struct cpsw_ale *ale; 389 bool quirk_irq; 390 bool rx_irq_disabled; 391 bool tx_irq_disabled; 392 u32 irqs_table[IRQ_NUM]; 393 struct cpts *cpts; 394 int rx_ch_num, tx_ch_num; 395 int speed; 396 int usage_count; 397 }; 398 399 struct cpsw_priv { 400 struct net_device *ndev; 401 struct device *dev; 402 u32 msg_enable; 403 u8 mac_addr[ETH_ALEN]; 404 bool rx_pause; 405 bool tx_pause; 406 bool mqprio_hw; 407 int fifo_bw[CPSW_TC_NUM]; 408 int shp_cfg_speed; 409 int tx_ts_enabled; 410 int rx_ts_enabled; 411 u32 emac_port; 412 struct cpsw_common *cpsw; 413 }; 414 415 #define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats) 416 #define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats) 417 418 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw) 419 #define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi) 420 421 #define cpsw_slave_index(cpsw, priv) \ 422 ((cpsw->data.dual_emac) ? priv->emac_port : \ 423 cpsw->data.active_slave) 424 425 static inline int cpsw_get_slave_port(u32 slave_num) 426 { 427 return slave_num + 1; 428 } 429 430 struct addr_sync_ctx { 431 struct net_device *ndev; 432 const u8 *addr; /* address to be synched */ 433 int consumed; /* number of address instances */ 434 int flush; /* flush flag */ 435 }; 436 437 int cpsw_init_common(struct cpsw_common *cpsw, void __iomem *ss_regs, 438 int ale_ageout, phys_addr_t desc_mem_phys, 439 int descs_pool_size); 440 441 #endif /* DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_ */ 442