1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Texas Instruments N-Port Ethernet Switch Address Lookup Engine 4 * 5 * Copyright (C) 2012 Texas Instruments 6 * 7 */ 8 #include <linux/bitmap.h> 9 #include <linux/if_vlan.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/seq_file.h> 14 #include <linux/slab.h> 15 #include <linux/err.h> 16 #include <linux/io.h> 17 #include <linux/stat.h> 18 #include <linux/sysfs.h> 19 #include <linux/etherdevice.h> 20 21 #include "cpsw_ale.h" 22 23 #define BITMASK(bits) (BIT(bits) - 1) 24 25 #define ALE_VERSION_MAJOR(rev, mask) (((rev) >> 8) & (mask)) 26 #define ALE_VERSION_MINOR(rev) (rev & 0xff) 27 #define ALE_VERSION_1R3 0x0103 28 #define ALE_VERSION_1R4 0x0104 29 30 /* ALE Registers */ 31 #define ALE_IDVER 0x00 32 #define ALE_STATUS 0x04 33 #define ALE_CONTROL 0x08 34 #define ALE_PRESCALE 0x10 35 #define ALE_AGING_TIMER 0x14 36 #define ALE_UNKNOWNVLAN 0x18 37 #define ALE_TABLE_CONTROL 0x20 38 #define ALE_TABLE 0x34 39 #define ALE_PORTCTL 0x40 40 41 /* ALE NetCP NU switch specific Registers */ 42 #define ALE_UNKNOWNVLAN_MEMBER 0x90 43 #define ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD 0x94 44 #define ALE_UNKNOWNVLAN_REG_MCAST_FLOOD 0x98 45 #define ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS 0x9C 46 #define ALE_VLAN_MASK_MUX(reg) (0xc0 + (0x4 * (reg))) 47 48 #define AM65_CPSW_ALE_THREAD_DEF_REG 0x134 49 50 /* ALE_AGING_TIMER */ 51 #define ALE_AGING_TIMER_MASK GENMASK(23, 0) 52 53 /** 54 * struct ale_entry_fld - The ALE tbl entry field description 55 * @start_bit: field start bit 56 * @num_bits: field bit length 57 * @flags: field flags 58 */ 59 struct ale_entry_fld { 60 u8 start_bit; 61 u8 num_bits; 62 u8 flags; 63 }; 64 65 enum { 66 CPSW_ALE_F_STATUS_REG = BIT(0), /* Status register present */ 67 CPSW_ALE_F_HW_AUTOAGING = BIT(1), /* HW auto aging */ 68 69 CPSW_ALE_F_COUNT 70 }; 71 72 /** 73 * struct ale_dev_id - The ALE version/SoC specific configuration 74 * @dev_id: ALE version/SoC id 75 * @features: features supported by ALE 76 * @tbl_entries: number of ALE entries 77 * @major_ver_mask: mask of ALE Major Version Value in ALE_IDVER reg. 78 * @nu_switch_ale: NU Switch ALE 79 * @vlan_entry_tbl: ALE vlan entry fields description tbl 80 */ 81 struct cpsw_ale_dev_id { 82 const char *dev_id; 83 u32 features; 84 u32 tbl_entries; 85 u32 major_ver_mask; 86 bool nu_switch_ale; 87 const struct ale_entry_fld *vlan_entry_tbl; 88 }; 89 90 #define ALE_TABLE_WRITE BIT(31) 91 92 #define ALE_TYPE_FREE 0 93 #define ALE_TYPE_ADDR 1 94 #define ALE_TYPE_VLAN 2 95 #define ALE_TYPE_VLAN_ADDR 3 96 97 #define ALE_UCAST_PERSISTANT 0 98 #define ALE_UCAST_UNTOUCHED 1 99 #define ALE_UCAST_OUI 2 100 #define ALE_UCAST_TOUCHED 3 101 102 #define ALE_TABLE_SIZE_MULTIPLIER 1024 103 #define ALE_STATUS_SIZE_MASK 0x1f 104 105 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits) 106 { 107 int idx; 108 109 idx = start / 32; 110 start -= idx * 32; 111 idx = 2 - idx; /* flip */ 112 return (ale_entry[idx] >> start) & BITMASK(bits); 113 } 114 115 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits, 116 u32 value) 117 { 118 int idx; 119 120 value &= BITMASK(bits); 121 idx = start / 32; 122 start -= idx * 32; 123 idx = 2 - idx; /* flip */ 124 ale_entry[idx] &= ~(BITMASK(bits) << start); 125 ale_entry[idx] |= (value << start); 126 } 127 128 #define DEFINE_ALE_FIELD(name, start, bits) \ 129 static inline int cpsw_ale_get_##name(u32 *ale_entry) \ 130 { \ 131 return cpsw_ale_get_field(ale_entry, start, bits); \ 132 } \ 133 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \ 134 { \ 135 cpsw_ale_set_field(ale_entry, start, bits, value); \ 136 } 137 138 #define DEFINE_ALE_FIELD1(name, start) \ 139 static inline int cpsw_ale_get_##name(u32 *ale_entry, u32 bits) \ 140 { \ 141 return cpsw_ale_get_field(ale_entry, start, bits); \ 142 } \ 143 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value, \ 144 u32 bits) \ 145 { \ 146 cpsw_ale_set_field(ale_entry, start, bits, value); \ 147 } 148 149 enum { 150 ALE_ENT_VID_MEMBER_LIST = 0, 151 ALE_ENT_VID_UNREG_MCAST_MSK, 152 ALE_ENT_VID_REG_MCAST_MSK, 153 ALE_ENT_VID_FORCE_UNTAGGED_MSK, 154 ALE_ENT_VID_UNREG_MCAST_IDX, 155 ALE_ENT_VID_REG_MCAST_IDX, 156 ALE_ENT_VID_LAST, 157 }; 158 159 #define ALE_FLD_ALLOWED BIT(0) 160 #define ALE_FLD_SIZE_PORT_MASK_BITS BIT(1) 161 #define ALE_FLD_SIZE_PORT_NUM_BITS BIT(2) 162 163 #define ALE_ENTRY_FLD(id, start, bits) \ 164 [id] = { \ 165 .start_bit = start, \ 166 .num_bits = bits, \ 167 .flags = ALE_FLD_ALLOWED, \ 168 } 169 170 #define ALE_ENTRY_FLD_DYN_MSK_SIZE(id, start) \ 171 [id] = { \ 172 .start_bit = start, \ 173 .num_bits = 0, \ 174 .flags = ALE_FLD_ALLOWED | \ 175 ALE_FLD_SIZE_PORT_MASK_BITS, \ 176 } 177 178 /* dm814x, am3/am4/am5, k2hk */ 179 static const struct ale_entry_fld vlan_entry_cpsw[ALE_ENT_VID_LAST] = { 180 ALE_ENTRY_FLD(ALE_ENT_VID_MEMBER_LIST, 0, 3), 181 ALE_ENTRY_FLD(ALE_ENT_VID_UNREG_MCAST_MSK, 8, 3), 182 ALE_ENTRY_FLD(ALE_ENT_VID_REG_MCAST_MSK, 16, 3), 183 ALE_ENTRY_FLD(ALE_ENT_VID_FORCE_UNTAGGED_MSK, 24, 3), 184 }; 185 186 /* k2e/k2l, k3 am65/j721e cpsw2g */ 187 static const struct ale_entry_fld vlan_entry_nu[ALE_ENT_VID_LAST] = { 188 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_MEMBER_LIST, 0), 189 ALE_ENTRY_FLD(ALE_ENT_VID_UNREG_MCAST_IDX, 20, 3), 190 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_FORCE_UNTAGGED_MSK, 24), 191 ALE_ENTRY_FLD(ALE_ENT_VID_REG_MCAST_IDX, 44, 3), 192 }; 193 194 /* K3 j721e/j7200 cpsw9g/5g, am64x cpsw3g */ 195 static const struct ale_entry_fld vlan_entry_k3_cpswxg[] = { 196 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_MEMBER_LIST, 0), 197 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_UNREG_MCAST_MSK, 12), 198 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_FORCE_UNTAGGED_MSK, 24), 199 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_REG_MCAST_MSK, 36), 200 }; 201 202 DEFINE_ALE_FIELD(entry_type, 60, 2) 203 DEFINE_ALE_FIELD(vlan_id, 48, 12) 204 DEFINE_ALE_FIELD(mcast_state, 62, 2) 205 DEFINE_ALE_FIELD1(port_mask, 66) 206 DEFINE_ALE_FIELD(super, 65, 1) 207 DEFINE_ALE_FIELD(ucast_type, 62, 2) 208 DEFINE_ALE_FIELD1(port_num, 66) 209 DEFINE_ALE_FIELD(blocked, 65, 1) 210 DEFINE_ALE_FIELD(secure, 64, 1) 211 DEFINE_ALE_FIELD(mcast, 40, 1) 212 213 #define NU_VLAN_UNREG_MCAST_IDX 1 214 215 static int cpsw_ale_entry_get_fld(struct cpsw_ale *ale, 216 u32 *ale_entry, 217 const struct ale_entry_fld *entry_tbl, 218 int fld_id) 219 { 220 const struct ale_entry_fld *entry_fld; 221 u32 bits; 222 223 if (!ale || !ale_entry) 224 return -EINVAL; 225 226 entry_fld = &entry_tbl[fld_id]; 227 if (!(entry_fld->flags & ALE_FLD_ALLOWED)) { 228 dev_err(ale->params.dev, "get: wrong ale fld id %d\n", fld_id); 229 return -ENOENT; 230 } 231 232 bits = entry_fld->num_bits; 233 if (entry_fld->flags & ALE_FLD_SIZE_PORT_MASK_BITS) 234 bits = ale->port_mask_bits; 235 236 return cpsw_ale_get_field(ale_entry, entry_fld->start_bit, bits); 237 } 238 239 static void cpsw_ale_entry_set_fld(struct cpsw_ale *ale, 240 u32 *ale_entry, 241 const struct ale_entry_fld *entry_tbl, 242 int fld_id, 243 u32 value) 244 { 245 const struct ale_entry_fld *entry_fld; 246 u32 bits; 247 248 if (!ale || !ale_entry) 249 return; 250 251 entry_fld = &entry_tbl[fld_id]; 252 if (!(entry_fld->flags & ALE_FLD_ALLOWED)) { 253 dev_err(ale->params.dev, "set: wrong ale fld id %d\n", fld_id); 254 return; 255 } 256 257 bits = entry_fld->num_bits; 258 if (entry_fld->flags & ALE_FLD_SIZE_PORT_MASK_BITS) 259 bits = ale->port_mask_bits; 260 261 cpsw_ale_set_field(ale_entry, entry_fld->start_bit, bits, value); 262 } 263 264 static int cpsw_ale_vlan_get_fld(struct cpsw_ale *ale, 265 u32 *ale_entry, 266 int fld_id) 267 { 268 return cpsw_ale_entry_get_fld(ale, ale_entry, 269 ale->vlan_entry_tbl, fld_id); 270 } 271 272 static void cpsw_ale_vlan_set_fld(struct cpsw_ale *ale, 273 u32 *ale_entry, 274 int fld_id, 275 u32 value) 276 { 277 cpsw_ale_entry_set_fld(ale, ale_entry, 278 ale->vlan_entry_tbl, fld_id, value); 279 } 280 281 /* The MAC address field in the ALE entry cannot be macroized as above */ 282 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr) 283 { 284 int i; 285 286 for (i = 0; i < 6; i++) 287 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8); 288 } 289 290 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr) 291 { 292 int i; 293 294 for (i = 0; i < 6; i++) 295 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]); 296 } 297 298 static int cpsw_ale_read(struct cpsw_ale *ale, int idx, u32 *ale_entry) 299 { 300 int i; 301 302 WARN_ON(idx > ale->params.ale_entries); 303 304 writel_relaxed(idx, ale->params.ale_regs + ALE_TABLE_CONTROL); 305 306 for (i = 0; i < ALE_ENTRY_WORDS; i++) 307 ale_entry[i] = readl_relaxed(ale->params.ale_regs + 308 ALE_TABLE + 4 * i); 309 310 return idx; 311 } 312 313 static int cpsw_ale_write(struct cpsw_ale *ale, int idx, u32 *ale_entry) 314 { 315 int i; 316 317 WARN_ON(idx > ale->params.ale_entries); 318 319 for (i = 0; i < ALE_ENTRY_WORDS; i++) 320 writel_relaxed(ale_entry[i], ale->params.ale_regs + 321 ALE_TABLE + 4 * i); 322 323 writel_relaxed(idx | ALE_TABLE_WRITE, ale->params.ale_regs + 324 ALE_TABLE_CONTROL); 325 326 return idx; 327 } 328 329 static int cpsw_ale_match_addr(struct cpsw_ale *ale, const u8 *addr, u16 vid) 330 { 331 u32 ale_entry[ALE_ENTRY_WORDS]; 332 int type, idx; 333 334 for (idx = 0; idx < ale->params.ale_entries; idx++) { 335 u8 entry_addr[6]; 336 337 cpsw_ale_read(ale, idx, ale_entry); 338 type = cpsw_ale_get_entry_type(ale_entry); 339 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 340 continue; 341 if (cpsw_ale_get_vlan_id(ale_entry) != vid) 342 continue; 343 cpsw_ale_get_addr(ale_entry, entry_addr); 344 if (ether_addr_equal(entry_addr, addr)) 345 return idx; 346 } 347 return -ENOENT; 348 } 349 350 static int cpsw_ale_match_vlan(struct cpsw_ale *ale, u16 vid) 351 { 352 u32 ale_entry[ALE_ENTRY_WORDS]; 353 int type, idx; 354 355 for (idx = 0; idx < ale->params.ale_entries; idx++) { 356 cpsw_ale_read(ale, idx, ale_entry); 357 type = cpsw_ale_get_entry_type(ale_entry); 358 if (type != ALE_TYPE_VLAN) 359 continue; 360 if (cpsw_ale_get_vlan_id(ale_entry) == vid) 361 return idx; 362 } 363 return -ENOENT; 364 } 365 366 static int cpsw_ale_match_free(struct cpsw_ale *ale) 367 { 368 u32 ale_entry[ALE_ENTRY_WORDS]; 369 int type, idx; 370 371 for (idx = 0; idx < ale->params.ale_entries; idx++) { 372 cpsw_ale_read(ale, idx, ale_entry); 373 type = cpsw_ale_get_entry_type(ale_entry); 374 if (type == ALE_TYPE_FREE) 375 return idx; 376 } 377 return -ENOENT; 378 } 379 380 static int cpsw_ale_find_ageable(struct cpsw_ale *ale) 381 { 382 u32 ale_entry[ALE_ENTRY_WORDS]; 383 int type, idx; 384 385 for (idx = 0; idx < ale->params.ale_entries; idx++) { 386 cpsw_ale_read(ale, idx, ale_entry); 387 type = cpsw_ale_get_entry_type(ale_entry); 388 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 389 continue; 390 if (cpsw_ale_get_mcast(ale_entry)) 391 continue; 392 type = cpsw_ale_get_ucast_type(ale_entry); 393 if (type != ALE_UCAST_PERSISTANT && 394 type != ALE_UCAST_OUI) 395 return idx; 396 } 397 return -ENOENT; 398 } 399 400 static void cpsw_ale_flush_mcast(struct cpsw_ale *ale, u32 *ale_entry, 401 int port_mask) 402 { 403 int mask; 404 405 mask = cpsw_ale_get_port_mask(ale_entry, 406 ale->port_mask_bits); 407 if ((mask & port_mask) == 0) 408 return; /* ports dont intersect, not interested */ 409 mask &= ~port_mask; 410 411 /* free if only remaining port is host port */ 412 if (mask) 413 cpsw_ale_set_port_mask(ale_entry, mask, 414 ale->port_mask_bits); 415 else 416 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 417 } 418 419 int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid) 420 { 421 u32 ale_entry[ALE_ENTRY_WORDS]; 422 int ret, idx; 423 424 for (idx = 0; idx < ale->params.ale_entries; idx++) { 425 cpsw_ale_read(ale, idx, ale_entry); 426 ret = cpsw_ale_get_entry_type(ale_entry); 427 if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR) 428 continue; 429 430 /* if vid passed is -1 then remove all multicast entry from 431 * the table irrespective of vlan id, if a valid vlan id is 432 * passed then remove only multicast added to that vlan id. 433 * if vlan id doesn't match then move on to next entry. 434 */ 435 if (vid != -1 && cpsw_ale_get_vlan_id(ale_entry) != vid) 436 continue; 437 438 if (cpsw_ale_get_mcast(ale_entry)) { 439 u8 addr[6]; 440 441 if (cpsw_ale_get_super(ale_entry)) 442 continue; 443 444 cpsw_ale_get_addr(ale_entry, addr); 445 if (!is_broadcast_ether_addr(addr)) 446 cpsw_ale_flush_mcast(ale, ale_entry, port_mask); 447 } 448 449 cpsw_ale_write(ale, idx, ale_entry); 450 } 451 return 0; 452 } 453 454 static inline void cpsw_ale_set_vlan_entry_type(u32 *ale_entry, 455 int flags, u16 vid) 456 { 457 if (flags & ALE_VLAN) { 458 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN_ADDR); 459 cpsw_ale_set_vlan_id(ale_entry, vid); 460 } else { 461 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR); 462 } 463 } 464 465 int cpsw_ale_add_ucast(struct cpsw_ale *ale, const u8 *addr, int port, 466 int flags, u16 vid) 467 { 468 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 469 int idx; 470 471 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid); 472 473 cpsw_ale_set_addr(ale_entry, addr); 474 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT); 475 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0); 476 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0); 477 cpsw_ale_set_port_num(ale_entry, port, ale->port_num_bits); 478 479 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0); 480 if (idx < 0) 481 idx = cpsw_ale_match_free(ale); 482 if (idx < 0) 483 idx = cpsw_ale_find_ageable(ale); 484 if (idx < 0) 485 return -ENOMEM; 486 487 cpsw_ale_write(ale, idx, ale_entry); 488 return 0; 489 } 490 491 int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port, 492 int flags, u16 vid) 493 { 494 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 495 int idx; 496 497 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0); 498 if (idx < 0) 499 return -ENOENT; 500 501 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 502 cpsw_ale_write(ale, idx, ale_entry); 503 return 0; 504 } 505 506 int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, 507 int flags, u16 vid, int mcast_state) 508 { 509 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 510 int idx, mask; 511 512 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0); 513 if (idx >= 0) 514 cpsw_ale_read(ale, idx, ale_entry); 515 516 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid); 517 518 cpsw_ale_set_addr(ale_entry, addr); 519 cpsw_ale_set_super(ale_entry, (flags & ALE_SUPER) ? 1 : 0); 520 cpsw_ale_set_mcast_state(ale_entry, mcast_state); 521 522 mask = cpsw_ale_get_port_mask(ale_entry, 523 ale->port_mask_bits); 524 port_mask |= mask; 525 cpsw_ale_set_port_mask(ale_entry, port_mask, 526 ale->port_mask_bits); 527 528 if (idx < 0) 529 idx = cpsw_ale_match_free(ale); 530 if (idx < 0) 531 idx = cpsw_ale_find_ageable(ale); 532 if (idx < 0) 533 return -ENOMEM; 534 535 cpsw_ale_write(ale, idx, ale_entry); 536 return 0; 537 } 538 539 int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, 540 int flags, u16 vid) 541 { 542 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 543 int mcast_members = 0; 544 int idx; 545 546 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0); 547 if (idx < 0) 548 return -ENOENT; 549 550 cpsw_ale_read(ale, idx, ale_entry); 551 552 if (port_mask) { 553 mcast_members = cpsw_ale_get_port_mask(ale_entry, 554 ale->port_mask_bits); 555 mcast_members &= ~port_mask; 556 } 557 558 if (mcast_members) 559 cpsw_ale_set_port_mask(ale_entry, mcast_members, 560 ale->port_mask_bits); 561 else 562 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 563 564 cpsw_ale_write(ale, idx, ale_entry); 565 return 0; 566 } 567 568 /* ALE NetCP NU switch specific vlan functions */ 569 static void cpsw_ale_set_vlan_mcast(struct cpsw_ale *ale, u32 *ale_entry, 570 int reg_mcast, int unreg_mcast) 571 { 572 int idx; 573 574 /* Set VLAN registered multicast flood mask */ 575 idx = cpsw_ale_vlan_get_fld(ale, ale_entry, 576 ALE_ENT_VID_REG_MCAST_IDX); 577 writel(reg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); 578 579 /* Set VLAN unregistered multicast flood mask */ 580 idx = cpsw_ale_vlan_get_fld(ale, ale_entry, 581 ALE_ENT_VID_UNREG_MCAST_IDX); 582 writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); 583 } 584 585 static void cpsw_ale_set_vlan_untag(struct cpsw_ale *ale, u32 *ale_entry, 586 u16 vid, int untag_mask) 587 { 588 cpsw_ale_vlan_set_fld(ale, ale_entry, 589 ALE_ENT_VID_FORCE_UNTAGGED_MSK, 590 untag_mask); 591 if (untag_mask & ALE_PORT_HOST) 592 bitmap_set(ale->p0_untag_vid_mask, vid, 1); 593 else 594 bitmap_clear(ale->p0_untag_vid_mask, vid, 1); 595 } 596 597 int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port_mask, int untag, 598 int reg_mcast, int unreg_mcast) 599 { 600 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 601 int idx; 602 603 idx = cpsw_ale_match_vlan(ale, vid); 604 if (idx >= 0) 605 cpsw_ale_read(ale, idx, ale_entry); 606 607 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN); 608 cpsw_ale_set_vlan_id(ale_entry, vid); 609 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag); 610 611 if (!ale->params.nu_switch_ale) { 612 cpsw_ale_vlan_set_fld(ale, ale_entry, 613 ALE_ENT_VID_REG_MCAST_MSK, reg_mcast); 614 cpsw_ale_vlan_set_fld(ale, ale_entry, 615 ALE_ENT_VID_UNREG_MCAST_MSK, unreg_mcast); 616 } else { 617 cpsw_ale_vlan_set_fld(ale, ale_entry, 618 ALE_ENT_VID_UNREG_MCAST_IDX, 619 NU_VLAN_UNREG_MCAST_IDX); 620 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast, unreg_mcast); 621 } 622 623 cpsw_ale_vlan_set_fld(ale, ale_entry, 624 ALE_ENT_VID_MEMBER_LIST, port_mask); 625 626 if (idx < 0) 627 idx = cpsw_ale_match_free(ale); 628 if (idx < 0) 629 idx = cpsw_ale_find_ageable(ale); 630 if (idx < 0) 631 return -ENOMEM; 632 633 cpsw_ale_write(ale, idx, ale_entry); 634 return 0; 635 } 636 637 static void cpsw_ale_del_vlan_modify(struct cpsw_ale *ale, u32 *ale_entry, 638 u16 vid, int port_mask) 639 { 640 int reg_mcast, unreg_mcast; 641 int members, untag; 642 643 members = cpsw_ale_vlan_get_fld(ale, ale_entry, 644 ALE_ENT_VID_MEMBER_LIST); 645 members &= ~port_mask; 646 if (!members) { 647 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 648 return; 649 } 650 651 untag = cpsw_ale_vlan_get_fld(ale, ale_entry, 652 ALE_ENT_VID_FORCE_UNTAGGED_MSK); 653 reg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry, 654 ALE_ENT_VID_REG_MCAST_MSK); 655 unreg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry, 656 ALE_ENT_VID_UNREG_MCAST_MSK); 657 untag &= members; 658 reg_mcast &= members; 659 unreg_mcast &= members; 660 661 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag); 662 663 if (!ale->params.nu_switch_ale) { 664 cpsw_ale_vlan_set_fld(ale, ale_entry, 665 ALE_ENT_VID_REG_MCAST_MSK, reg_mcast); 666 cpsw_ale_vlan_set_fld(ale, ale_entry, 667 ALE_ENT_VID_UNREG_MCAST_MSK, unreg_mcast); 668 } else { 669 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast, 670 unreg_mcast); 671 } 672 cpsw_ale_vlan_set_fld(ale, ale_entry, 673 ALE_ENT_VID_MEMBER_LIST, members); 674 } 675 676 int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask) 677 { 678 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 679 int idx; 680 681 idx = cpsw_ale_match_vlan(ale, vid); 682 if (idx < 0) 683 return -ENOENT; 684 685 cpsw_ale_read(ale, idx, ale_entry); 686 687 if (port_mask) { 688 cpsw_ale_del_vlan_modify(ale, ale_entry, vid, port_mask); 689 } else { 690 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, 0); 691 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 692 } 693 694 cpsw_ale_write(ale, idx, ale_entry); 695 696 return 0; 697 } 698 699 int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask, 700 int untag_mask, int reg_mask, int unreg_mask) 701 { 702 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 703 int reg_mcast_members, unreg_mcast_members; 704 int vlan_members, untag_members; 705 int idx, ret = 0; 706 707 idx = cpsw_ale_match_vlan(ale, vid); 708 if (idx >= 0) 709 cpsw_ale_read(ale, idx, ale_entry); 710 711 vlan_members = cpsw_ale_vlan_get_fld(ale, ale_entry, 712 ALE_ENT_VID_MEMBER_LIST); 713 reg_mcast_members = cpsw_ale_vlan_get_fld(ale, ale_entry, 714 ALE_ENT_VID_REG_MCAST_MSK); 715 unreg_mcast_members = 716 cpsw_ale_vlan_get_fld(ale, ale_entry, 717 ALE_ENT_VID_UNREG_MCAST_MSK); 718 untag_members = cpsw_ale_vlan_get_fld(ale, ale_entry, 719 ALE_ENT_VID_FORCE_UNTAGGED_MSK); 720 721 vlan_members |= port_mask; 722 untag_members = (untag_members & ~port_mask) | untag_mask; 723 reg_mcast_members = (reg_mcast_members & ~port_mask) | reg_mask; 724 unreg_mcast_members = (unreg_mcast_members & ~port_mask) | unreg_mask; 725 726 ret = cpsw_ale_add_vlan(ale, vid, vlan_members, untag_members, 727 reg_mcast_members, unreg_mcast_members); 728 if (ret) { 729 dev_err(ale->params.dev, "Unable to add vlan\n"); 730 return ret; 731 } 732 dev_dbg(ale->params.dev, "port mask 0x%x untag 0x%x\n", vlan_members, 733 untag_mask); 734 735 return ret; 736 } 737 738 void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask, 739 bool add) 740 { 741 u32 ale_entry[ALE_ENTRY_WORDS]; 742 int unreg_members = 0; 743 int type, idx; 744 745 for (idx = 0; idx < ale->params.ale_entries; idx++) { 746 cpsw_ale_read(ale, idx, ale_entry); 747 type = cpsw_ale_get_entry_type(ale_entry); 748 if (type != ALE_TYPE_VLAN) 749 continue; 750 751 unreg_members = 752 cpsw_ale_vlan_get_fld(ale, ale_entry, 753 ALE_ENT_VID_UNREG_MCAST_MSK); 754 if (add) 755 unreg_members |= unreg_mcast_mask; 756 else 757 unreg_members &= ~unreg_mcast_mask; 758 cpsw_ale_vlan_set_fld(ale, ale_entry, 759 ALE_ENT_VID_UNREG_MCAST_MSK, 760 unreg_members); 761 cpsw_ale_write(ale, idx, ale_entry); 762 } 763 } 764 765 static void cpsw_ale_vlan_set_unreg_mcast(struct cpsw_ale *ale, u32 *ale_entry, 766 int allmulti) 767 { 768 int unreg_mcast; 769 770 unreg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry, 771 ALE_ENT_VID_UNREG_MCAST_MSK); 772 if (allmulti) 773 unreg_mcast |= ALE_PORT_HOST; 774 else 775 unreg_mcast &= ~ALE_PORT_HOST; 776 777 cpsw_ale_vlan_set_fld(ale, ale_entry, 778 ALE_ENT_VID_UNREG_MCAST_MSK, unreg_mcast); 779 } 780 781 static void 782 cpsw_ale_vlan_set_unreg_mcast_idx(struct cpsw_ale *ale, u32 *ale_entry, 783 int allmulti) 784 { 785 int unreg_mcast; 786 int idx; 787 788 idx = cpsw_ale_vlan_get_fld(ale, ale_entry, 789 ALE_ENT_VID_UNREG_MCAST_IDX); 790 791 unreg_mcast = readl(ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); 792 793 if (allmulti) 794 unreg_mcast |= ALE_PORT_HOST; 795 else 796 unreg_mcast &= ~ALE_PORT_HOST; 797 798 writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); 799 } 800 801 void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti, int port) 802 { 803 u32 ale_entry[ALE_ENTRY_WORDS]; 804 int type, idx; 805 806 for (idx = 0; idx < ale->params.ale_entries; idx++) { 807 int vlan_members; 808 809 cpsw_ale_read(ale, idx, ale_entry); 810 type = cpsw_ale_get_entry_type(ale_entry); 811 if (type != ALE_TYPE_VLAN) 812 continue; 813 814 vlan_members = cpsw_ale_vlan_get_fld(ale, ale_entry, 815 ALE_ENT_VID_MEMBER_LIST); 816 817 if (port != -1 && !(vlan_members & BIT(port))) 818 continue; 819 820 if (!ale->params.nu_switch_ale) 821 cpsw_ale_vlan_set_unreg_mcast(ale, ale_entry, allmulti); 822 else 823 cpsw_ale_vlan_set_unreg_mcast_idx(ale, ale_entry, 824 allmulti); 825 826 cpsw_ale_write(ale, idx, ale_entry); 827 } 828 } 829 830 struct ale_control_info { 831 const char *name; 832 int offset, port_offset; 833 int shift, port_shift; 834 int bits; 835 }; 836 837 static struct ale_control_info ale_controls[ALE_NUM_CONTROLS] = { 838 [ALE_ENABLE] = { 839 .name = "enable", 840 .offset = ALE_CONTROL, 841 .port_offset = 0, 842 .shift = 31, 843 .port_shift = 0, 844 .bits = 1, 845 }, 846 [ALE_CLEAR] = { 847 .name = "clear", 848 .offset = ALE_CONTROL, 849 .port_offset = 0, 850 .shift = 30, 851 .port_shift = 0, 852 .bits = 1, 853 }, 854 [ALE_AGEOUT] = { 855 .name = "ageout", 856 .offset = ALE_CONTROL, 857 .port_offset = 0, 858 .shift = 29, 859 .port_shift = 0, 860 .bits = 1, 861 }, 862 [ALE_P0_UNI_FLOOD] = { 863 .name = "port0_unicast_flood", 864 .offset = ALE_CONTROL, 865 .port_offset = 0, 866 .shift = 8, 867 .port_shift = 0, 868 .bits = 1, 869 }, 870 [ALE_VLAN_NOLEARN] = { 871 .name = "vlan_nolearn", 872 .offset = ALE_CONTROL, 873 .port_offset = 0, 874 .shift = 7, 875 .port_shift = 0, 876 .bits = 1, 877 }, 878 [ALE_NO_PORT_VLAN] = { 879 .name = "no_port_vlan", 880 .offset = ALE_CONTROL, 881 .port_offset = 0, 882 .shift = 6, 883 .port_shift = 0, 884 .bits = 1, 885 }, 886 [ALE_OUI_DENY] = { 887 .name = "oui_deny", 888 .offset = ALE_CONTROL, 889 .port_offset = 0, 890 .shift = 5, 891 .port_shift = 0, 892 .bits = 1, 893 }, 894 [ALE_BYPASS] = { 895 .name = "bypass", 896 .offset = ALE_CONTROL, 897 .port_offset = 0, 898 .shift = 4, 899 .port_shift = 0, 900 .bits = 1, 901 }, 902 [ALE_RATE_LIMIT_TX] = { 903 .name = "rate_limit_tx", 904 .offset = ALE_CONTROL, 905 .port_offset = 0, 906 .shift = 3, 907 .port_shift = 0, 908 .bits = 1, 909 }, 910 [ALE_VLAN_AWARE] = { 911 .name = "vlan_aware", 912 .offset = ALE_CONTROL, 913 .port_offset = 0, 914 .shift = 2, 915 .port_shift = 0, 916 .bits = 1, 917 }, 918 [ALE_AUTH_ENABLE] = { 919 .name = "auth_enable", 920 .offset = ALE_CONTROL, 921 .port_offset = 0, 922 .shift = 1, 923 .port_shift = 0, 924 .bits = 1, 925 }, 926 [ALE_RATE_LIMIT] = { 927 .name = "rate_limit", 928 .offset = ALE_CONTROL, 929 .port_offset = 0, 930 .shift = 0, 931 .port_shift = 0, 932 .bits = 1, 933 }, 934 [ALE_PORT_STATE] = { 935 .name = "port_state", 936 .offset = ALE_PORTCTL, 937 .port_offset = 4, 938 .shift = 0, 939 .port_shift = 0, 940 .bits = 2, 941 }, 942 [ALE_PORT_DROP_UNTAGGED] = { 943 .name = "drop_untagged", 944 .offset = ALE_PORTCTL, 945 .port_offset = 4, 946 .shift = 2, 947 .port_shift = 0, 948 .bits = 1, 949 }, 950 [ALE_PORT_DROP_UNKNOWN_VLAN] = { 951 .name = "drop_unknown", 952 .offset = ALE_PORTCTL, 953 .port_offset = 4, 954 .shift = 3, 955 .port_shift = 0, 956 .bits = 1, 957 }, 958 [ALE_PORT_NOLEARN] = { 959 .name = "nolearn", 960 .offset = ALE_PORTCTL, 961 .port_offset = 4, 962 .shift = 4, 963 .port_shift = 0, 964 .bits = 1, 965 }, 966 [ALE_PORT_NO_SA_UPDATE] = { 967 .name = "no_source_update", 968 .offset = ALE_PORTCTL, 969 .port_offset = 4, 970 .shift = 5, 971 .port_shift = 0, 972 .bits = 1, 973 }, 974 [ALE_PORT_MACONLY] = { 975 .name = "mac_only_port_mode", 976 .offset = ALE_PORTCTL, 977 .port_offset = 4, 978 .shift = 11, 979 .port_shift = 0, 980 .bits = 1, 981 }, 982 [ALE_PORT_MACONLY_CAF] = { 983 .name = "mac_only_port_caf", 984 .offset = ALE_PORTCTL, 985 .port_offset = 4, 986 .shift = 13, 987 .port_shift = 0, 988 .bits = 1, 989 }, 990 [ALE_PORT_MCAST_LIMIT] = { 991 .name = "mcast_limit", 992 .offset = ALE_PORTCTL, 993 .port_offset = 4, 994 .shift = 16, 995 .port_shift = 0, 996 .bits = 8, 997 }, 998 [ALE_PORT_BCAST_LIMIT] = { 999 .name = "bcast_limit", 1000 .offset = ALE_PORTCTL, 1001 .port_offset = 4, 1002 .shift = 24, 1003 .port_shift = 0, 1004 .bits = 8, 1005 }, 1006 [ALE_PORT_UNKNOWN_VLAN_MEMBER] = { 1007 .name = "unknown_vlan_member", 1008 .offset = ALE_UNKNOWNVLAN, 1009 .port_offset = 0, 1010 .shift = 0, 1011 .port_shift = 0, 1012 .bits = 6, 1013 }, 1014 [ALE_PORT_UNKNOWN_MCAST_FLOOD] = { 1015 .name = "unknown_mcast_flood", 1016 .offset = ALE_UNKNOWNVLAN, 1017 .port_offset = 0, 1018 .shift = 8, 1019 .port_shift = 0, 1020 .bits = 6, 1021 }, 1022 [ALE_PORT_UNKNOWN_REG_MCAST_FLOOD] = { 1023 .name = "unknown_reg_flood", 1024 .offset = ALE_UNKNOWNVLAN, 1025 .port_offset = 0, 1026 .shift = 16, 1027 .port_shift = 0, 1028 .bits = 6, 1029 }, 1030 [ALE_PORT_UNTAGGED_EGRESS] = { 1031 .name = "untagged_egress", 1032 .offset = ALE_UNKNOWNVLAN, 1033 .port_offset = 0, 1034 .shift = 24, 1035 .port_shift = 0, 1036 .bits = 6, 1037 }, 1038 [ALE_DEFAULT_THREAD_ID] = { 1039 .name = "default_thread_id", 1040 .offset = AM65_CPSW_ALE_THREAD_DEF_REG, 1041 .port_offset = 0, 1042 .shift = 0, 1043 .port_shift = 0, 1044 .bits = 6, 1045 }, 1046 [ALE_DEFAULT_THREAD_ENABLE] = { 1047 .name = "default_thread_id_enable", 1048 .offset = AM65_CPSW_ALE_THREAD_DEF_REG, 1049 .port_offset = 0, 1050 .shift = 15, 1051 .port_shift = 0, 1052 .bits = 1, 1053 }, 1054 }; 1055 1056 int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control, 1057 int value) 1058 { 1059 const struct ale_control_info *info; 1060 int offset, shift; 1061 u32 tmp, mask; 1062 1063 if (control < 0 || control >= ARRAY_SIZE(ale_controls)) 1064 return -EINVAL; 1065 1066 info = &ale_controls[control]; 1067 if (info->port_offset == 0 && info->port_shift == 0) 1068 port = 0; /* global, port is a dont care */ 1069 1070 if (port < 0 || port >= ale->params.ale_ports) 1071 return -EINVAL; 1072 1073 mask = BITMASK(info->bits); 1074 if (value & ~mask) 1075 return -EINVAL; 1076 1077 offset = info->offset + (port * info->port_offset); 1078 shift = info->shift + (port * info->port_shift); 1079 1080 tmp = readl_relaxed(ale->params.ale_regs + offset); 1081 tmp = (tmp & ~(mask << shift)) | (value << shift); 1082 writel_relaxed(tmp, ale->params.ale_regs + offset); 1083 1084 return 0; 1085 } 1086 1087 int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control) 1088 { 1089 const struct ale_control_info *info; 1090 int offset, shift; 1091 u32 tmp; 1092 1093 if (control < 0 || control >= ARRAY_SIZE(ale_controls)) 1094 return -EINVAL; 1095 1096 info = &ale_controls[control]; 1097 if (info->port_offset == 0 && info->port_shift == 0) 1098 port = 0; /* global, port is a dont care */ 1099 1100 if (port < 0 || port >= ale->params.ale_ports) 1101 return -EINVAL; 1102 1103 offset = info->offset + (port * info->port_offset); 1104 shift = info->shift + (port * info->port_shift); 1105 1106 tmp = readl_relaxed(ale->params.ale_regs + offset) >> shift; 1107 return tmp & BITMASK(info->bits); 1108 } 1109 1110 static void cpsw_ale_timer(struct timer_list *t) 1111 { 1112 struct cpsw_ale *ale = from_timer(ale, t, timer); 1113 1114 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 1115 1116 if (ale->ageout) { 1117 ale->timer.expires = jiffies + ale->ageout; 1118 add_timer(&ale->timer); 1119 } 1120 } 1121 1122 static void cpsw_ale_hw_aging_timer_start(struct cpsw_ale *ale) 1123 { 1124 u32 aging_timer; 1125 1126 aging_timer = ale->params.bus_freq / 1000000; 1127 aging_timer *= ale->params.ale_ageout; 1128 1129 if (aging_timer & ~ALE_AGING_TIMER_MASK) { 1130 aging_timer = ALE_AGING_TIMER_MASK; 1131 dev_warn(ale->params.dev, 1132 "ALE aging timer overflow, set to max\n"); 1133 } 1134 1135 writel(aging_timer, ale->params.ale_regs + ALE_AGING_TIMER); 1136 } 1137 1138 static void cpsw_ale_hw_aging_timer_stop(struct cpsw_ale *ale) 1139 { 1140 writel(0, ale->params.ale_regs + ALE_AGING_TIMER); 1141 } 1142 1143 static void cpsw_ale_aging_start(struct cpsw_ale *ale) 1144 { 1145 if (!ale->params.ale_ageout) 1146 return; 1147 1148 if (ale->features & CPSW_ALE_F_HW_AUTOAGING) { 1149 cpsw_ale_hw_aging_timer_start(ale); 1150 return; 1151 } 1152 1153 timer_setup(&ale->timer, cpsw_ale_timer, 0); 1154 ale->timer.expires = jiffies + ale->ageout; 1155 add_timer(&ale->timer); 1156 } 1157 1158 static void cpsw_ale_aging_stop(struct cpsw_ale *ale) 1159 { 1160 if (!ale->params.ale_ageout) 1161 return; 1162 1163 if (ale->features & CPSW_ALE_F_HW_AUTOAGING) { 1164 cpsw_ale_hw_aging_timer_stop(ale); 1165 return; 1166 } 1167 1168 del_timer_sync(&ale->timer); 1169 } 1170 1171 void cpsw_ale_start(struct cpsw_ale *ale) 1172 { 1173 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 1); 1174 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1); 1175 1176 cpsw_ale_aging_start(ale); 1177 } 1178 1179 void cpsw_ale_stop(struct cpsw_ale *ale) 1180 { 1181 cpsw_ale_aging_stop(ale); 1182 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1); 1183 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0); 1184 } 1185 1186 static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = { 1187 { 1188 /* am3/4/5, dra7. dm814x, 66ak2hk-gbe */ 1189 .dev_id = "cpsw", 1190 .tbl_entries = 1024, 1191 .major_ver_mask = 0xff, 1192 .vlan_entry_tbl = vlan_entry_cpsw, 1193 }, 1194 { 1195 /* 66ak2h_xgbe */ 1196 .dev_id = "66ak2h-xgbe", 1197 .tbl_entries = 2048, 1198 .major_ver_mask = 0xff, 1199 .vlan_entry_tbl = vlan_entry_cpsw, 1200 }, 1201 { 1202 .dev_id = "66ak2el", 1203 .features = CPSW_ALE_F_STATUS_REG, 1204 .major_ver_mask = 0x7, 1205 .nu_switch_ale = true, 1206 .vlan_entry_tbl = vlan_entry_nu, 1207 }, 1208 { 1209 .dev_id = "66ak2g", 1210 .features = CPSW_ALE_F_STATUS_REG, 1211 .tbl_entries = 64, 1212 .major_ver_mask = 0x7, 1213 .nu_switch_ale = true, 1214 .vlan_entry_tbl = vlan_entry_nu, 1215 }, 1216 { 1217 .dev_id = "am65x-cpsw2g", 1218 .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING, 1219 .tbl_entries = 64, 1220 .major_ver_mask = 0x7, 1221 .nu_switch_ale = true, 1222 .vlan_entry_tbl = vlan_entry_nu, 1223 }, 1224 { 1225 .dev_id = "j721e-cpswxg", 1226 .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING, 1227 .major_ver_mask = 0x7, 1228 .vlan_entry_tbl = vlan_entry_k3_cpswxg, 1229 }, 1230 { }, 1231 }; 1232 1233 static const struct 1234 cpsw_ale_dev_id *cpsw_ale_match_id(const struct cpsw_ale_dev_id *id, 1235 const char *dev_id) 1236 { 1237 if (!dev_id) 1238 return NULL; 1239 1240 while (id->dev_id) { 1241 if (strcmp(dev_id, id->dev_id) == 0) 1242 return id; 1243 id++; 1244 } 1245 return NULL; 1246 } 1247 1248 struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) 1249 { 1250 const struct cpsw_ale_dev_id *ale_dev_id; 1251 struct cpsw_ale *ale; 1252 u32 rev, ale_entries; 1253 1254 ale_dev_id = cpsw_ale_match_id(cpsw_ale_id_match, params->dev_id); 1255 if (!ale_dev_id) 1256 return ERR_PTR(-EINVAL); 1257 1258 params->ale_entries = ale_dev_id->tbl_entries; 1259 params->major_ver_mask = ale_dev_id->major_ver_mask; 1260 params->nu_switch_ale = ale_dev_id->nu_switch_ale; 1261 1262 ale = devm_kzalloc(params->dev, sizeof(*ale), GFP_KERNEL); 1263 if (!ale) 1264 return ERR_PTR(-ENOMEM); 1265 1266 ale->p0_untag_vid_mask = 1267 devm_kmalloc_array(params->dev, BITS_TO_LONGS(VLAN_N_VID), 1268 sizeof(unsigned long), 1269 GFP_KERNEL); 1270 if (!ale->p0_untag_vid_mask) 1271 return ERR_PTR(-ENOMEM); 1272 1273 ale->params = *params; 1274 ale->ageout = ale->params.ale_ageout * HZ; 1275 ale->features = ale_dev_id->features; 1276 ale->vlan_entry_tbl = ale_dev_id->vlan_entry_tbl; 1277 1278 rev = readl_relaxed(ale->params.ale_regs + ALE_IDVER); 1279 ale->version = 1280 (ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask) << 8) | 1281 ALE_VERSION_MINOR(rev); 1282 dev_info(ale->params.dev, "initialized cpsw ale version %d.%d\n", 1283 ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask), 1284 ALE_VERSION_MINOR(rev)); 1285 1286 if (ale->features & CPSW_ALE_F_STATUS_REG && 1287 !ale->params.ale_entries) { 1288 ale_entries = 1289 readl_relaxed(ale->params.ale_regs + ALE_STATUS) & 1290 ALE_STATUS_SIZE_MASK; 1291 /* ALE available on newer NetCP switches has introduced 1292 * a register, ALE_STATUS, to indicate the size of ALE 1293 * table which shows the size as a multiple of 1024 entries. 1294 * For these, params.ale_entries will be set to zero. So 1295 * read the register and update the value of ale_entries. 1296 * return error if ale_entries is zero in ALE_STATUS. 1297 */ 1298 if (!ale_entries) 1299 return ERR_PTR(-EINVAL); 1300 1301 ale_entries *= ALE_TABLE_SIZE_MULTIPLIER; 1302 ale->params.ale_entries = ale_entries; 1303 } 1304 dev_info(ale->params.dev, 1305 "ALE Table size %ld\n", ale->params.ale_entries); 1306 1307 /* set default bits for existing h/w */ 1308 ale->port_mask_bits = ale->params.ale_ports; 1309 ale->port_num_bits = order_base_2(ale->params.ale_ports); 1310 ale->vlan_field_bits = ale->params.ale_ports; 1311 1312 /* Set defaults override for ALE on NetCP NU switch and for version 1313 * 1R3 1314 */ 1315 if (ale->params.nu_switch_ale) { 1316 /* Separate registers for unknown vlan configuration. 1317 * Also there are N bits, where N is number of ale 1318 * ports and shift value should be 0 1319 */ 1320 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].bits = 1321 ale->params.ale_ports; 1322 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].offset = 1323 ALE_UNKNOWNVLAN_MEMBER; 1324 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].bits = 1325 ale->params.ale_ports; 1326 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].shift = 0; 1327 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].offset = 1328 ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD; 1329 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].bits = 1330 ale->params.ale_ports; 1331 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].shift = 0; 1332 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].offset = 1333 ALE_UNKNOWNVLAN_REG_MCAST_FLOOD; 1334 ale_controls[ALE_PORT_UNTAGGED_EGRESS].bits = 1335 ale->params.ale_ports; 1336 ale_controls[ALE_PORT_UNTAGGED_EGRESS].shift = 0; 1337 ale_controls[ALE_PORT_UNTAGGED_EGRESS].offset = 1338 ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS; 1339 } 1340 1341 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1); 1342 return ale; 1343 } 1344 1345 void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data) 1346 { 1347 int i; 1348 1349 for (i = 0; i < ale->params.ale_entries; i++) { 1350 cpsw_ale_read(ale, i, data); 1351 data += ALE_ENTRY_WORDS; 1352 } 1353 } 1354 1355 u32 cpsw_ale_get_num_entries(struct cpsw_ale *ale) 1356 { 1357 return ale ? ale->params.ale_entries : 0; 1358 } 1359