1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Texas Instruments N-Port Ethernet Switch Address Lookup Engine 4 * 5 * Copyright (C) 2012 Texas Instruments 6 * 7 */ 8 #include <linux/bitmap.h> 9 #include <linux/if_vlan.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/seq_file.h> 14 #include <linux/slab.h> 15 #include <linux/err.h> 16 #include <linux/io.h> 17 #include <linux/stat.h> 18 #include <linux/sysfs.h> 19 #include <linux/etherdevice.h> 20 21 #include "cpsw_ale.h" 22 23 #define BITMASK(bits) (BIT(bits) - 1) 24 25 #define ALE_VERSION_MAJOR(rev, mask) (((rev) >> 8) & (mask)) 26 #define ALE_VERSION_MINOR(rev) (rev & 0xff) 27 #define ALE_VERSION_1R3 0x0103 28 #define ALE_VERSION_1R4 0x0104 29 30 /* ALE Registers */ 31 #define ALE_IDVER 0x00 32 #define ALE_STATUS 0x04 33 #define ALE_CONTROL 0x08 34 #define ALE_PRESCALE 0x10 35 #define ALE_UNKNOWNVLAN 0x18 36 #define ALE_TABLE_CONTROL 0x20 37 #define ALE_TABLE 0x34 38 #define ALE_PORTCTL 0x40 39 40 /* ALE NetCP NU switch specific Registers */ 41 #define ALE_UNKNOWNVLAN_MEMBER 0x90 42 #define ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD 0x94 43 #define ALE_UNKNOWNVLAN_REG_MCAST_FLOOD 0x98 44 #define ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS 0x9C 45 #define ALE_VLAN_MASK_MUX(reg) (0xc0 + (0x4 * (reg))) 46 47 #define AM65_CPSW_ALE_THREAD_DEF_REG 0x134 48 49 #define ALE_TABLE_WRITE BIT(31) 50 51 #define ALE_TYPE_FREE 0 52 #define ALE_TYPE_ADDR 1 53 #define ALE_TYPE_VLAN 2 54 #define ALE_TYPE_VLAN_ADDR 3 55 56 #define ALE_UCAST_PERSISTANT 0 57 #define ALE_UCAST_UNTOUCHED 1 58 #define ALE_UCAST_OUI 2 59 #define ALE_UCAST_TOUCHED 3 60 61 #define ALE_TABLE_SIZE_MULTIPLIER 1024 62 #define ALE_STATUS_SIZE_MASK 0x1f 63 #define ALE_TABLE_SIZE_DEFAULT 64 64 65 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits) 66 { 67 int idx; 68 69 idx = start / 32; 70 start -= idx * 32; 71 idx = 2 - idx; /* flip */ 72 return (ale_entry[idx] >> start) & BITMASK(bits); 73 } 74 75 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits, 76 u32 value) 77 { 78 int idx; 79 80 value &= BITMASK(bits); 81 idx = start / 32; 82 start -= idx * 32; 83 idx = 2 - idx; /* flip */ 84 ale_entry[idx] &= ~(BITMASK(bits) << start); 85 ale_entry[idx] |= (value << start); 86 } 87 88 #define DEFINE_ALE_FIELD(name, start, bits) \ 89 static inline int cpsw_ale_get_##name(u32 *ale_entry) \ 90 { \ 91 return cpsw_ale_get_field(ale_entry, start, bits); \ 92 } \ 93 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \ 94 { \ 95 cpsw_ale_set_field(ale_entry, start, bits, value); \ 96 } 97 98 #define DEFINE_ALE_FIELD1(name, start) \ 99 static inline int cpsw_ale_get_##name(u32 *ale_entry, u32 bits) \ 100 { \ 101 return cpsw_ale_get_field(ale_entry, start, bits); \ 102 } \ 103 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value, \ 104 u32 bits) \ 105 { \ 106 cpsw_ale_set_field(ale_entry, start, bits, value); \ 107 } 108 109 DEFINE_ALE_FIELD(entry_type, 60, 2) 110 DEFINE_ALE_FIELD(vlan_id, 48, 12) 111 DEFINE_ALE_FIELD(mcast_state, 62, 2) 112 DEFINE_ALE_FIELD1(port_mask, 66) 113 DEFINE_ALE_FIELD(super, 65, 1) 114 DEFINE_ALE_FIELD(ucast_type, 62, 2) 115 DEFINE_ALE_FIELD1(port_num, 66) 116 DEFINE_ALE_FIELD(blocked, 65, 1) 117 DEFINE_ALE_FIELD(secure, 64, 1) 118 DEFINE_ALE_FIELD1(vlan_untag_force, 24) 119 DEFINE_ALE_FIELD1(vlan_reg_mcast, 16) 120 DEFINE_ALE_FIELD1(vlan_unreg_mcast, 8) 121 DEFINE_ALE_FIELD1(vlan_member_list, 0) 122 DEFINE_ALE_FIELD(mcast, 40, 1) 123 /* ALE NetCP nu switch specific */ 124 DEFINE_ALE_FIELD(vlan_unreg_mcast_idx, 20, 3) 125 DEFINE_ALE_FIELD(vlan_reg_mcast_idx, 44, 3) 126 127 #define NU_VLAN_UNREG_MCAST_IDX 1 128 129 /* The MAC address field in the ALE entry cannot be macroized as above */ 130 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr) 131 { 132 int i; 133 134 for (i = 0; i < 6; i++) 135 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8); 136 } 137 138 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr) 139 { 140 int i; 141 142 for (i = 0; i < 6; i++) 143 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]); 144 } 145 146 static int cpsw_ale_read(struct cpsw_ale *ale, int idx, u32 *ale_entry) 147 { 148 int i; 149 150 WARN_ON(idx > ale->params.ale_entries); 151 152 writel_relaxed(idx, ale->params.ale_regs + ALE_TABLE_CONTROL); 153 154 for (i = 0; i < ALE_ENTRY_WORDS; i++) 155 ale_entry[i] = readl_relaxed(ale->params.ale_regs + 156 ALE_TABLE + 4 * i); 157 158 return idx; 159 } 160 161 static int cpsw_ale_write(struct cpsw_ale *ale, int idx, u32 *ale_entry) 162 { 163 int i; 164 165 WARN_ON(idx > ale->params.ale_entries); 166 167 for (i = 0; i < ALE_ENTRY_WORDS; i++) 168 writel_relaxed(ale_entry[i], ale->params.ale_regs + 169 ALE_TABLE + 4 * i); 170 171 writel_relaxed(idx | ALE_TABLE_WRITE, ale->params.ale_regs + 172 ALE_TABLE_CONTROL); 173 174 return idx; 175 } 176 177 static int cpsw_ale_match_addr(struct cpsw_ale *ale, const u8 *addr, u16 vid) 178 { 179 u32 ale_entry[ALE_ENTRY_WORDS]; 180 int type, idx; 181 182 for (idx = 0; idx < ale->params.ale_entries; idx++) { 183 u8 entry_addr[6]; 184 185 cpsw_ale_read(ale, idx, ale_entry); 186 type = cpsw_ale_get_entry_type(ale_entry); 187 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 188 continue; 189 if (cpsw_ale_get_vlan_id(ale_entry) != vid) 190 continue; 191 cpsw_ale_get_addr(ale_entry, entry_addr); 192 if (ether_addr_equal(entry_addr, addr)) 193 return idx; 194 } 195 return -ENOENT; 196 } 197 198 static int cpsw_ale_match_vlan(struct cpsw_ale *ale, u16 vid) 199 { 200 u32 ale_entry[ALE_ENTRY_WORDS]; 201 int type, idx; 202 203 for (idx = 0; idx < ale->params.ale_entries; idx++) { 204 cpsw_ale_read(ale, idx, ale_entry); 205 type = cpsw_ale_get_entry_type(ale_entry); 206 if (type != ALE_TYPE_VLAN) 207 continue; 208 if (cpsw_ale_get_vlan_id(ale_entry) == vid) 209 return idx; 210 } 211 return -ENOENT; 212 } 213 214 static int cpsw_ale_match_free(struct cpsw_ale *ale) 215 { 216 u32 ale_entry[ALE_ENTRY_WORDS]; 217 int type, idx; 218 219 for (idx = 0; idx < ale->params.ale_entries; idx++) { 220 cpsw_ale_read(ale, idx, ale_entry); 221 type = cpsw_ale_get_entry_type(ale_entry); 222 if (type == ALE_TYPE_FREE) 223 return idx; 224 } 225 return -ENOENT; 226 } 227 228 static int cpsw_ale_find_ageable(struct cpsw_ale *ale) 229 { 230 u32 ale_entry[ALE_ENTRY_WORDS]; 231 int type, idx; 232 233 for (idx = 0; idx < ale->params.ale_entries; idx++) { 234 cpsw_ale_read(ale, idx, ale_entry); 235 type = cpsw_ale_get_entry_type(ale_entry); 236 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 237 continue; 238 if (cpsw_ale_get_mcast(ale_entry)) 239 continue; 240 type = cpsw_ale_get_ucast_type(ale_entry); 241 if (type != ALE_UCAST_PERSISTANT && 242 type != ALE_UCAST_OUI) 243 return idx; 244 } 245 return -ENOENT; 246 } 247 248 static void cpsw_ale_flush_mcast(struct cpsw_ale *ale, u32 *ale_entry, 249 int port_mask) 250 { 251 int mask; 252 253 mask = cpsw_ale_get_port_mask(ale_entry, 254 ale->port_mask_bits); 255 if ((mask & port_mask) == 0) 256 return; /* ports dont intersect, not interested */ 257 mask &= ~port_mask; 258 259 /* free if only remaining port is host port */ 260 if (mask) 261 cpsw_ale_set_port_mask(ale_entry, mask, 262 ale->port_mask_bits); 263 else 264 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 265 } 266 267 int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid) 268 { 269 u32 ale_entry[ALE_ENTRY_WORDS]; 270 int ret, idx; 271 272 for (idx = 0; idx < ale->params.ale_entries; idx++) { 273 cpsw_ale_read(ale, idx, ale_entry); 274 ret = cpsw_ale_get_entry_type(ale_entry); 275 if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR) 276 continue; 277 278 /* if vid passed is -1 then remove all multicast entry from 279 * the table irrespective of vlan id, if a valid vlan id is 280 * passed then remove only multicast added to that vlan id. 281 * if vlan id doesn't match then move on to next entry. 282 */ 283 if (vid != -1 && cpsw_ale_get_vlan_id(ale_entry) != vid) 284 continue; 285 286 if (cpsw_ale_get_mcast(ale_entry)) { 287 u8 addr[6]; 288 289 if (cpsw_ale_get_super(ale_entry)) 290 continue; 291 292 cpsw_ale_get_addr(ale_entry, addr); 293 if (!is_broadcast_ether_addr(addr)) 294 cpsw_ale_flush_mcast(ale, ale_entry, port_mask); 295 } 296 297 cpsw_ale_write(ale, idx, ale_entry); 298 } 299 return 0; 300 } 301 302 static inline void cpsw_ale_set_vlan_entry_type(u32 *ale_entry, 303 int flags, u16 vid) 304 { 305 if (flags & ALE_VLAN) { 306 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN_ADDR); 307 cpsw_ale_set_vlan_id(ale_entry, vid); 308 } else { 309 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR); 310 } 311 } 312 313 int cpsw_ale_add_ucast(struct cpsw_ale *ale, const u8 *addr, int port, 314 int flags, u16 vid) 315 { 316 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 317 int idx; 318 319 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid); 320 321 cpsw_ale_set_addr(ale_entry, addr); 322 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT); 323 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0); 324 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0); 325 cpsw_ale_set_port_num(ale_entry, port, ale->port_num_bits); 326 327 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0); 328 if (idx < 0) 329 idx = cpsw_ale_match_free(ale); 330 if (idx < 0) 331 idx = cpsw_ale_find_ageable(ale); 332 if (idx < 0) 333 return -ENOMEM; 334 335 cpsw_ale_write(ale, idx, ale_entry); 336 return 0; 337 } 338 339 int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port, 340 int flags, u16 vid) 341 { 342 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 343 int idx; 344 345 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0); 346 if (idx < 0) 347 return -ENOENT; 348 349 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 350 cpsw_ale_write(ale, idx, ale_entry); 351 return 0; 352 } 353 354 int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, 355 int flags, u16 vid, int mcast_state) 356 { 357 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 358 int idx, mask; 359 360 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0); 361 if (idx >= 0) 362 cpsw_ale_read(ale, idx, ale_entry); 363 364 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid); 365 366 cpsw_ale_set_addr(ale_entry, addr); 367 cpsw_ale_set_super(ale_entry, (flags & ALE_SUPER) ? 1 : 0); 368 cpsw_ale_set_mcast_state(ale_entry, mcast_state); 369 370 mask = cpsw_ale_get_port_mask(ale_entry, 371 ale->port_mask_bits); 372 port_mask |= mask; 373 cpsw_ale_set_port_mask(ale_entry, port_mask, 374 ale->port_mask_bits); 375 376 if (idx < 0) 377 idx = cpsw_ale_match_free(ale); 378 if (idx < 0) 379 idx = cpsw_ale_find_ageable(ale); 380 if (idx < 0) 381 return -ENOMEM; 382 383 cpsw_ale_write(ale, idx, ale_entry); 384 return 0; 385 } 386 387 int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, 388 int flags, u16 vid) 389 { 390 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 391 int mcast_members = 0; 392 int idx; 393 394 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0); 395 if (idx < 0) 396 return -ENOENT; 397 398 cpsw_ale_read(ale, idx, ale_entry); 399 400 if (port_mask) { 401 mcast_members = cpsw_ale_get_port_mask(ale_entry, 402 ale->port_mask_bits); 403 mcast_members &= ~port_mask; 404 } 405 406 if (mcast_members) 407 cpsw_ale_set_port_mask(ale_entry, mcast_members, 408 ale->port_mask_bits); 409 else 410 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 411 412 cpsw_ale_write(ale, idx, ale_entry); 413 return 0; 414 } 415 416 /* ALE NetCP NU switch specific vlan functions */ 417 static void cpsw_ale_set_vlan_mcast(struct cpsw_ale *ale, u32 *ale_entry, 418 int reg_mcast, int unreg_mcast) 419 { 420 int idx; 421 422 /* Set VLAN registered multicast flood mask */ 423 idx = cpsw_ale_get_vlan_reg_mcast_idx(ale_entry); 424 writel(reg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); 425 426 /* Set VLAN unregistered multicast flood mask */ 427 idx = cpsw_ale_get_vlan_unreg_mcast_idx(ale_entry); 428 writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); 429 } 430 431 static void cpsw_ale_set_vlan_untag(struct cpsw_ale *ale, u32 *ale_entry, 432 u16 vid, int untag_mask) 433 { 434 cpsw_ale_set_vlan_untag_force(ale_entry, 435 untag_mask, ale->vlan_field_bits); 436 if (untag_mask & ALE_PORT_HOST) 437 bitmap_set(ale->p0_untag_vid_mask, vid, 1); 438 else 439 bitmap_clear(ale->p0_untag_vid_mask, vid, 1); 440 } 441 442 int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port_mask, int untag, 443 int reg_mcast, int unreg_mcast) 444 { 445 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 446 int idx; 447 448 idx = cpsw_ale_match_vlan(ale, vid); 449 if (idx >= 0) 450 cpsw_ale_read(ale, idx, ale_entry); 451 452 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN); 453 cpsw_ale_set_vlan_id(ale_entry, vid); 454 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag); 455 456 if (!ale->params.nu_switch_ale) { 457 cpsw_ale_set_vlan_reg_mcast(ale_entry, reg_mcast, 458 ale->vlan_field_bits); 459 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast, 460 ale->vlan_field_bits); 461 } else { 462 cpsw_ale_set_vlan_unreg_mcast_idx(ale_entry, 463 NU_VLAN_UNREG_MCAST_IDX); 464 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast, unreg_mcast); 465 } 466 cpsw_ale_set_vlan_member_list(ale_entry, port_mask, 467 ale->vlan_field_bits); 468 469 if (idx < 0) 470 idx = cpsw_ale_match_free(ale); 471 if (idx < 0) 472 idx = cpsw_ale_find_ageable(ale); 473 if (idx < 0) 474 return -ENOMEM; 475 476 cpsw_ale_write(ale, idx, ale_entry); 477 return 0; 478 } 479 480 static void cpsw_ale_del_vlan_modify(struct cpsw_ale *ale, u32 *ale_entry, 481 u16 vid, int port_mask) 482 { 483 int reg_mcast, unreg_mcast; 484 int members, untag; 485 486 members = cpsw_ale_get_vlan_member_list(ale_entry, 487 ale->vlan_field_bits); 488 members &= ~port_mask; 489 if (!members) { 490 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 491 return; 492 } 493 494 untag = cpsw_ale_get_vlan_untag_force(ale_entry, 495 ale->vlan_field_bits); 496 reg_mcast = cpsw_ale_get_vlan_reg_mcast(ale_entry, 497 ale->vlan_field_bits); 498 unreg_mcast = cpsw_ale_get_vlan_unreg_mcast(ale_entry, 499 ale->vlan_field_bits); 500 untag &= members; 501 reg_mcast &= members; 502 unreg_mcast &= members; 503 504 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag); 505 506 if (!ale->params.nu_switch_ale) { 507 cpsw_ale_set_vlan_reg_mcast(ale_entry, reg_mcast, 508 ale->vlan_field_bits); 509 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast, 510 ale->vlan_field_bits); 511 } else { 512 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast, 513 unreg_mcast); 514 } 515 cpsw_ale_set_vlan_member_list(ale_entry, members, 516 ale->vlan_field_bits); 517 } 518 519 int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask) 520 { 521 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 522 int idx; 523 524 idx = cpsw_ale_match_vlan(ale, vid); 525 if (idx < 0) 526 return -ENOENT; 527 528 cpsw_ale_read(ale, idx, ale_entry); 529 530 if (port_mask) { 531 cpsw_ale_del_vlan_modify(ale, ale_entry, vid, port_mask); 532 } else { 533 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, 0); 534 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 535 } 536 537 cpsw_ale_write(ale, idx, ale_entry); 538 539 return 0; 540 } 541 542 int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask, 543 int untag_mask, int reg_mask, int unreg_mask) 544 { 545 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 546 int reg_mcast_members, unreg_mcast_members; 547 int vlan_members, untag_members; 548 int idx, ret = 0; 549 550 idx = cpsw_ale_match_vlan(ale, vid); 551 if (idx >= 0) 552 cpsw_ale_read(ale, idx, ale_entry); 553 554 vlan_members = cpsw_ale_get_vlan_member_list(ale_entry, 555 ale->vlan_field_bits); 556 reg_mcast_members = cpsw_ale_get_vlan_reg_mcast(ale_entry, 557 ale->vlan_field_bits); 558 unreg_mcast_members = 559 cpsw_ale_get_vlan_unreg_mcast(ale_entry, 560 ale->vlan_field_bits); 561 untag_members = cpsw_ale_get_vlan_untag_force(ale_entry, 562 ale->vlan_field_bits); 563 564 vlan_members |= port_mask; 565 untag_members = (untag_members & ~port_mask) | untag_mask; 566 reg_mcast_members = (reg_mcast_members & ~port_mask) | reg_mask; 567 unreg_mcast_members = (unreg_mcast_members & ~port_mask) | unreg_mask; 568 569 ret = cpsw_ale_add_vlan(ale, vid, vlan_members, untag_members, 570 reg_mcast_members, unreg_mcast_members); 571 if (ret) { 572 dev_err(ale->params.dev, "Unable to add vlan\n"); 573 return ret; 574 } 575 dev_dbg(ale->params.dev, "port mask 0x%x untag 0x%x\n", vlan_members, 576 untag_mask); 577 578 return ret; 579 } 580 581 void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask, 582 bool add) 583 { 584 u32 ale_entry[ALE_ENTRY_WORDS]; 585 int unreg_members = 0; 586 int type, idx; 587 588 for (idx = 0; idx < ale->params.ale_entries; idx++) { 589 cpsw_ale_read(ale, idx, ale_entry); 590 type = cpsw_ale_get_entry_type(ale_entry); 591 if (type != ALE_TYPE_VLAN) 592 continue; 593 594 unreg_members = 595 cpsw_ale_get_vlan_unreg_mcast(ale_entry, 596 ale->vlan_field_bits); 597 if (add) 598 unreg_members |= unreg_mcast_mask; 599 else 600 unreg_members &= ~unreg_mcast_mask; 601 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_members, 602 ale->vlan_field_bits); 603 cpsw_ale_write(ale, idx, ale_entry); 604 } 605 } 606 607 static void cpsw_ale_vlan_set_unreg_mcast(struct cpsw_ale *ale, u32 *ale_entry, 608 int allmulti) 609 { 610 int unreg_mcast; 611 612 unreg_mcast = 613 cpsw_ale_get_vlan_unreg_mcast(ale_entry, 614 ale->vlan_field_bits); 615 if (allmulti) 616 unreg_mcast |= ALE_PORT_HOST; 617 else 618 unreg_mcast &= ~ALE_PORT_HOST; 619 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast, 620 ale->vlan_field_bits); 621 } 622 623 static void 624 cpsw_ale_vlan_set_unreg_mcast_idx(struct cpsw_ale *ale, u32 *ale_entry, 625 int allmulti) 626 { 627 int unreg_mcast; 628 int idx; 629 630 idx = cpsw_ale_get_vlan_unreg_mcast_idx(ale_entry); 631 632 unreg_mcast = readl(ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); 633 634 if (allmulti) 635 unreg_mcast |= ALE_PORT_HOST; 636 else 637 unreg_mcast &= ~ALE_PORT_HOST; 638 639 writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); 640 } 641 642 void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti, int port) 643 { 644 u32 ale_entry[ALE_ENTRY_WORDS]; 645 int type, idx; 646 647 for (idx = 0; idx < ale->params.ale_entries; idx++) { 648 int vlan_members; 649 650 cpsw_ale_read(ale, idx, ale_entry); 651 type = cpsw_ale_get_entry_type(ale_entry); 652 if (type != ALE_TYPE_VLAN) 653 continue; 654 vlan_members = 655 cpsw_ale_get_vlan_member_list(ale_entry, 656 ale->vlan_field_bits); 657 658 if (port != -1 && !(vlan_members & BIT(port))) 659 continue; 660 661 if (!ale->params.nu_switch_ale) 662 cpsw_ale_vlan_set_unreg_mcast(ale, ale_entry, allmulti); 663 else 664 cpsw_ale_vlan_set_unreg_mcast_idx(ale, ale_entry, 665 allmulti); 666 667 cpsw_ale_write(ale, idx, ale_entry); 668 } 669 } 670 671 struct ale_control_info { 672 const char *name; 673 int offset, port_offset; 674 int shift, port_shift; 675 int bits; 676 }; 677 678 static struct ale_control_info ale_controls[ALE_NUM_CONTROLS] = { 679 [ALE_ENABLE] = { 680 .name = "enable", 681 .offset = ALE_CONTROL, 682 .port_offset = 0, 683 .shift = 31, 684 .port_shift = 0, 685 .bits = 1, 686 }, 687 [ALE_CLEAR] = { 688 .name = "clear", 689 .offset = ALE_CONTROL, 690 .port_offset = 0, 691 .shift = 30, 692 .port_shift = 0, 693 .bits = 1, 694 }, 695 [ALE_AGEOUT] = { 696 .name = "ageout", 697 .offset = ALE_CONTROL, 698 .port_offset = 0, 699 .shift = 29, 700 .port_shift = 0, 701 .bits = 1, 702 }, 703 [ALE_P0_UNI_FLOOD] = { 704 .name = "port0_unicast_flood", 705 .offset = ALE_CONTROL, 706 .port_offset = 0, 707 .shift = 8, 708 .port_shift = 0, 709 .bits = 1, 710 }, 711 [ALE_VLAN_NOLEARN] = { 712 .name = "vlan_nolearn", 713 .offset = ALE_CONTROL, 714 .port_offset = 0, 715 .shift = 7, 716 .port_shift = 0, 717 .bits = 1, 718 }, 719 [ALE_NO_PORT_VLAN] = { 720 .name = "no_port_vlan", 721 .offset = ALE_CONTROL, 722 .port_offset = 0, 723 .shift = 6, 724 .port_shift = 0, 725 .bits = 1, 726 }, 727 [ALE_OUI_DENY] = { 728 .name = "oui_deny", 729 .offset = ALE_CONTROL, 730 .port_offset = 0, 731 .shift = 5, 732 .port_shift = 0, 733 .bits = 1, 734 }, 735 [ALE_BYPASS] = { 736 .name = "bypass", 737 .offset = ALE_CONTROL, 738 .port_offset = 0, 739 .shift = 4, 740 .port_shift = 0, 741 .bits = 1, 742 }, 743 [ALE_RATE_LIMIT_TX] = { 744 .name = "rate_limit_tx", 745 .offset = ALE_CONTROL, 746 .port_offset = 0, 747 .shift = 3, 748 .port_shift = 0, 749 .bits = 1, 750 }, 751 [ALE_VLAN_AWARE] = { 752 .name = "vlan_aware", 753 .offset = ALE_CONTROL, 754 .port_offset = 0, 755 .shift = 2, 756 .port_shift = 0, 757 .bits = 1, 758 }, 759 [ALE_AUTH_ENABLE] = { 760 .name = "auth_enable", 761 .offset = ALE_CONTROL, 762 .port_offset = 0, 763 .shift = 1, 764 .port_shift = 0, 765 .bits = 1, 766 }, 767 [ALE_RATE_LIMIT] = { 768 .name = "rate_limit", 769 .offset = ALE_CONTROL, 770 .port_offset = 0, 771 .shift = 0, 772 .port_shift = 0, 773 .bits = 1, 774 }, 775 [ALE_PORT_STATE] = { 776 .name = "port_state", 777 .offset = ALE_PORTCTL, 778 .port_offset = 4, 779 .shift = 0, 780 .port_shift = 0, 781 .bits = 2, 782 }, 783 [ALE_PORT_DROP_UNTAGGED] = { 784 .name = "drop_untagged", 785 .offset = ALE_PORTCTL, 786 .port_offset = 4, 787 .shift = 2, 788 .port_shift = 0, 789 .bits = 1, 790 }, 791 [ALE_PORT_DROP_UNKNOWN_VLAN] = { 792 .name = "drop_unknown", 793 .offset = ALE_PORTCTL, 794 .port_offset = 4, 795 .shift = 3, 796 .port_shift = 0, 797 .bits = 1, 798 }, 799 [ALE_PORT_NOLEARN] = { 800 .name = "nolearn", 801 .offset = ALE_PORTCTL, 802 .port_offset = 4, 803 .shift = 4, 804 .port_shift = 0, 805 .bits = 1, 806 }, 807 [ALE_PORT_NO_SA_UPDATE] = { 808 .name = "no_source_update", 809 .offset = ALE_PORTCTL, 810 .port_offset = 4, 811 .shift = 5, 812 .port_shift = 0, 813 .bits = 1, 814 }, 815 [ALE_PORT_MACONLY] = { 816 .name = "mac_only_port_mode", 817 .offset = ALE_PORTCTL, 818 .port_offset = 4, 819 .shift = 11, 820 .port_shift = 0, 821 .bits = 1, 822 }, 823 [ALE_PORT_MACONLY_CAF] = { 824 .name = "mac_only_port_caf", 825 .offset = ALE_PORTCTL, 826 .port_offset = 4, 827 .shift = 13, 828 .port_shift = 0, 829 .bits = 1, 830 }, 831 [ALE_PORT_MCAST_LIMIT] = { 832 .name = "mcast_limit", 833 .offset = ALE_PORTCTL, 834 .port_offset = 4, 835 .shift = 16, 836 .port_shift = 0, 837 .bits = 8, 838 }, 839 [ALE_PORT_BCAST_LIMIT] = { 840 .name = "bcast_limit", 841 .offset = ALE_PORTCTL, 842 .port_offset = 4, 843 .shift = 24, 844 .port_shift = 0, 845 .bits = 8, 846 }, 847 [ALE_PORT_UNKNOWN_VLAN_MEMBER] = { 848 .name = "unknown_vlan_member", 849 .offset = ALE_UNKNOWNVLAN, 850 .port_offset = 0, 851 .shift = 0, 852 .port_shift = 0, 853 .bits = 6, 854 }, 855 [ALE_PORT_UNKNOWN_MCAST_FLOOD] = { 856 .name = "unknown_mcast_flood", 857 .offset = ALE_UNKNOWNVLAN, 858 .port_offset = 0, 859 .shift = 8, 860 .port_shift = 0, 861 .bits = 6, 862 }, 863 [ALE_PORT_UNKNOWN_REG_MCAST_FLOOD] = { 864 .name = "unknown_reg_flood", 865 .offset = ALE_UNKNOWNVLAN, 866 .port_offset = 0, 867 .shift = 16, 868 .port_shift = 0, 869 .bits = 6, 870 }, 871 [ALE_PORT_UNTAGGED_EGRESS] = { 872 .name = "untagged_egress", 873 .offset = ALE_UNKNOWNVLAN, 874 .port_offset = 0, 875 .shift = 24, 876 .port_shift = 0, 877 .bits = 6, 878 }, 879 [ALE_DEFAULT_THREAD_ID] = { 880 .name = "default_thread_id", 881 .offset = AM65_CPSW_ALE_THREAD_DEF_REG, 882 .port_offset = 0, 883 .shift = 0, 884 .port_shift = 0, 885 .bits = 6, 886 }, 887 [ALE_DEFAULT_THREAD_ENABLE] = { 888 .name = "default_thread_id_enable", 889 .offset = AM65_CPSW_ALE_THREAD_DEF_REG, 890 .port_offset = 0, 891 .shift = 15, 892 .port_shift = 0, 893 .bits = 1, 894 }, 895 }; 896 897 int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control, 898 int value) 899 { 900 const struct ale_control_info *info; 901 int offset, shift; 902 u32 tmp, mask; 903 904 if (control < 0 || control >= ARRAY_SIZE(ale_controls)) 905 return -EINVAL; 906 907 info = &ale_controls[control]; 908 if (info->port_offset == 0 && info->port_shift == 0) 909 port = 0; /* global, port is a dont care */ 910 911 if (port < 0 || port >= ale->params.ale_ports) 912 return -EINVAL; 913 914 mask = BITMASK(info->bits); 915 if (value & ~mask) 916 return -EINVAL; 917 918 offset = info->offset + (port * info->port_offset); 919 shift = info->shift + (port * info->port_shift); 920 921 tmp = readl_relaxed(ale->params.ale_regs + offset); 922 tmp = (tmp & ~(mask << shift)) | (value << shift); 923 writel_relaxed(tmp, ale->params.ale_regs + offset); 924 925 return 0; 926 } 927 928 int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control) 929 { 930 const struct ale_control_info *info; 931 int offset, shift; 932 u32 tmp; 933 934 if (control < 0 || control >= ARRAY_SIZE(ale_controls)) 935 return -EINVAL; 936 937 info = &ale_controls[control]; 938 if (info->port_offset == 0 && info->port_shift == 0) 939 port = 0; /* global, port is a dont care */ 940 941 if (port < 0 || port >= ale->params.ale_ports) 942 return -EINVAL; 943 944 offset = info->offset + (port * info->port_offset); 945 shift = info->shift + (port * info->port_shift); 946 947 tmp = readl_relaxed(ale->params.ale_regs + offset) >> shift; 948 return tmp & BITMASK(info->bits); 949 } 950 951 static void cpsw_ale_timer(struct timer_list *t) 952 { 953 struct cpsw_ale *ale = from_timer(ale, t, timer); 954 955 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 956 957 if (ale->ageout) { 958 ale->timer.expires = jiffies + ale->ageout; 959 add_timer(&ale->timer); 960 } 961 } 962 963 void cpsw_ale_start(struct cpsw_ale *ale) 964 { 965 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 1); 966 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1); 967 968 timer_setup(&ale->timer, cpsw_ale_timer, 0); 969 if (ale->ageout) { 970 ale->timer.expires = jiffies + ale->ageout; 971 add_timer(&ale->timer); 972 } 973 } 974 975 void cpsw_ale_stop(struct cpsw_ale *ale) 976 { 977 del_timer_sync(&ale->timer); 978 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1); 979 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0); 980 } 981 982 struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) 983 { 984 struct cpsw_ale *ale; 985 u32 rev, ale_entries; 986 987 ale = devm_kzalloc(params->dev, sizeof(*ale), GFP_KERNEL); 988 if (!ale) 989 return ERR_PTR(-ENOMEM); 990 991 ale->p0_untag_vid_mask = 992 devm_kmalloc_array(params->dev, BITS_TO_LONGS(VLAN_N_VID), 993 sizeof(unsigned long), 994 GFP_KERNEL); 995 if (!ale->p0_untag_vid_mask) 996 return ERR_PTR(-ENOMEM); 997 998 ale->params = *params; 999 ale->ageout = ale->params.ale_ageout * HZ; 1000 1001 rev = readl_relaxed(ale->params.ale_regs + ALE_IDVER); 1002 if (!ale->params.major_ver_mask) 1003 ale->params.major_ver_mask = 0xff; 1004 ale->version = 1005 (ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask) << 8) | 1006 ALE_VERSION_MINOR(rev); 1007 dev_info(ale->params.dev, "initialized cpsw ale version %d.%d\n", 1008 ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask), 1009 ALE_VERSION_MINOR(rev)); 1010 1011 if (!ale->params.ale_entries) { 1012 ale_entries = 1013 readl_relaxed(ale->params.ale_regs + ALE_STATUS) & 1014 ALE_STATUS_SIZE_MASK; 1015 /* ALE available on newer NetCP switches has introduced 1016 * a register, ALE_STATUS, to indicate the size of ALE 1017 * table which shows the size as a multiple of 1024 entries. 1018 * For these, params.ale_entries will be set to zero. So 1019 * read the register and update the value of ale_entries. 1020 * ALE table on NetCP lite, is much smaller and is indicated 1021 * by a value of zero in ALE_STATUS. So use a default value 1022 * of ALE_TABLE_SIZE_DEFAULT for this. Caller is expected 1023 * to set the value of ale_entries for all other versions 1024 * of ALE. 1025 */ 1026 if (!ale_entries) 1027 ale_entries = ALE_TABLE_SIZE_DEFAULT; 1028 else 1029 ale_entries *= ALE_TABLE_SIZE_MULTIPLIER; 1030 ale->params.ale_entries = ale_entries; 1031 } 1032 dev_info(ale->params.dev, 1033 "ALE Table size %ld\n", ale->params.ale_entries); 1034 1035 /* set default bits for existing h/w */ 1036 ale->port_mask_bits = ale->params.ale_ports; 1037 ale->port_num_bits = order_base_2(ale->params.ale_ports); 1038 ale->vlan_field_bits = ale->params.ale_ports; 1039 1040 /* Set defaults override for ALE on NetCP NU switch and for version 1041 * 1R3 1042 */ 1043 if (ale->params.nu_switch_ale) { 1044 /* Separate registers for unknown vlan configuration. 1045 * Also there are N bits, where N is number of ale 1046 * ports and shift value should be 0 1047 */ 1048 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].bits = 1049 ale->params.ale_ports; 1050 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].offset = 1051 ALE_UNKNOWNVLAN_MEMBER; 1052 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].bits = 1053 ale->params.ale_ports; 1054 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].shift = 0; 1055 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].offset = 1056 ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD; 1057 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].bits = 1058 ale->params.ale_ports; 1059 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].shift = 0; 1060 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].offset = 1061 ALE_UNKNOWNVLAN_REG_MCAST_FLOOD; 1062 ale_controls[ALE_PORT_UNTAGGED_EGRESS].bits = 1063 ale->params.ale_ports; 1064 ale_controls[ALE_PORT_UNTAGGED_EGRESS].shift = 0; 1065 ale_controls[ALE_PORT_UNTAGGED_EGRESS].offset = 1066 ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS; 1067 } 1068 1069 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1); 1070 return ale; 1071 } 1072 1073 void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data) 1074 { 1075 int i; 1076 1077 for (i = 0; i < ale->params.ale_entries; i++) { 1078 cpsw_ale_read(ale, i, data); 1079 data += ALE_ENTRY_WORDS; 1080 } 1081 } 1082