1 /* 2 * Texas Instruments Ethernet Switch Driver 3 * 4 * Copyright (C) 2012 Texas Instruments 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/io.h> 18 #include <linux/clk.h> 19 #include <linux/timer.h> 20 #include <linux/module.h> 21 #include <linux/platform_device.h> 22 #include <linux/irqreturn.h> 23 #include <linux/interrupt.h> 24 #include <linux/if_ether.h> 25 #include <linux/etherdevice.h> 26 #include <linux/netdevice.h> 27 #include <linux/net_tstamp.h> 28 #include <linux/phy.h> 29 #include <linux/workqueue.h> 30 #include <linux/delay.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/of.h> 33 #include <linux/of_net.h> 34 #include <linux/of_device.h> 35 #include <linux/if_vlan.h> 36 37 #include <linux/pinctrl/consumer.h> 38 39 #include "cpsw.h" 40 #include "cpsw_ale.h" 41 #include "cpts.h" 42 #include "davinci_cpdma.h" 43 44 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 45 NETIF_MSG_DRV | NETIF_MSG_LINK | \ 46 NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 47 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 48 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 49 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 50 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 51 NETIF_MSG_RX_STATUS) 52 53 #define cpsw_info(priv, type, format, ...) \ 54 do { \ 55 if (netif_msg_##type(priv) && net_ratelimit()) \ 56 dev_info(priv->dev, format, ## __VA_ARGS__); \ 57 } while (0) 58 59 #define cpsw_err(priv, type, format, ...) \ 60 do { \ 61 if (netif_msg_##type(priv) && net_ratelimit()) \ 62 dev_err(priv->dev, format, ## __VA_ARGS__); \ 63 } while (0) 64 65 #define cpsw_dbg(priv, type, format, ...) \ 66 do { \ 67 if (netif_msg_##type(priv) && net_ratelimit()) \ 68 dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 69 } while (0) 70 71 #define cpsw_notice(priv, type, format, ...) \ 72 do { \ 73 if (netif_msg_##type(priv) && net_ratelimit()) \ 74 dev_notice(priv->dev, format, ## __VA_ARGS__); \ 75 } while (0) 76 77 #define ALE_ALL_PORTS 0x7 78 79 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 80 #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 81 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 82 83 #define CPSW_VERSION_1 0x19010a 84 #define CPSW_VERSION_2 0x19010c 85 #define CPSW_VERSION_3 0x19010f 86 #define CPSW_VERSION_4 0x190112 87 88 #define HOST_PORT_NUM 0 89 #define SLIVER_SIZE 0x40 90 91 #define CPSW1_HOST_PORT_OFFSET 0x028 92 #define CPSW1_SLAVE_OFFSET 0x050 93 #define CPSW1_SLAVE_SIZE 0x040 94 #define CPSW1_CPDMA_OFFSET 0x100 95 #define CPSW1_STATERAM_OFFSET 0x200 96 #define CPSW1_HW_STATS 0x400 97 #define CPSW1_CPTS_OFFSET 0x500 98 #define CPSW1_ALE_OFFSET 0x600 99 #define CPSW1_SLIVER_OFFSET 0x700 100 101 #define CPSW2_HOST_PORT_OFFSET 0x108 102 #define CPSW2_SLAVE_OFFSET 0x200 103 #define CPSW2_SLAVE_SIZE 0x100 104 #define CPSW2_CPDMA_OFFSET 0x800 105 #define CPSW2_HW_STATS 0x900 106 #define CPSW2_STATERAM_OFFSET 0xa00 107 #define CPSW2_CPTS_OFFSET 0xc00 108 #define CPSW2_ALE_OFFSET 0xd00 109 #define CPSW2_SLIVER_OFFSET 0xd80 110 #define CPSW2_BD_OFFSET 0x2000 111 112 #define CPDMA_RXTHRESH 0x0c0 113 #define CPDMA_RXFREE 0x0e0 114 #define CPDMA_TXHDP 0x00 115 #define CPDMA_RXHDP 0x20 116 #define CPDMA_TXCP 0x40 117 #define CPDMA_RXCP 0x60 118 119 #define CPSW_POLL_WEIGHT 64 120 #define CPSW_MIN_PACKET_SIZE 60 121 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 122 123 #define RX_PRIORITY_MAPPING 0x76543210 124 #define TX_PRIORITY_MAPPING 0x33221100 125 #define CPDMA_TX_PRIORITY_MAP 0x76543210 126 127 #define CPSW_VLAN_AWARE BIT(1) 128 #define CPSW_ALE_VLAN_AWARE 1 129 130 #define CPSW_FIFO_NORMAL_MODE (0 << 15) 131 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 15) 132 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15) 133 134 #define CPSW_INTPACEEN (0x3f << 16) 135 #define CPSW_INTPRESCALE_MASK (0x7FF << 0) 136 #define CPSW_CMINTMAX_CNT 63 137 #define CPSW_CMINTMIN_CNT 2 138 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) 139 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) 140 141 #define cpsw_enable_irq(priv) \ 142 do { \ 143 u32 i; \ 144 for (i = 0; i < priv->num_irqs; i++) \ 145 enable_irq(priv->irqs_table[i]); \ 146 } while (0); 147 #define cpsw_disable_irq(priv) \ 148 do { \ 149 u32 i; \ 150 for (i = 0; i < priv->num_irqs; i++) \ 151 disable_irq_nosync(priv->irqs_table[i]); \ 152 } while (0); 153 154 #define cpsw_slave_index(priv) \ 155 ((priv->data.dual_emac) ? priv->emac_port : \ 156 priv->data.active_slave) 157 158 static int debug_level; 159 module_param(debug_level, int, 0); 160 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 161 162 static int ale_ageout = 10; 163 module_param(ale_ageout, int, 0); 164 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 165 166 static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 167 module_param(rx_packet_max, int, 0); 168 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 169 170 struct cpsw_wr_regs { 171 u32 id_ver; 172 u32 soft_reset; 173 u32 control; 174 u32 int_control; 175 u32 rx_thresh_en; 176 u32 rx_en; 177 u32 tx_en; 178 u32 misc_en; 179 u32 mem_allign1[8]; 180 u32 rx_thresh_stat; 181 u32 rx_stat; 182 u32 tx_stat; 183 u32 misc_stat; 184 u32 mem_allign2[8]; 185 u32 rx_imax; 186 u32 tx_imax; 187 188 }; 189 190 struct cpsw_ss_regs { 191 u32 id_ver; 192 u32 control; 193 u32 soft_reset; 194 u32 stat_port_en; 195 u32 ptype; 196 u32 soft_idle; 197 u32 thru_rate; 198 u32 gap_thresh; 199 u32 tx_start_wds; 200 u32 flow_control; 201 u32 vlan_ltype; 202 u32 ts_ltype; 203 u32 dlr_ltype; 204 }; 205 206 /* CPSW_PORT_V1 */ 207 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 208 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 209 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 210 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 211 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 212 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 213 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 214 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 215 216 /* CPSW_PORT_V2 */ 217 #define CPSW2_CONTROL 0x00 /* Control Register */ 218 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 219 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 220 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 221 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 222 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 223 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 224 225 /* CPSW_PORT_V1 and V2 */ 226 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 227 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 228 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 229 230 /* CPSW_PORT_V2 only */ 231 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 232 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 233 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 234 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 235 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 236 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 237 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 238 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 239 240 /* Bit definitions for the CPSW2_CONTROL register */ 241 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 242 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 243 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 244 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 245 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 246 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 247 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 248 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 249 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 250 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 251 #define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */ 252 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 253 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 254 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 255 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 256 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 257 258 #define CTRL_TS_BITS \ 259 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \ 260 TS_ANNEX_D_EN | TS_LTYPE1_EN) 261 262 #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN) 263 #define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN) 264 #define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN) 265 266 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 267 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 268 #define TS_SEQ_ID_OFFSET_MASK (0x3f) 269 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 270 #define TS_MSG_TYPE_EN_MASK (0xffff) 271 272 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 273 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 274 275 /* Bit definitions for the CPSW1_TS_CTL register */ 276 #define CPSW_V1_TS_RX_EN BIT(0) 277 #define CPSW_V1_TS_TX_EN BIT(4) 278 #define CPSW_V1_MSG_TYPE_OFS 16 279 280 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 281 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 282 283 struct cpsw_host_regs { 284 u32 max_blks; 285 u32 blk_cnt; 286 u32 tx_in_ctl; 287 u32 port_vlan; 288 u32 tx_pri_map; 289 u32 cpdma_tx_pri_map; 290 u32 cpdma_rx_chan_map; 291 }; 292 293 struct cpsw_sliver_regs { 294 u32 id_ver; 295 u32 mac_control; 296 u32 mac_status; 297 u32 soft_reset; 298 u32 rx_maxlen; 299 u32 __reserved_0; 300 u32 rx_pause; 301 u32 tx_pause; 302 u32 __reserved_1; 303 u32 rx_pri_map; 304 }; 305 306 struct cpsw_hw_stats { 307 u32 rxgoodframes; 308 u32 rxbroadcastframes; 309 u32 rxmulticastframes; 310 u32 rxpauseframes; 311 u32 rxcrcerrors; 312 u32 rxaligncodeerrors; 313 u32 rxoversizedframes; 314 u32 rxjabberframes; 315 u32 rxundersizedframes; 316 u32 rxfragments; 317 u32 __pad_0[2]; 318 u32 rxoctets; 319 u32 txgoodframes; 320 u32 txbroadcastframes; 321 u32 txmulticastframes; 322 u32 txpauseframes; 323 u32 txdeferredframes; 324 u32 txcollisionframes; 325 u32 txsinglecollframes; 326 u32 txmultcollframes; 327 u32 txexcessivecollisions; 328 u32 txlatecollisions; 329 u32 txunderrun; 330 u32 txcarriersenseerrors; 331 u32 txoctets; 332 u32 octetframes64; 333 u32 octetframes65t127; 334 u32 octetframes128t255; 335 u32 octetframes256t511; 336 u32 octetframes512t1023; 337 u32 octetframes1024tup; 338 u32 netoctets; 339 u32 rxsofoverruns; 340 u32 rxmofoverruns; 341 u32 rxdmaoverruns; 342 }; 343 344 struct cpsw_slave { 345 void __iomem *regs; 346 struct cpsw_sliver_regs __iomem *sliver; 347 int slave_num; 348 u32 mac_control; 349 struct cpsw_slave_data *data; 350 struct phy_device *phy; 351 struct net_device *ndev; 352 u32 port_vlan; 353 u32 open_stat; 354 }; 355 356 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 357 { 358 return __raw_readl(slave->regs + offset); 359 } 360 361 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 362 { 363 __raw_writel(val, slave->regs + offset); 364 } 365 366 struct cpsw_priv { 367 spinlock_t lock; 368 struct platform_device *pdev; 369 struct net_device *ndev; 370 struct napi_struct napi; 371 struct device *dev; 372 struct cpsw_platform_data data; 373 struct cpsw_ss_regs __iomem *regs; 374 struct cpsw_wr_regs __iomem *wr_regs; 375 u8 __iomem *hw_stats; 376 struct cpsw_host_regs __iomem *host_port_regs; 377 u32 msg_enable; 378 u32 version; 379 u32 coal_intvl; 380 u32 bus_freq_mhz; 381 int rx_packet_max; 382 int host_port; 383 struct clk *clk; 384 u8 mac_addr[ETH_ALEN]; 385 struct cpsw_slave *slaves; 386 struct cpdma_ctlr *dma; 387 struct cpdma_chan *txch, *rxch; 388 struct cpsw_ale *ale; 389 /* snapshot of IRQ numbers */ 390 u32 irqs_table[4]; 391 u32 num_irqs; 392 bool irq_enabled; 393 struct cpts *cpts; 394 u32 emac_port; 395 }; 396 397 struct cpsw_stats { 398 char stat_string[ETH_GSTRING_LEN]; 399 int type; 400 int sizeof_stat; 401 int stat_offset; 402 }; 403 404 enum { 405 CPSW_STATS, 406 CPDMA_RX_STATS, 407 CPDMA_TX_STATS, 408 }; 409 410 #define CPSW_STAT(m) CPSW_STATS, \ 411 sizeof(((struct cpsw_hw_stats *)0)->m), \ 412 offsetof(struct cpsw_hw_stats, m) 413 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ 414 sizeof(((struct cpdma_chan_stats *)0)->m), \ 415 offsetof(struct cpdma_chan_stats, m) 416 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ 417 sizeof(((struct cpdma_chan_stats *)0)->m), \ 418 offsetof(struct cpdma_chan_stats, m) 419 420 static const struct cpsw_stats cpsw_gstrings_stats[] = { 421 { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, 422 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, 423 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, 424 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, 425 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, 426 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, 427 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, 428 { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, 429 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, 430 { "Rx Fragments", CPSW_STAT(rxfragments) }, 431 { "Rx Octets", CPSW_STAT(rxoctets) }, 432 { "Good Tx Frames", CPSW_STAT(txgoodframes) }, 433 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, 434 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, 435 { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, 436 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, 437 { "Collisions", CPSW_STAT(txcollisionframes) }, 438 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, 439 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, 440 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, 441 { "Late Collisions", CPSW_STAT(txlatecollisions) }, 442 { "Tx Underrun", CPSW_STAT(txunderrun) }, 443 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, 444 { "Tx Octets", CPSW_STAT(txoctets) }, 445 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, 446 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, 447 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, 448 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, 449 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, 450 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, 451 { "Net Octets", CPSW_STAT(netoctets) }, 452 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, 453 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, 454 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, 455 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) }, 456 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, 457 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, 458 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) }, 459 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, 460 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, 461 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, 462 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, 463 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, 464 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, 465 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) }, 466 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) }, 467 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, 468 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) }, 469 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) }, 470 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) }, 471 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) }, 472 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) }, 473 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) }, 474 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) }, 475 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) }, 476 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) }, 477 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) }, 478 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) }, 479 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) }, 480 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) }, 481 }; 482 483 #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats) 484 485 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) 486 #define for_each_slave(priv, func, arg...) \ 487 do { \ 488 struct cpsw_slave *slave; \ 489 int n; \ 490 if (priv->data.dual_emac) \ 491 (func)((priv)->slaves + priv->emac_port, ##arg);\ 492 else \ 493 for (n = (priv)->data.slaves, \ 494 slave = (priv)->slaves; \ 495 n; n--) \ 496 (func)(slave++, ##arg); \ 497 } while (0) 498 #define cpsw_get_slave_ndev(priv, __slave_no__) \ 499 (priv->slaves[__slave_no__].ndev) 500 #define cpsw_get_slave_priv(priv, __slave_no__) \ 501 ((priv->slaves[__slave_no__].ndev) ? \ 502 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \ 503 504 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \ 505 do { \ 506 if (!priv->data.dual_emac) \ 507 break; \ 508 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ 509 ndev = cpsw_get_slave_ndev(priv, 0); \ 510 priv = netdev_priv(ndev); \ 511 skb->dev = ndev; \ 512 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ 513 ndev = cpsw_get_slave_ndev(priv, 1); \ 514 priv = netdev_priv(ndev); \ 515 skb->dev = ndev; \ 516 } \ 517 } while (0) 518 #define cpsw_add_mcast(priv, addr) \ 519 do { \ 520 if (priv->data.dual_emac) { \ 521 struct cpsw_slave *slave = priv->slaves + \ 522 priv->emac_port; \ 523 int slave_port = cpsw_get_slave_port(priv, \ 524 slave->slave_num); \ 525 cpsw_ale_add_mcast(priv->ale, addr, \ 526 1 << slave_port | 1 << priv->host_port, \ 527 ALE_VLAN, slave->port_vlan, 0); \ 528 } else { \ 529 cpsw_ale_add_mcast(priv->ale, addr, \ 530 ALE_ALL_PORTS << priv->host_port, \ 531 0, 0, 0); \ 532 } \ 533 } while (0) 534 535 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 536 { 537 if (priv->host_port == 0) 538 return slave_num + 1; 539 else 540 return slave_num; 541 } 542 543 static void cpsw_set_promiscious(struct net_device *ndev, bool enable) 544 { 545 struct cpsw_priv *priv = netdev_priv(ndev); 546 struct cpsw_ale *ale = priv->ale; 547 int i; 548 549 if (priv->data.dual_emac) { 550 bool flag = false; 551 552 /* Enabling promiscuous mode for one interface will be 553 * common for both the interface as the interface shares 554 * the same hardware resource. 555 */ 556 for (i = 0; i < priv->data.slaves; i++) 557 if (priv->slaves[i].ndev->flags & IFF_PROMISC) 558 flag = true; 559 560 if (!enable && flag) { 561 enable = true; 562 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n"); 563 } 564 565 if (enable) { 566 /* Enable Bypass */ 567 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1); 568 569 dev_dbg(&ndev->dev, "promiscuity enabled\n"); 570 } else { 571 /* Disable Bypass */ 572 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0); 573 dev_dbg(&ndev->dev, "promiscuity disabled\n"); 574 } 575 } else { 576 if (enable) { 577 unsigned long timeout = jiffies + HZ; 578 579 /* Disable Learn for all ports */ 580 for (i = 0; i < priv->data.slaves; i++) { 581 cpsw_ale_control_set(ale, i, 582 ALE_PORT_NOLEARN, 1); 583 cpsw_ale_control_set(ale, i, 584 ALE_PORT_NO_SA_UPDATE, 1); 585 } 586 587 /* Clear All Untouched entries */ 588 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 589 do { 590 cpu_relax(); 591 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT)) 592 break; 593 } while (time_after(timeout, jiffies)); 594 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 595 596 /* Clear all mcast from ALE */ 597 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS << 598 priv->host_port); 599 600 /* Flood All Unicast Packets to Host port */ 601 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1); 602 dev_dbg(&ndev->dev, "promiscuity enabled\n"); 603 } else { 604 /* Flood All Unicast Packets to Host port */ 605 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0); 606 607 /* Enable Learn for all ports */ 608 for (i = 0; i < priv->data.slaves; i++) { 609 cpsw_ale_control_set(ale, i, 610 ALE_PORT_NOLEARN, 0); 611 cpsw_ale_control_set(ale, i, 612 ALE_PORT_NO_SA_UPDATE, 0); 613 } 614 dev_dbg(&ndev->dev, "promiscuity disabled\n"); 615 } 616 } 617 } 618 619 static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 620 { 621 struct cpsw_priv *priv = netdev_priv(ndev); 622 623 if (ndev->flags & IFF_PROMISC) { 624 /* Enable promiscuous mode */ 625 cpsw_set_promiscious(ndev, true); 626 return; 627 } else { 628 /* Disable promiscuous mode */ 629 cpsw_set_promiscious(ndev, false); 630 } 631 632 /* Clear all mcast from ALE */ 633 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port); 634 635 if (!netdev_mc_empty(ndev)) { 636 struct netdev_hw_addr *ha; 637 638 /* program multicast address list into ALE register */ 639 netdev_for_each_mc_addr(ha, ndev) { 640 cpsw_add_mcast(priv, (u8 *)ha->addr); 641 } 642 } 643 } 644 645 static void cpsw_intr_enable(struct cpsw_priv *priv) 646 { 647 __raw_writel(0xFF, &priv->wr_regs->tx_en); 648 __raw_writel(0xFF, &priv->wr_regs->rx_en); 649 650 cpdma_ctlr_int_ctrl(priv->dma, true); 651 return; 652 } 653 654 static void cpsw_intr_disable(struct cpsw_priv *priv) 655 { 656 __raw_writel(0, &priv->wr_regs->tx_en); 657 __raw_writel(0, &priv->wr_regs->rx_en); 658 659 cpdma_ctlr_int_ctrl(priv->dma, false); 660 return; 661 } 662 663 static void cpsw_tx_handler(void *token, int len, int status) 664 { 665 struct sk_buff *skb = token; 666 struct net_device *ndev = skb->dev; 667 struct cpsw_priv *priv = netdev_priv(ndev); 668 669 /* Check whether the queue is stopped due to stalled tx dma, if the 670 * queue is stopped then start the queue as we have free desc for tx 671 */ 672 if (unlikely(netif_queue_stopped(ndev))) 673 netif_wake_queue(ndev); 674 cpts_tx_timestamp(priv->cpts, skb); 675 ndev->stats.tx_packets++; 676 ndev->stats.tx_bytes += len; 677 dev_kfree_skb_any(skb); 678 } 679 680 static void cpsw_rx_handler(void *token, int len, int status) 681 { 682 struct sk_buff *skb = token; 683 struct sk_buff *new_skb; 684 struct net_device *ndev = skb->dev; 685 struct cpsw_priv *priv = netdev_priv(ndev); 686 int ret = 0; 687 688 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb); 689 690 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) { 691 /* the interface is going down, skbs are purged */ 692 dev_kfree_skb_any(skb); 693 return; 694 } 695 696 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); 697 if (new_skb) { 698 skb_put(skb, len); 699 cpts_rx_timestamp(priv->cpts, skb); 700 skb->protocol = eth_type_trans(skb, ndev); 701 netif_receive_skb(skb); 702 ndev->stats.rx_bytes += len; 703 ndev->stats.rx_packets++; 704 } else { 705 ndev->stats.rx_dropped++; 706 new_skb = skb; 707 } 708 709 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data, 710 skb_tailroom(new_skb), 0); 711 if (WARN_ON(ret < 0)) 712 dev_kfree_skb_any(new_skb); 713 } 714 715 static irqreturn_t cpsw_interrupt(int irq, void *dev_id) 716 { 717 struct cpsw_priv *priv = dev_id; 718 719 cpsw_intr_disable(priv); 720 if (priv->irq_enabled == true) { 721 cpsw_disable_irq(priv); 722 priv->irq_enabled = false; 723 } 724 725 if (netif_running(priv->ndev)) { 726 napi_schedule(&priv->napi); 727 return IRQ_HANDLED; 728 } 729 730 priv = cpsw_get_slave_priv(priv, 1); 731 if (!priv) 732 return IRQ_NONE; 733 734 if (netif_running(priv->ndev)) { 735 napi_schedule(&priv->napi); 736 return IRQ_HANDLED; 737 } 738 return IRQ_NONE; 739 } 740 741 static int cpsw_poll(struct napi_struct *napi, int budget) 742 { 743 struct cpsw_priv *priv = napi_to_priv(napi); 744 int num_tx, num_rx; 745 746 num_tx = cpdma_chan_process(priv->txch, 128); 747 if (num_tx) 748 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 749 750 num_rx = cpdma_chan_process(priv->rxch, budget); 751 if (num_rx < budget) { 752 struct cpsw_priv *prim_cpsw; 753 754 napi_complete(napi); 755 cpsw_intr_enable(priv); 756 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 757 prim_cpsw = cpsw_get_slave_priv(priv, 0); 758 if (prim_cpsw->irq_enabled == false) { 759 prim_cpsw->irq_enabled = true; 760 cpsw_enable_irq(priv); 761 } 762 } 763 764 if (num_rx || num_tx) 765 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n", 766 num_rx, num_tx); 767 768 return num_rx; 769 } 770 771 static inline void soft_reset(const char *module, void __iomem *reg) 772 { 773 unsigned long timeout = jiffies + HZ; 774 775 __raw_writel(1, reg); 776 do { 777 cpu_relax(); 778 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 779 780 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 781 } 782 783 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 784 ((mac)[2] << 16) | ((mac)[3] << 24)) 785 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 786 787 static void cpsw_set_slave_mac(struct cpsw_slave *slave, 788 struct cpsw_priv *priv) 789 { 790 slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 791 slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 792 } 793 794 static void _cpsw_adjust_link(struct cpsw_slave *slave, 795 struct cpsw_priv *priv, bool *link) 796 { 797 struct phy_device *phy = slave->phy; 798 u32 mac_control = 0; 799 u32 slave_port; 800 801 if (!phy) 802 return; 803 804 slave_port = cpsw_get_slave_port(priv, slave->slave_num); 805 806 if (phy->link) { 807 mac_control = priv->data.mac_control; 808 809 /* enable forwarding */ 810 cpsw_ale_control_set(priv->ale, slave_port, 811 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 812 813 if (phy->speed == 1000) 814 mac_control |= BIT(7); /* GIGABITEN */ 815 if (phy->duplex) 816 mac_control |= BIT(0); /* FULLDUPLEXEN */ 817 818 /* set speed_in input in case RMII mode is used in 100Mbps */ 819 if (phy->speed == 100) 820 mac_control |= BIT(15); 821 else if (phy->speed == 10) 822 mac_control |= BIT(18); /* In Band mode */ 823 824 *link = true; 825 } else { 826 mac_control = 0; 827 /* disable forwarding */ 828 cpsw_ale_control_set(priv->ale, slave_port, 829 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 830 } 831 832 if (mac_control != slave->mac_control) { 833 phy_print_status(phy); 834 __raw_writel(mac_control, &slave->sliver->mac_control); 835 } 836 837 slave->mac_control = mac_control; 838 } 839 840 static void cpsw_adjust_link(struct net_device *ndev) 841 { 842 struct cpsw_priv *priv = netdev_priv(ndev); 843 bool link = false; 844 845 for_each_slave(priv, _cpsw_adjust_link, priv, &link); 846 847 if (link) { 848 netif_carrier_on(ndev); 849 if (netif_running(ndev)) 850 netif_wake_queue(ndev); 851 } else { 852 netif_carrier_off(ndev); 853 netif_stop_queue(ndev); 854 } 855 } 856 857 static int cpsw_get_coalesce(struct net_device *ndev, 858 struct ethtool_coalesce *coal) 859 { 860 struct cpsw_priv *priv = netdev_priv(ndev); 861 862 coal->rx_coalesce_usecs = priv->coal_intvl; 863 return 0; 864 } 865 866 static int cpsw_set_coalesce(struct net_device *ndev, 867 struct ethtool_coalesce *coal) 868 { 869 struct cpsw_priv *priv = netdev_priv(ndev); 870 u32 int_ctrl; 871 u32 num_interrupts = 0; 872 u32 prescale = 0; 873 u32 addnl_dvdr = 1; 874 u32 coal_intvl = 0; 875 876 if (!coal->rx_coalesce_usecs) 877 return -EINVAL; 878 879 coal_intvl = coal->rx_coalesce_usecs; 880 881 int_ctrl = readl(&priv->wr_regs->int_control); 882 prescale = priv->bus_freq_mhz * 4; 883 884 if (coal_intvl < CPSW_CMINTMIN_INTVL) 885 coal_intvl = CPSW_CMINTMIN_INTVL; 886 887 if (coal_intvl > CPSW_CMINTMAX_INTVL) { 888 /* Interrupt pacer works with 4us Pulse, we can 889 * throttle further by dilating the 4us pulse. 890 */ 891 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; 892 893 if (addnl_dvdr > 1) { 894 prescale *= addnl_dvdr; 895 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) 896 coal_intvl = (CPSW_CMINTMAX_INTVL 897 * addnl_dvdr); 898 } else { 899 addnl_dvdr = 1; 900 coal_intvl = CPSW_CMINTMAX_INTVL; 901 } 902 } 903 904 num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 905 writel(num_interrupts, &priv->wr_regs->rx_imax); 906 writel(num_interrupts, &priv->wr_regs->tx_imax); 907 908 int_ctrl |= CPSW_INTPACEEN; 909 int_ctrl &= (~CPSW_INTPRESCALE_MASK); 910 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); 911 writel(int_ctrl, &priv->wr_regs->int_control); 912 913 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); 914 if (priv->data.dual_emac) { 915 int i; 916 917 for (i = 0; i < priv->data.slaves; i++) { 918 priv = netdev_priv(priv->slaves[i].ndev); 919 priv->coal_intvl = coal_intvl; 920 } 921 } else { 922 priv->coal_intvl = coal_intvl; 923 } 924 925 return 0; 926 } 927 928 static int cpsw_get_sset_count(struct net_device *ndev, int sset) 929 { 930 switch (sset) { 931 case ETH_SS_STATS: 932 return CPSW_STATS_LEN; 933 default: 934 return -EOPNOTSUPP; 935 } 936 } 937 938 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 939 { 940 u8 *p = data; 941 int i; 942 943 switch (stringset) { 944 case ETH_SS_STATS: 945 for (i = 0; i < CPSW_STATS_LEN; i++) { 946 memcpy(p, cpsw_gstrings_stats[i].stat_string, 947 ETH_GSTRING_LEN); 948 p += ETH_GSTRING_LEN; 949 } 950 break; 951 } 952 } 953 954 static void cpsw_get_ethtool_stats(struct net_device *ndev, 955 struct ethtool_stats *stats, u64 *data) 956 { 957 struct cpsw_priv *priv = netdev_priv(ndev); 958 struct cpdma_chan_stats rx_stats; 959 struct cpdma_chan_stats tx_stats; 960 u32 val; 961 u8 *p; 962 int i; 963 964 /* Collect Davinci CPDMA stats for Rx and Tx Channel */ 965 cpdma_chan_get_stats(priv->rxch, &rx_stats); 966 cpdma_chan_get_stats(priv->txch, &tx_stats); 967 968 for (i = 0; i < CPSW_STATS_LEN; i++) { 969 switch (cpsw_gstrings_stats[i].type) { 970 case CPSW_STATS: 971 val = readl(priv->hw_stats + 972 cpsw_gstrings_stats[i].stat_offset); 973 data[i] = val; 974 break; 975 976 case CPDMA_RX_STATS: 977 p = (u8 *)&rx_stats + 978 cpsw_gstrings_stats[i].stat_offset; 979 data[i] = *(u32 *)p; 980 break; 981 982 case CPDMA_TX_STATS: 983 p = (u8 *)&tx_stats + 984 cpsw_gstrings_stats[i].stat_offset; 985 data[i] = *(u32 *)p; 986 break; 987 } 988 } 989 } 990 991 static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val) 992 { 993 static char *leader = "........................................"; 994 995 if (!val) 996 return 0; 997 else 998 return snprintf(buf, maxlen, "%s %s %10d\n", name, 999 leader + strlen(name), val); 1000 } 1001 1002 static int cpsw_common_res_usage_state(struct cpsw_priv *priv) 1003 { 1004 u32 i; 1005 u32 usage_count = 0; 1006 1007 if (!priv->data.dual_emac) 1008 return 0; 1009 1010 for (i = 0; i < priv->data.slaves; i++) 1011 if (priv->slaves[i].open_stat) 1012 usage_count++; 1013 1014 return usage_count; 1015 } 1016 1017 static inline int cpsw_tx_packet_submit(struct net_device *ndev, 1018 struct cpsw_priv *priv, struct sk_buff *skb) 1019 { 1020 if (!priv->data.dual_emac) 1021 return cpdma_chan_submit(priv->txch, skb, skb->data, 1022 skb->len, 0); 1023 1024 if (ndev == cpsw_get_slave_ndev(priv, 0)) 1025 return cpdma_chan_submit(priv->txch, skb, skb->data, 1026 skb->len, 1); 1027 else 1028 return cpdma_chan_submit(priv->txch, skb, skb->data, 1029 skb->len, 2); 1030 } 1031 1032 static inline void cpsw_add_dual_emac_def_ale_entries( 1033 struct cpsw_priv *priv, struct cpsw_slave *slave, 1034 u32 slave_port) 1035 { 1036 u32 port_mask = 1 << slave_port | 1 << priv->host_port; 1037 1038 if (priv->version == CPSW_VERSION_1) 1039 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); 1040 else 1041 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); 1042 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask, 1043 port_mask, port_mask, 0); 1044 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1045 port_mask, ALE_VLAN, slave->port_vlan, 0); 1046 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 1047 priv->host_port, ALE_VLAN, slave->port_vlan); 1048 } 1049 1050 static void soft_reset_slave(struct cpsw_slave *slave) 1051 { 1052 char name[32]; 1053 1054 snprintf(name, sizeof(name), "slave-%d", slave->slave_num); 1055 soft_reset(name, &slave->sliver->soft_reset); 1056 } 1057 1058 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 1059 { 1060 u32 slave_port; 1061 1062 soft_reset_slave(slave); 1063 1064 /* setup priority mapping */ 1065 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 1066 1067 switch (priv->version) { 1068 case CPSW_VERSION_1: 1069 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 1070 break; 1071 case CPSW_VERSION_2: 1072 case CPSW_VERSION_3: 1073 case CPSW_VERSION_4: 1074 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 1075 break; 1076 } 1077 1078 /* setup max packet size, and mac address */ 1079 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); 1080 cpsw_set_slave_mac(slave, priv); 1081 1082 slave->mac_control = 0; /* no link yet */ 1083 1084 slave_port = cpsw_get_slave_port(priv, slave->slave_num); 1085 1086 if (priv->data.dual_emac) 1087 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); 1088 else 1089 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1090 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 1091 1092 slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 1093 &cpsw_adjust_link, slave->data->phy_if); 1094 if (IS_ERR(slave->phy)) { 1095 dev_err(priv->dev, "phy %s not found on slave %d\n", 1096 slave->data->phy_id, slave->slave_num); 1097 slave->phy = NULL; 1098 } else { 1099 dev_info(priv->dev, "phy found : id is : 0x%x\n", 1100 slave->phy->phy_id); 1101 phy_start(slave->phy); 1102 1103 /* Configure GMII_SEL register */ 1104 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface, 1105 slave->slave_num); 1106 } 1107 } 1108 1109 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 1110 { 1111 const int vlan = priv->data.default_vlan; 1112 const int port = priv->host_port; 1113 u32 reg; 1114 int i; 1115 1116 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 1117 CPSW2_PORT_VLAN; 1118 1119 writel(vlan, &priv->host_port_regs->port_vlan); 1120 1121 for (i = 0; i < priv->data.slaves; i++) 1122 slave_write(priv->slaves + i, vlan, reg); 1123 1124 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port, 1125 ALE_ALL_PORTS << port, ALE_ALL_PORTS << port, 1126 (ALE_PORT_1 | ALE_PORT_2) << port); 1127 } 1128 1129 static void cpsw_init_host_port(struct cpsw_priv *priv) 1130 { 1131 u32 control_reg; 1132 u32 fifo_mode; 1133 1134 /* soft reset the controller and initialize ale */ 1135 soft_reset("cpsw", &priv->regs->soft_reset); 1136 cpsw_ale_start(priv->ale); 1137 1138 /* switch to vlan unaware mode */ 1139 cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE, 1140 CPSW_ALE_VLAN_AWARE); 1141 control_reg = readl(&priv->regs->control); 1142 control_reg |= CPSW_VLAN_AWARE; 1143 writel(control_reg, &priv->regs->control); 1144 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : 1145 CPSW_FIFO_NORMAL_MODE; 1146 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl); 1147 1148 /* setup host port priority mapping */ 1149 __raw_writel(CPDMA_TX_PRIORITY_MAP, 1150 &priv->host_port_regs->cpdma_tx_pri_map); 1151 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 1152 1153 cpsw_ale_control_set(priv->ale, priv->host_port, 1154 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1155 1156 if (!priv->data.dual_emac) { 1157 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 1158 0, 0); 1159 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1160 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2); 1161 } 1162 } 1163 1164 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) 1165 { 1166 u32 slave_port; 1167 1168 slave_port = cpsw_get_slave_port(priv, slave->slave_num); 1169 1170 if (!slave->phy) 1171 return; 1172 phy_stop(slave->phy); 1173 phy_disconnect(slave->phy); 1174 slave->phy = NULL; 1175 cpsw_ale_control_set(priv->ale, slave_port, 1176 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1177 } 1178 1179 static int cpsw_ndo_open(struct net_device *ndev) 1180 { 1181 struct cpsw_priv *priv = netdev_priv(ndev); 1182 struct cpsw_priv *prim_cpsw; 1183 int i, ret; 1184 u32 reg; 1185 1186 if (!cpsw_common_res_usage_state(priv)) 1187 cpsw_intr_disable(priv); 1188 netif_carrier_off(ndev); 1189 1190 pm_runtime_get_sync(&priv->pdev->dev); 1191 1192 reg = priv->version; 1193 1194 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 1195 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 1196 CPSW_RTL_VERSION(reg)); 1197 1198 /* initialize host and slave ports */ 1199 if (!cpsw_common_res_usage_state(priv)) 1200 cpsw_init_host_port(priv); 1201 for_each_slave(priv, cpsw_slave_open, priv); 1202 1203 /* Add default VLAN */ 1204 cpsw_add_default_vlan(priv); 1205 1206 if (!cpsw_common_res_usage_state(priv)) { 1207 /* setup tx dma to fixed prio and zero offset */ 1208 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); 1209 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); 1210 1211 /* disable priority elevation */ 1212 __raw_writel(0, &priv->regs->ptype); 1213 1214 /* enable statistics collection only on all ports */ 1215 __raw_writel(0x7, &priv->regs->stat_port_en); 1216 1217 if (WARN_ON(!priv->data.rx_descs)) 1218 priv->data.rx_descs = 128; 1219 1220 for (i = 0; i < priv->data.rx_descs; i++) { 1221 struct sk_buff *skb; 1222 1223 ret = -ENOMEM; 1224 skb = __netdev_alloc_skb_ip_align(priv->ndev, 1225 priv->rx_packet_max, GFP_KERNEL); 1226 if (!skb) 1227 goto err_cleanup; 1228 ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 1229 skb_tailroom(skb), 0); 1230 if (ret < 0) { 1231 kfree_skb(skb); 1232 goto err_cleanup; 1233 } 1234 } 1235 /* continue even if we didn't manage to submit all 1236 * receive descs 1237 */ 1238 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); 1239 1240 if (cpts_register(&priv->pdev->dev, priv->cpts, 1241 priv->data.cpts_clock_mult, 1242 priv->data.cpts_clock_shift)) 1243 dev_err(priv->dev, "error registering cpts device\n"); 1244 1245 } 1246 1247 /* Enable Interrupt pacing if configured */ 1248 if (priv->coal_intvl != 0) { 1249 struct ethtool_coalesce coal; 1250 1251 coal.rx_coalesce_usecs = (priv->coal_intvl << 4); 1252 cpsw_set_coalesce(ndev, &coal); 1253 } 1254 1255 napi_enable(&priv->napi); 1256 cpdma_ctlr_start(priv->dma); 1257 cpsw_intr_enable(priv); 1258 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1259 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1260 1261 prim_cpsw = cpsw_get_slave_priv(priv, 0); 1262 if (prim_cpsw->irq_enabled == false) { 1263 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) { 1264 prim_cpsw->irq_enabled = true; 1265 cpsw_enable_irq(prim_cpsw); 1266 } 1267 } 1268 1269 if (priv->data.dual_emac) 1270 priv->slaves[priv->emac_port].open_stat = true; 1271 return 0; 1272 1273 err_cleanup: 1274 cpdma_ctlr_stop(priv->dma); 1275 for_each_slave(priv, cpsw_slave_stop, priv); 1276 pm_runtime_put_sync(&priv->pdev->dev); 1277 netif_carrier_off(priv->ndev); 1278 return ret; 1279 } 1280 1281 static int cpsw_ndo_stop(struct net_device *ndev) 1282 { 1283 struct cpsw_priv *priv = netdev_priv(ndev); 1284 1285 cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 1286 netif_stop_queue(priv->ndev); 1287 napi_disable(&priv->napi); 1288 netif_carrier_off(priv->ndev); 1289 1290 if (cpsw_common_res_usage_state(priv) <= 1) { 1291 cpts_unregister(priv->cpts); 1292 cpsw_intr_disable(priv); 1293 cpdma_ctlr_int_ctrl(priv->dma, false); 1294 cpdma_ctlr_stop(priv->dma); 1295 cpsw_ale_stop(priv->ale); 1296 } 1297 for_each_slave(priv, cpsw_slave_stop, priv); 1298 pm_runtime_put_sync(&priv->pdev->dev); 1299 if (priv->data.dual_emac) 1300 priv->slaves[priv->emac_port].open_stat = false; 1301 return 0; 1302 } 1303 1304 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 1305 struct net_device *ndev) 1306 { 1307 struct cpsw_priv *priv = netdev_priv(ndev); 1308 int ret; 1309 1310 ndev->trans_start = jiffies; 1311 1312 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 1313 cpsw_err(priv, tx_err, "packet pad failed\n"); 1314 ndev->stats.tx_dropped++; 1315 return NETDEV_TX_OK; 1316 } 1317 1318 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 1319 priv->cpts->tx_enable) 1320 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1321 1322 skb_tx_timestamp(skb); 1323 1324 ret = cpsw_tx_packet_submit(ndev, priv, skb); 1325 if (unlikely(ret != 0)) { 1326 cpsw_err(priv, tx_err, "desc submit failed\n"); 1327 goto fail; 1328 } 1329 1330 /* If there is no more tx desc left free then we need to 1331 * tell the kernel to stop sending us tx frames. 1332 */ 1333 if (unlikely(!cpdma_check_free_tx_desc(priv->txch))) 1334 netif_stop_queue(ndev); 1335 1336 return NETDEV_TX_OK; 1337 fail: 1338 ndev->stats.tx_dropped++; 1339 netif_stop_queue(ndev); 1340 return NETDEV_TX_BUSY; 1341 } 1342 1343 #ifdef CONFIG_TI_CPTS 1344 1345 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) 1346 { 1347 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave]; 1348 u32 ts_en, seq_id; 1349 1350 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) { 1351 slave_write(slave, 0, CPSW1_TS_CTL); 1352 return; 1353 } 1354 1355 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 1356 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 1357 1358 if (priv->cpts->tx_enable) 1359 ts_en |= CPSW_V1_TS_TX_EN; 1360 1361 if (priv->cpts->rx_enable) 1362 ts_en |= CPSW_V1_TS_RX_EN; 1363 1364 slave_write(slave, ts_en, CPSW1_TS_CTL); 1365 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 1366 } 1367 1368 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 1369 { 1370 struct cpsw_slave *slave; 1371 u32 ctrl, mtype; 1372 1373 if (priv->data.dual_emac) 1374 slave = &priv->slaves[priv->emac_port]; 1375 else 1376 slave = &priv->slaves[priv->data.active_slave]; 1377 1378 ctrl = slave_read(slave, CPSW2_CONTROL); 1379 ctrl &= ~CTRL_ALL_TS_MASK; 1380 1381 if (priv->cpts->tx_enable) 1382 ctrl |= CTRL_TX_TS_BITS; 1383 1384 if (priv->cpts->rx_enable) 1385 ctrl |= CTRL_RX_TS_BITS; 1386 1387 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 1388 1389 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 1390 slave_write(slave, ctrl, CPSW2_CONTROL); 1391 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); 1392 } 1393 1394 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 1395 { 1396 struct cpsw_priv *priv = netdev_priv(dev); 1397 struct cpts *cpts = priv->cpts; 1398 struct hwtstamp_config cfg; 1399 1400 if (priv->version != CPSW_VERSION_1 && 1401 priv->version != CPSW_VERSION_2) 1402 return -EOPNOTSUPP; 1403 1404 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1405 return -EFAULT; 1406 1407 /* reserved for future extensions */ 1408 if (cfg.flags) 1409 return -EINVAL; 1410 1411 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 1412 return -ERANGE; 1413 1414 switch (cfg.rx_filter) { 1415 case HWTSTAMP_FILTER_NONE: 1416 cpts->rx_enable = 0; 1417 break; 1418 case HWTSTAMP_FILTER_ALL: 1419 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1420 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1421 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1422 return -ERANGE; 1423 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1424 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1425 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1426 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1427 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1428 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1429 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1430 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1431 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1432 cpts->rx_enable = 1; 1433 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1434 break; 1435 default: 1436 return -ERANGE; 1437 } 1438 1439 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON; 1440 1441 switch (priv->version) { 1442 case CPSW_VERSION_1: 1443 cpsw_hwtstamp_v1(priv); 1444 break; 1445 case CPSW_VERSION_2: 1446 cpsw_hwtstamp_v2(priv); 1447 break; 1448 default: 1449 WARN_ON(1); 1450 } 1451 1452 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1453 } 1454 1455 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 1456 { 1457 struct cpsw_priv *priv = netdev_priv(dev); 1458 struct cpts *cpts = priv->cpts; 1459 struct hwtstamp_config cfg; 1460 1461 if (priv->version != CPSW_VERSION_1 && 1462 priv->version != CPSW_VERSION_2) 1463 return -EOPNOTSUPP; 1464 1465 cfg.flags = 0; 1466 cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1467 cfg.rx_filter = (cpts->rx_enable ? 1468 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE); 1469 1470 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1471 } 1472 1473 #endif /*CONFIG_TI_CPTS*/ 1474 1475 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 1476 { 1477 struct cpsw_priv *priv = netdev_priv(dev); 1478 int slave_no = cpsw_slave_index(priv); 1479 1480 if (!netif_running(dev)) 1481 return -EINVAL; 1482 1483 switch (cmd) { 1484 #ifdef CONFIG_TI_CPTS 1485 case SIOCSHWTSTAMP: 1486 return cpsw_hwtstamp_set(dev, req); 1487 case SIOCGHWTSTAMP: 1488 return cpsw_hwtstamp_get(dev, req); 1489 #endif 1490 } 1491 1492 if (!priv->slaves[slave_no].phy) 1493 return -EOPNOTSUPP; 1494 return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd); 1495 } 1496 1497 static void cpsw_ndo_tx_timeout(struct net_device *ndev) 1498 { 1499 struct cpsw_priv *priv = netdev_priv(ndev); 1500 1501 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 1502 ndev->stats.tx_errors++; 1503 cpsw_intr_disable(priv); 1504 cpdma_ctlr_int_ctrl(priv->dma, false); 1505 cpdma_chan_stop(priv->txch); 1506 cpdma_chan_start(priv->txch); 1507 cpdma_ctlr_int_ctrl(priv->dma, true); 1508 cpsw_intr_enable(priv); 1509 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1510 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1511 1512 } 1513 1514 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) 1515 { 1516 struct cpsw_priv *priv = netdev_priv(ndev); 1517 struct sockaddr *addr = (struct sockaddr *)p; 1518 int flags = 0; 1519 u16 vid = 0; 1520 1521 if (!is_valid_ether_addr(addr->sa_data)) 1522 return -EADDRNOTAVAIL; 1523 1524 if (priv->data.dual_emac) { 1525 vid = priv->slaves[priv->emac_port].port_vlan; 1526 flags = ALE_VLAN; 1527 } 1528 1529 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port, 1530 flags, vid); 1531 cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port, 1532 flags, vid); 1533 1534 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN); 1535 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1536 for_each_slave(priv, cpsw_set_slave_mac, priv); 1537 1538 return 0; 1539 } 1540 1541 #ifdef CONFIG_NET_POLL_CONTROLLER 1542 static void cpsw_ndo_poll_controller(struct net_device *ndev) 1543 { 1544 struct cpsw_priv *priv = netdev_priv(ndev); 1545 1546 cpsw_intr_disable(priv); 1547 cpdma_ctlr_int_ctrl(priv->dma, false); 1548 cpsw_interrupt(ndev->irq, priv); 1549 cpdma_ctlr_int_ctrl(priv->dma, true); 1550 cpsw_intr_enable(priv); 1551 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1552 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1553 1554 } 1555 #endif 1556 1557 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 1558 unsigned short vid) 1559 { 1560 int ret; 1561 1562 ret = cpsw_ale_add_vlan(priv->ale, vid, 1563 ALE_ALL_PORTS << priv->host_port, 1564 0, ALE_ALL_PORTS << priv->host_port, 1565 (ALE_PORT_1 | ALE_PORT_2) << priv->host_port); 1566 if (ret != 0) 1567 return ret; 1568 1569 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 1570 priv->host_port, ALE_VLAN, vid); 1571 if (ret != 0) 1572 goto clean_vid; 1573 1574 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1575 ALE_ALL_PORTS << priv->host_port, 1576 ALE_VLAN, vid, 0); 1577 if (ret != 0) 1578 goto clean_vlan_ucast; 1579 return 0; 1580 1581 clean_vlan_ucast: 1582 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 1583 priv->host_port, ALE_VLAN, vid); 1584 clean_vid: 1585 cpsw_ale_del_vlan(priv->ale, vid, 0); 1586 return ret; 1587 } 1588 1589 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 1590 __be16 proto, u16 vid) 1591 { 1592 struct cpsw_priv *priv = netdev_priv(ndev); 1593 1594 if (vid == priv->data.default_vlan) 1595 return 0; 1596 1597 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 1598 return cpsw_add_vlan_ale_entry(priv, vid); 1599 } 1600 1601 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 1602 __be16 proto, u16 vid) 1603 { 1604 struct cpsw_priv *priv = netdev_priv(ndev); 1605 int ret; 1606 1607 if (vid == priv->data.default_vlan) 1608 return 0; 1609 1610 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 1611 ret = cpsw_ale_del_vlan(priv->ale, vid, 0); 1612 if (ret != 0) 1613 return ret; 1614 1615 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 1616 priv->host_port, ALE_VLAN, vid); 1617 if (ret != 0) 1618 return ret; 1619 1620 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast, 1621 0, ALE_VLAN, vid); 1622 } 1623 1624 static const struct net_device_ops cpsw_netdev_ops = { 1625 .ndo_open = cpsw_ndo_open, 1626 .ndo_stop = cpsw_ndo_stop, 1627 .ndo_start_xmit = cpsw_ndo_start_xmit, 1628 .ndo_set_mac_address = cpsw_ndo_set_mac_address, 1629 .ndo_do_ioctl = cpsw_ndo_ioctl, 1630 .ndo_validate_addr = eth_validate_addr, 1631 .ndo_change_mtu = eth_change_mtu, 1632 .ndo_tx_timeout = cpsw_ndo_tx_timeout, 1633 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 1634 #ifdef CONFIG_NET_POLL_CONTROLLER 1635 .ndo_poll_controller = cpsw_ndo_poll_controller, 1636 #endif 1637 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 1638 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 1639 }; 1640 1641 static void cpsw_get_drvinfo(struct net_device *ndev, 1642 struct ethtool_drvinfo *info) 1643 { 1644 struct cpsw_priv *priv = netdev_priv(ndev); 1645 1646 strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver)); 1647 strlcpy(info->version, "1.0", sizeof(info->version)); 1648 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info)); 1649 } 1650 1651 static u32 cpsw_get_msglevel(struct net_device *ndev) 1652 { 1653 struct cpsw_priv *priv = netdev_priv(ndev); 1654 return priv->msg_enable; 1655 } 1656 1657 static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 1658 { 1659 struct cpsw_priv *priv = netdev_priv(ndev); 1660 priv->msg_enable = value; 1661 } 1662 1663 static int cpsw_get_ts_info(struct net_device *ndev, 1664 struct ethtool_ts_info *info) 1665 { 1666 #ifdef CONFIG_TI_CPTS 1667 struct cpsw_priv *priv = netdev_priv(ndev); 1668 1669 info->so_timestamping = 1670 SOF_TIMESTAMPING_TX_HARDWARE | 1671 SOF_TIMESTAMPING_TX_SOFTWARE | 1672 SOF_TIMESTAMPING_RX_HARDWARE | 1673 SOF_TIMESTAMPING_RX_SOFTWARE | 1674 SOF_TIMESTAMPING_SOFTWARE | 1675 SOF_TIMESTAMPING_RAW_HARDWARE; 1676 info->phc_index = priv->cpts->phc_index; 1677 info->tx_types = 1678 (1 << HWTSTAMP_TX_OFF) | 1679 (1 << HWTSTAMP_TX_ON); 1680 info->rx_filters = 1681 (1 << HWTSTAMP_FILTER_NONE) | 1682 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 1683 #else 1684 info->so_timestamping = 1685 SOF_TIMESTAMPING_TX_SOFTWARE | 1686 SOF_TIMESTAMPING_RX_SOFTWARE | 1687 SOF_TIMESTAMPING_SOFTWARE; 1688 info->phc_index = -1; 1689 info->tx_types = 0; 1690 info->rx_filters = 0; 1691 #endif 1692 return 0; 1693 } 1694 1695 static int cpsw_get_settings(struct net_device *ndev, 1696 struct ethtool_cmd *ecmd) 1697 { 1698 struct cpsw_priv *priv = netdev_priv(ndev); 1699 int slave_no = cpsw_slave_index(priv); 1700 1701 if (priv->slaves[slave_no].phy) 1702 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd); 1703 else 1704 return -EOPNOTSUPP; 1705 } 1706 1707 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 1708 { 1709 struct cpsw_priv *priv = netdev_priv(ndev); 1710 int slave_no = cpsw_slave_index(priv); 1711 1712 if (priv->slaves[slave_no].phy) 1713 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd); 1714 else 1715 return -EOPNOTSUPP; 1716 } 1717 1718 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1719 { 1720 struct cpsw_priv *priv = netdev_priv(ndev); 1721 int slave_no = cpsw_slave_index(priv); 1722 1723 wol->supported = 0; 1724 wol->wolopts = 0; 1725 1726 if (priv->slaves[slave_no].phy) 1727 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol); 1728 } 1729 1730 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1731 { 1732 struct cpsw_priv *priv = netdev_priv(ndev); 1733 int slave_no = cpsw_slave_index(priv); 1734 1735 if (priv->slaves[slave_no].phy) 1736 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol); 1737 else 1738 return -EOPNOTSUPP; 1739 } 1740 1741 static const struct ethtool_ops cpsw_ethtool_ops = { 1742 .get_drvinfo = cpsw_get_drvinfo, 1743 .get_msglevel = cpsw_get_msglevel, 1744 .set_msglevel = cpsw_set_msglevel, 1745 .get_link = ethtool_op_get_link, 1746 .get_ts_info = cpsw_get_ts_info, 1747 .get_settings = cpsw_get_settings, 1748 .set_settings = cpsw_set_settings, 1749 .get_coalesce = cpsw_get_coalesce, 1750 .set_coalesce = cpsw_set_coalesce, 1751 .get_sset_count = cpsw_get_sset_count, 1752 .get_strings = cpsw_get_strings, 1753 .get_ethtool_stats = cpsw_get_ethtool_stats, 1754 .get_wol = cpsw_get_wol, 1755 .set_wol = cpsw_set_wol, 1756 }; 1757 1758 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, 1759 u32 slave_reg_ofs, u32 sliver_reg_ofs) 1760 { 1761 void __iomem *regs = priv->regs; 1762 int slave_num = slave->slave_num; 1763 struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 1764 1765 slave->data = data; 1766 slave->regs = regs + slave_reg_ofs; 1767 slave->sliver = regs + sliver_reg_ofs; 1768 slave->port_vlan = data->dual_emac_res_vlan; 1769 } 1770 1771 static int cpsw_probe_dt(struct cpsw_platform_data *data, 1772 struct platform_device *pdev) 1773 { 1774 struct device_node *node = pdev->dev.of_node; 1775 struct device_node *slave_node; 1776 int i = 0, ret; 1777 u32 prop; 1778 1779 if (!node) 1780 return -EINVAL; 1781 1782 if (of_property_read_u32(node, "slaves", &prop)) { 1783 pr_err("Missing slaves property in the DT.\n"); 1784 return -EINVAL; 1785 } 1786 data->slaves = prop; 1787 1788 if (of_property_read_u32(node, "active_slave", &prop)) { 1789 pr_err("Missing active_slave property in the DT.\n"); 1790 return -EINVAL; 1791 } 1792 data->active_slave = prop; 1793 1794 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { 1795 pr_err("Missing cpts_clock_mult property in the DT.\n"); 1796 return -EINVAL; 1797 } 1798 data->cpts_clock_mult = prop; 1799 1800 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { 1801 pr_err("Missing cpts_clock_shift property in the DT.\n"); 1802 return -EINVAL; 1803 } 1804 data->cpts_clock_shift = prop; 1805 1806 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves 1807 * sizeof(struct cpsw_slave_data), 1808 GFP_KERNEL); 1809 if (!data->slave_data) 1810 return -ENOMEM; 1811 1812 if (of_property_read_u32(node, "cpdma_channels", &prop)) { 1813 pr_err("Missing cpdma_channels property in the DT.\n"); 1814 return -EINVAL; 1815 } 1816 data->channels = prop; 1817 1818 if (of_property_read_u32(node, "ale_entries", &prop)) { 1819 pr_err("Missing ale_entries property in the DT.\n"); 1820 return -EINVAL; 1821 } 1822 data->ale_entries = prop; 1823 1824 if (of_property_read_u32(node, "bd_ram_size", &prop)) { 1825 pr_err("Missing bd_ram_size property in the DT.\n"); 1826 return -EINVAL; 1827 } 1828 data->bd_ram_size = prop; 1829 1830 if (of_property_read_u32(node, "rx_descs", &prop)) { 1831 pr_err("Missing rx_descs property in the DT.\n"); 1832 return -EINVAL; 1833 } 1834 data->rx_descs = prop; 1835 1836 if (of_property_read_u32(node, "mac_control", &prop)) { 1837 pr_err("Missing mac_control property in the DT.\n"); 1838 return -EINVAL; 1839 } 1840 data->mac_control = prop; 1841 1842 if (of_property_read_bool(node, "dual_emac")) 1843 data->dual_emac = 1; 1844 1845 /* 1846 * Populate all the child nodes here... 1847 */ 1848 ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 1849 /* We do not want to force this, as in some cases may not have child */ 1850 if (ret) 1851 pr_warn("Doesn't have any child node\n"); 1852 1853 for_each_child_of_node(node, slave_node) { 1854 struct cpsw_slave_data *slave_data = data->slave_data + i; 1855 const void *mac_addr = NULL; 1856 u32 phyid; 1857 int lenp; 1858 const __be32 *parp; 1859 struct device_node *mdio_node; 1860 struct platform_device *mdio; 1861 1862 /* This is no slave child node, continue */ 1863 if (strcmp(slave_node->name, "slave")) 1864 continue; 1865 1866 parp = of_get_property(slave_node, "phy_id", &lenp); 1867 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) { 1868 pr_err("Missing slave[%d] phy_id property\n", i); 1869 return -EINVAL; 1870 } 1871 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 1872 phyid = be32_to_cpup(parp+1); 1873 mdio = of_find_device_by_node(mdio_node); 1874 1875 if (strncmp(mdio->name, "gpio", 4) == 0) { 1876 /* GPIO bitbang MDIO driver attached */ 1877 struct mii_bus *bus = dev_get_drvdata(&mdio->dev); 1878 1879 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 1880 PHY_ID_FMT, bus->id, phyid); 1881 } else { 1882 /* davinci MDIO driver attached */ 1883 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 1884 PHY_ID_FMT, mdio->name, phyid); 1885 } 1886 1887 mac_addr = of_get_mac_address(slave_node); 1888 if (mac_addr) 1889 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 1890 1891 slave_data->phy_if = of_get_phy_mode(slave_node); 1892 if (slave_data->phy_if < 0) { 1893 pr_err("Missing or malformed slave[%d] phy-mode property\n", 1894 i); 1895 return slave_data->phy_if; 1896 } 1897 1898 if (data->dual_emac) { 1899 if (of_property_read_u32(slave_node, "dual_emac_res_vlan", 1900 &prop)) { 1901 pr_err("Missing dual_emac_res_vlan in DT.\n"); 1902 slave_data->dual_emac_res_vlan = i+1; 1903 pr_err("Using %d as Reserved VLAN for %d slave\n", 1904 slave_data->dual_emac_res_vlan, i); 1905 } else { 1906 slave_data->dual_emac_res_vlan = prop; 1907 } 1908 } 1909 1910 i++; 1911 if (i == data->slaves) 1912 break; 1913 } 1914 1915 return 0; 1916 } 1917 1918 static int cpsw_probe_dual_emac(struct platform_device *pdev, 1919 struct cpsw_priv *priv) 1920 { 1921 struct cpsw_platform_data *data = &priv->data; 1922 struct net_device *ndev; 1923 struct cpsw_priv *priv_sl2; 1924 int ret = 0, i; 1925 1926 ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 1927 if (!ndev) { 1928 pr_err("cpsw: error allocating net_device\n"); 1929 return -ENOMEM; 1930 } 1931 1932 priv_sl2 = netdev_priv(ndev); 1933 spin_lock_init(&priv_sl2->lock); 1934 priv_sl2->data = *data; 1935 priv_sl2->pdev = pdev; 1936 priv_sl2->ndev = ndev; 1937 priv_sl2->dev = &ndev->dev; 1938 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 1939 priv_sl2->rx_packet_max = max(rx_packet_max, 128); 1940 1941 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 1942 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 1943 ETH_ALEN); 1944 pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr); 1945 } else { 1946 random_ether_addr(priv_sl2->mac_addr); 1947 pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr); 1948 } 1949 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 1950 1951 priv_sl2->slaves = priv->slaves; 1952 priv_sl2->clk = priv->clk; 1953 1954 priv_sl2->coal_intvl = 0; 1955 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz; 1956 1957 priv_sl2->regs = priv->regs; 1958 priv_sl2->host_port = priv->host_port; 1959 priv_sl2->host_port_regs = priv->host_port_regs; 1960 priv_sl2->wr_regs = priv->wr_regs; 1961 priv_sl2->hw_stats = priv->hw_stats; 1962 priv_sl2->dma = priv->dma; 1963 priv_sl2->txch = priv->txch; 1964 priv_sl2->rxch = priv->rxch; 1965 priv_sl2->ale = priv->ale; 1966 priv_sl2->emac_port = 1; 1967 priv->slaves[1].ndev = ndev; 1968 priv_sl2->cpts = priv->cpts; 1969 priv_sl2->version = priv->version; 1970 1971 for (i = 0; i < priv->num_irqs; i++) { 1972 priv_sl2->irqs_table[i] = priv->irqs_table[i]; 1973 priv_sl2->num_irqs = priv->num_irqs; 1974 } 1975 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1976 1977 ndev->netdev_ops = &cpsw_netdev_ops; 1978 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); 1979 netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT); 1980 1981 /* register the network device */ 1982 SET_NETDEV_DEV(ndev, &pdev->dev); 1983 ret = register_netdev(ndev); 1984 if (ret) { 1985 pr_err("cpsw: error registering net device\n"); 1986 free_netdev(ndev); 1987 ret = -ENODEV; 1988 } 1989 1990 return ret; 1991 } 1992 1993 static int cpsw_probe(struct platform_device *pdev) 1994 { 1995 struct cpsw_platform_data *data; 1996 struct net_device *ndev; 1997 struct cpsw_priv *priv; 1998 struct cpdma_params dma_params; 1999 struct cpsw_ale_params ale_params; 2000 void __iomem *ss_regs; 2001 struct resource *res, *ss_res; 2002 u32 slave_offset, sliver_offset, slave_size; 2003 int ret = 0, i, k = 0; 2004 2005 ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 2006 if (!ndev) { 2007 pr_err("error allocating net_device\n"); 2008 return -ENOMEM; 2009 } 2010 2011 platform_set_drvdata(pdev, ndev); 2012 priv = netdev_priv(ndev); 2013 spin_lock_init(&priv->lock); 2014 priv->pdev = pdev; 2015 priv->ndev = ndev; 2016 priv->dev = &ndev->dev; 2017 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 2018 priv->rx_packet_max = max(rx_packet_max, 128); 2019 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL); 2020 priv->irq_enabled = true; 2021 if (!priv->cpts) { 2022 pr_err("error allocating cpts\n"); 2023 goto clean_ndev_ret; 2024 } 2025 2026 /* 2027 * This may be required here for child devices. 2028 */ 2029 pm_runtime_enable(&pdev->dev); 2030 2031 /* Select default pin state */ 2032 pinctrl_pm_select_default_state(&pdev->dev); 2033 2034 if (cpsw_probe_dt(&priv->data, pdev)) { 2035 pr_err("cpsw: platform data missing\n"); 2036 ret = -ENODEV; 2037 goto clean_runtime_disable_ret; 2038 } 2039 data = &priv->data; 2040 2041 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 2042 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 2043 pr_info("Detected MACID = %pM\n", priv->mac_addr); 2044 } else { 2045 eth_random_addr(priv->mac_addr); 2046 pr_info("Random MACID = %pM\n", priv->mac_addr); 2047 } 2048 2049 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 2050 2051 priv->slaves = devm_kzalloc(&pdev->dev, 2052 sizeof(struct cpsw_slave) * data->slaves, 2053 GFP_KERNEL); 2054 if (!priv->slaves) { 2055 ret = -ENOMEM; 2056 goto clean_runtime_disable_ret; 2057 } 2058 for (i = 0; i < data->slaves; i++) 2059 priv->slaves[i].slave_num = i; 2060 2061 priv->slaves[0].ndev = ndev; 2062 priv->emac_port = 0; 2063 2064 priv->clk = devm_clk_get(&pdev->dev, "fck"); 2065 if (IS_ERR(priv->clk)) { 2066 dev_err(priv->dev, "fck is not found\n"); 2067 ret = -ENODEV; 2068 goto clean_runtime_disable_ret; 2069 } 2070 priv->coal_intvl = 0; 2071 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000; 2072 2073 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2074 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res); 2075 if (IS_ERR(ss_regs)) { 2076 ret = PTR_ERR(ss_regs); 2077 goto clean_runtime_disable_ret; 2078 } 2079 priv->regs = ss_regs; 2080 priv->host_port = HOST_PORT_NUM; 2081 2082 /* Need to enable clocks with runtime PM api to access module 2083 * registers 2084 */ 2085 pm_runtime_get_sync(&pdev->dev); 2086 priv->version = readl(&priv->regs->id_ver); 2087 pm_runtime_put_sync(&pdev->dev); 2088 2089 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2090 priv->wr_regs = devm_ioremap_resource(&pdev->dev, res); 2091 if (IS_ERR(priv->wr_regs)) { 2092 ret = PTR_ERR(priv->wr_regs); 2093 goto clean_runtime_disable_ret; 2094 } 2095 2096 memset(&dma_params, 0, sizeof(dma_params)); 2097 memset(&ale_params, 0, sizeof(ale_params)); 2098 2099 switch (priv->version) { 2100 case CPSW_VERSION_1: 2101 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 2102 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET; 2103 priv->hw_stats = ss_regs + CPSW1_HW_STATS; 2104 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 2105 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 2106 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 2107 slave_offset = CPSW1_SLAVE_OFFSET; 2108 slave_size = CPSW1_SLAVE_SIZE; 2109 sliver_offset = CPSW1_SLIVER_OFFSET; 2110 dma_params.desc_mem_phys = 0; 2111 break; 2112 case CPSW_VERSION_2: 2113 case CPSW_VERSION_3: 2114 case CPSW_VERSION_4: 2115 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 2116 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET; 2117 priv->hw_stats = ss_regs + CPSW2_HW_STATS; 2118 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 2119 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 2120 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 2121 slave_offset = CPSW2_SLAVE_OFFSET; 2122 slave_size = CPSW2_SLAVE_SIZE; 2123 sliver_offset = CPSW2_SLIVER_OFFSET; 2124 dma_params.desc_mem_phys = 2125 (u32 __force) ss_res->start + CPSW2_BD_OFFSET; 2126 break; 2127 default: 2128 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); 2129 ret = -ENODEV; 2130 goto clean_runtime_disable_ret; 2131 } 2132 for (i = 0; i < priv->data.slaves; i++) { 2133 struct cpsw_slave *slave = &priv->slaves[i]; 2134 cpsw_slave_init(slave, priv, slave_offset, sliver_offset); 2135 slave_offset += slave_size; 2136 sliver_offset += SLIVER_SIZE; 2137 } 2138 2139 dma_params.dev = &pdev->dev; 2140 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 2141 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 2142 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 2143 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 2144 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 2145 2146 dma_params.num_chan = data->channels; 2147 dma_params.has_soft_reset = true; 2148 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 2149 dma_params.desc_mem_size = data->bd_ram_size; 2150 dma_params.desc_align = 16; 2151 dma_params.has_ext_regs = true; 2152 dma_params.desc_hw_addr = dma_params.desc_mem_phys; 2153 2154 priv->dma = cpdma_ctlr_create(&dma_params); 2155 if (!priv->dma) { 2156 dev_err(priv->dev, "error initializing dma\n"); 2157 ret = -ENOMEM; 2158 goto clean_runtime_disable_ret; 2159 } 2160 2161 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), 2162 cpsw_tx_handler); 2163 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), 2164 cpsw_rx_handler); 2165 2166 if (WARN_ON(!priv->txch || !priv->rxch)) { 2167 dev_err(priv->dev, "error initializing dma channels\n"); 2168 ret = -ENOMEM; 2169 goto clean_dma_ret; 2170 } 2171 2172 ale_params.dev = &ndev->dev; 2173 ale_params.ale_ageout = ale_ageout; 2174 ale_params.ale_entries = data->ale_entries; 2175 ale_params.ale_ports = data->slaves; 2176 2177 priv->ale = cpsw_ale_create(&ale_params); 2178 if (!priv->ale) { 2179 dev_err(priv->dev, "error initializing ale engine\n"); 2180 ret = -ENODEV; 2181 goto clean_dma_ret; 2182 } 2183 2184 ndev->irq = platform_get_irq(pdev, 0); 2185 if (ndev->irq < 0) { 2186 dev_err(priv->dev, "error getting irq resource\n"); 2187 ret = -ENOENT; 2188 goto clean_ale_ret; 2189 } 2190 2191 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { 2192 for (i = res->start; i <= res->end; i++) { 2193 if (devm_request_irq(&pdev->dev, i, cpsw_interrupt, 0, 2194 dev_name(&pdev->dev), priv)) { 2195 dev_err(priv->dev, "error attaching irq\n"); 2196 goto clean_ale_ret; 2197 } 2198 priv->irqs_table[k] = i; 2199 priv->num_irqs = k + 1; 2200 } 2201 k++; 2202 } 2203 2204 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2205 2206 ndev->netdev_ops = &cpsw_netdev_ops; 2207 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); 2208 netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); 2209 2210 /* register the network device */ 2211 SET_NETDEV_DEV(ndev, &pdev->dev); 2212 ret = register_netdev(ndev); 2213 if (ret) { 2214 dev_err(priv->dev, "error registering net device\n"); 2215 ret = -ENODEV; 2216 goto clean_ale_ret; 2217 } 2218 2219 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n", 2220 &ss_res->start, ndev->irq); 2221 2222 if (priv->data.dual_emac) { 2223 ret = cpsw_probe_dual_emac(pdev, priv); 2224 if (ret) { 2225 cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); 2226 goto clean_ale_ret; 2227 } 2228 } 2229 2230 return 0; 2231 2232 clean_ale_ret: 2233 cpsw_ale_destroy(priv->ale); 2234 clean_dma_ret: 2235 cpdma_chan_destroy(priv->txch); 2236 cpdma_chan_destroy(priv->rxch); 2237 cpdma_ctlr_destroy(priv->dma); 2238 clean_runtime_disable_ret: 2239 pm_runtime_disable(&pdev->dev); 2240 clean_ndev_ret: 2241 free_netdev(priv->ndev); 2242 return ret; 2243 } 2244 2245 static int cpsw_remove(struct platform_device *pdev) 2246 { 2247 struct net_device *ndev = platform_get_drvdata(pdev); 2248 struct cpsw_priv *priv = netdev_priv(ndev); 2249 2250 if (priv->data.dual_emac) 2251 unregister_netdev(cpsw_get_slave_ndev(priv, 1)); 2252 unregister_netdev(ndev); 2253 2254 cpsw_ale_destroy(priv->ale); 2255 cpdma_chan_destroy(priv->txch); 2256 cpdma_chan_destroy(priv->rxch); 2257 cpdma_ctlr_destroy(priv->dma); 2258 pm_runtime_disable(&pdev->dev); 2259 if (priv->data.dual_emac) 2260 free_netdev(cpsw_get_slave_ndev(priv, 1)); 2261 free_netdev(ndev); 2262 return 0; 2263 } 2264 2265 static int cpsw_suspend(struct device *dev) 2266 { 2267 struct platform_device *pdev = to_platform_device(dev); 2268 struct net_device *ndev = platform_get_drvdata(pdev); 2269 struct cpsw_priv *priv = netdev_priv(ndev); 2270 2271 if (netif_running(ndev)) 2272 cpsw_ndo_stop(ndev); 2273 2274 for_each_slave(priv, soft_reset_slave); 2275 2276 pm_runtime_put_sync(&pdev->dev); 2277 2278 /* Select sleep pin state */ 2279 pinctrl_pm_select_sleep_state(&pdev->dev); 2280 2281 return 0; 2282 } 2283 2284 static int cpsw_resume(struct device *dev) 2285 { 2286 struct platform_device *pdev = to_platform_device(dev); 2287 struct net_device *ndev = platform_get_drvdata(pdev); 2288 2289 pm_runtime_get_sync(&pdev->dev); 2290 2291 /* Select default pin state */ 2292 pinctrl_pm_select_default_state(&pdev->dev); 2293 2294 if (netif_running(ndev)) 2295 cpsw_ndo_open(ndev); 2296 return 0; 2297 } 2298 2299 static const struct dev_pm_ops cpsw_pm_ops = { 2300 .suspend = cpsw_suspend, 2301 .resume = cpsw_resume, 2302 }; 2303 2304 static const struct of_device_id cpsw_of_mtable[] = { 2305 { .compatible = "ti,cpsw", }, 2306 { /* sentinel */ }, 2307 }; 2308 MODULE_DEVICE_TABLE(of, cpsw_of_mtable); 2309 2310 static struct platform_driver cpsw_driver = { 2311 .driver = { 2312 .name = "cpsw", 2313 .owner = THIS_MODULE, 2314 .pm = &cpsw_pm_ops, 2315 .of_match_table = cpsw_of_mtable, 2316 }, 2317 .probe = cpsw_probe, 2318 .remove = cpsw_remove, 2319 }; 2320 2321 static int __init cpsw_init(void) 2322 { 2323 return platform_driver_register(&cpsw_driver); 2324 } 2325 late_initcall(cpsw_init); 2326 2327 static void __exit cpsw_exit(void) 2328 { 2329 platform_driver_unregister(&cpsw_driver); 2330 } 2331 module_exit(cpsw_exit); 2332 2333 MODULE_LICENSE("GPL"); 2334 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 2335 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 2336 MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 2337